arch/arm/mach-shmobile/setup-sh7372.c

   1 /*
   2  * sh7372 processor support
   3  *
   4  * Copyright (C) 2010  Magnus Damm
   5  * Copyright (C) 2008  Yoshihiro Shimoda
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/delay.h>
  26 #include <linux/input.h>
  27 #include <linux/io.h>
  28 #include <linux/serial_sci.h>
  29 #include <linux/sh_dma.h>
  30 #include <linux/sh_intc.h>
  31 #include <linux/sh_timer.h>
  32 #include <mach/hardware.h>
  33 #include <mach/sh7372.h>
  34 #include <asm/mach-types.h>
  35 #include <asm/mach/arch.h>
  36
  37 /* SCIFA0 */
  38 static struct plat_sci_port scif0_platform_data = {
  39         .mapbase        = 0xe6c40000,
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .type           = PORT_SCIFA,
  42         .irqs           = { evt2irq(0x0c00), evt2irq(0x0c00),
  43                             evt2irq(0x0c00), evt2irq(0x0c00) },
  44 };
  45
  46 static struct platform_device scif0_device = {
  47         .name           = "sh-sci",
  48         .id             = 0,
  49         .dev            = {
  50                 .platform_data  = &scif0_platform_data,
  51         },
  52 };
  53
  54 /* SCIFA1 */
  55 static struct plat_sci_port scif1_platform_data = {
  56         .mapbase        = 0xe6c50000,
  57         .flags          = UPF_BOOT_AUTOCONF,
  58         .type           = PORT_SCIFA,
  59         .irqs           = { evt2irq(0x0c20), evt2irq(0x0c20),
  60                             evt2irq(0x0c20), evt2irq(0x0c20) },
  61 };
  62
  63 static struct platform_device scif1_device = {
  64         .name           = "sh-sci",
  65         .id             = 1,
  66         .dev            = {
  67                 .platform_data  = &scif1_platform_data,
  68         },
  69 };
  70
  71 /* SCIFA2 */
  72 static struct plat_sci_port scif2_platform_data = {
  73         .mapbase        = 0xe6c60000,
  74         .flags          = UPF_BOOT_AUTOCONF,
  75         .type           = PORT_SCIFA,
  76         .irqs           = { evt2irq(0x0c40), evt2irq(0x0c40),
  77                             evt2irq(0x0c40), evt2irq(0x0c40) },
  78 };
  79
  80 static struct platform_device scif2_device = {
  81         .name           = "sh-sci",
  82         .id             = 2,
  83         .dev            = {
  84                 .platform_data  = &scif2_platform_data,
  85         },
  86 };
  87
  88 /* SCIFA3 */
  89 static struct plat_sci_port scif3_platform_data = {
  90         .mapbase        = 0xe6c70000,
  91         .flags          = UPF_BOOT_AUTOCONF,
  92         .type           = PORT_SCIFA,
  93         .irqs           = { evt2irq(0x0c60), evt2irq(0x0c60),
  94                             evt2irq(0x0c60), evt2irq(0x0c60) },
  95 };
  96
  97 static struct platform_device scif3_device = {
  98         .name           = "sh-sci",
  99         .id             = 3,
 100         .dev            = {
 101                 .platform_data  = &scif3_platform_data,
 102         },
 103 };
 104
 105 /* SCIFA4 */
 106 static struct plat_sci_port scif4_platform_data = {
 107         .mapbase        = 0xe6c80000,
 108         .flags          = UPF_BOOT_AUTOCONF,
 109         .type           = PORT_SCIFA,
 110         .irqs           = { evt2irq(0x0d20), evt2irq(0x0d20),
 111                             evt2irq(0x0d20), evt2irq(0x0d20) },
 112 };
 113
 114 static struct platform_device scif4_device = {
 115         .name           = "sh-sci",
 116         .id             = 4,
 117         .dev            = {
 118                 .platform_data  = &scif4_platform_data,
 119         },
 120 };
 121
 122 /* SCIFA5 */
 123 static struct plat_sci_port scif5_platform_data = {
 124         .mapbase        = 0xe6cb0000,
 125         .flags          = UPF_BOOT_AUTOCONF,
 126         .type           = PORT_SCIFA,
 127         .irqs           = { evt2irq(0x0d40), evt2irq(0x0d40),
 128                             evt2irq(0x0d40), evt2irq(0x0d40) },
 129 };
 130
 131 static struct platform_device scif5_device = {
 132         .name           = "sh-sci",
 133         .id             = 5,
 134         .dev            = {
 135                 .platform_data  = &scif5_platform_data,
 136         },
 137 };
 138
 139 /* SCIFB */
 140 static struct plat_sci_port scif6_platform_data = {
 141         .mapbase        = 0xe6c30000,
 142         .flags          = UPF_BOOT_AUTOCONF,
 143         .type           = PORT_SCIFB,
 144         .irqs           = { evt2irq(0x0d60), evt2irq(0x0d60),
 145                             evt2irq(0x0d60), evt2irq(0x0d60) },
 146 };
 147
 148 static struct platform_device scif6_device = {
 149         .name           = "sh-sci",
 150         .id             = 6,
 151         .dev            = {
 152                 .platform_data  = &scif6_platform_data,
 153         },
 154 };
 155
 156 /* CMT */
 157 static struct sh_timer_config cmt10_platform_data = {
 158         .name = "CMT10",
 159         .channel_offset = 0x10,
 160         .timer_bit = 0,
 161         .clockevent_rating = 125,
 162         .clocksource_rating = 125,
 163 };
 164
 165 static struct resource cmt10_resources[] = {
 166         [0] = {
 167                 .name   = "CMT10",
 168                 .start  = 0xe6138010,
 169                 .end    = 0xe613801b,
 170                 .flags  = IORESOURCE_MEM,
 171         },
 172         [1] = {
 173                 .start  = evt2irq(0x0b00), /* CMT1_CMT10 */
 174                 .flags  = IORESOURCE_IRQ,
 175         },
 176 };
 177
 178 static struct platform_device cmt10_device = {
 179         .name           = "sh_cmt",
 180         .id             = 10,
 181         .dev = {
 182                 .platform_data  = &cmt10_platform_data,
 183         },
 184         .resource       = cmt10_resources,
 185         .num_resources  = ARRAY_SIZE(cmt10_resources),
 186 };
 187
 188 /* I2C */
 189 static struct resource iic0_resources[] = {
 190         [0] = {
 191                 .name   = "IIC0",
 192                 .start  = 0xFFF20000,
 193                 .end    = 0xFFF20425 - 1,
 194                 .flags  = IORESOURCE_MEM,
 195         },
 196         [1] = {
 197                 .start  = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
 198                 .end    = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
 199                 .flags  = IORESOURCE_IRQ,
 200         },
 201 };
 202
 203 static struct platform_device iic0_device = {
 204         .name           = "i2c-sh_mobile",
 205         .id             = 0, /* "i2c0" clock */
 206         .num_resources  = ARRAY_SIZE(iic0_resources),
 207         .resource       = iic0_resources,
 208 };
 209
 210 static struct resource iic1_resources[] = {
 211         [0] = {
 212                 .name   = "IIC1",
 213                 .start  = 0xE6C20000,
 214                 .end    = 0xE6C20425 - 1,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         [1] = {
 218                 .start  = evt2irq(0x780), /* IIC1_ALI1 */
 219                 .end    = evt2irq(0x7e0), /* IIC1_DTEI1 */
 220                 .flags  = IORESOURCE_IRQ,
 221         },
 222 };
 223
 224 static struct platform_device iic1_device = {
 225         .name           = "i2c-sh_mobile",
 226         .id             = 1, /* "i2c1" clock */
 227         .num_resources  = ARRAY_SIZE(iic1_resources),
 228         .resource       = iic1_resources,
 229 };
 230
 231 /* DMA */
 232 /* Transmit sizes and respective CHCR register values */
 233 enum {
 234         XMIT_SZ_8BIT            = 0,
 235         XMIT_SZ_16BIT           = 1,
 236         XMIT_SZ_32BIT           = 2,
 237         XMIT_SZ_64BIT           = 7,
 238         XMIT_SZ_128BIT          = 3,
 239         XMIT_SZ_256BIT          = 4,
 240         XMIT_SZ_512BIT          = 5,
 241 };
 242
 243 /* log2(size / 8) - used to calculate number of transfers */
 244 #define TS_SHIFT {                      \
 245         [XMIT_SZ_8BIT]          = 0,    \
 246         [XMIT_SZ_16BIT]         = 1,    \
 247         [XMIT_SZ_32BIT]         = 2,    \
 248         [XMIT_SZ_64BIT]         = 3,    \
 249         [XMIT_SZ_128BIT]        = 4,    \
 250         [XMIT_SZ_256BIT]        = 5,    \
 251         [XMIT_SZ_512BIT]        = 6,    \
 252 }
 253
 254 #define TS_INDEX2VAL(i) ((((i) & 3) << 3) | \
 255                          (((i) & 0xc) << (20 - 2)))
 256
 257 static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
 258         {
 259                 .slave_id       = SHDMA_SLAVE_SCIF0_TX,
 260                 .addr           = 0xe6c40020,
 261                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 262                 .mid_rid        = 0x21,
 263         }, {
 264                 .slave_id       = SHDMA_SLAVE_SCIF0_RX,
 265                 .addr           = 0xe6c40024,
 266                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 267                 .mid_rid        = 0x22,
 268         }, {
 269                 .slave_id       = SHDMA_SLAVE_SCIF1_TX,
 270                 .addr           = 0xe6c50020,
 271                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 272                 .mid_rid        = 0x25,
 273         }, {
 274                 .slave_id       = SHDMA_SLAVE_SCIF1_RX,
 275                 .addr           = 0xe6c50024,
 276                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 277                 .mid_rid        = 0x26,
 278         }, {
 279                 .slave_id       = SHDMA_SLAVE_SCIF2_TX,
 280                 .addr           = 0xe6c60020,
 281                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 282                 .mid_rid        = 0x29,
 283         }, {
 284                 .slave_id       = SHDMA_SLAVE_SCIF2_RX,
 285                 .addr           = 0xe6c60024,
 286                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 287                 .mid_rid        = 0x2a,
 288         }, {
 289                 .slave_id       = SHDMA_SLAVE_SCIF3_TX,
 290                 .addr           = 0xe6c70020,
 291                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 292                 .mid_rid        = 0x2d,
 293         }, {
 294                 .slave_id       = SHDMA_SLAVE_SCIF3_RX,
 295                 .addr           = 0xe6c70024,
 296                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 297                 .mid_rid        = 0x2e,
 298         }, {
 299                 .slave_id       = SHDMA_SLAVE_SCIF4_TX,
 300                 .addr           = 0xe6c80020,
 301                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 302                 .mid_rid        = 0x39,
 303         }, {
 304                 .slave_id       = SHDMA_SLAVE_SCIF4_RX,
 305                 .addr           = 0xe6c80024,
 306                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 307                 .mid_rid        = 0x3a,
 308         }, {
 309                 .slave_id       = SHDMA_SLAVE_SCIF5_TX,
 310                 .addr           = 0xe6cb0020,
 311                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 312                 .mid_rid        = 0x35,
 313         }, {
 314                 .slave_id       = SHDMA_SLAVE_SCIF5_RX,
 315                 .addr           = 0xe6cb0024,
 316                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 317                 .mid_rid        = 0x36,
 318         }, {
 319                 .slave_id       = SHDMA_SLAVE_SCIF6_TX,
 320                 .addr           = 0xe6c30040,
 321                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 322                 .mid_rid        = 0x3d,
 323         }, {
 324                 .slave_id       = SHDMA_SLAVE_SCIF6_RX,
 325                 .addr           = 0xe6c30060,
 326                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
 327                 .mid_rid        = 0x3e,
 328         }, {
 329                 .slave_id       = SHDMA_SLAVE_SDHI0_TX,
 330                 .addr           = 0xe6850030,
 331                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 332                 .mid_rid        = 0xc1,
 333         }, {
 334                 .slave_id       = SHDMA_SLAVE_SDHI0_RX,
 335                 .addr           = 0xe6850030,
 336                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 337                 .mid_rid        = 0xc2,
 338         }, {
 339                 .slave_id       = SHDMA_SLAVE_SDHI1_TX,
 340                 .addr           = 0xe6860030,
 341                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 342                 .mid_rid        = 0xc9,
 343         }, {
 344                 .slave_id       = SHDMA_SLAVE_SDHI1_RX,
 345                 .addr           = 0xe6860030,
 346                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 347                 .mid_rid        = 0xca,
 348         }, {
 349                 .slave_id       = SHDMA_SLAVE_SDHI2_TX,
 350                 .addr           = 0xe6870030,
 351                 .chcr           = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 352                 .mid_rid        = 0xcd,
 353         }, {
 354                 .slave_id       = SHDMA_SLAVE_SDHI2_RX,
 355                 .addr           = 0xe6870030,
 356                 .chcr           = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
 357                 .mid_rid        = 0xce,
 358         },
 359 };
 360
 361 static const struct sh_dmae_channel sh7372_dmae_channels[] = {
 362         {
 363                 .offset = 0,
 364                 .dmars = 0,
 365                 .dmars_bit = 0,
 366         }, {
 367                 .offset = 0x10,
 368                 .dmars = 0,
 369                 .dmars_bit = 8,
 370         }, {
 371                 .offset = 0x20,
 372                 .dmars = 4,
 373                 .dmars_bit = 0,
 374         }, {
 375                 .offset = 0x30,
 376                 .dmars = 4,
 377                 .dmars_bit = 8,
 378         }, {
 379                 .offset = 0x50,
 380                 .dmars = 8,
 381                 .dmars_bit = 0,
 382         }, {
 383                 .offset = 0x60,
 384                 .dmars = 8,
 385                 .dmars_bit = 8,
 386         }
 387 };
 388
 389 static const unsigned int ts_shift[] = TS_SHIFT;
 390
 391 static struct sh_dmae_pdata dma_platform_data = {
 392         .slave          = sh7372_dmae_slaves,
 393         .slave_num      = ARRAY_SIZE(sh7372_dmae_slaves),
 394         .channel        = sh7372_dmae_channels,
 395         .channel_num    = ARRAY_SIZE(sh7372_dmae_channels),
 396         .ts_low_shift   = 3,
 397         .ts_low_mask    = 0x18,
 398         .ts_high_shift  = (20 - 2),     /* 2 bits for shifted low TS */
 399         .ts_high_mask   = 0x00300000,
 400         .ts_shift       = ts_shift,
 401         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 402         .dmaor_init     = DMAOR_DME,
 403 };
 404
 405 /* Resource order important! */
 406 static struct resource sh7372_dmae0_resources[] = {
 407         {
 408                 /* Channel registers and DMAOR */
 409                 .start  = 0xfe008020,
 410                 .end    = 0xfe00808f,
 411                 .flags  = IORESOURCE_MEM,
 412         },
 413         {
 414                 /* DMARSx */
 415                 .start  = 0xfe009000,
 416                 .end    = 0xfe00900b,
 417                 .flags  = IORESOURCE_MEM,
 418         },
 419         {
 420                 /* DMA error IRQ */
 421                 .start  = evt2irq(0x20c0),
 422                 .end    = evt2irq(0x20c0),
 423                 .flags  = IORESOURCE_IRQ,
 424         },
 425         {
 426                 /* IRQ for channels 0-5 */
 427                 .start  = evt2irq(0x2000),
 428                 .end    = evt2irq(0x20a0),
 429                 .flags  = IORESOURCE_IRQ,
 430         },
 431 };
 432
 433 /* Resource order important! */
 434 static struct resource sh7372_dmae1_resources[] = {
 435         {
 436                 /* Channel registers and DMAOR */
 437                 .start  = 0xfe018020,
 438                 .end    = 0xfe01808f,
 439                 .flags  = IORESOURCE_MEM,
 440         },
 441         {
 442                 /* DMARSx */
 443                 .start  = 0xfe019000,
 444                 .end    = 0xfe01900b,
 445                 .flags  = IORESOURCE_MEM,
 446         },
 447         {
 448                 /* DMA error IRQ */
 449                 .start  = evt2irq(0x21c0),
 450                 .end    = evt2irq(0x21c0),
 451                 .flags  = IORESOURCE_IRQ,
 452         },
 453         {
 454                 /* IRQ for channels 0-5 */
 455                 .start  = evt2irq(0x2100),
 456                 .end    = evt2irq(0x21a0),
 457                 .flags  = IORESOURCE_IRQ,
 458         },
 459 };
 460
 461 /* Resource order important! */
 462 static struct resource sh7372_dmae2_resources[] = {
 463         {
 464                 /* Channel registers and DMAOR */
 465                 .start  = 0xfe028020,
 466                 .end    = 0xfe02808f,
 467                 .flags  = IORESOURCE_MEM,
 468         },
 469         {
 470                 /* DMARSx */
 471                 .start  = 0xfe029000,
 472                 .end    = 0xfe02900b,
 473                 .flags  = IORESOURCE_MEM,
 474         },
 475         {
 476                 /* DMA error IRQ */
 477                 .start  = evt2irq(0x22c0),
 478                 .end    = evt2irq(0x22c0),
 479                 .flags  = IORESOURCE_IRQ,
 480         },
 481         {
 482                 /* IRQ for channels 0-5 */
 483                 .start  = evt2irq(0x2200),
 484                 .end    = evt2irq(0x22a0),
 485                 .flags  = IORESOURCE_IRQ,
 486         },
 487 };
 488
 489 static struct platform_device dma0_device = {
 490         .name           = "sh-dma-engine",
 491         .id             = 0,
 492         .resource       = sh7372_dmae0_resources,
 493         .num_resources  = ARRAY_SIZE(sh7372_dmae0_resources),
 494         .dev            = {
 495                 .platform_data  = &dma_platform_data,
 496         },
 497 };
 498
 499 static struct platform_device dma1_device = {
 500         .name           = "sh-dma-engine",
 501         .id             = 1,
 502         .resource       = sh7372_dmae1_resources,
 503         .num_resources  = ARRAY_SIZE(sh7372_dmae1_resources),
 504         .dev            = {
 505                 .platform_data  = &dma_platform_data,
 506         },
 507 };
 508
 509 static struct platform_device dma2_device = {
 510         .name           = "sh-dma-engine",
 511         .id             = 2,
 512         .resource       = sh7372_dmae2_resources,
 513         .num_resources  = ARRAY_SIZE(sh7372_dmae2_resources),
 514         .dev            = {
 515                 .platform_data  = &dma_platform_data,
 516         },
 517 };
 518
 519 static struct platform_device *sh7372_early_devices[] __initdata = {
 520         &scif0_device,
 521         &scif1_device,
 522         &scif2_device,
 523         &scif3_device,
 524         &scif4_device,
 525         &scif5_device,
 526         &scif6_device,
 527         &cmt10_device,
 528 };
 529
 530 static struct platform_device *sh7372_late_devices[] __initdata = {
 531         &iic0_device,
 532         &iic1_device,
 533         &dma0_device,
 534         &dma1_device,
 535         &dma2_device,
 536 };
 537
 538 void __init sh7372_add_standard_devices(void)
 539 {
 540         platform_add_devices(sh7372_early_devices,
 541                             ARRAY_SIZE(sh7372_early_devices));
 542
 543         platform_add_devices(sh7372_late_devices,
 544                             ARRAY_SIZE(sh7372_late_devices));
 545 }
 546
 547 void __init sh7372_add_early_devices(void)
 548 {
 549         early_platform_add_devices(sh7372_early_devices,
 550                                    ARRAY_SIZE(sh7372_early_devices));
 551 }