2 * sh7372 Power management support
4 * Copyright (C) 2011 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/suspend.h>
13 #include <linux/cpuidle.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/pm_clock.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/bitrev.h>
23 #include <asm/system.h>
25 #include <asm/tlbflush.h>
26 #include <asm/suspend.h>
27 #include <mach/common.h>
28 #include <mach/sh7372.h>
31 #define DBGREG1 0xe6100020
32 #define DBGREG9 0xe6100040
35 #define SYSTBCR 0xe6150024
36 #define MSTPSR0 0xe6150030
37 #define MSTPSR1 0xe6150038
38 #define MSTPSR2 0xe6150040
39 #define MSTPSR3 0xe6150048
40 #define MSTPSR4 0xe615004c
41 #define PLLC01STPCR 0xe61500c8
44 #define SPDCR 0xe6180008
45 #define SWUCR 0xe6180014
46 #define SBAR 0xe6180020
47 #define WUPSMSK 0xe618002c
48 #define WUPSMSK2 0xe6180048
49 #define PSTR 0xe6180080
50 #define WUPSFAC 0xe6180098
51 #define IRQCR 0xe618022c
52 #define IRQCR2 0xe6180238
53 #define IRQCR3 0xe6180244
54 #define IRQCR4 0xe6180248
55 #define PDNSEL 0xe6180254
58 #define ICR1A 0xe6900000
59 #define ICR2A 0xe6900004
60 #define ICR3A 0xe6900008
61 #define ICR4A 0xe690000c
62 #define INTMSK00A 0xe6900040
63 #define INTMSK10A 0xe6900044
64 #define INTMSK20A 0xe6900048
65 #define INTMSK30A 0xe690004c
68 #define SMFRAM 0xe6a70000
71 #define APARMBAREA 0xe6f10020
73 #define PSTR_RETRIES 100
74 #define PSTR_DELAY_US 10
78 static int pd_power_down(struct generic_pm_domain *genpd)
80 struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
81 unsigned int mask = 1 << sh7372_pd->bit_shift;
83 if (__raw_readl(PSTR) & mask) {
84 unsigned int retry_count;
86 __raw_writel(mask, SPDCR);
88 for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
89 if (!(__raw_readl(SPDCR) & mask))
95 pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
96 mask, __raw_readl(PSTR));
101 static int pd_power_up(struct generic_pm_domain *genpd)
103 struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
104 unsigned int mask = 1 << sh7372_pd->bit_shift;
105 unsigned int retry_count;
108 if (__raw_readl(PSTR) & mask)
111 __raw_writel(mask, SWUCR);
113 for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
114 if (!(__raw_readl(SWUCR) & mask))
116 if (retry_count > PSTR_RETRIES)
117 udelay(PSTR_DELAY_US);
121 if (__raw_readl(SWUCR) & mask)
125 pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
126 mask, __raw_readl(PSTR));
131 static bool pd_active_wakeup(struct device *dev)
136 void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
138 struct generic_pm_domain *genpd = &sh7372_pd->genpd;
140 pm_genpd_init(genpd, NULL, false);
141 genpd->stop_device = pm_clk_suspend;
142 genpd->start_device = pm_clk_resume;
143 genpd->dev_irq_safe = true;
144 genpd->active_wakeup = pd_active_wakeup;
145 genpd->power_off = pd_power_down;
146 genpd->power_on = pd_power_up;
147 genpd->power_on(&sh7372_pd->genpd);
150 void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
151 struct platform_device *pdev)
153 struct device *dev = &pdev->dev;
155 pm_genpd_add_device(&sh7372_pd->genpd, dev);
156 if (pm_clk_no_clocks(dev))
157 pm_clk_add(dev, NULL);
160 void sh7372_pm_add_subdomain(struct sh7372_pm_domain *sh7372_pd,
161 struct sh7372_pm_domain *sh7372_sd)
163 pm_genpd_add_subdomain(&sh7372_pd->genpd, &sh7372_sd->genpd);
166 struct sh7372_pm_domain sh7372_a4lc = {
170 struct sh7372_pm_domain sh7372_a4mp = {
174 struct sh7372_pm_domain sh7372_d4 = {
178 struct sh7372_pm_domain sh7372_a3rv = {
182 struct sh7372_pm_domain sh7372_a3ri = {
186 struct sh7372_pm_domain sh7372_a3sg = {
190 #endif /* CONFIG_PM */
192 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
193 static int sh7372_do_idle_core_standby(unsigned long unused)
195 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
199 static void sh7372_enter_core_standby(void)
201 /* set reset vector, translate 4k */
202 __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
203 __raw_writel(0, APARMBAREA);
205 /* enter sleep mode with SYSTBCR to 0x10 */
206 __raw_writel(0x10, SYSTBCR);
207 cpu_suspend(0, sh7372_do_idle_core_standby);
208 __raw_writel(0, SYSTBCR);
210 /* disable reset vector translation */
211 __raw_writel(0, SBAR);
215 #ifdef CONFIG_SUSPEND
216 static void sh7372_enter_a3sm_common(int pllc0_on)
218 /* set reset vector, translate 4k */
219 __raw_writel(__pa(sh7372_resume_core_standby_a3sm), SBAR);
220 __raw_writel(0, APARMBAREA);
223 __raw_writel(0, PLLC01STPCR);
225 __raw_writel(1 << 28, PLLC01STPCR);
227 __raw_writel(0, PDNSEL); /* power-down A3SM only, not A4S */
228 __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
229 cpu_suspend(0, sh7372_do_idle_a3sm);
230 __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
232 /* disable reset vector translation */
233 __raw_writel(0, SBAR);
236 static int sh7372_a3sm_valid(unsigned long *mskp, unsigned long *msk2p)
238 unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
239 unsigned long msk, msk2;
241 /* check active clocks to determine potential wakeup sources */
243 mstpsr0 = __raw_readl(MSTPSR0);
244 if ((mstpsr0 & 0x00000003) != 0x00000003) {
245 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
249 mstpsr1 = __raw_readl(MSTPSR1);
250 if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
251 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
255 mstpsr2 = __raw_readl(MSTPSR2);
256 if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
257 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
261 mstpsr3 = __raw_readl(MSTPSR3);
262 if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
263 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
267 mstpsr4 = __raw_readl(MSTPSR4);
268 if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
269 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
276 /* make bitmaps of limited number of wakeup sources */
278 if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
281 if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
284 if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
287 if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
290 if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
293 if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
296 if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
305 static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
307 u16 tmp, irqcr1, irqcr2;
313 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
314 for (k = 0; k <= 7; k++) {
315 tmp = (icr >> ((7 - k) * 4)) & 0xf;
316 irqcr1 |= (tmp & 0x03) << (k * 2);
317 irqcr2 |= (tmp >> 2) << (k * 2);
324 static void sh7372_setup_a3sm(unsigned long msk, unsigned long msk2)
326 u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
329 /* read IRQ0A -> IRQ15A mask */
330 tmp = bitrev8(__raw_readb(INTMSK00A));
331 tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
333 /* setup WUPSMSK from clocks and external IRQ mask */
334 msk = (~msk & 0xc030000f) | (tmp << 4);
335 __raw_writel(msk, WUPSMSK);
337 /* propage level/edge trigger for external IRQ 0->15 */
338 sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
339 sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
340 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
341 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
343 /* read IRQ16A -> IRQ31A mask */
344 tmp = bitrev8(__raw_readb(INTMSK20A));
345 tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
347 /* setup WUPSMSK2 from clocks and external IRQ mask */
348 msk2 = (~msk2 & 0x00030000) | tmp;
349 __raw_writel(msk2, WUPSMSK2);
351 /* propage level/edge trigger for external IRQ 16->31 */
352 sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
353 sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
354 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
355 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
359 #ifdef CONFIG_CPU_IDLE
361 static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
363 struct cpuidle_state *state;
364 int i = dev->state_count;
366 state = &dev->states[i];
367 snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
368 strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
369 state->exit_latency = 10;
370 state->target_residency = 20 + 10;
371 state->power_usage = 1; /* perhaps not */
373 state->flags |= CPUIDLE_FLAG_TIME_VALID;
374 shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
376 dev->state_count = i + 1;
379 static void sh7372_cpuidle_init(void)
381 shmobile_cpuidle_setup = sh7372_cpuidle_setup;
384 static void sh7372_cpuidle_init(void) {}
387 #ifdef CONFIG_SUSPEND
389 static int sh7372_enter_suspend(suspend_state_t suspend_state)
391 unsigned long msk, msk2;
393 /* check active clocks to determine potential wakeup sources */
394 if (sh7372_a3sm_valid(&msk, &msk2)) {
396 /* convert INTC mask and sense to SYSC mask and sense */
397 sh7372_setup_a3sm(msk, msk2);
399 /* enter A3SM sleep with PLLC0 off */
400 pr_debug("entering A3SM\n");
401 sh7372_enter_a3sm_common(0);
403 /* default to Core Standby that supports all wakeup sources */
404 pr_debug("entering Core Standby\n");
405 sh7372_enter_core_standby();
410 static void sh7372_suspend_init(void)
412 shmobile_suspend_ops.enter = sh7372_enter_suspend;
415 static void sh7372_suspend_init(void) {}
418 void __init sh7372_pm_init(void)
420 /* enable DBG hardware block to kick SYSC */
421 __raw_writel(0x0000a500, DBGREG9);
422 __raw_writel(0x0000a501, DBGREG9);
423 __raw_writel(0x00000000, DBGREG1);
425 sh7372_suspend_init();
426 sh7372_cpuidle_init();