arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static unsigned long xtal;
  35
  36 static struct clksrc_clk clk_mout_apll = {
  37         .clk    = {
  38                 .name           = "mout_apll",
  39         },
  40         .sources        = &clk_src_apll,
  41         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  42 };
  43
  44 static struct clksrc_clk clk_mout_epll = {
  45         .clk    = {
  46                 .name           = "mout_epll",
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55         },
  56         .sources        = &clk_src_mpll,
  57         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  58 };
  59
  60 static struct clk *clkset_armclk_list[] = {
  61         [0] = &clk_mout_apll.clk,
  62         [1] = &clk_mout_mpll.clk,
  63 };
  64
  65 static struct clksrc_sources clkset_armclk = {
  66         .sources        = clkset_armclk_list,
  67         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  68 };
  69
  70 static struct clksrc_clk clk_armclk = {
  71         .clk    = {
  72                 .name           = "armclk",
  73         },
  74         .sources        = &clkset_armclk,
  75         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  76         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  77 };
  78
  79 static struct clksrc_clk clk_hclk_msys = {
  80         .clk    = {
  81                 .name           = "hclk_msys",
  82                 .parent         = &clk_armclk.clk,
  83         },
  84         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  85 };
  86
  87 static struct clksrc_clk clk_pclk_msys = {
  88         .clk    = {
  89                 .name           = "pclk_msys",
  90                 .parent         = &clk_hclk_msys.clk,
  91         },
  92         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  93 };
  94
  95 static struct clksrc_clk clk_sclk_a2m = {
  96         .clk    = {
  97                 .name           = "sclk_a2m",
  98                 .parent         = &clk_mout_apll.clk,
  99         },
 100         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 101 };
 102
 103 static struct clk *clkset_hclk_sys_list[] = {
 104         [0] = &clk_mout_mpll.clk,
 105         [1] = &clk_sclk_a2m.clk,
 106 };
 107
 108 static struct clksrc_sources clkset_hclk_sys = {
 109         .sources        = clkset_hclk_sys_list,
 110         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 111 };
 112
 113 static struct clksrc_clk clk_hclk_dsys = {
 114         .clk    = {
 115                 .name   = "hclk_dsys",
 116         },
 117         .sources        = &clkset_hclk_sys,
 118         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 119         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 120 };
 121
 122 static struct clksrc_clk clk_pclk_dsys = {
 123         .clk    = {
 124                 .name   = "pclk_dsys",
 125                 .parent = &clk_hclk_dsys.clk,
 126         },
 127         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 128 };
 129
 130 static struct clksrc_clk clk_hclk_psys = {
 131         .clk    = {
 132                 .name   = "hclk_psys",
 133         },
 134         .sources        = &clkset_hclk_sys,
 135         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 136         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 137 };
 138
 139 static struct clksrc_clk clk_pclk_psys = {
 140         .clk    = {
 141                 .name   = "pclk_psys",
 142                 .parent = &clk_hclk_psys.clk,
 143         },
 144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 145 };
 146
 147 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 148 {
 149         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 150 }
 151
 152 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 153 {
 154         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 155 }
 156
 157 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 158 {
 159         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 160 }
 161
 162 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 163 {
 164         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 165 }
 166
 167 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 168 {
 169         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 170 }
 171
 172 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 173 {
 174         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 175 }
 176
 177 static struct clk clk_sclk_hdmi27m = {
 178         .name           = "sclk_hdmi27m",
 179         .rate           = 27000000,
 180 };
 181
 182 static struct clk clk_sclk_hdmiphy = {
 183         .name           = "sclk_hdmiphy",
 184 };
 185
 186 static struct clk clk_sclk_usbphy0 = {
 187         .name           = "sclk_usbphy0",
 188 };
 189
 190 static struct clk clk_sclk_usbphy1 = {
 191         .name           = "sclk_usbphy1",
 192 };
 193
 194 static struct clk clk_pcmcdclk0 = {
 195         .name           = "pcmcdclk",
 196 };
 197
 198 static struct clk clk_pcmcdclk1 = {
 199         .name           = "pcmcdclk",
 200 };
 201
 202 static struct clk clk_pcmcdclk2 = {
 203         .name           = "pcmcdclk",
 204 };
 205
 206 static struct clk *clkset_vpllsrc_list[] = {
 207         [0] = &clk_fin_vpll,
 208         [1] = &clk_sclk_hdmi27m,
 209 };
 210
 211 static struct clksrc_sources clkset_vpllsrc = {
 212         .sources        = clkset_vpllsrc_list,
 213         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 214 };
 215
 216 static struct clksrc_clk clk_vpllsrc = {
 217         .clk    = {
 218                 .name           = "vpll_src",
 219                 .enable         = s5pv210_clk_mask0_ctrl,
 220                 .ctrlbit        = (1 << 7),
 221         },
 222         .sources        = &clkset_vpllsrc,
 223         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 224 };
 225
 226 static struct clk *clkset_sclk_vpll_list[] = {
 227         [0] = &clk_vpllsrc.clk,
 228         [1] = &clk_fout_vpll,
 229 };
 230
 231 static struct clksrc_sources clkset_sclk_vpll = {
 232         .sources        = clkset_sclk_vpll_list,
 233         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 234 };
 235
 236 static struct clksrc_clk clk_sclk_vpll = {
 237         .clk    = {
 238                 .name           = "sclk_vpll",
 239         },
 240         .sources        = &clkset_sclk_vpll,
 241         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 242 };
 243
 244 static struct clk *clkset_moutdmc0src_list[] = {
 245         [0] = &clk_sclk_a2m.clk,
 246         [1] = &clk_mout_mpll.clk,
 247         [2] = NULL,
 248         [3] = NULL,
 249 };
 250
 251 static struct clksrc_sources clkset_moutdmc0src = {
 252         .sources        = clkset_moutdmc0src_list,
 253         .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
 254 };
 255
 256 static struct clksrc_clk clk_mout_dmc0 = {
 257         .clk    = {
 258                 .name           = "mout_dmc0",
 259         },
 260         .sources        = &clkset_moutdmc0src,
 261         .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 262 };
 263
 264 static struct clksrc_clk clk_sclk_dmc0 = {
 265         .clk    = {
 266                 .name           = "sclk_dmc0",
 267                 .parent         = &clk_mout_dmc0.clk,
 268         },
 269         .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 270 };
 271
 272 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 273 {
 274         return clk_get_rate(clk->parent) / 2;
 275 }
 276
 277 static struct clk_ops clk_hclk_imem_ops = {
 278         .get_rate       = s5pv210_clk_imem_get_rate,
 279 };
 280
 281 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
 282 {
 283         return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 284 }
 285
 286 static struct clk_ops clk_fout_apll_ops = {
 287         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 288 };
 289
 290 static struct clk init_clocks_off[] = {
 291         {
 292                 .name           = "pdma",
 293                 .devname        = "s3c-pl330.0",
 294                 .parent         = &clk_hclk_psys.clk,
 295                 .enable         = s5pv210_clk_ip0_ctrl,
 296                 .ctrlbit        = (1 << 3),
 297         }, {
 298                 .name           = "pdma",
 299                 .devname        = "s3c-pl330.1",
 300                 .parent         = &clk_hclk_psys.clk,
 301                 .enable         = s5pv210_clk_ip0_ctrl,
 302                 .ctrlbit        = (1 << 4),
 303         }, {
 304                 .name           = "rot",
 305                 .parent         = &clk_hclk_dsys.clk,
 306                 .enable         = s5pv210_clk_ip0_ctrl,
 307                 .ctrlbit        = (1<<29),
 308         }, {
 309                 .name           = "fimc",
 310                 .devname        = "s5pv210-fimc.0",
 311                 .parent         = &clk_hclk_dsys.clk,
 312                 .enable         = s5pv210_clk_ip0_ctrl,
 313                 .ctrlbit        = (1 << 24),
 314         }, {
 315                 .name           = "fimc",
 316                 .devname        = "s5pv210-fimc.1",
 317                 .parent         = &clk_hclk_dsys.clk,
 318                 .enable         = s5pv210_clk_ip0_ctrl,
 319                 .ctrlbit        = (1 << 25),
 320         }, {
 321                 .name           = "fimc",
 322                 .devname        = "s5pv210-fimc.2",
 323                 .parent         = &clk_hclk_dsys.clk,
 324                 .enable         = s5pv210_clk_ip0_ctrl,
 325                 .ctrlbit        = (1 << 26),
 326         }, {
 327                 .name           = "otg",
 328                 .parent         = &clk_hclk_psys.clk,
 329                 .enable         = s5pv210_clk_ip1_ctrl,
 330                 .ctrlbit        = (1<<16),
 331         }, {
 332                 .name           = "usb-host",
 333                 .parent         = &clk_hclk_psys.clk,
 334                 .enable         = s5pv210_clk_ip1_ctrl,
 335                 .ctrlbit        = (1<<17),
 336         }, {
 337                 .name           = "lcd",
 338                 .parent         = &clk_hclk_dsys.clk,
 339                 .enable         = s5pv210_clk_ip1_ctrl,
 340                 .ctrlbit        = (1<<0),
 341         }, {
 342                 .name           = "cfcon",
 343                 .parent         = &clk_hclk_psys.clk,
 344                 .enable         = s5pv210_clk_ip1_ctrl,
 345                 .ctrlbit        = (1<<25),
 346         }, {
 347                 .name           = "hsmmc",
 348                 .devname        = "s3c-sdhci.0",
 349                 .parent         = &clk_hclk_psys.clk,
 350                 .enable         = s5pv210_clk_ip2_ctrl,
 351                 .ctrlbit        = (1<<16),
 352         }, {
 353                 .name           = "hsmmc",
 354                 .devname        = "s3c-sdhci.1",
 355                 .parent         = &clk_hclk_psys.clk,
 356                 .enable         = s5pv210_clk_ip2_ctrl,
 357                 .ctrlbit        = (1<<17),
 358         }, {
 359                 .name           = "hsmmc",
 360                 .devname        = "s3c-sdhci.2",
 361                 .parent         = &clk_hclk_psys.clk,
 362                 .enable         = s5pv210_clk_ip2_ctrl,
 363                 .ctrlbit        = (1<<18),
 364         }, {
 365                 .name           = "hsmmc",
 366                 .devname        = "s3c-sdhci.3",
 367                 .parent         = &clk_hclk_psys.clk,
 368                 .enable         = s5pv210_clk_ip2_ctrl,
 369                 .ctrlbit        = (1<<19),
 370         }, {
 371                 .name           = "systimer",
 372                 .parent         = &clk_pclk_psys.clk,
 373                 .enable         = s5pv210_clk_ip3_ctrl,
 374                 .ctrlbit        = (1<<16),
 375         }, {
 376                 .name           = "watchdog",
 377                 .parent         = &clk_pclk_psys.clk,
 378                 .enable         = s5pv210_clk_ip3_ctrl,
 379                 .ctrlbit        = (1<<22),
 380         }, {
 381                 .name           = "rtc",
 382                 .parent         = &clk_pclk_psys.clk,
 383                 .enable         = s5pv210_clk_ip3_ctrl,
 384                 .ctrlbit        = (1<<15),
 385         }, {
 386                 .name           = "i2c",
 387                 .devname        = "s3c2440-i2c.0",
 388                 .parent         = &clk_pclk_psys.clk,
 389                 .enable         = s5pv210_clk_ip3_ctrl,
 390                 .ctrlbit        = (1<<7),
 391         }, {
 392                 .name           = "i2c",
 393                 .devname        = "s3c2440-i2c.1",
 394                 .parent         = &clk_pclk_psys.clk,
 395                 .enable         = s5pv210_clk_ip3_ctrl,
 396                 .ctrlbit        = (1 << 10),
 397         }, {
 398                 .name           = "i2c",
 399                 .devname        = "s3c2440-i2c.2",
 400                 .parent         = &clk_pclk_psys.clk,
 401                 .enable         = s5pv210_clk_ip3_ctrl,
 402                 .ctrlbit        = (1<<9),
 403         }, {
 404                 .name           = "spi",
 405                 .devname        = "s3c64xx-spi.0",
 406                 .parent         = &clk_pclk_psys.clk,
 407                 .enable         = s5pv210_clk_ip3_ctrl,
 408                 .ctrlbit        = (1<<12),
 409         }, {
 410                 .name           = "spi",
 411                 .devname        = "s3c64xx-spi.1",
 412                 .parent         = &clk_pclk_psys.clk,
 413                 .enable         = s5pv210_clk_ip3_ctrl,
 414                 .ctrlbit        = (1<<13),
 415         }, {
 416                 .name           = "spi",
 417                 .devname        = "s3c64xx-spi.2",
 418                 .parent         = &clk_pclk_psys.clk,
 419                 .enable         = s5pv210_clk_ip3_ctrl,
 420                 .ctrlbit        = (1<<14),
 421         }, {
 422                 .name           = "timers",
 423                 .parent         = &clk_pclk_psys.clk,
 424                 .enable         = s5pv210_clk_ip3_ctrl,
 425                 .ctrlbit        = (1<<23),
 426         }, {
 427                 .name           = "adc",
 428                 .parent         = &clk_pclk_psys.clk,
 429                 .enable         = s5pv210_clk_ip3_ctrl,
 430                 .ctrlbit        = (1<<24),
 431         }, {
 432                 .name           = "keypad",
 433                 .parent         = &clk_pclk_psys.clk,
 434                 .enable         = s5pv210_clk_ip3_ctrl,
 435                 .ctrlbit        = (1<<21),
 436         }, {
 437                 .name           = "iis",
 438                 .devname        = "samsung-i2s.0",
 439                 .parent         = &clk_p,
 440                 .enable         = s5pv210_clk_ip3_ctrl,
 441                 .ctrlbit        = (1<<4),
 442         }, {
 443                 .name           = "iis",
 444                 .devname        = "samsung-i2s.1",
 445                 .parent         = &clk_p,
 446                 .enable         = s5pv210_clk_ip3_ctrl,
 447                 .ctrlbit        = (1 << 5),
 448         }, {
 449                 .name           = "iis",
 450                 .devname        = "samsung-i2s.2",
 451                 .parent         = &clk_p,
 452                 .enable         = s5pv210_clk_ip3_ctrl,
 453                 .ctrlbit        = (1 << 6),
 454         }, {
 455                 .name           = "spdif",
 456                 .parent         = &clk_p,
 457                 .enable         = s5pv210_clk_ip3_ctrl,
 458                 .ctrlbit        = (1 << 0),
 459         },
 460 };
 461
 462 static struct clk init_clocks[] = {
 463         {
 464                 .name           = "hclk_imem",
 465                 .parent         = &clk_hclk_msys.clk,
 466                 .ctrlbit        = (1 << 5),
 467                 .enable         = s5pv210_clk_ip0_ctrl,
 468                 .ops            = &clk_hclk_imem_ops,
 469         }, {
 470                 .name           = "uart",
 471                 .devname        = "s5pv210-uart.0",
 472                 .parent         = &clk_pclk_psys.clk,
 473                 .enable         = s5pv210_clk_ip3_ctrl,
 474                 .ctrlbit        = (1 << 17),
 475         }, {
 476                 .name           = "uart",
 477                 .devname        = "s5pv210-uart.1",
 478                 .parent         = &clk_pclk_psys.clk,
 479                 .enable         = s5pv210_clk_ip3_ctrl,
 480                 .ctrlbit        = (1 << 18),
 481         }, {
 482                 .name           = "uart",
 483                 .devname        = "s5pv210-uart.2",
 484                 .parent         = &clk_pclk_psys.clk,
 485                 .enable         = s5pv210_clk_ip3_ctrl,
 486                 .ctrlbit        = (1 << 19),
 487         }, {
 488                 .name           = "uart",
 489                 .devname        = "s5pv210-uart.3",
 490                 .parent         = &clk_pclk_psys.clk,
 491                 .enable         = s5pv210_clk_ip3_ctrl,
 492                 .ctrlbit        = (1 << 20),
 493         }, {
 494                 .name           = "sromc",
 495                 .parent         = &clk_hclk_psys.clk,
 496                 .enable         = s5pv210_clk_ip1_ctrl,
 497                 .ctrlbit        = (1 << 26),
 498         },
 499 };
 500
 501 static struct clk *clkset_uart_list[] = {
 502         [6] = &clk_mout_mpll.clk,
 503         [7] = &clk_mout_epll.clk,
 504 };
 505
 506 static struct clksrc_sources clkset_uart = {
 507         .sources        = clkset_uart_list,
 508         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 509 };
 510
 511 static struct clk *clkset_group1_list[] = {
 512         [0] = &clk_sclk_a2m.clk,
 513         [1] = &clk_mout_mpll.clk,
 514         [2] = &clk_mout_epll.clk,
 515         [3] = &clk_sclk_vpll.clk,
 516 };
 517
 518 static struct clksrc_sources clkset_group1 = {
 519         .sources        = clkset_group1_list,
 520         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 521 };
 522
 523 static struct clk *clkset_sclk_onenand_list[] = {
 524         [0] = &clk_hclk_psys.clk,
 525         [1] = &clk_hclk_dsys.clk,
 526 };
 527
 528 static struct clksrc_sources clkset_sclk_onenand = {
 529         .sources        = clkset_sclk_onenand_list,
 530         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 531 };
 532
 533 static struct clk *clkset_sclk_dac_list[] = {
 534         [0] = &clk_sclk_vpll.clk,
 535         [1] = &clk_sclk_hdmiphy,
 536 };
 537
 538 static struct clksrc_sources clkset_sclk_dac = {
 539         .sources        = clkset_sclk_dac_list,
 540         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 541 };
 542
 543 static struct clksrc_clk clk_sclk_dac = {
 544         .clk            = {
 545                 .name           = "sclk_dac",
 546                 .enable         = s5pv210_clk_mask0_ctrl,
 547                 .ctrlbit        = (1 << 2),
 548         },
 549         .sources        = &clkset_sclk_dac,
 550         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 551 };
 552
 553 static struct clksrc_clk clk_sclk_pixel = {
 554         .clk            = {
 555                 .name           = "sclk_pixel",
 556                 .parent         = &clk_sclk_vpll.clk,
 557         },
 558         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 559 };
 560
 561 static struct clk *clkset_sclk_hdmi_list[] = {
 562         [0] = &clk_sclk_pixel.clk,
 563         [1] = &clk_sclk_hdmiphy,
 564 };
 565
 566 static struct clksrc_sources clkset_sclk_hdmi = {
 567         .sources        = clkset_sclk_hdmi_list,
 568         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 569 };
 570
 571 static struct clksrc_clk clk_sclk_hdmi = {
 572         .clk            = {
 573                 .name           = "sclk_hdmi",
 574                 .enable         = s5pv210_clk_mask0_ctrl,
 575                 .ctrlbit        = (1 << 0),
 576         },
 577         .sources        = &clkset_sclk_hdmi,
 578         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 579 };
 580
 581 static struct clk *clkset_sclk_mixer_list[] = {
 582         [0] = &clk_sclk_dac.clk,
 583         [1] = &clk_sclk_hdmi.clk,
 584 };
 585
 586 static struct clksrc_sources clkset_sclk_mixer = {
 587         .sources        = clkset_sclk_mixer_list,
 588         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 589 };
 590
 591 static struct clk *clkset_sclk_audio0_list[] = {
 592         [0] = &clk_ext_xtal_mux,
 593         [1] = &clk_pcmcdclk0,
 594         [2] = &clk_sclk_hdmi27m,
 595         [3] = &clk_sclk_usbphy0,
 596         [4] = &clk_sclk_usbphy1,
 597         [5] = &clk_sclk_hdmiphy,
 598         [6] = &clk_mout_mpll.clk,
 599         [7] = &clk_mout_epll.clk,
 600         [8] = &clk_sclk_vpll.clk,
 601 };
 602
 603 static struct clksrc_sources clkset_sclk_audio0 = {
 604         .sources        = clkset_sclk_audio0_list,
 605         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 606 };
 607
 608 static struct clksrc_clk clk_sclk_audio0 = {
 609         .clk            = {
 610                 .name           = "sclk_audio",
 611                 .devname        = "soc-audio.0",
 612                 .enable         = s5pv210_clk_mask0_ctrl,
 613                 .ctrlbit        = (1 << 24),
 614         },
 615         .sources = &clkset_sclk_audio0,
 616         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 617         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 618 };
 619
 620 static struct clk *clkset_sclk_audio1_list[] = {
 621         [0] = &clk_ext_xtal_mux,
 622         [1] = &clk_pcmcdclk1,
 623         [2] = &clk_sclk_hdmi27m,
 624         [3] = &clk_sclk_usbphy0,
 625         [4] = &clk_sclk_usbphy1,
 626         [5] = &clk_sclk_hdmiphy,
 627         [6] = &clk_mout_mpll.clk,
 628         [7] = &clk_mout_epll.clk,
 629         [8] = &clk_sclk_vpll.clk,
 630 };
 631
 632 static struct clksrc_sources clkset_sclk_audio1 = {
 633         .sources        = clkset_sclk_audio1_list,
 634         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 635 };
 636
 637 static struct clksrc_clk clk_sclk_audio1 = {
 638         .clk            = {
 639                 .name           = "sclk_audio",
 640                 .devname        = "soc-audio.1",
 641                 .enable         = s5pv210_clk_mask0_ctrl,
 642                 .ctrlbit        = (1 << 25),
 643         },
 644         .sources = &clkset_sclk_audio1,
 645         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 646         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 647 };
 648
 649 static struct clk *clkset_sclk_audio2_list[] = {
 650         [0] = &clk_ext_xtal_mux,
 651         [1] = &clk_pcmcdclk0,
 652         [2] = &clk_sclk_hdmi27m,
 653         [3] = &clk_sclk_usbphy0,
 654         [4] = &clk_sclk_usbphy1,
 655         [5] = &clk_sclk_hdmiphy,
 656         [6] = &clk_mout_mpll.clk,
 657         [7] = &clk_mout_epll.clk,
 658         [8] = &clk_sclk_vpll.clk,
 659 };
 660
 661 static struct clksrc_sources clkset_sclk_audio2 = {
 662         .sources        = clkset_sclk_audio2_list,
 663         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 664 };
 665
 666 static struct clksrc_clk clk_sclk_audio2 = {
 667         .clk            = {
 668                 .name           = "sclk_audio",
 669                 .devname        = "soc-audio.2",
 670                 .enable         = s5pv210_clk_mask0_ctrl,
 671                 .ctrlbit        = (1 << 26),
 672         },
 673         .sources = &clkset_sclk_audio2,
 674         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 675         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 676 };
 677
 678 static struct clk *clkset_sclk_spdif_list[] = {
 679         [0] = &clk_sclk_audio0.clk,
 680         [1] = &clk_sclk_audio1.clk,
 681         [2] = &clk_sclk_audio2.clk,
 682 };
 683
 684 static struct clksrc_sources clkset_sclk_spdif = {
 685         .sources        = clkset_sclk_spdif_list,
 686         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 687 };
 688
 689 static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
 690 {
 691         struct clk *pclk;
 692         int ret;
 693
 694         pclk = clk_get_parent(clk);
 695         if (IS_ERR(pclk))
 696                 return -EINVAL;
 697
 698         ret = pclk->ops->set_rate(pclk, rate);
 699         clk_put(pclk);
 700
 701         return ret;
 702 }
 703
 704 static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
 705 {
 706         struct clk *pclk;
 707         int rate;
 708
 709         pclk = clk_get_parent(clk);
 710         if (IS_ERR(pclk))
 711                 return -EINVAL;
 712
 713         rate = pclk->ops->get_rate(clk);
 714         clk_put(pclk);
 715
 716         return rate;
 717 }
 718
 719 static struct clk_ops s5pv210_sclk_spdif_ops = {
 720         .set_rate       = s5pv210_spdif_set_rate,
 721         .get_rate       = s5pv210_spdif_get_rate,
 722 };
 723
 724 static struct clksrc_clk clk_sclk_spdif = {
 725         .clk            = {
 726                 .name           = "sclk_spdif",
 727                 .enable         = s5pv210_clk_mask0_ctrl,
 728                 .ctrlbit        = (1 << 27),
 729                 .ops            = &s5pv210_sclk_spdif_ops,
 730         },
 731         .sources = &clkset_sclk_spdif,
 732         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 733 };
 734
 735 static struct clk *clkset_group2_list[] = {
 736         [0] = &clk_ext_xtal_mux,
 737         [1] = &clk_xusbxti,
 738         [2] = &clk_sclk_hdmi27m,
 739         [3] = &clk_sclk_usbphy0,
 740         [4] = &clk_sclk_usbphy1,
 741         [5] = &clk_sclk_hdmiphy,
 742         [6] = &clk_mout_mpll.clk,
 743         [7] = &clk_mout_epll.clk,
 744         [8] = &clk_sclk_vpll.clk,
 745 };
 746
 747 static struct clksrc_sources clkset_group2 = {
 748         .sources        = clkset_group2_list,
 749         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 750 };
 751
 752 static struct clksrc_clk clksrcs[] = {
 753         {
 754                 .clk    = {
 755                         .name           = "sclk_dmc",
 756                 },
 757                 .sources = &clkset_group1,
 758                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 759                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 760         }, {
 761                 .clk    = {
 762                         .name           = "sclk_onenand",
 763                 },
 764                 .sources = &clkset_sclk_onenand,
 765                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 766                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 767         }, {
 768                 .clk    = {
 769                         .name           = "uclk1",
 770                         .devname        = "s5pv210-uart.0",
 771                         .enable         = s5pv210_clk_mask0_ctrl,
 772                         .ctrlbit        = (1 << 12),
 773                 },
 774                 .sources = &clkset_uart,
 775                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 776                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 777         }, {
 778                 .clk            = {
 779                         .name           = "uclk1",
 780                         .devname        = "s5pv210-uart.1",
 781                         .enable         = s5pv210_clk_mask0_ctrl,
 782                         .ctrlbit        = (1 << 13),
 783                 },
 784                 .sources = &clkset_uart,
 785                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
 786                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 787         }, {
 788                 .clk            = {
 789                         .name           = "uclk1",
 790                         .devname        = "s5pv210-uart.2",
 791                         .enable         = s5pv210_clk_mask0_ctrl,
 792                         .ctrlbit        = (1 << 14),
 793                 },
 794                 .sources = &clkset_uart,
 795                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
 796                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
 797         }, {
 798                 .clk            = {
 799                         .name           = "uclk1",
 800                         .devname        = "s5pv210-uart.3",
 801                         .enable         = s5pv210_clk_mask0_ctrl,
 802                         .ctrlbit        = (1 << 15),
 803                 },
 804                 .sources = &clkset_uart,
 805                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
 806                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 807         }, {
 808                 .clk    = {
 809                         .name           = "sclk_mixer",
 810                         .enable         = s5pv210_clk_mask0_ctrl,
 811                         .ctrlbit        = (1 << 1),
 812                 },
 813                 .sources = &clkset_sclk_mixer,
 814                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 815         }, {
 816                 .clk    = {
 817                         .name           = "sclk_fimc",
 818                         .devname        = "s5pv210-fimc.0",
 819                         .enable         = s5pv210_clk_mask1_ctrl,
 820                         .ctrlbit        = (1 << 2),
 821                 },
 822                 .sources = &clkset_group2,
 823                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 824                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 825         }, {
 826                 .clk    = {
 827                         .name           = "sclk_fimc",
 828                         .devname        = "s5pv210-fimc.1",
 829                         .enable         = s5pv210_clk_mask1_ctrl,
 830                         .ctrlbit        = (1 << 3),
 831                 },
 832                 .sources = &clkset_group2,
 833                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 834                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 835         }, {
 836                 .clk    = {
 837                         .name           = "sclk_fimc",
 838                         .devname        = "s5pv210-fimc.2",
 839                         .enable         = s5pv210_clk_mask1_ctrl,
 840                         .ctrlbit        = (1 << 4),
 841                 },
 842                 .sources = &clkset_group2,
 843                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 844                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 845         }, {
 846                 .clk            = {
 847                         .name           = "sclk_cam",
 848                         .devname        = "s5pv210-fimc.0",
 849                         .enable         = s5pv210_clk_mask0_ctrl,
 850                         .ctrlbit        = (1 << 3),
 851                 },
 852                 .sources = &clkset_group2,
 853                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 854                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 855         }, {
 856                 .clk            = {
 857                         .name           = "sclk_cam",
 858                         .devname        = "s5pv210-fimc.1",
 859                         .enable         = s5pv210_clk_mask0_ctrl,
 860                         .ctrlbit        = (1 << 4),
 861                 },
 862                 .sources = &clkset_group2,
 863                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 864                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 865         }, {
 866                 .clk            = {
 867                         .name           = "sclk_fimd",
 868                         .enable         = s5pv210_clk_mask0_ctrl,
 869                         .ctrlbit        = (1 << 5),
 870                 },
 871                 .sources = &clkset_group2,
 872                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 873                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 874         }, {
 875                 .clk            = {
 876                         .name           = "sclk_mmc",
 877                         .devname        = "s3c-sdhci.0",
 878                         .enable         = s5pv210_clk_mask0_ctrl,
 879                         .ctrlbit        = (1 << 8),
 880                 },
 881                 .sources = &clkset_group2,
 882                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 883                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 884         }, {
 885                 .clk            = {
 886                         .name           = "sclk_mmc",
 887                         .devname        = "s3c-sdhci.1",
 888                         .enable         = s5pv210_clk_mask0_ctrl,
 889                         .ctrlbit        = (1 << 9),
 890                 },
 891                 .sources = &clkset_group2,
 892                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 893                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 894         }, {
 895                 .clk            = {
 896                         .name           = "sclk_mmc",
 897                         .devname        = "s3c-sdhci.2",
 898                         .enable         = s5pv210_clk_mask0_ctrl,
 899                         .ctrlbit        = (1 << 10),
 900                 },
 901                 .sources = &clkset_group2,
 902                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 903                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 904         }, {
 905                 .clk            = {
 906                         .name           = "sclk_mmc",
 907                         .devname        = "s3c-sdhci.3",
 908                         .enable         = s5pv210_clk_mask0_ctrl,
 909                         .ctrlbit        = (1 << 11),
 910                 },
 911                 .sources = &clkset_group2,
 912                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 913                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 914         }, {
 915                 .clk            = {
 916                         .name           = "sclk_mfc",
 917                         .enable         = s5pv210_clk_ip0_ctrl,
 918                         .ctrlbit        = (1 << 16),
 919                 },
 920                 .sources = &clkset_group1,
 921                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 922                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 923         }, {
 924                 .clk            = {
 925                         .name           = "sclk_g2d",
 926                         .enable         = s5pv210_clk_ip0_ctrl,
 927                         .ctrlbit        = (1 << 12),
 928                 },
 929                 .sources = &clkset_group1,
 930                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 931                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 932         }, {
 933                 .clk            = {
 934                         .name           = "sclk_g3d",
 935                         .enable         = s5pv210_clk_ip0_ctrl,
 936                         .ctrlbit        = (1 << 8),
 937                 },
 938                 .sources = &clkset_group1,
 939                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 940                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 941         }, {
 942                 .clk            = {
 943                         .name           = "sclk_csis",
 944                         .enable         = s5pv210_clk_mask0_ctrl,
 945                         .ctrlbit        = (1 << 6),
 946                 },
 947                 .sources = &clkset_group2,
 948                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 949                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 950         }, {
 951                 .clk            = {
 952                         .name           = "sclk_spi",
 953                         .devname        = "s3c64xx-spi.0",
 954                         .enable         = s5pv210_clk_mask0_ctrl,
 955                         .ctrlbit        = (1 << 16),
 956                 },
 957                 .sources = &clkset_group2,
 958                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
 959                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
 960         }, {
 961                 .clk            = {
 962                         .name           = "sclk_spi",
 963                         .devname        = "s3c64xx-spi.1",
 964                         .enable         = s5pv210_clk_mask0_ctrl,
 965                         .ctrlbit        = (1 << 17),
 966                 },
 967                 .sources = &clkset_group2,
 968                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
 969                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
 970         }, {
 971                 .clk            = {
 972                         .name           = "sclk_pwi",
 973                         .enable         = s5pv210_clk_mask0_ctrl,
 974                         .ctrlbit        = (1 << 29),
 975                 },
 976                 .sources = &clkset_group2,
 977                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
 978                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
 979         }, {
 980                 .clk            = {
 981                         .name           = "sclk_pwm",
 982                         .enable         = s5pv210_clk_mask0_ctrl,
 983                         .ctrlbit        = (1 << 19),
 984                 },
 985                 .sources = &clkset_group2,
 986                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
 987                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
 988         },
 989 };
 990
 991 /* Clock initialisation code */
 992 static struct clksrc_clk *sysclks[] = {
 993         &clk_mout_apll,
 994         &clk_mout_epll,
 995         &clk_mout_mpll,
 996         &clk_armclk,
 997         &clk_hclk_msys,
 998         &clk_sclk_a2m,
 999         &clk_hclk_dsys,
1000         &clk_hclk_psys,
1001         &clk_pclk_msys,
1002         &clk_pclk_dsys,
1003         &clk_pclk_psys,
1004         &clk_vpllsrc,
1005         &clk_sclk_vpll,
1006         &clk_sclk_dac,
1007         &clk_sclk_pixel,
1008         &clk_sclk_hdmi,
1009         &clk_mout_dmc0,
1010         &clk_sclk_dmc0,
1011         &clk_sclk_audio0,
1012         &clk_sclk_audio1,
1013         &clk_sclk_audio2,
1014         &clk_sclk_spdif,
1015 };
1016
1017 static u32 epll_div[][6] = {
1018         {  48000000, 0, 48, 3, 3, 0 },
1019         {  96000000, 0, 48, 3, 2, 0 },
1020         { 144000000, 1, 72, 3, 2, 0 },
1021         { 192000000, 0, 48, 3, 1, 0 },
1022         { 288000000, 1, 72, 3, 1, 0 },
1023         {  32750000, 1, 65, 3, 4, 35127 },
1024         {  32768000, 1, 65, 3, 4, 35127 },
1025         {  45158400, 0, 45, 3, 3, 10355 },
1026         {  45000000, 0, 45, 3, 3, 10355 },
1027         {  45158000, 0, 45, 3, 3, 10355 },
1028         {  49125000, 0, 49, 3, 3, 9961 },
1029         {  49152000, 0, 49, 3, 3, 9961 },
1030         {  67737600, 1, 67, 3, 3, 48366 },
1031         {  67738000, 1, 67, 3, 3, 48366 },
1032         {  73800000, 1, 73, 3, 3, 47710 },
1033         {  73728000, 1, 73, 3, 3, 47710 },
1034         {  36000000, 1, 32, 3, 4, 0 },
1035         {  60000000, 1, 60, 3, 3, 0 },
1036         {  72000000, 1, 72, 3, 3, 0 },
1037         {  80000000, 1, 80, 3, 3, 0 },
1038         {  84000000, 0, 42, 3, 2, 0 },
1039         {  50000000, 0, 50, 3, 3, 0 },
1040 };
1041
1042 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1043 {
1044         unsigned int epll_con, epll_con_k;
1045         unsigned int i;
1046
1047         /* Return if nothing changed */
1048         if (clk->rate == rate)
1049                 return 0;
1050
1051         epll_con = __raw_readl(S5P_EPLL_CON);
1052         epll_con_k = __raw_readl(S5P_EPLL_CON1);
1053
1054         epll_con_k &= ~PLL46XX_KDIV_MASK;
1055         epll_con &= ~(1 << 27 |
1056                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1057                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1058                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1059
1060         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1061                 if (epll_div[i][0] == rate) {
1062                         epll_con_k |= epll_div[i][5] << 0;
1063                         epll_con |= (epll_div[i][1] << 27 |
1064                                         epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1065                                         epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1066                                         epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1067                         break;
1068                 }
1069         }
1070
1071         if (i == ARRAY_SIZE(epll_div)) {
1072                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1073                                 __func__);
1074                 return -EINVAL;
1075         }
1076
1077         __raw_writel(epll_con, S5P_EPLL_CON);
1078         __raw_writel(epll_con_k, S5P_EPLL_CON1);
1079
1080         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1081                         clk->rate, rate);
1082
1083         clk->rate = rate;
1084
1085         return 0;
1086 }
1087
1088 static struct clk_ops s5pv210_epll_ops = {
1089         .set_rate = s5pv210_epll_set_rate,
1090         .get_rate = s5p_epll_get_rate,
1091 };
1092
1093 void __init_or_cpufreq s5pv210_setup_clocks(void)
1094 {
1095         struct clk *xtal_clk;
1096         unsigned long vpllsrc;
1097         unsigned long armclk;
1098         unsigned long hclk_msys;
1099         unsigned long hclk_dsys;
1100         unsigned long hclk_psys;
1101         unsigned long pclk_msys;
1102         unsigned long pclk_dsys;
1103         unsigned long pclk_psys;
1104         unsigned long apll;
1105         unsigned long mpll;
1106         unsigned long epll;
1107         unsigned long vpll;
1108         unsigned int ptr;
1109         u32 clkdiv0, clkdiv1;
1110
1111         /* Set functions for clk_fout_epll */
1112         clk_fout_epll.enable = s5p_epll_enable;
1113         clk_fout_epll.ops = &s5pv210_epll_ops;
1114
1115         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1116
1117         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1118         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1119
1120         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1121                                 __func__, clkdiv0, clkdiv1);
1122
1123         xtal_clk = clk_get(NULL, "xtal");
1124         BUG_ON(IS_ERR(xtal_clk));
1125
1126         xtal = clk_get_rate(xtal_clk);
1127         clk_put(xtal_clk);
1128
1129         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1130
1131         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1132         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1133         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1134                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1135         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1136         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1137
1138         clk_fout_apll.ops = &clk_fout_apll_ops;
1139         clk_fout_mpll.rate = mpll;
1140         clk_fout_epll.rate = epll;
1141         clk_fout_vpll.rate = vpll;
1142
1143         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1144                         apll, mpll, epll, vpll);
1145
1146         armclk = clk_get_rate(&clk_armclk.clk);
1147         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1148         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1149         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1150         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1151         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1152         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1153
1154         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1155                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1156                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1157                         pclk_msys, pclk_dsys, pclk_psys);
1158
1159         clk_f.rate = armclk;
1160         clk_h.rate = hclk_psys;
1161         clk_p.rate = pclk_psys;
1162
1163         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1164                 s3c_set_clksrc(&clksrcs[ptr], true);
1165 }
1166
1167 static struct clk *clks[] __initdata = {
1168         &clk_sclk_hdmi27m,
1169         &clk_sclk_hdmiphy,
1170         &clk_sclk_usbphy0,
1171         &clk_sclk_usbphy1,
1172         &clk_pcmcdclk0,
1173         &clk_pcmcdclk1,
1174         &clk_pcmcdclk2,
1175 };
1176
1177 void __init s5pv210_register_clocks(void)
1178 {
1179         int ptr;
1180
1181         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1182
1183         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1184                 s3c_register_clksrc(sysclks[ptr], 1);
1185
1186         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1187         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1188
1189         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1190         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1191
1192         s3c_pwmclk_init();
1193 }