arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static unsigned long xtal;
  35
  36 static struct clksrc_clk clk_mout_apll = {
  37         .clk    = {
  38                 .name           = "mout_apll",
  39                 .id             = -1,
  40         },
  41         .sources        = &clk_src_apll,
  42         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  43 };
  44
  45 static struct clksrc_clk clk_mout_epll = {
  46         .clk    = {
  47                 .name           = "mout_epll",
  48                 .id             = -1,
  49         },
  50         .sources        = &clk_src_epll,
  51         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  52 };
  53
  54 static struct clksrc_clk clk_mout_mpll = {
  55         .clk = {
  56                 .name           = "mout_mpll",
  57                 .id             = -1,
  58         },
  59         .sources        = &clk_src_mpll,
  60         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  61 };
  62
  63 static struct clk *clkset_armclk_list[] = {
  64         [0] = &clk_mout_apll.clk,
  65         [1] = &clk_mout_mpll.clk,
  66 };
  67
  68 static struct clksrc_sources clkset_armclk = {
  69         .sources        = clkset_armclk_list,
  70         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  71 };
  72
  73 static struct clksrc_clk clk_armclk = {
  74         .clk    = {
  75                 .name           = "armclk",
  76                 .id             = -1,
  77         },
  78         .sources        = &clkset_armclk,
  79         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  80         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  81 };
  82
  83 static struct clksrc_clk clk_hclk_msys = {
  84         .clk    = {
  85                 .name           = "hclk_msys",
  86                 .id             = -1,
  87                 .parent         = &clk_armclk.clk,
  88         },
  89         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  90 };
  91
  92 static struct clksrc_clk clk_pclk_msys = {
  93         .clk    = {
  94                 .name           = "pclk_msys",
  95                 .id             = -1,
  96                 .parent         = &clk_hclk_msys.clk,
  97         },
  98         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  99 };
 100
 101 static struct clksrc_clk clk_sclk_a2m = {
 102         .clk    = {
 103                 .name           = "sclk_a2m",
 104                 .id             = -1,
 105                 .parent         = &clk_mout_apll.clk,
 106         },
 107         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 108 };
 109
 110 static struct clk *clkset_hclk_sys_list[] = {
 111         [0] = &clk_mout_mpll.clk,
 112         [1] = &clk_sclk_a2m.clk,
 113 };
 114
 115 static struct clksrc_sources clkset_hclk_sys = {
 116         .sources        = clkset_hclk_sys_list,
 117         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 118 };
 119
 120 static struct clksrc_clk clk_hclk_dsys = {
 121         .clk    = {
 122                 .name   = "hclk_dsys",
 123                 .id     = -1,
 124         },
 125         .sources        = &clkset_hclk_sys,
 126         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 127         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 128 };
 129
 130 static struct clksrc_clk clk_pclk_dsys = {
 131         .clk    = {
 132                 .name   = "pclk_dsys",
 133                 .id     = -1,
 134                 .parent = &clk_hclk_dsys.clk,
 135         },
 136         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 137 };
 138
 139 static struct clksrc_clk clk_hclk_psys = {
 140         .clk    = {
 141                 .name   = "hclk_psys",
 142                 .id     = -1,
 143         },
 144         .sources        = &clkset_hclk_sys,
 145         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 146         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 147 };
 148
 149 static struct clksrc_clk clk_pclk_psys = {
 150         .clk    = {
 151                 .name   = "pclk_psys",
 152                 .id     = -1,
 153                 .parent = &clk_hclk_psys.clk,
 154         },
 155         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 156 };
 157
 158 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 159 {
 160         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 161 }
 162
 163 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 164 {
 165         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 166 }
 167
 168 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 169 {
 170         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 171 }
 172
 173 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 174 {
 175         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 176 }
 177
 178 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 179 {
 180         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 181 }
 182
 183 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 184 {
 185         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 186 }
 187
 188 static struct clk clk_sclk_hdmi27m = {
 189         .name           = "sclk_hdmi27m",
 190         .id             = -1,
 191         .rate           = 27000000,
 192 };
 193
 194 static struct clk clk_sclk_hdmiphy = {
 195         .name           = "sclk_hdmiphy",
 196         .id             = -1,
 197 };
 198
 199 static struct clk clk_sclk_usbphy0 = {
 200         .name           = "sclk_usbphy0",
 201         .id             = -1,
 202 };
 203
 204 static struct clk clk_sclk_usbphy1 = {
 205         .name           = "sclk_usbphy1",
 206         .id             = -1,
 207 };
 208
 209 static struct clk clk_pcmcdclk0 = {
 210         .name           = "pcmcdclk",
 211         .id             = -1,
 212 };
 213
 214 static struct clk clk_pcmcdclk1 = {
 215         .name           = "pcmcdclk",
 216         .id             = -1,
 217 };
 218
 219 static struct clk clk_pcmcdclk2 = {
 220         .name           = "pcmcdclk",
 221         .id             = -1,
 222 };
 223
 224 static struct clk *clkset_vpllsrc_list[] = {
 225         [0] = &clk_fin_vpll,
 226         [1] = &clk_sclk_hdmi27m,
 227 };
 228
 229 static struct clksrc_sources clkset_vpllsrc = {
 230         .sources        = clkset_vpllsrc_list,
 231         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 232 };
 233
 234 static struct clksrc_clk clk_vpllsrc = {
 235         .clk    = {
 236                 .name           = "vpll_src",
 237                 .id             = -1,
 238                 .enable         = s5pv210_clk_mask0_ctrl,
 239                 .ctrlbit        = (1 << 7),
 240         },
 241         .sources        = &clkset_vpllsrc,
 242         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 243 };
 244
 245 static struct clk *clkset_sclk_vpll_list[] = {
 246         [0] = &clk_vpllsrc.clk,
 247         [1] = &clk_fout_vpll,
 248 };
 249
 250 static struct clksrc_sources clkset_sclk_vpll = {
 251         .sources        = clkset_sclk_vpll_list,
 252         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 253 };
 254
 255 static struct clksrc_clk clk_sclk_vpll = {
 256         .clk    = {
 257                 .name           = "sclk_vpll",
 258                 .id             = -1,
 259         },
 260         .sources        = &clkset_sclk_vpll,
 261         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 262 };
 263
 264 static struct clk *clkset_moutdmc0src_list[] = {
 265         [0] = &clk_sclk_a2m.clk,
 266         [1] = &clk_mout_mpll.clk,
 267         [2] = NULL,
 268         [3] = NULL,
 269 };
 270
 271 static struct clksrc_sources clkset_moutdmc0src = {
 272         .sources        = clkset_moutdmc0src_list,
 273         .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
 274 };
 275
 276 static struct clksrc_clk clk_mout_dmc0 = {
 277         .clk    = {
 278                 .name           = "mout_dmc0",
 279                 .id             = -1,
 280         },
 281         .sources        = &clkset_moutdmc0src,
 282         .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 283 };
 284
 285 static struct clksrc_clk clk_sclk_dmc0 = {
 286         .clk    = {
 287                 .name           = "sclk_dmc0",
 288                 .id             = -1,
 289                 .parent         = &clk_mout_dmc0.clk,
 290         },
 291         .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 292 };
 293
 294 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 295 {
 296         return clk_get_rate(clk->parent) / 2;
 297 }
 298
 299 static struct clk_ops clk_hclk_imem_ops = {
 300         .get_rate       = s5pv210_clk_imem_get_rate,
 301 };
 302
 303 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
 304 {
 305         return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 306 }
 307
 308 static struct clk_ops clk_fout_apll_ops = {
 309         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 310 };
 311
 312 static struct clk init_clocks_disable[] = {
 313         {
 314                 .name           = "rot",
 315                 .id             = -1,
 316                 .parent         = &clk_hclk_dsys.clk,
 317                 .enable         = s5pv210_clk_ip0_ctrl,
 318                 .ctrlbit        = (1<<29),
 319         }, {
 320                 .name           = "fimc",
 321                 .id             = 0,
 322                 .parent         = &clk_hclk_dsys.clk,
 323                 .enable         = s5pv210_clk_ip0_ctrl,
 324                 .ctrlbit        = (1 << 24),
 325         }, {
 326                 .name           = "fimc",
 327                 .id             = 1,
 328                 .parent         = &clk_hclk_dsys.clk,
 329                 .enable         = s5pv210_clk_ip0_ctrl,
 330                 .ctrlbit        = (1 << 25),
 331         }, {
 332                 .name           = "fimc",
 333                 .id             = 2,
 334                 .parent         = &clk_hclk_dsys.clk,
 335                 .enable         = s5pv210_clk_ip0_ctrl,
 336                 .ctrlbit        = (1 << 26),
 337         }, {
 338                 .name           = "otg",
 339                 .id             = -1,
 340                 .parent         = &clk_hclk_psys.clk,
 341                 .enable         = s5pv210_clk_ip1_ctrl,
 342                 .ctrlbit        = (1<<16),
 343         }, {
 344                 .name           = "usb-host",
 345                 .id             = -1,
 346                 .parent         = &clk_hclk_psys.clk,
 347                 .enable         = s5pv210_clk_ip1_ctrl,
 348                 .ctrlbit        = (1<<17),
 349         }, {
 350                 .name           = "lcd",
 351                 .id             = -1,
 352                 .parent         = &clk_hclk_dsys.clk,
 353                 .enable         = s5pv210_clk_ip1_ctrl,
 354                 .ctrlbit        = (1<<0),
 355         }, {
 356                 .name           = "cfcon",
 357                 .id             = 0,
 358                 .parent         = &clk_hclk_psys.clk,
 359                 .enable         = s5pv210_clk_ip1_ctrl,
 360                 .ctrlbit        = (1<<25),
 361         }, {
 362                 .name           = "hsmmc",
 363                 .id             = 0,
 364                 .parent         = &clk_hclk_psys.clk,
 365                 .enable         = s5pv210_clk_ip2_ctrl,
 366                 .ctrlbit        = (1<<16),
 367         }, {
 368                 .name           = "hsmmc",
 369                 .id             = 1,
 370                 .parent         = &clk_hclk_psys.clk,
 371                 .enable         = s5pv210_clk_ip2_ctrl,
 372                 .ctrlbit        = (1<<17),
 373         }, {
 374                 .name           = "hsmmc",
 375                 .id             = 2,
 376                 .parent         = &clk_hclk_psys.clk,
 377                 .enable         = s5pv210_clk_ip2_ctrl,
 378                 .ctrlbit        = (1<<18),
 379         }, {
 380                 .name           = "hsmmc",
 381                 .id             = 3,
 382                 .parent         = &clk_hclk_psys.clk,
 383                 .enable         = s5pv210_clk_ip2_ctrl,
 384                 .ctrlbit        = (1<<19),
 385         }, {
 386                 .name           = "systimer",
 387                 .id             = -1,
 388                 .parent         = &clk_pclk_psys.clk,
 389                 .enable         = s5pv210_clk_ip3_ctrl,
 390                 .ctrlbit        = (1<<16),
 391         }, {
 392                 .name           = "watchdog",
 393                 .id             = -1,
 394                 .parent         = &clk_pclk_psys.clk,
 395                 .enable         = s5pv210_clk_ip3_ctrl,
 396                 .ctrlbit        = (1<<22),
 397         }, {
 398                 .name           = "rtc",
 399                 .id             = -1,
 400                 .parent         = &clk_pclk_psys.clk,
 401                 .enable         = s5pv210_clk_ip3_ctrl,
 402                 .ctrlbit        = (1<<15),
 403         }, {
 404                 .name           = "i2c",
 405                 .id             = 0,
 406                 .parent         = &clk_pclk_psys.clk,
 407                 .enable         = s5pv210_clk_ip3_ctrl,
 408                 .ctrlbit        = (1<<7),
 409         }, {
 410                 .name           = "i2c",
 411                 .id             = 1,
 412                 .parent         = &clk_pclk_psys.clk,
 413                 .enable         = s5pv210_clk_ip3_ctrl,
 414                 .ctrlbit        = (1 << 10),
 415         }, {
 416                 .name           = "i2c",
 417                 .id             = 2,
 418                 .parent         = &clk_pclk_psys.clk,
 419                 .enable         = s5pv210_clk_ip3_ctrl,
 420                 .ctrlbit        = (1<<9),
 421         }, {
 422                 .name           = "spi",
 423                 .id             = 0,
 424                 .parent         = &clk_pclk_psys.clk,
 425                 .enable         = s5pv210_clk_ip3_ctrl,
 426                 .ctrlbit        = (1<<12),
 427         }, {
 428                 .name           = "spi",
 429                 .id             = 1,
 430                 .parent         = &clk_pclk_psys.clk,
 431                 .enable         = s5pv210_clk_ip3_ctrl,
 432                 .ctrlbit        = (1<<13),
 433         }, {
 434                 .name           = "spi",
 435                 .id             = 2,
 436                 .parent         = &clk_pclk_psys.clk,
 437                 .enable         = s5pv210_clk_ip3_ctrl,
 438                 .ctrlbit        = (1<<14),
 439         }, {
 440                 .name           = "timers",
 441                 .id             = -1,
 442                 .parent         = &clk_pclk_psys.clk,
 443                 .enable         = s5pv210_clk_ip3_ctrl,
 444                 .ctrlbit        = (1<<23),
 445         }, {
 446                 .name           = "adc",
 447                 .id             = -1,
 448                 .parent         = &clk_pclk_psys.clk,
 449                 .enable         = s5pv210_clk_ip3_ctrl,
 450                 .ctrlbit        = (1<<24),
 451         }, {
 452                 .name           = "keypad",
 453                 .id             = -1,
 454                 .parent         = &clk_pclk_psys.clk,
 455                 .enable         = s5pv210_clk_ip3_ctrl,
 456                 .ctrlbit        = (1<<21),
 457         }, {
 458                 .name           = "i2s_v50",
 459                 .id             = 0,
 460                 .parent         = &clk_p,
 461                 .enable         = s5pv210_clk_ip3_ctrl,
 462                 .ctrlbit        = (1<<4),
 463         }, {
 464                 .name           = "i2s_v32",
 465                 .id             = 0,
 466                 .parent         = &clk_p,
 467                 .enable         = s5pv210_clk_ip3_ctrl,
 468                 .ctrlbit        = (1 << 5),
 469         }, {
 470                 .name           = "i2s_v32",
 471                 .id             = 1,
 472                 .parent         = &clk_p,
 473                 .enable         = s5pv210_clk_ip3_ctrl,
 474                 .ctrlbit        = (1 << 6),
 475         }, {
 476                 .name           = "spdif",
 477                 .id             = -1,
 478                 .parent         = &clk_p,
 479                 .enable         = s5pv210_clk_ip3_ctrl,
 480                 .ctrlbit        = (1 << 0),
 481         },
 482 };
 483
 484 static struct clk init_clocks[] = {
 485         {
 486                 .name           = "hclk_imem",
 487                 .id             = -1,
 488                 .parent         = &clk_hclk_msys.clk,
 489                 .ctrlbit        = (1 << 5),
 490                 .enable         = s5pv210_clk_ip0_ctrl,
 491                 .ops            = &clk_hclk_imem_ops,
 492         }, {
 493                 .name           = "uart",
 494                 .id             = 0,
 495                 .parent         = &clk_pclk_psys.clk,
 496                 .enable         = s5pv210_clk_ip3_ctrl,
 497                 .ctrlbit        = (1 << 17),
 498         }, {
 499                 .name           = "uart",
 500                 .id             = 1,
 501                 .parent         = &clk_pclk_psys.clk,
 502                 .enable         = s5pv210_clk_ip3_ctrl,
 503                 .ctrlbit        = (1 << 18),
 504         }, {
 505                 .name           = "uart",
 506                 .id             = 2,
 507                 .parent         = &clk_pclk_psys.clk,
 508                 .enable         = s5pv210_clk_ip3_ctrl,
 509                 .ctrlbit        = (1 << 19),
 510         }, {
 511                 .name           = "uart",
 512                 .id             = 3,
 513                 .parent         = &clk_pclk_psys.clk,
 514                 .enable         = s5pv210_clk_ip3_ctrl,
 515                 .ctrlbit        = (1 << 20),
 516         },
 517 };
 518
 519 static struct clk *clkset_uart_list[] = {
 520         [6] = &clk_mout_mpll.clk,
 521         [7] = &clk_mout_epll.clk,
 522 };
 523
 524 static struct clksrc_sources clkset_uart = {
 525         .sources        = clkset_uart_list,
 526         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 527 };
 528
 529 static struct clk *clkset_group1_list[] = {
 530         [0] = &clk_sclk_a2m.clk,
 531         [1] = &clk_mout_mpll.clk,
 532         [2] = &clk_mout_epll.clk,
 533         [3] = &clk_sclk_vpll.clk,
 534 };
 535
 536 static struct clksrc_sources clkset_group1 = {
 537         .sources        = clkset_group1_list,
 538         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 539 };
 540
 541 static struct clk *clkset_sclk_onenand_list[] = {
 542         [0] = &clk_hclk_psys.clk,
 543         [1] = &clk_hclk_dsys.clk,
 544 };
 545
 546 static struct clksrc_sources clkset_sclk_onenand = {
 547         .sources        = clkset_sclk_onenand_list,
 548         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 549 };
 550
 551 static struct clk *clkset_sclk_dac_list[] = {
 552         [0] = &clk_sclk_vpll.clk,
 553         [1] = &clk_sclk_hdmiphy,
 554 };
 555
 556 static struct clksrc_sources clkset_sclk_dac = {
 557         .sources        = clkset_sclk_dac_list,
 558         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 559 };
 560
 561 static struct clksrc_clk clk_sclk_dac = {
 562         .clk            = {
 563                 .name           = "sclk_dac",
 564                 .id             = -1,
 565                 .enable         = s5pv210_clk_mask0_ctrl,
 566                 .ctrlbit        = (1 << 2),
 567         },
 568         .sources        = &clkset_sclk_dac,
 569         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 570 };
 571
 572 static struct clksrc_clk clk_sclk_pixel = {
 573         .clk            = {
 574                 .name           = "sclk_pixel",
 575                 .id             = -1,
 576                 .parent         = &clk_sclk_vpll.clk,
 577         },
 578         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 579 };
 580
 581 static struct clk *clkset_sclk_hdmi_list[] = {
 582         [0] = &clk_sclk_pixel.clk,
 583         [1] = &clk_sclk_hdmiphy,
 584 };
 585
 586 static struct clksrc_sources clkset_sclk_hdmi = {
 587         .sources        = clkset_sclk_hdmi_list,
 588         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 589 };
 590
 591 static struct clksrc_clk clk_sclk_hdmi = {
 592         .clk            = {
 593                 .name           = "sclk_hdmi",
 594                 .id             = -1,
 595                 .enable         = s5pv210_clk_mask0_ctrl,
 596                 .ctrlbit        = (1 << 0),
 597         },
 598         .sources        = &clkset_sclk_hdmi,
 599         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 600 };
 601
 602 static struct clk *clkset_sclk_mixer_list[] = {
 603         [0] = &clk_sclk_dac.clk,
 604         [1] = &clk_sclk_hdmi.clk,
 605 };
 606
 607 static struct clksrc_sources clkset_sclk_mixer = {
 608         .sources        = clkset_sclk_mixer_list,
 609         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 610 };
 611
 612 static struct clk *clkset_sclk_audio0_list[] = {
 613         [0] = &clk_ext_xtal_mux,
 614         [1] = &clk_pcmcdclk0,
 615         [2] = &clk_sclk_hdmi27m,
 616         [3] = &clk_sclk_usbphy0,
 617         [4] = &clk_sclk_usbphy1,
 618         [5] = &clk_sclk_hdmiphy,
 619         [6] = &clk_mout_mpll.clk,
 620         [7] = &clk_mout_epll.clk,
 621         [8] = &clk_sclk_vpll.clk,
 622 };
 623
 624 static struct clksrc_sources clkset_sclk_audio0 = {
 625         .sources        = clkset_sclk_audio0_list,
 626         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 627 };
 628
 629 static struct clksrc_clk clk_sclk_audio0 = {
 630         .clk            = {
 631                 .name           = "sclk_audio",
 632                 .id             = 0,
 633                 .enable         = s5pv210_clk_mask0_ctrl,
 634                 .ctrlbit        = (1 << 24),
 635         },
 636         .sources = &clkset_sclk_audio0,
 637         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 638         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 639 };
 640
 641 static struct clk *clkset_sclk_audio1_list[] = {
 642         [0] = &clk_ext_xtal_mux,
 643         [1] = &clk_pcmcdclk1,
 644         [2] = &clk_sclk_hdmi27m,
 645         [3] = &clk_sclk_usbphy0,
 646         [4] = &clk_sclk_usbphy1,
 647         [5] = &clk_sclk_hdmiphy,
 648         [6] = &clk_mout_mpll.clk,
 649         [7] = &clk_mout_epll.clk,
 650         [8] = &clk_sclk_vpll.clk,
 651 };
 652
 653 static struct clksrc_sources clkset_sclk_audio1 = {
 654         .sources        = clkset_sclk_audio1_list,
 655         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 656 };
 657
 658 static struct clksrc_clk clk_sclk_audio1 = {
 659         .clk            = {
 660                 .name           = "sclk_audio",
 661                 .id             = 1,
 662                 .enable         = s5pv210_clk_mask0_ctrl,
 663                 .ctrlbit        = (1 << 25),
 664         },
 665         .sources = &clkset_sclk_audio1,
 666         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 667         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 668 };
 669
 670 static struct clk *clkset_sclk_audio2_list[] = {
 671         [0] = &clk_ext_xtal_mux,
 672         [1] = &clk_pcmcdclk0,
 673         [2] = &clk_sclk_hdmi27m,
 674         [3] = &clk_sclk_usbphy0,
 675         [4] = &clk_sclk_usbphy1,
 676         [5] = &clk_sclk_hdmiphy,
 677         [6] = &clk_mout_mpll.clk,
 678         [7] = &clk_mout_epll.clk,
 679         [8] = &clk_sclk_vpll.clk,
 680 };
 681
 682 static struct clksrc_sources clkset_sclk_audio2 = {
 683         .sources        = clkset_sclk_audio2_list,
 684         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 685 };
 686
 687 static struct clksrc_clk clk_sclk_audio2 = {
 688         .clk            = {
 689                 .name           = "sclk_audio",
 690                 .id             = 2,
 691                 .enable         = s5pv210_clk_mask0_ctrl,
 692                 .ctrlbit        = (1 << 26),
 693         },
 694         .sources = &clkset_sclk_audio2,
 695         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 696         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 697 };
 698
 699 static struct clk *clkset_sclk_spdif_list[] = {
 700         [0] = &clk_sclk_audio0.clk,
 701         [1] = &clk_sclk_audio1.clk,
 702         [2] = &clk_sclk_audio2.clk,
 703 };
 704
 705 static struct clksrc_sources clkset_sclk_spdif = {
 706         .sources        = clkset_sclk_spdif_list,
 707         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 708 };
 709
 710 static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
 711 {
 712         struct clk *pclk;
 713         int ret;
 714
 715         pclk = clk_get_parent(clk);
 716         if (IS_ERR(pclk))
 717                 return -EINVAL;
 718
 719         ret = pclk->ops->set_rate(pclk, rate);
 720         clk_put(pclk);
 721
 722         return ret;
 723 }
 724
 725 static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
 726 {
 727         struct clk *pclk;
 728         int rate;
 729
 730         pclk = clk_get_parent(clk);
 731         if (IS_ERR(pclk))
 732                 return -EINVAL;
 733
 734         rate = pclk->ops->get_rate(clk);
 735         clk_put(pclk);
 736
 737         return rate;
 738 }
 739
 740 static struct clk_ops s5pv210_sclk_spdif_ops = {
 741         .set_rate       = s5pv210_spdif_set_rate,
 742         .get_rate       = s5pv210_spdif_get_rate,
 743 };
 744
 745 static struct clksrc_clk clk_sclk_spdif = {
 746         .clk            = {
 747                 .name           = "sclk_spdif",
 748                 .id             = -1,
 749                 .enable         = s5pv210_clk_mask0_ctrl,
 750                 .ctrlbit        = (1 << 27),
 751                 .ops            = &s5pv210_sclk_spdif_ops,
 752         },
 753         .sources = &clkset_sclk_spdif,
 754         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 755 };
 756
 757 static struct clk *clkset_group2_list[] = {
 758         [0] = &clk_ext_xtal_mux,
 759         [1] = &clk_xusbxti,
 760         [2] = &clk_sclk_hdmi27m,
 761         [3] = &clk_sclk_usbphy0,
 762         [4] = &clk_sclk_usbphy1,
 763         [5] = &clk_sclk_hdmiphy,
 764         [6] = &clk_mout_mpll.clk,
 765         [7] = &clk_mout_epll.clk,
 766         [8] = &clk_sclk_vpll.clk,
 767 };
 768
 769 static struct clksrc_sources clkset_group2 = {
 770         .sources        = clkset_group2_list,
 771         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 772 };
 773
 774 static struct clksrc_clk clksrcs[] = {
 775         {
 776                 .clk    = {
 777                         .name           = "sclk_dmc",
 778                         .id             = -1,
 779                 },
 780                 .sources = &clkset_group1,
 781                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 782                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 783         }, {
 784                 .clk    = {
 785                         .name           = "sclk_onenand",
 786                         .id             = -1,
 787                 },
 788                 .sources = &clkset_sclk_onenand,
 789                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 790                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 791         }, {
 792                 .clk    = {
 793                         .name           = "uclk1",
 794                         .id             = 0,
 795                         .enable         = s5pv210_clk_mask0_ctrl,
 796                         .ctrlbit        = (1 << 12),
 797                 },
 798                 .sources = &clkset_uart,
 799                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 800                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 801         }, {
 802                 .clk            = {
 803                         .name           = "uclk1",
 804                         .id             = 1,
 805                         .enable         = s5pv210_clk_mask0_ctrl,
 806                         .ctrlbit        = (1 << 13),
 807                 },
 808                 .sources = &clkset_uart,
 809                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
 810                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 811         }, {
 812                 .clk            = {
 813                         .name           = "uclk1",
 814                         .id             = 2,
 815                         .enable         = s5pv210_clk_mask0_ctrl,
 816                         .ctrlbit        = (1 << 14),
 817                 },
 818                 .sources = &clkset_uart,
 819                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
 820                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
 821         }, {
 822                 .clk            = {
 823                         .name           = "uclk1",
 824                         .id             = 3,
 825                         .enable         = s5pv210_clk_mask0_ctrl,
 826                         .ctrlbit        = (1 << 15),
 827                 },
 828                 .sources = &clkset_uart,
 829                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
 830                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 831         }, {
 832                 .clk    = {
 833                         .name           = "sclk_mixer",
 834                         .id             = -1,
 835                         .enable         = s5pv210_clk_mask0_ctrl,
 836                         .ctrlbit        = (1 << 1),
 837                 },
 838                 .sources = &clkset_sclk_mixer,
 839                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 840         }, {
 841                 .clk    = {
 842                         .name           = "sclk_fimc",
 843                         .id             = 0,
 844                         .enable         = s5pv210_clk_mask1_ctrl,
 845                         .ctrlbit        = (1 << 2),
 846                 },
 847                 .sources = &clkset_group2,
 848                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 849                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 850         }, {
 851                 .clk    = {
 852                         .name           = "sclk_fimc",
 853                         .id             = 1,
 854                         .enable         = s5pv210_clk_mask1_ctrl,
 855                         .ctrlbit        = (1 << 3),
 856                 },
 857                 .sources = &clkset_group2,
 858                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 859                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 860         }, {
 861                 .clk    = {
 862                         .name           = "sclk_fimc",
 863                         .id             = 2,
 864                         .enable         = s5pv210_clk_mask1_ctrl,
 865                         .ctrlbit        = (1 << 4),
 866                 },
 867                 .sources = &clkset_group2,
 868                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 869                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 870         }, {
 871                 .clk            = {
 872                         .name           = "sclk_cam",
 873                         .id             = 0,
 874                         .enable         = s5pv210_clk_mask0_ctrl,
 875                         .ctrlbit        = (1 << 3),
 876                 },
 877                 .sources = &clkset_group2,
 878                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 879                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 880         }, {
 881                 .clk            = {
 882                         .name           = "sclk_cam",
 883                         .id             = 1,
 884                         .enable         = s5pv210_clk_mask0_ctrl,
 885                         .ctrlbit        = (1 << 4),
 886                 },
 887                 .sources = &clkset_group2,
 888                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 889                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 890         }, {
 891                 .clk            = {
 892                         .name           = "sclk_fimd",
 893                         .id             = -1,
 894                         .enable         = s5pv210_clk_mask0_ctrl,
 895                         .ctrlbit        = (1 << 5),
 896                 },
 897                 .sources = &clkset_group2,
 898                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 899                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 900         }, {
 901                 .clk            = {
 902                         .name           = "sclk_mmc",
 903                         .id             = 0,
 904                         .enable         = s5pv210_clk_mask0_ctrl,
 905                         .ctrlbit        = (1 << 8),
 906                 },
 907                 .sources = &clkset_group2,
 908                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 909                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 910         }, {
 911                 .clk            = {
 912                         .name           = "sclk_mmc",
 913                         .id             = 1,
 914                         .enable         = s5pv210_clk_mask0_ctrl,
 915                         .ctrlbit        = (1 << 9),
 916                 },
 917                 .sources = &clkset_group2,
 918                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 919                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 920         }, {
 921                 .clk            = {
 922                         .name           = "sclk_mmc",
 923                         .id             = 2,
 924                         .enable         = s5pv210_clk_mask0_ctrl,
 925                         .ctrlbit        = (1 << 10),
 926                 },
 927                 .sources = &clkset_group2,
 928                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 929                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 930         }, {
 931                 .clk            = {
 932                         .name           = "sclk_mmc",
 933                         .id             = 3,
 934                         .enable         = s5pv210_clk_mask0_ctrl,
 935                         .ctrlbit        = (1 << 11),
 936                 },
 937                 .sources = &clkset_group2,
 938                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 939                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 940         }, {
 941                 .clk            = {
 942                         .name           = "sclk_mfc",
 943                         .id             = -1,
 944                         .enable         = s5pv210_clk_ip0_ctrl,
 945                         .ctrlbit        = (1 << 16),
 946                 },
 947                 .sources = &clkset_group1,
 948                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 949                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 950         }, {
 951                 .clk            = {
 952                         .name           = "sclk_g2d",
 953                         .id             = -1,
 954                         .enable         = s5pv210_clk_ip0_ctrl,
 955                         .ctrlbit        = (1 << 12),
 956                 },
 957                 .sources = &clkset_group1,
 958                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 959                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 960         }, {
 961                 .clk            = {
 962                         .name           = "sclk_g3d",
 963                         .id             = -1,
 964                         .enable         = s5pv210_clk_ip0_ctrl,
 965                         .ctrlbit        = (1 << 8),
 966                 },
 967                 .sources = &clkset_group1,
 968                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 969                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 970         }, {
 971                 .clk            = {
 972                         .name           = "sclk_csis",
 973                         .id             = -1,
 974                         .enable         = s5pv210_clk_mask0_ctrl,
 975                         .ctrlbit        = (1 << 6),
 976                 },
 977                 .sources = &clkset_group2,
 978                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 979                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 980         }, {
 981                 .clk            = {
 982                         .name           = "sclk_spi",
 983                         .id             = 0,
 984                         .enable         = s5pv210_clk_mask0_ctrl,
 985                         .ctrlbit        = (1 << 16),
 986                 },
 987                 .sources = &clkset_group2,
 988                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
 989                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
 990         }, {
 991                 .clk            = {
 992                         .name           = "sclk_spi",
 993                         .id             = 1,
 994                         .enable         = s5pv210_clk_mask0_ctrl,
 995                         .ctrlbit        = (1 << 17),
 996                 },
 997                 .sources = &clkset_group2,
 998                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
 999                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
1000         }, {
1001                 .clk            = {
1002                         .name           = "sclk_pwi",
1003                         .id             = -1,
1004                         .enable         = s5pv210_clk_mask0_ctrl,
1005                         .ctrlbit        = (1 << 29),
1006                 },
1007                 .sources = &clkset_group2,
1008                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
1009                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
1010         }, {
1011                 .clk            = {
1012                         .name           = "sclk_pwm",
1013                         .id             = -1,
1014                         .enable         = s5pv210_clk_mask0_ctrl,
1015                         .ctrlbit        = (1 << 19),
1016                 },
1017                 .sources = &clkset_group2,
1018                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
1019                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
1020         },
1021 };
1022
1023 /* Clock initialisation code */
1024 static struct clksrc_clk *sysclks[] = {
1025         &clk_mout_apll,
1026         &clk_mout_epll,
1027         &clk_mout_mpll,
1028         &clk_armclk,
1029         &clk_hclk_msys,
1030         &clk_sclk_a2m,
1031         &clk_hclk_dsys,
1032         &clk_hclk_psys,
1033         &clk_pclk_msys,
1034         &clk_pclk_dsys,
1035         &clk_pclk_psys,
1036         &clk_vpllsrc,
1037         &clk_sclk_vpll,
1038         &clk_sclk_dac,
1039         &clk_sclk_pixel,
1040         &clk_sclk_hdmi,
1041         &clk_mout_dmc0,
1042         &clk_sclk_dmc0,
1043         &clk_sclk_audio0,
1044         &clk_sclk_audio1,
1045         &clk_sclk_audio2,
1046         &clk_sclk_spdif,
1047 };
1048
1049 static u32 epll_div[][6] = {
1050         {  48000000, 0, 48, 3, 3, 0 },
1051         {  96000000, 0, 48, 3, 2, 0 },
1052         { 144000000, 1, 72, 3, 2, 0 },
1053         { 192000000, 0, 48, 3, 1, 0 },
1054         { 288000000, 1, 72, 3, 1, 0 },
1055         {  32750000, 1, 65, 3, 4, 35127 },
1056         {  32768000, 1, 65, 3, 4, 35127 },
1057         {  45158400, 0, 45, 3, 3, 10355 },
1058         {  45000000, 0, 45, 3, 3, 10355 },
1059         {  45158000, 0, 45, 3, 3, 10355 },
1060         {  49125000, 0, 49, 3, 3, 9961 },
1061         {  49152000, 0, 49, 3, 3, 9961 },
1062         {  67737600, 1, 67, 3, 3, 48366 },
1063         {  67738000, 1, 67, 3, 3, 48366 },
1064         {  73800000, 1, 73, 3, 3, 47710 },
1065         {  73728000, 1, 73, 3, 3, 47710 },
1066         {  36000000, 1, 32, 3, 4, 0 },
1067         {  60000000, 1, 60, 3, 3, 0 },
1068         {  72000000, 1, 72, 3, 3, 0 },
1069         {  80000000, 1, 80, 3, 3, 0 },
1070         {  84000000, 0, 42, 3, 2, 0 },
1071         {  50000000, 0, 50, 3, 3, 0 },
1072 };
1073
1074 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1075 {
1076         unsigned int epll_con, epll_con_k;
1077         unsigned int i;
1078
1079         /* Return if nothing changed */
1080         if (clk->rate == rate)
1081                 return 0;
1082
1083         epll_con = __raw_readl(S5P_EPLL_CON);
1084         epll_con_k = __raw_readl(S5P_EPLL_CON1);
1085
1086         epll_con_k &= ~PLL46XX_KDIV_MASK;
1087         epll_con &= ~(1 << 27 |
1088                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1089                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1090                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1091
1092         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1093                 if (epll_div[i][0] == rate) {
1094                         epll_con_k |= epll_div[i][5] << 0;
1095                         epll_con |= (epll_div[i][1] << 27 |
1096                                         epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1097                                         epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1098                                         epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1099                         break;
1100                 }
1101         }
1102
1103         if (i == ARRAY_SIZE(epll_div)) {
1104                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1105                                 __func__);
1106                 return -EINVAL;
1107         }
1108
1109         __raw_writel(epll_con, S5P_EPLL_CON);
1110         __raw_writel(epll_con_k, S5P_EPLL_CON1);
1111
1112         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1113                         clk->rate, rate);
1114
1115         clk->rate = rate;
1116
1117         return 0;
1118 }
1119
1120 static struct clk_ops s5pv210_epll_ops = {
1121         .set_rate = s5pv210_epll_set_rate,
1122         .get_rate = s5p_epll_get_rate,
1123 };
1124
1125 void __init_or_cpufreq s5pv210_setup_clocks(void)
1126 {
1127         struct clk *xtal_clk;
1128         unsigned long vpllsrc;
1129         unsigned long armclk;
1130         unsigned long hclk_msys;
1131         unsigned long hclk_dsys;
1132         unsigned long hclk_psys;
1133         unsigned long pclk_msys;
1134         unsigned long pclk_dsys;
1135         unsigned long pclk_psys;
1136         unsigned long apll;
1137         unsigned long mpll;
1138         unsigned long epll;
1139         unsigned long vpll;
1140         unsigned int ptr;
1141         u32 clkdiv0, clkdiv1;
1142
1143         /* Set functions for clk_fout_epll */
1144         clk_fout_epll.enable = s5p_epll_enable;
1145         clk_fout_epll.ops = &s5pv210_epll_ops;
1146
1147         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1148
1149         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1150         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1151
1152         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1153                                 __func__, clkdiv0, clkdiv1);
1154
1155         xtal_clk = clk_get(NULL, "xtal");
1156         BUG_ON(IS_ERR(xtal_clk));
1157
1158         xtal = clk_get_rate(xtal_clk);
1159         clk_put(xtal_clk);
1160
1161         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1162
1163         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1164         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1165         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1166                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1167         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1168         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1169
1170         clk_fout_apll.ops = &clk_fout_apll_ops;
1171         clk_fout_mpll.rate = mpll;
1172         clk_fout_epll.rate = epll;
1173         clk_fout_vpll.rate = vpll;
1174
1175         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1176                         apll, mpll, epll, vpll);
1177
1178         armclk = clk_get_rate(&clk_armclk.clk);
1179         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1180         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1181         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1182         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1183         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1184         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1185
1186         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1187                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1188                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1189                         pclk_msys, pclk_dsys, pclk_psys);
1190
1191         clk_f.rate = armclk;
1192         clk_h.rate = hclk_psys;
1193         clk_p.rate = pclk_psys;
1194
1195         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1196                 s3c_set_clksrc(&clksrcs[ptr], true);
1197 }
1198
1199 static struct clk *clks[] __initdata = {
1200         &clk_sclk_hdmi27m,
1201         &clk_sclk_hdmiphy,
1202         &clk_sclk_usbphy0,
1203         &clk_sclk_usbphy1,
1204         &clk_pcmcdclk0,
1205         &clk_pcmcdclk1,
1206         &clk_pcmcdclk2,
1207 };
1208
1209 void __init s5pv210_register_clocks(void)
1210 {
1211         struct clk *clkp;
1212         int ret;
1213         int ptr;
1214
1215         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1216         if (ret > 0)
1217                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1218
1219         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1220                 s3c_register_clksrc(sysclks[ptr], 1);
1221
1222         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1223         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1224
1225         clkp = init_clocks_disable;
1226         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1227                 ret = s3c24xx_register_clock(clkp);
1228                 if (ret < 0) {
1229                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
1230                                clkp->name, ret);
1231                 }
1232                 (clkp->enable)(clkp, 0);
1233         }
1234
1235         s3c_pwmclk_init();
1236 }