1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static unsigned long xtal;
36 static struct clksrc_clk clk_mout_apll = {
40 .sources = &clk_src_apll,
41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
44 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
56 .sources = &clk_src_mpll,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
60 static struct clk *clkset_armclk_list[] = {
61 [0] = &clk_mout_apll.clk,
62 [1] = &clk_mout_mpll.clk,
65 static struct clksrc_sources clkset_armclk = {
66 .sources = clkset_armclk_list,
67 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
70 static struct clksrc_clk clk_armclk = {
74 .sources = &clkset_armclk,
75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
76 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
79 static struct clksrc_clk clk_hclk_msys = {
82 .parent = &clk_armclk.clk,
84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
87 static struct clksrc_clk clk_pclk_msys = {
90 .parent = &clk_hclk_msys.clk,
92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
95 static struct clksrc_clk clk_sclk_a2m = {
98 .parent = &clk_mout_apll.clk,
100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
103 static struct clk *clkset_hclk_sys_list[] = {
104 [0] = &clk_mout_mpll.clk,
105 [1] = &clk_sclk_a2m.clk,
108 static struct clksrc_sources clkset_hclk_sys = {
109 .sources = clkset_hclk_sys_list,
110 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
113 static struct clksrc_clk clk_hclk_dsys = {
117 .sources = &clkset_hclk_sys,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
122 static struct clksrc_clk clk_pclk_dsys = {
125 .parent = &clk_hclk_dsys.clk,
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
130 static struct clksrc_clk clk_hclk_psys = {
134 .sources = &clkset_hclk_sys,
135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
139 static struct clksrc_clk clk_pclk_psys = {
142 .parent = &clk_hclk_psys.clk,
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
147 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
149 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
152 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
154 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
157 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
159 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
162 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
164 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
167 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
169 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
172 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
174 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
177 static struct clk clk_sclk_hdmi27m = {
178 .name = "sclk_hdmi27m",
182 static struct clk clk_sclk_hdmiphy = {
183 .name = "sclk_hdmiphy",
186 static struct clk clk_sclk_usbphy0 = {
187 .name = "sclk_usbphy0",
190 static struct clk clk_sclk_usbphy1 = {
191 .name = "sclk_usbphy1",
194 static struct clk clk_pcmcdclk0 = {
198 static struct clk clk_pcmcdclk1 = {
202 static struct clk clk_pcmcdclk2 = {
206 static struct clk *clkset_vpllsrc_list[] = {
208 [1] = &clk_sclk_hdmi27m,
211 static struct clksrc_sources clkset_vpllsrc = {
212 .sources = clkset_vpllsrc_list,
213 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
216 static struct clksrc_clk clk_vpllsrc = {
219 .enable = s5pv210_clk_mask0_ctrl,
222 .sources = &clkset_vpllsrc,
223 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
226 static struct clk *clkset_sclk_vpll_list[] = {
227 [0] = &clk_vpllsrc.clk,
228 [1] = &clk_fout_vpll,
231 static struct clksrc_sources clkset_sclk_vpll = {
232 .sources = clkset_sclk_vpll_list,
233 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
236 static struct clksrc_clk clk_sclk_vpll = {
240 .sources = &clkset_sclk_vpll,
241 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
244 static struct clk *clkset_moutdmc0src_list[] = {
245 [0] = &clk_sclk_a2m.clk,
246 [1] = &clk_mout_mpll.clk,
251 static struct clksrc_sources clkset_moutdmc0src = {
252 .sources = clkset_moutdmc0src_list,
253 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
256 static struct clksrc_clk clk_mout_dmc0 = {
260 .sources = &clkset_moutdmc0src,
261 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
264 static struct clksrc_clk clk_sclk_dmc0 = {
267 .parent = &clk_mout_dmc0.clk,
269 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
272 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
274 return clk_get_rate(clk->parent) / 2;
277 static struct clk_ops clk_hclk_imem_ops = {
278 .get_rate = s5pv210_clk_imem_get_rate,
281 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
283 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
286 static struct clk_ops clk_fout_apll_ops = {
287 .get_rate = s5pv210_clk_fout_apll_get_rate,
290 static struct clk init_clocks_off[] = {
293 .devname = "s3c-pl330.0",
294 .parent = &clk_hclk_psys.clk,
295 .enable = s5pv210_clk_ip0_ctrl,
299 .devname = "s3c-pl330.1",
300 .parent = &clk_hclk_psys.clk,
301 .enable = s5pv210_clk_ip0_ctrl,
305 .parent = &clk_hclk_dsys.clk,
306 .enable = s5pv210_clk_ip0_ctrl,
310 .devname = "s5pv210-fimc.0",
311 .parent = &clk_hclk_dsys.clk,
312 .enable = s5pv210_clk_ip0_ctrl,
313 .ctrlbit = (1 << 24),
316 .devname = "s5pv210-fimc.1",
317 .parent = &clk_hclk_dsys.clk,
318 .enable = s5pv210_clk_ip0_ctrl,
319 .ctrlbit = (1 << 25),
322 .devname = "s5pv210-fimc.2",
323 .parent = &clk_hclk_dsys.clk,
324 .enable = s5pv210_clk_ip0_ctrl,
325 .ctrlbit = (1 << 26),
328 .parent = &clk_hclk_psys.clk,
329 .enable = s5pv210_clk_ip1_ctrl,
333 .parent = &clk_hclk_psys.clk,
334 .enable = s5pv210_clk_ip1_ctrl,
338 .parent = &clk_hclk_dsys.clk,
339 .enable = s5pv210_clk_ip1_ctrl,
343 .parent = &clk_hclk_psys.clk,
344 .enable = s5pv210_clk_ip1_ctrl,
348 .devname = "s3c-sdhci.0",
349 .parent = &clk_hclk_psys.clk,
350 .enable = s5pv210_clk_ip2_ctrl,
354 .devname = "s3c-sdhci.1",
355 .parent = &clk_hclk_psys.clk,
356 .enable = s5pv210_clk_ip2_ctrl,
360 .devname = "s3c-sdhci.2",
361 .parent = &clk_hclk_psys.clk,
362 .enable = s5pv210_clk_ip2_ctrl,
366 .devname = "s3c-sdhci.3",
367 .parent = &clk_hclk_psys.clk,
368 .enable = s5pv210_clk_ip2_ctrl,
372 .parent = &clk_pclk_psys.clk,
373 .enable = s5pv210_clk_ip3_ctrl,
377 .parent = &clk_pclk_psys.clk,
378 .enable = s5pv210_clk_ip3_ctrl,
382 .parent = &clk_pclk_psys.clk,
383 .enable = s5pv210_clk_ip3_ctrl,
387 .devname = "s3c2440-i2c.0",
388 .parent = &clk_pclk_psys.clk,
389 .enable = s5pv210_clk_ip3_ctrl,
393 .devname = "s3c2440-i2c.1",
394 .parent = &clk_pclk_psys.clk,
395 .enable = s5pv210_clk_ip3_ctrl,
396 .ctrlbit = (1 << 10),
399 .devname = "s3c2440-i2c.2",
400 .parent = &clk_pclk_psys.clk,
401 .enable = s5pv210_clk_ip3_ctrl,
405 .devname = "s3c64xx-spi.0",
406 .parent = &clk_pclk_psys.clk,
407 .enable = s5pv210_clk_ip3_ctrl,
411 .devname = "s3c64xx-spi.1",
412 .parent = &clk_pclk_psys.clk,
413 .enable = s5pv210_clk_ip3_ctrl,
417 .devname = "s3c64xx-spi.2",
418 .parent = &clk_pclk_psys.clk,
419 .enable = s5pv210_clk_ip3_ctrl,
423 .parent = &clk_pclk_psys.clk,
424 .enable = s5pv210_clk_ip3_ctrl,
428 .parent = &clk_pclk_psys.clk,
429 .enable = s5pv210_clk_ip3_ctrl,
433 .parent = &clk_pclk_psys.clk,
434 .enable = s5pv210_clk_ip3_ctrl,
438 .devname = "samsung-i2s.0",
440 .enable = s5pv210_clk_ip3_ctrl,
444 .devname = "samsung-i2s.1",
446 .enable = s5pv210_clk_ip3_ctrl,
450 .devname = "samsung-i2s.2",
452 .enable = s5pv210_clk_ip3_ctrl,
457 .enable = s5pv210_clk_ip3_ctrl,
462 static struct clk init_clocks[] = {
465 .parent = &clk_hclk_msys.clk,
467 .enable = s5pv210_clk_ip0_ctrl,
468 .ops = &clk_hclk_imem_ops,
471 .devname = "s5pv210-uart.0",
472 .parent = &clk_pclk_psys.clk,
473 .enable = s5pv210_clk_ip3_ctrl,
474 .ctrlbit = (1 << 17),
477 .devname = "s5pv210-uart.1",
478 .parent = &clk_pclk_psys.clk,
479 .enable = s5pv210_clk_ip3_ctrl,
480 .ctrlbit = (1 << 18),
483 .devname = "s5pv210-uart.2",
484 .parent = &clk_pclk_psys.clk,
485 .enable = s5pv210_clk_ip3_ctrl,
486 .ctrlbit = (1 << 19),
489 .devname = "s5pv210-uart.3",
490 .parent = &clk_pclk_psys.clk,
491 .enable = s5pv210_clk_ip3_ctrl,
492 .ctrlbit = (1 << 20),
495 .parent = &clk_hclk_psys.clk,
496 .enable = s5pv210_clk_ip1_ctrl,
497 .ctrlbit = (1 << 26),
501 static struct clk *clkset_uart_list[] = {
502 [6] = &clk_mout_mpll.clk,
503 [7] = &clk_mout_epll.clk,
506 static struct clksrc_sources clkset_uart = {
507 .sources = clkset_uart_list,
508 .nr_sources = ARRAY_SIZE(clkset_uart_list),
511 static struct clk *clkset_group1_list[] = {
512 [0] = &clk_sclk_a2m.clk,
513 [1] = &clk_mout_mpll.clk,
514 [2] = &clk_mout_epll.clk,
515 [3] = &clk_sclk_vpll.clk,
518 static struct clksrc_sources clkset_group1 = {
519 .sources = clkset_group1_list,
520 .nr_sources = ARRAY_SIZE(clkset_group1_list),
523 static struct clk *clkset_sclk_onenand_list[] = {
524 [0] = &clk_hclk_psys.clk,
525 [1] = &clk_hclk_dsys.clk,
528 static struct clksrc_sources clkset_sclk_onenand = {
529 .sources = clkset_sclk_onenand_list,
530 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
533 static struct clk *clkset_sclk_dac_list[] = {
534 [0] = &clk_sclk_vpll.clk,
535 [1] = &clk_sclk_hdmiphy,
538 static struct clksrc_sources clkset_sclk_dac = {
539 .sources = clkset_sclk_dac_list,
540 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
543 static struct clksrc_clk clk_sclk_dac = {
546 .enable = s5pv210_clk_mask0_ctrl,
549 .sources = &clkset_sclk_dac,
550 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
553 static struct clksrc_clk clk_sclk_pixel = {
555 .name = "sclk_pixel",
556 .parent = &clk_sclk_vpll.clk,
558 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
561 static struct clk *clkset_sclk_hdmi_list[] = {
562 [0] = &clk_sclk_pixel.clk,
563 [1] = &clk_sclk_hdmiphy,
566 static struct clksrc_sources clkset_sclk_hdmi = {
567 .sources = clkset_sclk_hdmi_list,
568 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
571 static struct clksrc_clk clk_sclk_hdmi = {
574 .enable = s5pv210_clk_mask0_ctrl,
577 .sources = &clkset_sclk_hdmi,
578 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
581 static struct clk *clkset_sclk_mixer_list[] = {
582 [0] = &clk_sclk_dac.clk,
583 [1] = &clk_sclk_hdmi.clk,
586 static struct clksrc_sources clkset_sclk_mixer = {
587 .sources = clkset_sclk_mixer_list,
588 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
591 static struct clk *clkset_sclk_audio0_list[] = {
592 [0] = &clk_ext_xtal_mux,
593 [1] = &clk_pcmcdclk0,
594 [2] = &clk_sclk_hdmi27m,
595 [3] = &clk_sclk_usbphy0,
596 [4] = &clk_sclk_usbphy1,
597 [5] = &clk_sclk_hdmiphy,
598 [6] = &clk_mout_mpll.clk,
599 [7] = &clk_mout_epll.clk,
600 [8] = &clk_sclk_vpll.clk,
603 static struct clksrc_sources clkset_sclk_audio0 = {
604 .sources = clkset_sclk_audio0_list,
605 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
608 static struct clksrc_clk clk_sclk_audio0 = {
610 .name = "sclk_audio",
611 .devname = "soc-audio.0",
612 .enable = s5pv210_clk_mask0_ctrl,
613 .ctrlbit = (1 << 24),
615 .sources = &clkset_sclk_audio0,
616 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
617 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
620 static struct clk *clkset_sclk_audio1_list[] = {
621 [0] = &clk_ext_xtal_mux,
622 [1] = &clk_pcmcdclk1,
623 [2] = &clk_sclk_hdmi27m,
624 [3] = &clk_sclk_usbphy0,
625 [4] = &clk_sclk_usbphy1,
626 [5] = &clk_sclk_hdmiphy,
627 [6] = &clk_mout_mpll.clk,
628 [7] = &clk_mout_epll.clk,
629 [8] = &clk_sclk_vpll.clk,
632 static struct clksrc_sources clkset_sclk_audio1 = {
633 .sources = clkset_sclk_audio1_list,
634 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
637 static struct clksrc_clk clk_sclk_audio1 = {
639 .name = "sclk_audio",
640 .devname = "soc-audio.1",
641 .enable = s5pv210_clk_mask0_ctrl,
642 .ctrlbit = (1 << 25),
644 .sources = &clkset_sclk_audio1,
645 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
646 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
649 static struct clk *clkset_sclk_audio2_list[] = {
650 [0] = &clk_ext_xtal_mux,
651 [1] = &clk_pcmcdclk0,
652 [2] = &clk_sclk_hdmi27m,
653 [3] = &clk_sclk_usbphy0,
654 [4] = &clk_sclk_usbphy1,
655 [5] = &clk_sclk_hdmiphy,
656 [6] = &clk_mout_mpll.clk,
657 [7] = &clk_mout_epll.clk,
658 [8] = &clk_sclk_vpll.clk,
661 static struct clksrc_sources clkset_sclk_audio2 = {
662 .sources = clkset_sclk_audio2_list,
663 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
666 static struct clksrc_clk clk_sclk_audio2 = {
668 .name = "sclk_audio",
669 .devname = "soc-audio.2",
670 .enable = s5pv210_clk_mask0_ctrl,
671 .ctrlbit = (1 << 26),
673 .sources = &clkset_sclk_audio2,
674 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
675 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
678 static struct clk *clkset_sclk_spdif_list[] = {
679 [0] = &clk_sclk_audio0.clk,
680 [1] = &clk_sclk_audio1.clk,
681 [2] = &clk_sclk_audio2.clk,
684 static struct clksrc_sources clkset_sclk_spdif = {
685 .sources = clkset_sclk_spdif_list,
686 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
689 static struct clksrc_clk clk_sclk_spdif = {
691 .name = "sclk_spdif",
692 .enable = s5pv210_clk_mask0_ctrl,
693 .ctrlbit = (1 << 27),
694 .ops = &s5p_sclk_spdif_ops,
696 .sources = &clkset_sclk_spdif,
697 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
700 static struct clk *clkset_group2_list[] = {
701 [0] = &clk_ext_xtal_mux,
703 [2] = &clk_sclk_hdmi27m,
704 [3] = &clk_sclk_usbphy0,
705 [4] = &clk_sclk_usbphy1,
706 [5] = &clk_sclk_hdmiphy,
707 [6] = &clk_mout_mpll.clk,
708 [7] = &clk_mout_epll.clk,
709 [8] = &clk_sclk_vpll.clk,
712 static struct clksrc_sources clkset_group2 = {
713 .sources = clkset_group2_list,
714 .nr_sources = ARRAY_SIZE(clkset_group2_list),
717 static struct clksrc_clk clksrcs[] = {
722 .sources = &clkset_group1,
723 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
724 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
727 .name = "sclk_onenand",
729 .sources = &clkset_sclk_onenand,
730 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
731 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
735 .devname = "s5pv210-uart.0",
736 .enable = s5pv210_clk_mask0_ctrl,
737 .ctrlbit = (1 << 12),
739 .sources = &clkset_uart,
740 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
741 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
745 .devname = "s5pv210-uart.1",
746 .enable = s5pv210_clk_mask0_ctrl,
747 .ctrlbit = (1 << 13),
749 .sources = &clkset_uart,
750 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
751 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
755 .devname = "s5pv210-uart.2",
756 .enable = s5pv210_clk_mask0_ctrl,
757 .ctrlbit = (1 << 14),
759 .sources = &clkset_uart,
760 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
761 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
765 .devname = "s5pv210-uart.3",
766 .enable = s5pv210_clk_mask0_ctrl,
767 .ctrlbit = (1 << 15),
769 .sources = &clkset_uart,
770 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
771 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
774 .name = "sclk_mixer",
775 .enable = s5pv210_clk_mask0_ctrl,
778 .sources = &clkset_sclk_mixer,
779 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
783 .devname = "s5pv210-fimc.0",
784 .enable = s5pv210_clk_mask1_ctrl,
787 .sources = &clkset_group2,
788 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
789 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
793 .devname = "s5pv210-fimc.1",
794 .enable = s5pv210_clk_mask1_ctrl,
797 .sources = &clkset_group2,
798 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
799 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
803 .devname = "s5pv210-fimc.2",
804 .enable = s5pv210_clk_mask1_ctrl,
807 .sources = &clkset_group2,
808 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
809 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
813 .devname = "s5pv210-fimc.0",
814 .enable = s5pv210_clk_mask0_ctrl,
817 .sources = &clkset_group2,
818 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
819 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
823 .devname = "s5pv210-fimc.1",
824 .enable = s5pv210_clk_mask0_ctrl,
827 .sources = &clkset_group2,
828 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
833 .enable = s5pv210_clk_mask0_ctrl,
836 .sources = &clkset_group2,
837 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
838 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
842 .devname = "s3c-sdhci.0",
843 .enable = s5pv210_clk_mask0_ctrl,
846 .sources = &clkset_group2,
847 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
848 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
852 .devname = "s3c-sdhci.1",
853 .enable = s5pv210_clk_mask0_ctrl,
856 .sources = &clkset_group2,
857 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
858 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
862 .devname = "s3c-sdhci.2",
863 .enable = s5pv210_clk_mask0_ctrl,
864 .ctrlbit = (1 << 10),
866 .sources = &clkset_group2,
867 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
868 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
872 .devname = "s3c-sdhci.3",
873 .enable = s5pv210_clk_mask0_ctrl,
874 .ctrlbit = (1 << 11),
876 .sources = &clkset_group2,
877 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
878 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
882 .enable = s5pv210_clk_ip0_ctrl,
883 .ctrlbit = (1 << 16),
885 .sources = &clkset_group1,
886 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
887 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
891 .enable = s5pv210_clk_ip0_ctrl,
892 .ctrlbit = (1 << 12),
894 .sources = &clkset_group1,
895 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
896 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
900 .enable = s5pv210_clk_ip0_ctrl,
903 .sources = &clkset_group1,
904 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
905 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
909 .enable = s5pv210_clk_mask0_ctrl,
912 .sources = &clkset_group2,
913 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
914 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
918 .devname = "s3c64xx-spi.0",
919 .enable = s5pv210_clk_mask0_ctrl,
920 .ctrlbit = (1 << 16),
922 .sources = &clkset_group2,
923 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
924 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
928 .devname = "s3c64xx-spi.1",
929 .enable = s5pv210_clk_mask0_ctrl,
930 .ctrlbit = (1 << 17),
932 .sources = &clkset_group2,
933 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
934 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
938 .enable = s5pv210_clk_mask0_ctrl,
939 .ctrlbit = (1 << 29),
941 .sources = &clkset_group2,
942 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
943 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
947 .enable = s5pv210_clk_mask0_ctrl,
948 .ctrlbit = (1 << 19),
950 .sources = &clkset_group2,
951 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
952 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
956 /* Clock initialisation code */
957 static struct clksrc_clk *sysclks[] = {
982 static u32 epll_div[][6] = {
983 { 48000000, 0, 48, 3, 3, 0 },
984 { 96000000, 0, 48, 3, 2, 0 },
985 { 144000000, 1, 72, 3, 2, 0 },
986 { 192000000, 0, 48, 3, 1, 0 },
987 { 288000000, 1, 72, 3, 1, 0 },
988 { 32750000, 1, 65, 3, 4, 35127 },
989 { 32768000, 1, 65, 3, 4, 35127 },
990 { 45158400, 0, 45, 3, 3, 10355 },
991 { 45000000, 0, 45, 3, 3, 10355 },
992 { 45158000, 0, 45, 3, 3, 10355 },
993 { 49125000, 0, 49, 3, 3, 9961 },
994 { 49152000, 0, 49, 3, 3, 9961 },
995 { 67737600, 1, 67, 3, 3, 48366 },
996 { 67738000, 1, 67, 3, 3, 48366 },
997 { 73800000, 1, 73, 3, 3, 47710 },
998 { 73728000, 1, 73, 3, 3, 47710 },
999 { 36000000, 1, 32, 3, 4, 0 },
1000 { 60000000, 1, 60, 3, 3, 0 },
1001 { 72000000, 1, 72, 3, 3, 0 },
1002 { 80000000, 1, 80, 3, 3, 0 },
1003 { 84000000, 0, 42, 3, 2, 0 },
1004 { 50000000, 0, 50, 3, 3, 0 },
1007 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1009 unsigned int epll_con, epll_con_k;
1012 /* Return if nothing changed */
1013 if (clk->rate == rate)
1016 epll_con = __raw_readl(S5P_EPLL_CON);
1017 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1019 epll_con_k &= ~PLL46XX_KDIV_MASK;
1020 epll_con &= ~(1 << 27 |
1021 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1022 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1023 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1025 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1026 if (epll_div[i][0] == rate) {
1027 epll_con_k |= epll_div[i][5] << 0;
1028 epll_con |= (epll_div[i][1] << 27 |
1029 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1030 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1031 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1036 if (i == ARRAY_SIZE(epll_div)) {
1037 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1042 __raw_writel(epll_con, S5P_EPLL_CON);
1043 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1045 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1053 static struct clk_ops s5pv210_epll_ops = {
1054 .set_rate = s5pv210_epll_set_rate,
1055 .get_rate = s5p_epll_get_rate,
1058 void __init_or_cpufreq s5pv210_setup_clocks(void)
1060 struct clk *xtal_clk;
1061 unsigned long vpllsrc;
1062 unsigned long armclk;
1063 unsigned long hclk_msys;
1064 unsigned long hclk_dsys;
1065 unsigned long hclk_psys;
1066 unsigned long pclk_msys;
1067 unsigned long pclk_dsys;
1068 unsigned long pclk_psys;
1074 u32 clkdiv0, clkdiv1;
1076 /* Set functions for clk_fout_epll */
1077 clk_fout_epll.enable = s5p_epll_enable;
1078 clk_fout_epll.ops = &s5pv210_epll_ops;
1080 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1082 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1083 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1085 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1086 __func__, clkdiv0, clkdiv1);
1088 xtal_clk = clk_get(NULL, "xtal");
1089 BUG_ON(IS_ERR(xtal_clk));
1091 xtal = clk_get_rate(xtal_clk);
1094 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1096 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1097 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1098 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1099 __raw_readl(S5P_EPLL_CON1), pll_4600);
1100 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1101 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1103 clk_fout_apll.ops = &clk_fout_apll_ops;
1104 clk_fout_mpll.rate = mpll;
1105 clk_fout_epll.rate = epll;
1106 clk_fout_vpll.rate = vpll;
1108 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1109 apll, mpll, epll, vpll);
1111 armclk = clk_get_rate(&clk_armclk.clk);
1112 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1113 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1114 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1115 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1116 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1117 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1119 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1120 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1121 armclk, hclk_msys, hclk_dsys, hclk_psys,
1122 pclk_msys, pclk_dsys, pclk_psys);
1124 clk_f.rate = armclk;
1125 clk_h.rate = hclk_psys;
1126 clk_p.rate = pclk_psys;
1128 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1129 s3c_set_clksrc(&clksrcs[ptr], true);
1132 static struct clk *clks[] __initdata = {
1142 void __init s5pv210_register_clocks(void)
1146 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1148 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1149 s3c_register_clksrc(sysclks[ptr], 1);
1151 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1152 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1154 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1155 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));