arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static unsigned long xtal;
  35
  36 static struct clksrc_clk clk_mout_apll = {
  37         .clk    = {
  38                 .name           = "mout_apll",
  39                 .id             = -1,
  40         },
  41         .sources        = &clk_src_apll,
  42         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  43 };
  44
  45 static struct clksrc_clk clk_mout_epll = {
  46         .clk    = {
  47                 .name           = "mout_epll",
  48                 .id             = -1,
  49         },
  50         .sources        = &clk_src_epll,
  51         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  52 };
  53
  54 static struct clksrc_clk clk_mout_mpll = {
  55         .clk = {
  56                 .name           = "mout_mpll",
  57                 .id             = -1,
  58         },
  59         .sources        = &clk_src_mpll,
  60         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  61 };
  62
  63 static struct clk *clkset_armclk_list[] = {
  64         [0] = &clk_mout_apll.clk,
  65         [1] = &clk_mout_mpll.clk,
  66 };
  67
  68 static struct clksrc_sources clkset_armclk = {
  69         .sources        = clkset_armclk_list,
  70         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  71 };
  72
  73 static struct clksrc_clk clk_armclk = {
  74         .clk    = {
  75                 .name           = "armclk",
  76                 .id             = -1,
  77         },
  78         .sources        = &clkset_armclk,
  79         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  80         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  81 };
  82
  83 static struct clksrc_clk clk_hclk_msys = {
  84         .clk    = {
  85                 .name           = "hclk_msys",
  86                 .id             = -1,
  87                 .parent         = &clk_armclk.clk,
  88         },
  89         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  90 };
  91
  92 static struct clksrc_clk clk_pclk_msys = {
  93         .clk    = {
  94                 .name           = "pclk_msys",
  95                 .id             = -1,
  96                 .parent         = &clk_hclk_msys.clk,
  97         },
  98         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  99 };
 100
 101 static struct clksrc_clk clk_sclk_a2m = {
 102         .clk    = {
 103                 .name           = "sclk_a2m",
 104                 .id             = -1,
 105                 .parent         = &clk_mout_apll.clk,
 106         },
 107         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 108 };
 109
 110 static struct clk *clkset_hclk_sys_list[] = {
 111         [0] = &clk_mout_mpll.clk,
 112         [1] = &clk_sclk_a2m.clk,
 113 };
 114
 115 static struct clksrc_sources clkset_hclk_sys = {
 116         .sources        = clkset_hclk_sys_list,
 117         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 118 };
 119
 120 static struct clksrc_clk clk_hclk_dsys = {
 121         .clk    = {
 122                 .name   = "hclk_dsys",
 123                 .id     = -1,
 124         },
 125         .sources        = &clkset_hclk_sys,
 126         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 127         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 128 };
 129
 130 static struct clksrc_clk clk_pclk_dsys = {
 131         .clk    = {
 132                 .name   = "pclk_dsys",
 133                 .id     = -1,
 134                 .parent = &clk_hclk_dsys.clk,
 135         },
 136         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 137 };
 138
 139 static struct clksrc_clk clk_hclk_psys = {
 140         .clk    = {
 141                 .name   = "hclk_psys",
 142                 .id     = -1,
 143         },
 144         .sources        = &clkset_hclk_sys,
 145         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 146         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 147 };
 148
 149 static struct clksrc_clk clk_pclk_psys = {
 150         .clk    = {
 151                 .name   = "pclk_psys",
 152                 .id     = -1,
 153                 .parent = &clk_hclk_psys.clk,
 154         },
 155         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 156 };
 157
 158 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 159 {
 160         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 161 }
 162
 163 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 164 {
 165         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 166 }
 167
 168 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 169 {
 170         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 171 }
 172
 173 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 174 {
 175         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 176 }
 177
 178 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 179 {
 180         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 181 }
 182
 183 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 184 {
 185         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 186 }
 187
 188 static struct clk clk_sclk_hdmi27m = {
 189         .name           = "sclk_hdmi27m",
 190         .id             = -1,
 191         .rate           = 27000000,
 192 };
 193
 194 static struct clk clk_sclk_hdmiphy = {
 195         .name           = "sclk_hdmiphy",
 196         .id             = -1,
 197 };
 198
 199 static struct clk clk_sclk_usbphy0 = {
 200         .name           = "sclk_usbphy0",
 201         .id             = -1,
 202 };
 203
 204 static struct clk clk_sclk_usbphy1 = {
 205         .name           = "sclk_usbphy1",
 206         .id             = -1,
 207 };
 208
 209 static struct clk clk_pcmcdclk0 = {
 210         .name           = "pcmcdclk",
 211         .id             = -1,
 212 };
 213
 214 static struct clk clk_pcmcdclk1 = {
 215         .name           = "pcmcdclk",
 216         .id             = -1,
 217 };
 218
 219 static struct clk clk_pcmcdclk2 = {
 220         .name           = "pcmcdclk",
 221         .id             = -1,
 222 };
 223
 224 static struct clk *clkset_vpllsrc_list[] = {
 225         [0] = &clk_fin_vpll,
 226         [1] = &clk_sclk_hdmi27m,
 227 };
 228
 229 static struct clksrc_sources clkset_vpllsrc = {
 230         .sources        = clkset_vpllsrc_list,
 231         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 232 };
 233
 234 static struct clksrc_clk clk_vpllsrc = {
 235         .clk    = {
 236                 .name           = "vpll_src",
 237                 .id             = -1,
 238                 .enable         = s5pv210_clk_mask0_ctrl,
 239                 .ctrlbit        = (1 << 7),
 240         },
 241         .sources        = &clkset_vpllsrc,
 242         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 243 };
 244
 245 static struct clk *clkset_sclk_vpll_list[] = {
 246         [0] = &clk_vpllsrc.clk,
 247         [1] = &clk_fout_vpll,
 248 };
 249
 250 static struct clksrc_sources clkset_sclk_vpll = {
 251         .sources        = clkset_sclk_vpll_list,
 252         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 253 };
 254
 255 static struct clksrc_clk clk_sclk_vpll = {
 256         .clk    = {
 257                 .name           = "sclk_vpll",
 258                 .id             = -1,
 259         },
 260         .sources        = &clkset_sclk_vpll,
 261         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 262 };
 263
 264 static struct clk *clkset_moutdmc0src_list[] = {
 265         [0] = &clk_sclk_a2m.clk,
 266         [1] = &clk_mout_mpll.clk,
 267         [2] = NULL,
 268         [3] = NULL,
 269 };
 270
 271 static struct clksrc_sources clkset_moutdmc0src = {
 272         .sources        = clkset_moutdmc0src_list,
 273         .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
 274 };
 275
 276 static struct clksrc_clk clk_mout_dmc0 = {
 277         .clk    = {
 278                 .name           = "mout_dmc0",
 279                 .id             = -1,
 280         },
 281         .sources        = &clkset_moutdmc0src,
 282         .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 283 };
 284
 285 static struct clksrc_clk clk_sclk_dmc0 = {
 286         .clk    = {
 287                 .name           = "sclk_dmc0",
 288                 .id             = -1,
 289                 .parent         = &clk_mout_dmc0.clk,
 290         },
 291         .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 292 };
 293
 294 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 295 {
 296         return clk_get_rate(clk->parent) / 2;
 297 }
 298
 299 static struct clk_ops clk_hclk_imem_ops = {
 300         .get_rate       = s5pv210_clk_imem_get_rate,
 301 };
 302
 303 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
 304 {
 305         return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 306 }
 307
 308 static struct clk_ops clk_fout_apll_ops = {
 309         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 310 };
 311
 312 static struct clk init_clocks_disable[] = {
 313         {
 314                 .name           = "rot",
 315                 .id             = -1,
 316                 .parent         = &clk_hclk_dsys.clk,
 317                 .enable         = s5pv210_clk_ip0_ctrl,
 318                 .ctrlbit        = (1<<29),
 319         }, {
 320                 .name           = "fimc",
 321                 .id             = 0,
 322                 .parent         = &clk_hclk_dsys.clk,
 323                 .enable         = s5pv210_clk_ip0_ctrl,
 324                 .ctrlbit        = (1 << 24),
 325         }, {
 326                 .name           = "fimc",
 327                 .id             = 1,
 328                 .parent         = &clk_hclk_dsys.clk,
 329                 .enable         = s5pv210_clk_ip0_ctrl,
 330                 .ctrlbit        = (1 << 25),
 331         }, {
 332                 .name           = "fimc",
 333                 .id             = 2,
 334                 .parent         = &clk_hclk_dsys.clk,
 335                 .enable         = s5pv210_clk_ip0_ctrl,
 336                 .ctrlbit        = (1 << 26),
 337         }, {
 338                 .name           = "otg",
 339                 .id             = -1,
 340                 .parent         = &clk_hclk_psys.clk,
 341                 .enable         = s5pv210_clk_ip1_ctrl,
 342                 .ctrlbit        = (1<<16),
 343         }, {
 344                 .name           = "usb-host",
 345                 .id             = -1,
 346                 .parent         = &clk_hclk_psys.clk,
 347                 .enable         = s5pv210_clk_ip1_ctrl,
 348                 .ctrlbit        = (1<<17),
 349         }, {
 350                 .name           = "lcd",
 351                 .id             = -1,
 352                 .parent         = &clk_hclk_dsys.clk,
 353                 .enable         = s5pv210_clk_ip1_ctrl,
 354                 .ctrlbit        = (1<<0),
 355         }, {
 356                 .name           = "cfcon",
 357                 .id             = 0,
 358                 .parent         = &clk_hclk_psys.clk,
 359                 .enable         = s5pv210_clk_ip1_ctrl,
 360                 .ctrlbit        = (1<<25),
 361         }, {
 362                 .name           = "hsmmc",
 363                 .id             = 0,
 364                 .parent         = &clk_hclk_psys.clk,
 365                 .enable         = s5pv210_clk_ip2_ctrl,
 366                 .ctrlbit        = (1<<16),
 367         }, {
 368                 .name           = "hsmmc",
 369                 .id             = 1,
 370                 .parent         = &clk_hclk_psys.clk,
 371                 .enable         = s5pv210_clk_ip2_ctrl,
 372                 .ctrlbit        = (1<<17),
 373         }, {
 374                 .name           = "hsmmc",
 375                 .id             = 2,
 376                 .parent         = &clk_hclk_psys.clk,
 377                 .enable         = s5pv210_clk_ip2_ctrl,
 378                 .ctrlbit        = (1<<18),
 379         }, {
 380                 .name           = "hsmmc",
 381                 .id             = 3,
 382                 .parent         = &clk_hclk_psys.clk,
 383                 .enable         = s5pv210_clk_ip2_ctrl,
 384                 .ctrlbit        = (1<<19),
 385         }, {
 386                 .name           = "systimer",
 387                 .id             = -1,
 388                 .parent         = &clk_pclk_psys.clk,
 389                 .enable         = s5pv210_clk_ip3_ctrl,
 390                 .ctrlbit        = (1<<16),
 391         }, {
 392                 .name           = "watchdog",
 393                 .id             = -1,
 394                 .parent         = &clk_pclk_psys.clk,
 395                 .enable         = s5pv210_clk_ip3_ctrl,
 396                 .ctrlbit        = (1<<22),
 397         }, {
 398                 .name           = "rtc",
 399                 .id             = -1,
 400                 .parent         = &clk_pclk_psys.clk,
 401                 .enable         = s5pv210_clk_ip3_ctrl,
 402                 .ctrlbit        = (1<<15),
 403         }, {
 404                 .name           = "i2c",
 405                 .id             = 0,
 406                 .parent         = &clk_pclk_psys.clk,
 407                 .enable         = s5pv210_clk_ip3_ctrl,
 408                 .ctrlbit        = (1<<7),
 409         }, {
 410                 .name           = "i2c",
 411                 .id             = 1,
 412                 .parent         = &clk_pclk_psys.clk,
 413                 .enable         = s5pv210_clk_ip3_ctrl,
 414                 .ctrlbit        = (1 << 10),
 415         }, {
 416                 .name           = "i2c",
 417                 .id             = 2,
 418                 .parent         = &clk_pclk_psys.clk,
 419                 .enable         = s5pv210_clk_ip3_ctrl,
 420                 .ctrlbit        = (1<<9),
 421         }, {
 422                 .name           = "spi",
 423                 .id             = 0,
 424                 .parent         = &clk_pclk_psys.clk,
 425                 .enable         = s5pv210_clk_ip3_ctrl,
 426                 .ctrlbit        = (1<<12),
 427         }, {
 428                 .name           = "spi",
 429                 .id             = 1,
 430                 .parent         = &clk_pclk_psys.clk,
 431                 .enable         = s5pv210_clk_ip3_ctrl,
 432                 .ctrlbit        = (1<<13),
 433         }, {
 434                 .name           = "spi",
 435                 .id             = 2,
 436                 .parent         = &clk_pclk_psys.clk,
 437                 .enable         = s5pv210_clk_ip3_ctrl,
 438                 .ctrlbit        = (1<<14),
 439         }, {
 440                 .name           = "timers",
 441                 .id             = -1,
 442                 .parent         = &clk_pclk_psys.clk,
 443                 .enable         = s5pv210_clk_ip3_ctrl,
 444                 .ctrlbit        = (1<<23),
 445         }, {
 446                 .name           = "adc",
 447                 .id             = -1,
 448                 .parent         = &clk_pclk_psys.clk,
 449                 .enable         = s5pv210_clk_ip3_ctrl,
 450                 .ctrlbit        = (1<<24),
 451         }, {
 452                 .name           = "keypad",
 453                 .id             = -1,
 454                 .parent         = &clk_pclk_psys.clk,
 455                 .enable         = s5pv210_clk_ip3_ctrl,
 456                 .ctrlbit        = (1<<21),
 457         }, {
 458                 .name           = "i2s_v50",
 459                 .id             = 0,
 460                 .parent         = &clk_p,
 461                 .enable         = s5pv210_clk_ip3_ctrl,
 462                 .ctrlbit        = (1<<4),
 463         }, {
 464                 .name           = "i2s_v32",
 465                 .id             = 0,
 466                 .parent         = &clk_p,
 467                 .enable         = s5pv210_clk_ip3_ctrl,
 468                 .ctrlbit        = (1 << 5),
 469         }, {
 470                 .name           = "i2s_v32",
 471                 .id             = 1,
 472                 .parent         = &clk_p,
 473                 .enable         = s5pv210_clk_ip3_ctrl,
 474                 .ctrlbit        = (1 << 6),
 475         },
 476 };
 477
 478 static struct clk init_clocks[] = {
 479         {
 480                 .name           = "hclk_imem",
 481                 .id             = -1,
 482                 .parent         = &clk_hclk_msys.clk,
 483                 .ctrlbit        = (1 << 5),
 484                 .enable         = s5pv210_clk_ip0_ctrl,
 485                 .ops            = &clk_hclk_imem_ops,
 486         }, {
 487                 .name           = "uart",
 488                 .id             = 0,
 489                 .parent         = &clk_pclk_psys.clk,
 490                 .enable         = s5pv210_clk_ip3_ctrl,
 491                 .ctrlbit        = (1 << 17),
 492         }, {
 493                 .name           = "uart",
 494                 .id             = 1,
 495                 .parent         = &clk_pclk_psys.clk,
 496                 .enable         = s5pv210_clk_ip3_ctrl,
 497                 .ctrlbit        = (1 << 18),
 498         }, {
 499                 .name           = "uart",
 500                 .id             = 2,
 501                 .parent         = &clk_pclk_psys.clk,
 502                 .enable         = s5pv210_clk_ip3_ctrl,
 503                 .ctrlbit        = (1 << 19),
 504         }, {
 505                 .name           = "uart",
 506                 .id             = 3,
 507                 .parent         = &clk_pclk_psys.clk,
 508                 .enable         = s5pv210_clk_ip3_ctrl,
 509                 .ctrlbit        = (1 << 20),
 510         },
 511 };
 512
 513 static struct clk *clkset_uart_list[] = {
 514         [6] = &clk_mout_mpll.clk,
 515         [7] = &clk_mout_epll.clk,
 516 };
 517
 518 static struct clksrc_sources clkset_uart = {
 519         .sources        = clkset_uart_list,
 520         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 521 };
 522
 523 static struct clk *clkset_group1_list[] = {
 524         [0] = &clk_sclk_a2m.clk,
 525         [1] = &clk_mout_mpll.clk,
 526         [2] = &clk_mout_epll.clk,
 527         [3] = &clk_sclk_vpll.clk,
 528 };
 529
 530 static struct clksrc_sources clkset_group1 = {
 531         .sources        = clkset_group1_list,
 532         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 533 };
 534
 535 static struct clk *clkset_sclk_onenand_list[] = {
 536         [0] = &clk_hclk_psys.clk,
 537         [1] = &clk_hclk_dsys.clk,
 538 };
 539
 540 static struct clksrc_sources clkset_sclk_onenand = {
 541         .sources        = clkset_sclk_onenand_list,
 542         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 543 };
 544
 545 static struct clk *clkset_sclk_dac_list[] = {
 546         [0] = &clk_sclk_vpll.clk,
 547         [1] = &clk_sclk_hdmiphy,
 548 };
 549
 550 static struct clksrc_sources clkset_sclk_dac = {
 551         .sources        = clkset_sclk_dac_list,
 552         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 553 };
 554
 555 static struct clksrc_clk clk_sclk_dac = {
 556         .clk            = {
 557                 .name           = "sclk_dac",
 558                 .id             = -1,
 559                 .enable         = s5pv210_clk_mask0_ctrl,
 560                 .ctrlbit        = (1 << 2),
 561         },
 562         .sources        = &clkset_sclk_dac,
 563         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 564 };
 565
 566 static struct clksrc_clk clk_sclk_pixel = {
 567         .clk            = {
 568                 .name           = "sclk_pixel",
 569                 .id             = -1,
 570                 .parent         = &clk_sclk_vpll.clk,
 571         },
 572         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 573 };
 574
 575 static struct clk *clkset_sclk_hdmi_list[] = {
 576         [0] = &clk_sclk_pixel.clk,
 577         [1] = &clk_sclk_hdmiphy,
 578 };
 579
 580 static struct clksrc_sources clkset_sclk_hdmi = {
 581         .sources        = clkset_sclk_hdmi_list,
 582         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 583 };
 584
 585 static struct clksrc_clk clk_sclk_hdmi = {
 586         .clk            = {
 587                 .name           = "sclk_hdmi",
 588                 .id             = -1,
 589                 .enable         = s5pv210_clk_mask0_ctrl,
 590                 .ctrlbit        = (1 << 0),
 591         },
 592         .sources        = &clkset_sclk_hdmi,
 593         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 594 };
 595
 596 static struct clk *clkset_sclk_mixer_list[] = {
 597         [0] = &clk_sclk_dac.clk,
 598         [1] = &clk_sclk_hdmi.clk,
 599 };
 600
 601 static struct clksrc_sources clkset_sclk_mixer = {
 602         .sources        = clkset_sclk_mixer_list,
 603         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 604 };
 605
 606 static struct clk *clkset_sclk_audio0_list[] = {
 607         [0] = &clk_ext_xtal_mux,
 608         [1] = &clk_pcmcdclk0,
 609         [2] = &clk_sclk_hdmi27m,
 610         [3] = &clk_sclk_usbphy0,
 611         [4] = &clk_sclk_usbphy1,
 612         [5] = &clk_sclk_hdmiphy,
 613         [6] = &clk_mout_mpll.clk,
 614         [7] = &clk_mout_epll.clk,
 615         [8] = &clk_sclk_vpll.clk,
 616 };
 617
 618 static struct clksrc_sources clkset_sclk_audio0 = {
 619         .sources        = clkset_sclk_audio0_list,
 620         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 621 };
 622
 623 static struct clksrc_clk clk_sclk_audio0 = {
 624         .clk            = {
 625                 .name           = "sclk_audio",
 626                 .id             = 0,
 627                 .enable         = s5pv210_clk_mask0_ctrl,
 628                 .ctrlbit        = (1 << 24),
 629         },
 630         .sources = &clkset_sclk_audio0,
 631         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 632         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 633 };
 634
 635 static struct clk *clkset_sclk_audio1_list[] = {
 636         [0] = &clk_ext_xtal_mux,
 637         [1] = &clk_pcmcdclk1,
 638         [2] = &clk_sclk_hdmi27m,
 639         [3] = &clk_sclk_usbphy0,
 640         [4] = &clk_sclk_usbphy1,
 641         [5] = &clk_sclk_hdmiphy,
 642         [6] = &clk_mout_mpll.clk,
 643         [7] = &clk_mout_epll.clk,
 644         [8] = &clk_sclk_vpll.clk,
 645 };
 646
 647 static struct clksrc_sources clkset_sclk_audio1 = {
 648         .sources        = clkset_sclk_audio1_list,
 649         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 650 };
 651
 652 static struct clksrc_clk clk_sclk_audio1 = {
 653         .clk            = {
 654                 .name           = "sclk_audio",
 655                 .id             = 1,
 656                 .enable         = s5pv210_clk_mask0_ctrl,
 657                 .ctrlbit        = (1 << 25),
 658         },
 659         .sources = &clkset_sclk_audio1,
 660         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 661         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 662 };
 663
 664 static struct clk *clkset_sclk_audio2_list[] = {
 665         [0] = &clk_ext_xtal_mux,
 666         [1] = &clk_pcmcdclk0,
 667         [2] = &clk_sclk_hdmi27m,
 668         [3] = &clk_sclk_usbphy0,
 669         [4] = &clk_sclk_usbphy1,
 670         [5] = &clk_sclk_hdmiphy,
 671         [6] = &clk_mout_mpll.clk,
 672         [7] = &clk_mout_epll.clk,
 673         [8] = &clk_sclk_vpll.clk,
 674 };
 675
 676 static struct clksrc_sources clkset_sclk_audio2 = {
 677         .sources        = clkset_sclk_audio2_list,
 678         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 679 };
 680
 681 static struct clksrc_clk clk_sclk_audio2 = {
 682         .clk            = {
 683                 .name           = "sclk_audio",
 684                 .id             = 2,
 685                 .enable         = s5pv210_clk_mask0_ctrl,
 686                 .ctrlbit        = (1 << 26),
 687         },
 688         .sources = &clkset_sclk_audio2,
 689         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 690         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 691 };
 692
 693 static struct clk *clkset_sclk_spdif_list[] = {
 694         [0] = &clk_sclk_audio0.clk,
 695         [1] = &clk_sclk_audio1.clk,
 696         [2] = &clk_sclk_audio2.clk,
 697 };
 698
 699 static struct clksrc_sources clkset_sclk_spdif = {
 700         .sources        = clkset_sclk_spdif_list,
 701         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 702 };
 703
 704 static struct clk *clkset_group2_list[] = {
 705         [0] = &clk_ext_xtal_mux,
 706         [1] = &clk_xusbxti,
 707         [2] = &clk_sclk_hdmi27m,
 708         [3] = &clk_sclk_usbphy0,
 709         [4] = &clk_sclk_usbphy1,
 710         [5] = &clk_sclk_hdmiphy,
 711         [6] = &clk_mout_mpll.clk,
 712         [7] = &clk_mout_epll.clk,
 713         [8] = &clk_sclk_vpll.clk,
 714 };
 715
 716 static struct clksrc_sources clkset_group2 = {
 717         .sources        = clkset_group2_list,
 718         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 719 };
 720
 721 static struct clksrc_clk clksrcs[] = {
 722         {
 723                 .clk    = {
 724                         .name           = "sclk_dmc",
 725                         .id             = -1,
 726                 },
 727                 .sources = &clkset_group1,
 728                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 729                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 730         }, {
 731                 .clk    = {
 732                         .name           = "sclk_onenand",
 733                         .id             = -1,
 734                 },
 735                 .sources = &clkset_sclk_onenand,
 736                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 737                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 738         }, {
 739                 .clk    = {
 740                         .name           = "uclk1",
 741                         .id             = 0,
 742                         .enable         = s5pv210_clk_mask0_ctrl,
 743                         .ctrlbit        = (1 << 12),
 744                 },
 745                 .sources = &clkset_uart,
 746                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 747                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 748         }, {
 749                 .clk            = {
 750                         .name           = "uclk1",
 751                         .id             = 1,
 752                         .enable         = s5pv210_clk_mask0_ctrl,
 753                         .ctrlbit        = (1 << 13),
 754                 },
 755                 .sources = &clkset_uart,
 756                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
 757                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 758         }, {
 759                 .clk            = {
 760                         .name           = "uclk1",
 761                         .id             = 2,
 762                         .enable         = s5pv210_clk_mask0_ctrl,
 763                         .ctrlbit        = (1 << 14),
 764                 },
 765                 .sources = &clkset_uart,
 766                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
 767                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
 768         }, {
 769                 .clk            = {
 770                         .name           = "uclk1",
 771                         .id             = 3,
 772                         .enable         = s5pv210_clk_mask0_ctrl,
 773                         .ctrlbit        = (1 << 15),
 774                 },
 775                 .sources = &clkset_uart,
 776                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
 777                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 778         }, {
 779                 .clk    = {
 780                         .name           = "sclk_mixer",
 781                         .id             = -1,
 782                         .enable         = s5pv210_clk_mask0_ctrl,
 783                         .ctrlbit        = (1 << 1),
 784                 },
 785                 .sources = &clkset_sclk_mixer,
 786                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 787         }, {
 788                 .clk            = {
 789                         .name           = "sclk_spdif",
 790                         .id             = -1,
 791                         .enable         = s5pv210_clk_mask0_ctrl,
 792                         .ctrlbit        = (1 << 27),
 793                 },
 794                 .sources = &clkset_sclk_spdif,
 795                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 796         }, {
 797                 .clk    = {
 798                         .name           = "sclk_fimc",
 799                         .id             = 0,
 800                         .enable         = s5pv210_clk_mask1_ctrl,
 801                         .ctrlbit        = (1 << 2),
 802                 },
 803                 .sources = &clkset_group2,
 804                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 805                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 806         }, {
 807                 .clk    = {
 808                         .name           = "sclk_fimc",
 809                         .id             = 1,
 810                         .enable         = s5pv210_clk_mask1_ctrl,
 811                         .ctrlbit        = (1 << 3),
 812                 },
 813                 .sources = &clkset_group2,
 814                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 815                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 816         }, {
 817                 .clk    = {
 818                         .name           = "sclk_fimc",
 819                         .id             = 2,
 820                         .enable         = s5pv210_clk_mask1_ctrl,
 821                         .ctrlbit        = (1 << 4),
 822                 },
 823                 .sources = &clkset_group2,
 824                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 825                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 826         }, {
 827                 .clk            = {
 828                         .name           = "sclk_cam",
 829                         .id             = 0,
 830                         .enable         = s5pv210_clk_mask0_ctrl,
 831                         .ctrlbit        = (1 << 3),
 832                 },
 833                 .sources = &clkset_group2,
 834                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 835                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 836         }, {
 837                 .clk            = {
 838                         .name           = "sclk_cam",
 839                         .id             = 1,
 840                         .enable         = s5pv210_clk_mask0_ctrl,
 841                         .ctrlbit        = (1 << 4),
 842                 },
 843                 .sources = &clkset_group2,
 844                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 845                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 846         }, {
 847                 .clk            = {
 848                         .name           = "sclk_fimd",
 849                         .id             = -1,
 850                         .enable         = s5pv210_clk_mask0_ctrl,
 851                         .ctrlbit        = (1 << 5),
 852                 },
 853                 .sources = &clkset_group2,
 854                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 855                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 856         }, {
 857                 .clk            = {
 858                         .name           = "sclk_mmc",
 859                         .id             = 0,
 860                         .enable         = s5pv210_clk_mask0_ctrl,
 861                         .ctrlbit        = (1 << 8),
 862                 },
 863                 .sources = &clkset_group2,
 864                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 865                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 866         }, {
 867                 .clk            = {
 868                         .name           = "sclk_mmc",
 869                         .id             = 1,
 870                         .enable         = s5pv210_clk_mask0_ctrl,
 871                         .ctrlbit        = (1 << 9),
 872                 },
 873                 .sources = &clkset_group2,
 874                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 875                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 876         }, {
 877                 .clk            = {
 878                         .name           = "sclk_mmc",
 879                         .id             = 2,
 880                         .enable         = s5pv210_clk_mask0_ctrl,
 881                         .ctrlbit        = (1 << 10),
 882                 },
 883                 .sources = &clkset_group2,
 884                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 885                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 886         }, {
 887                 .clk            = {
 888                         .name           = "sclk_mmc",
 889                         .id             = 3,
 890                         .enable         = s5pv210_clk_mask0_ctrl,
 891                         .ctrlbit        = (1 << 11),
 892                 },
 893                 .sources = &clkset_group2,
 894                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 895                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 896         }, {
 897                 .clk            = {
 898                         .name           = "sclk_mfc",
 899                         .id             = -1,
 900                         .enable         = s5pv210_clk_ip0_ctrl,
 901                         .ctrlbit        = (1 << 16),
 902                 },
 903                 .sources = &clkset_group1,
 904                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 905                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 906         }, {
 907                 .clk            = {
 908                         .name           = "sclk_g2d",
 909                         .id             = -1,
 910                         .enable         = s5pv210_clk_ip0_ctrl,
 911                         .ctrlbit        = (1 << 12),
 912                 },
 913                 .sources = &clkset_group1,
 914                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 915                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 916         }, {
 917                 .clk            = {
 918                         .name           = "sclk_g3d",
 919                         .id             = -1,
 920                         .enable         = s5pv210_clk_ip0_ctrl,
 921                         .ctrlbit        = (1 << 8),
 922                 },
 923                 .sources = &clkset_group1,
 924                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 925                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 926         }, {
 927                 .clk            = {
 928                         .name           = "sclk_csis",
 929                         .id             = -1,
 930                         .enable         = s5pv210_clk_mask0_ctrl,
 931                         .ctrlbit        = (1 << 6),
 932                 },
 933                 .sources = &clkset_group2,
 934                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 935                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 936         }, {
 937                 .clk            = {
 938                         .name           = "sclk_spi",
 939                         .id             = 0,
 940                         .enable         = s5pv210_clk_mask0_ctrl,
 941                         .ctrlbit        = (1 << 16),
 942                 },
 943                 .sources = &clkset_group2,
 944                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
 945                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
 946         }, {
 947                 .clk            = {
 948                         .name           = "sclk_spi",
 949                         .id             = 1,
 950                         .enable         = s5pv210_clk_mask0_ctrl,
 951                         .ctrlbit        = (1 << 17),
 952                 },
 953                 .sources = &clkset_group2,
 954                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
 955                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
 956         }, {
 957                 .clk            = {
 958                         .name           = "sclk_pwi",
 959                         .id             = -1,
 960                         .enable         = s5pv210_clk_mask0_ctrl,
 961                         .ctrlbit        = (1 << 29),
 962                 },
 963                 .sources = &clkset_group2,
 964                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
 965                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
 966         }, {
 967                 .clk            = {
 968                         .name           = "sclk_pwm",
 969                         .id             = -1,
 970                         .enable         = s5pv210_clk_mask0_ctrl,
 971                         .ctrlbit        = (1 << 19),
 972                 },
 973                 .sources = &clkset_group2,
 974                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
 975                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
 976         },
 977 };
 978
 979 /* Clock initialisation code */
 980 static struct clksrc_clk *sysclks[] = {
 981         &clk_mout_apll,
 982         &clk_mout_epll,
 983         &clk_mout_mpll,
 984         &clk_armclk,
 985         &clk_hclk_msys,
 986         &clk_sclk_a2m,
 987         &clk_hclk_dsys,
 988         &clk_hclk_psys,
 989         &clk_pclk_msys,
 990         &clk_pclk_dsys,
 991         &clk_pclk_psys,
 992         &clk_vpllsrc,
 993         &clk_sclk_vpll,
 994         &clk_sclk_dac,
 995         &clk_sclk_pixel,
 996         &clk_sclk_hdmi,
 997         &clk_mout_dmc0,
 998         &clk_sclk_dmc0,
 999 };
1000
1001 void __init_or_cpufreq s5pv210_setup_clocks(void)
1002 {
1003         struct clk *xtal_clk;
1004         unsigned long vpllsrc;
1005         unsigned long armclk;
1006         unsigned long hclk_msys;
1007         unsigned long hclk_dsys;
1008         unsigned long hclk_psys;
1009         unsigned long pclk_msys;
1010         unsigned long pclk_dsys;
1011         unsigned long pclk_psys;
1012         unsigned long apll;
1013         unsigned long mpll;
1014         unsigned long epll;
1015         unsigned long vpll;
1016         unsigned int ptr;
1017         u32 clkdiv0, clkdiv1;
1018
1019         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1020
1021         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1022         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1023
1024         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1025                                 __func__, clkdiv0, clkdiv1);
1026
1027         xtal_clk = clk_get(NULL, "xtal");
1028         BUG_ON(IS_ERR(xtal_clk));
1029
1030         xtal = clk_get_rate(xtal_clk);
1031         clk_put(xtal_clk);
1032
1033         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1034
1035         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1036         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1037         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
1038         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1039         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1040
1041         clk_fout_apll.ops = &clk_fout_apll_ops;
1042         clk_fout_mpll.rate = mpll;
1043         clk_fout_epll.rate = epll;
1044         clk_fout_vpll.rate = vpll;
1045
1046         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1047                         apll, mpll, epll, vpll);
1048
1049         armclk = clk_get_rate(&clk_armclk.clk);
1050         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1051         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1052         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1053         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1054         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1055         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1056
1057         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1058                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1059                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1060                         pclk_msys, pclk_dsys, pclk_psys);
1061
1062         clk_f.rate = armclk;
1063         clk_h.rate = hclk_psys;
1064         clk_p.rate = pclk_psys;
1065
1066         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1067                 s3c_set_clksrc(&clksrcs[ptr], true);
1068 }
1069
1070 static struct clk *clks[] __initdata = {
1071         &clk_sclk_hdmi27m,
1072         &clk_sclk_hdmiphy,
1073         &clk_sclk_usbphy0,
1074         &clk_sclk_usbphy1,
1075         &clk_pcmcdclk0,
1076         &clk_pcmcdclk1,
1077         &clk_pcmcdclk2,
1078 };
1079
1080 void __init s5pv210_register_clocks(void)
1081 {
1082         struct clk *clkp;
1083         int ret;
1084         int ptr;
1085
1086         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1087         if (ret > 0)
1088                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1089
1090         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1091                 s3c_register_clksrc(sysclks[ptr], 1);
1092
1093         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1094         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1095
1096         clkp = init_clocks_disable;
1097         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1098                 ret = s3c24xx_register_clock(clkp);
1099                 if (ret < 0) {
1100                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
1101                                clkp->name, ret);
1102                 }
1103                 (clkp->enable)(clkp, 0);
1104         }
1105
1106         s3c_pwmclk_init();
1107 }