arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static struct clksrc_clk clk_mout_apll = {
  35         .clk    = {
  36                 .name           = "mout_apll",
  37                 .id             = -1,
  38         },
  39         .sources        = &clk_src_apll,
  40         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  41 };
  42
  43 static struct clksrc_clk clk_mout_epll = {
  44         .clk    = {
  45                 .name           = "mout_epll",
  46                 .id             = -1,
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55                 .id             = -1,
  56         },
  57         .sources        = &clk_src_mpll,
  58         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  59 };
  60
  61 static struct clk *clkset_armclk_list[] = {
  62         [0] = &clk_mout_apll.clk,
  63         [1] = &clk_mout_mpll.clk,
  64 };
  65
  66 static struct clksrc_sources clkset_armclk = {
  67         .sources        = clkset_armclk_list,
  68         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  69 };
  70
  71 static struct clksrc_clk clk_armclk = {
  72         .clk    = {
  73                 .name           = "armclk",
  74                 .id             = -1,
  75         },
  76         .sources        = &clkset_armclk,
  77         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  78         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  79 };
  80
  81 static struct clksrc_clk clk_hclk_msys = {
  82         .clk    = {
  83                 .name           = "hclk_msys",
  84                 .id             = -1,
  85                 .parent         = &clk_armclk.clk,
  86         },
  87         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  88 };
  89
  90 static struct clksrc_clk clk_pclk_msys = {
  91         .clk    = {
  92                 .name           = "pclk_msys",
  93                 .id             = -1,
  94                 .parent         = &clk_hclk_msys.clk,
  95         },
  96         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  97 };
  98
  99 static struct clksrc_clk clk_sclk_a2m = {
 100         .clk    = {
 101                 .name           = "sclk_a2m",
 102                 .id             = -1,
 103                 .parent         = &clk_mout_apll.clk,
 104         },
 105         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 106 };
 107
 108 static struct clk *clkset_hclk_sys_list[] = {
 109         [0] = &clk_mout_mpll.clk,
 110         [1] = &clk_sclk_a2m.clk,
 111 };
 112
 113 static struct clksrc_sources clkset_hclk_sys = {
 114         .sources        = clkset_hclk_sys_list,
 115         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 116 };
 117
 118 static struct clksrc_clk clk_hclk_dsys = {
 119         .clk    = {
 120                 .name   = "hclk_dsys",
 121                 .id     = -1,
 122         },
 123         .sources        = &clkset_hclk_sys,
 124         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 125         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 126 };
 127
 128 static struct clksrc_clk clk_pclk_dsys = {
 129         .clk    = {
 130                 .name   = "pclk_dsys",
 131                 .id     = -1,
 132                 .parent = &clk_hclk_dsys.clk,
 133         },
 134         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 135 };
 136
 137 static struct clksrc_clk clk_hclk_psys = {
 138         .clk    = {
 139                 .name   = "hclk_psys",
 140                 .id     = -1,
 141         },
 142         .sources        = &clkset_hclk_sys,
 143         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 145 };
 146
 147 static struct clksrc_clk clk_pclk_psys = {
 148         .clk    = {
 149                 .name   = "pclk_psys",
 150                 .id     = -1,
 151                 .parent = &clk_hclk_psys.clk,
 152         },
 153         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 154 };
 155
 156 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 157 {
 158         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 159 }
 160
 161 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 162 {
 163         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 164 }
 165
 166 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 167 {
 168         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 169 }
 170
 171 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 172 {
 173         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 174 }
 175
 176 static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
 177 {
 178         return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
 179 }
 180
 181 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 182 {
 183         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 184 }
 185
 186 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 187 {
 188         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 189 }
 190
 191 static struct clk clk_sclk_hdmi27m = {
 192         .name           = "sclk_hdmi27m",
 193         .id             = -1,
 194         .rate           = 27000000,
 195 };
 196
 197 static struct clk clk_sclk_hdmiphy = {
 198         .name           = "sclk_hdmiphy",
 199         .id             = -1,
 200 };
 201
 202 static struct clk clk_sclk_usbphy0 = {
 203         .name           = "sclk_usbphy0",
 204         .id             = -1,
 205 };
 206
 207 static struct clk clk_sclk_usbphy1 = {
 208         .name           = "sclk_usbphy1",
 209         .id             = -1,
 210 };
 211
 212 static struct clk clk_pcmcdclk0 = {
 213         .name           = "pcmcdclk",
 214         .id             = -1,
 215 };
 216
 217 static struct clk clk_pcmcdclk1 = {
 218         .name           = "pcmcdclk",
 219         .id             = -1,
 220 };
 221
 222 static struct clk clk_pcmcdclk2 = {
 223         .name           = "pcmcdclk",
 224         .id             = -1,
 225 };
 226
 227 static struct clk *clkset_vpllsrc_list[] = {
 228         [0] = &clk_fin_vpll,
 229         [1] = &clk_sclk_hdmi27m,
 230 };
 231
 232 static struct clksrc_sources clkset_vpllsrc = {
 233         .sources        = clkset_vpllsrc_list,
 234         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 235 };
 236
 237 static struct clksrc_clk clk_vpllsrc = {
 238         .clk    = {
 239                 .name           = "vpll_src",
 240                 .id             = -1,
 241                 .enable         = s5pv210_clk_mask0_ctrl,
 242                 .ctrlbit        = (1 << 7),
 243         },
 244         .sources        = &clkset_vpllsrc,
 245         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 246 };
 247
 248 static struct clk *clkset_sclk_vpll_list[] = {
 249         [0] = &clk_vpllsrc.clk,
 250         [1] = &clk_fout_vpll,
 251 };
 252
 253 static struct clksrc_sources clkset_sclk_vpll = {
 254         .sources        = clkset_sclk_vpll_list,
 255         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 256 };
 257
 258 static struct clksrc_clk clk_sclk_vpll = {
 259         .clk    = {
 260                 .name           = "sclk_vpll",
 261                 .id             = -1,
 262         },
 263         .sources        = &clkset_sclk_vpll,
 264         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 265 };
 266
 267 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 268 {
 269         return clk_get_rate(clk->parent) / 2;
 270 }
 271
 272 static struct clk_ops clk_hclk_imem_ops = {
 273         .get_rate       = s5pv210_clk_imem_get_rate,
 274 };
 275
 276 static struct clk init_clocks_disable[] = {
 277         {
 278                 .name           = "rot",
 279                 .id             = -1,
 280                 .parent         = &clk_hclk_dsys.clk,
 281                 .enable         = s5pv210_clk_ip0_ctrl,
 282                 .ctrlbit        = (1<<29),
 283         }, {
 284                 .name           = "fimc",
 285                 .id             = 0,
 286                 .parent         = &clk_hclk_dsys.clk,
 287                 .enable         = s5pv210_clk_ip0_ctrl,
 288                 .ctrlbit        = (1 << 24),
 289         }, {
 290                 .name           = "fimc",
 291                 .id             = 1,
 292                 .parent         = &clk_hclk_dsys.clk,
 293                 .enable         = s5pv210_clk_ip0_ctrl,
 294                 .ctrlbit        = (1 << 25),
 295         }, {
 296                 .name           = "fimc",
 297                 .id             = 2,
 298                 .parent         = &clk_hclk_dsys.clk,
 299                 .enable         = s5pv210_clk_ip0_ctrl,
 300                 .ctrlbit        = (1 << 26),
 301         }, {
 302                 .name           = "otg",
 303                 .id             = -1,
 304                 .parent         = &clk_hclk_psys.clk,
 305                 .enable         = s5pv210_clk_ip1_ctrl,
 306                 .ctrlbit        = (1<<16),
 307         }, {
 308                 .name           = "usb-host",
 309                 .id             = -1,
 310                 .parent         = &clk_hclk_psys.clk,
 311                 .enable         = s5pv210_clk_ip1_ctrl,
 312                 .ctrlbit        = (1<<17),
 313         }, {
 314                 .name           = "lcd",
 315                 .id             = -1,
 316                 .parent         = &clk_hclk_dsys.clk,
 317                 .enable         = s5pv210_clk_ip1_ctrl,
 318                 .ctrlbit        = (1<<0),
 319         }, {
 320                 .name           = "cfcon",
 321                 .id             = 0,
 322                 .parent         = &clk_hclk_psys.clk,
 323                 .enable         = s5pv210_clk_ip1_ctrl,
 324                 .ctrlbit        = (1<<25),
 325         }, {
 326                 .name           = "hsmmc",
 327                 .id             = 0,
 328                 .parent         = &clk_hclk_psys.clk,
 329                 .enable         = s5pv210_clk_ip2_ctrl,
 330                 .ctrlbit        = (1<<16),
 331         }, {
 332                 .name           = "hsmmc",
 333                 .id             = 1,
 334                 .parent         = &clk_hclk_psys.clk,
 335                 .enable         = s5pv210_clk_ip2_ctrl,
 336                 .ctrlbit        = (1<<17),
 337         }, {
 338                 .name           = "hsmmc",
 339                 .id             = 2,
 340                 .parent         = &clk_hclk_psys.clk,
 341                 .enable         = s5pv210_clk_ip2_ctrl,
 342                 .ctrlbit        = (1<<18),
 343         }, {
 344                 .name           = "hsmmc",
 345                 .id             = 3,
 346                 .parent         = &clk_hclk_psys.clk,
 347                 .enable         = s5pv210_clk_ip2_ctrl,
 348                 .ctrlbit        = (1<<19),
 349         }, {
 350                 .name           = "systimer",
 351                 .id             = -1,
 352                 .parent         = &clk_pclk_psys.clk,
 353                 .enable         = s5pv210_clk_ip3_ctrl,
 354                 .ctrlbit        = (1<<16),
 355         }, {
 356                 .name           = "watchdog",
 357                 .id             = -1,
 358                 .parent         = &clk_pclk_psys.clk,
 359                 .enable         = s5pv210_clk_ip3_ctrl,
 360                 .ctrlbit        = (1<<22),
 361         }, {
 362                 .name           = "rtc",
 363                 .id             = -1,
 364                 .parent         = &clk_pclk_psys.clk,
 365                 .enable         = s5pv210_clk_ip3_ctrl,
 366                 .ctrlbit        = (1<<15),
 367         }, {
 368                 .name           = "i2c",
 369                 .id             = 0,
 370                 .parent         = &clk_pclk_psys.clk,
 371                 .enable         = s5pv210_clk_ip3_ctrl,
 372                 .ctrlbit        = (1<<7),
 373         }, {
 374                 .name           = "i2c",
 375                 .id             = 1,
 376                 .parent         = &clk_pclk_psys.clk,
 377                 .enable         = s5pv210_clk_ip3_ctrl,
 378                 .ctrlbit        = (1 << 10),
 379         }, {
 380                 .name           = "i2c",
 381                 .id             = 2,
 382                 .parent         = &clk_pclk_psys.clk,
 383                 .enable         = s5pv210_clk_ip3_ctrl,
 384                 .ctrlbit        = (1<<9),
 385         }, {
 386                 .name           = "spi",
 387                 .id             = 0,
 388                 .parent         = &clk_pclk_psys.clk,
 389                 .enable         = s5pv210_clk_ip3_ctrl,
 390                 .ctrlbit        = (1<<12),
 391         }, {
 392                 .name           = "spi",
 393                 .id             = 1,
 394                 .parent         = &clk_pclk_psys.clk,
 395                 .enable         = s5pv210_clk_ip3_ctrl,
 396                 .ctrlbit        = (1<<13),
 397         }, {
 398                 .name           = "spi",
 399                 .id             = 2,
 400                 .parent         = &clk_pclk_psys.clk,
 401                 .enable         = s5pv210_clk_ip3_ctrl,
 402                 .ctrlbit        = (1<<14),
 403         }, {
 404                 .name           = "timers",
 405                 .id             = -1,
 406                 .parent         = &clk_pclk_psys.clk,
 407                 .enable         = s5pv210_clk_ip3_ctrl,
 408                 .ctrlbit        = (1<<23),
 409         }, {
 410                 .name           = "adc",
 411                 .id             = -1,
 412                 .parent         = &clk_pclk_psys.clk,
 413                 .enable         = s5pv210_clk_ip3_ctrl,
 414                 .ctrlbit        = (1<<24),
 415         }, {
 416                 .name           = "keypad",
 417                 .id             = -1,
 418                 .parent         = &clk_pclk_psys.clk,
 419                 .enable         = s5pv210_clk_ip3_ctrl,
 420                 .ctrlbit        = (1<<21),
 421         }, {
 422                 .name           = "i2s_v50",
 423                 .id             = 0,
 424                 .parent         = &clk_p,
 425                 .enable         = s5pv210_clk_ip3_ctrl,
 426                 .ctrlbit        = (1<<4),
 427         }, {
 428                 .name           = "i2s_v32",
 429                 .id             = 0,
 430                 .parent         = &clk_p,
 431                 .enable         = s5pv210_clk_ip3_ctrl,
 432                 .ctrlbit        = (1 << 5),
 433         }, {
 434                 .name           = "i2s_v32",
 435                 .id             = 1,
 436                 .parent         = &clk_p,
 437                 .enable         = s5pv210_clk_ip3_ctrl,
 438                 .ctrlbit        = (1 << 6),
 439         },
 440 };
 441
 442 static struct clk init_clocks[] = {
 443         {
 444                 .name           = "hclk_imem",
 445                 .id             = -1,
 446                 .parent         = &clk_hclk_msys.clk,
 447                 .ctrlbit        = (1 << 5),
 448                 .enable         = s5pv210_clk_ip0_ctrl,
 449                 .ops            = &clk_hclk_imem_ops,
 450         }, {
 451                 .name           = "uart",
 452                 .id             = 0,
 453                 .parent         = &clk_pclk_psys.clk,
 454                 .enable         = s5pv210_clk_ip3_ctrl,
 455                 .ctrlbit        = (1 << 17),
 456         }, {
 457                 .name           = "uart",
 458                 .id             = 1,
 459                 .parent         = &clk_pclk_psys.clk,
 460                 .enable         = s5pv210_clk_ip3_ctrl,
 461                 .ctrlbit        = (1 << 18),
 462         }, {
 463                 .name           = "uart",
 464                 .id             = 2,
 465                 .parent         = &clk_pclk_psys.clk,
 466                 .enable         = s5pv210_clk_ip3_ctrl,
 467                 .ctrlbit        = (1 << 19),
 468         }, {
 469                 .name           = "uart",
 470                 .id             = 3,
 471                 .parent         = &clk_pclk_psys.clk,
 472                 .enable         = s5pv210_clk_ip3_ctrl,
 473                 .ctrlbit        = (1 << 20),
 474         },
 475 };
 476
 477 static struct clk *clkset_uart_list[] = {
 478         [6] = &clk_mout_mpll.clk,
 479         [7] = &clk_mout_epll.clk,
 480 };
 481
 482 static struct clksrc_sources clkset_uart = {
 483         .sources        = clkset_uart_list,
 484         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 485 };
 486
 487 static struct clk *clkset_group1_list[] = {
 488         [0] = &clk_sclk_a2m.clk,
 489         [1] = &clk_mout_mpll.clk,
 490         [2] = &clk_mout_epll.clk,
 491         [3] = &clk_sclk_vpll.clk,
 492 };
 493
 494 static struct clksrc_sources clkset_group1 = {
 495         .sources        = clkset_group1_list,
 496         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 497 };
 498
 499 static struct clk *clkset_sclk_onenand_list[] = {
 500         [0] = &clk_hclk_psys.clk,
 501         [1] = &clk_hclk_dsys.clk,
 502 };
 503
 504 static struct clksrc_sources clkset_sclk_onenand = {
 505         .sources        = clkset_sclk_onenand_list,
 506         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 507 };
 508
 509 static struct clk *clkset_sclk_dac_list[] = {
 510         [0] = &clk_sclk_vpll.clk,
 511         [1] = &clk_sclk_hdmiphy,
 512 };
 513
 514 static struct clksrc_sources clkset_sclk_dac = {
 515         .sources        = clkset_sclk_dac_list,
 516         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 517 };
 518
 519 static struct clksrc_clk clk_sclk_dac = {
 520         .clk            = {
 521                 .name           = "sclk_dac",
 522                 .id             = -1,
 523                 .enable         = s5pv210_clk_mask0_ctrl,
 524                 .ctrlbit        = (1 << 2),
 525         },
 526         .sources        = &clkset_sclk_dac,
 527         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 528 };
 529
 530 static struct clksrc_clk clk_sclk_pixel = {
 531         .clk            = {
 532                 .name           = "sclk_pixel",
 533                 .id             = -1,
 534                 .parent         = &clk_sclk_vpll.clk,
 535         },
 536         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 537 };
 538
 539 static struct clk *clkset_sclk_hdmi_list[] = {
 540         [0] = &clk_sclk_pixel.clk,
 541         [1] = &clk_sclk_hdmiphy,
 542 };
 543
 544 static struct clksrc_sources clkset_sclk_hdmi = {
 545         .sources        = clkset_sclk_hdmi_list,
 546         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 547 };
 548
 549 static struct clksrc_clk clk_sclk_hdmi = {
 550         .clk            = {
 551                 .name           = "sclk_hdmi",
 552                 .id             = -1,
 553                 .enable         = s5pv210_clk_mask0_ctrl,
 554                 .ctrlbit        = (1 << 0),
 555         },
 556         .sources        = &clkset_sclk_hdmi,
 557         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 558 };
 559
 560 static struct clk *clkset_sclk_mixer_list[] = {
 561         [0] = &clk_sclk_dac.clk,
 562         [1] = &clk_sclk_hdmi.clk,
 563 };
 564
 565 static struct clksrc_sources clkset_sclk_mixer = {
 566         .sources        = clkset_sclk_mixer_list,
 567         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 568 };
 569
 570 static struct clk *clkset_sclk_audio0_list[] = {
 571         [0] = &clk_ext_xtal_mux,
 572         [1] = &clk_pcmcdclk0,
 573         [2] = &clk_sclk_hdmi27m,
 574         [3] = &clk_sclk_usbphy0,
 575         [4] = &clk_sclk_usbphy1,
 576         [5] = &clk_sclk_hdmiphy,
 577         [6] = &clk_mout_mpll.clk,
 578         [7] = &clk_mout_epll.clk,
 579         [8] = &clk_sclk_vpll.clk,
 580 };
 581
 582 static struct clksrc_sources clkset_sclk_audio0 = {
 583         .sources        = clkset_sclk_audio0_list,
 584         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 585 };
 586
 587 static struct clksrc_clk clk_sclk_audio0 = {
 588         .clk            = {
 589                 .name           = "sclk_audio",
 590                 .id             = 0,
 591                 .enable         = s5pv210_clk_mask0_ctrl,
 592                 .ctrlbit        = (1 << 24),
 593         },
 594         .sources = &clkset_sclk_audio0,
 595         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 596         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 597 };
 598
 599 static struct clk *clkset_sclk_audio1_list[] = {
 600         [0] = &clk_ext_xtal_mux,
 601         [1] = &clk_pcmcdclk1,
 602         [2] = &clk_sclk_hdmi27m,
 603         [3] = &clk_sclk_usbphy0,
 604         [4] = &clk_sclk_usbphy1,
 605         [5] = &clk_sclk_hdmiphy,
 606         [6] = &clk_mout_mpll.clk,
 607         [7] = &clk_mout_epll.clk,
 608         [8] = &clk_sclk_vpll.clk,
 609 };
 610
 611 static struct clksrc_sources clkset_sclk_audio1 = {
 612         .sources        = clkset_sclk_audio1_list,
 613         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 614 };
 615
 616 static struct clksrc_clk clk_sclk_audio1 = {
 617         .clk            = {
 618                 .name           = "sclk_audio",
 619                 .id             = 1,
 620                 .enable         = s5pv210_clk_mask0_ctrl,
 621                 .ctrlbit        = (1 << 25),
 622         },
 623         .sources = &clkset_sclk_audio1,
 624         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 625         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 626 };
 627
 628 static struct clk *clkset_sclk_audio2_list[] = {
 629         [0] = &clk_ext_xtal_mux,
 630         [1] = &clk_pcmcdclk0,
 631         [2] = &clk_sclk_hdmi27m,
 632         [3] = &clk_sclk_usbphy0,
 633         [4] = &clk_sclk_usbphy1,
 634         [5] = &clk_sclk_hdmiphy,
 635         [6] = &clk_mout_mpll.clk,
 636         [7] = &clk_mout_epll.clk,
 637         [8] = &clk_sclk_vpll.clk,
 638 };
 639
 640 static struct clksrc_sources clkset_sclk_audio2 = {
 641         .sources        = clkset_sclk_audio2_list,
 642         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 643 };
 644
 645 static struct clksrc_clk clk_sclk_audio2 = {
 646         .clk            = {
 647                 .name           = "sclk_audio",
 648                 .id             = 2,
 649                 .enable         = s5pv210_clk_mask0_ctrl,
 650                 .ctrlbit        = (1 << 26),
 651         },
 652         .sources = &clkset_sclk_audio2,
 653         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 654         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 655 };
 656
 657 static struct clk *clkset_sclk_spdif_list[] = {
 658         [0] = &clk_sclk_audio0.clk,
 659         [1] = &clk_sclk_audio1.clk,
 660         [2] = &clk_sclk_audio2.clk,
 661 };
 662
 663 static struct clksrc_sources clkset_sclk_spdif = {
 664         .sources        = clkset_sclk_spdif_list,
 665         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 666 };
 667
 668 static struct clk *clkset_group2_list[] = {
 669         [0] = &clk_ext_xtal_mux,
 670         [1] = &clk_xusbxti,
 671         [2] = &clk_sclk_hdmi27m,
 672         [3] = &clk_sclk_usbphy0,
 673         [4] = &clk_sclk_usbphy1,
 674         [5] = &clk_sclk_hdmiphy,
 675         [6] = &clk_mout_mpll.clk,
 676         [7] = &clk_mout_epll.clk,
 677         [8] = &clk_sclk_vpll.clk,
 678 };
 679
 680 static struct clksrc_sources clkset_group2 = {
 681         .sources        = clkset_group2_list,
 682         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 683 };
 684
 685 static struct clksrc_clk clksrcs[] = {
 686         {
 687                 .clk    = {
 688                         .name           = "sclk_dmc",
 689                         .id             = -1,
 690                 },
 691                 .sources = &clkset_group1,
 692                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 693                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 694         }, {
 695                 .clk    = {
 696                         .name           = "sclk_onenand",
 697                         .id             = -1,
 698                 },
 699                 .sources = &clkset_sclk_onenand,
 700                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 701                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 702         }, {
 703                 .clk    = {
 704                         .name           = "uclk1",
 705                         .id             = 0,
 706                         .enable         = s5pv210_clk_mask0_ctrl,
 707                         .ctrlbit        = (1 << 12),
 708                 },
 709                 .sources = &clkset_uart,
 710                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 711                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 712         }, {
 713                 .clk            = {
 714                         .name           = "uclk1",
 715                         .id             = 1,
 716                         .enable         = s5pv210_clk_mask0_ctrl,
 717                         .ctrlbit        = (1 << 13),
 718                 },
 719                 .sources = &clkset_uart,
 720                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
 721                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 722         }, {
 723                 .clk            = {
 724                         .name           = "uclk1",
 725                         .id             = 2,
 726                         .enable         = s5pv210_clk_mask0_ctrl,
 727                         .ctrlbit        = (1 << 14),
 728                 },
 729                 .sources = &clkset_uart,
 730                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
 731                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
 732         }, {
 733                 .clk            = {
 734                         .name           = "uclk1",
 735                         .id             = 3,
 736                         .enable         = s5pv210_clk_mask0_ctrl,
 737                         .ctrlbit        = (1 << 15),
 738                 },
 739                 .sources = &clkset_uart,
 740                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
 741                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 742         }, {
 743                 .clk    = {
 744                         .name           = "sclk_mixer",
 745                         .id             = -1,
 746                         .enable         = s5pv210_clk_mask0_ctrl,
 747                         .ctrlbit        = (1 << 1),
 748                 },
 749                 .sources = &clkset_sclk_mixer,
 750                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 751         }, {
 752                 .clk            = {
 753                         .name           = "sclk_spdif",
 754                         .id             = -1,
 755                         .enable         = s5pv210_clk_mask0_ctrl,
 756                         .ctrlbit        = (1 << 27),
 757                 },
 758                 .sources = &clkset_sclk_spdif,
 759                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 760         }, {
 761                 .clk    = {
 762                         .name           = "sclk_fimc",
 763                         .id             = 0,
 764                         .enable         = s5pv210_clk_mask1_ctrl,
 765                         .ctrlbit        = (1 << 2),
 766                 },
 767                 .sources = &clkset_group2,
 768                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 769                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 770         }, {
 771                 .clk    = {
 772                         .name           = "sclk_fimc",
 773                         .id             = 1,
 774                         .enable         = s5pv210_clk_mask1_ctrl,
 775                         .ctrlbit        = (1 << 3),
 776                 },
 777                 .sources = &clkset_group2,
 778                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 779                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 780         }, {
 781                 .clk    = {
 782                         .name           = "sclk_fimc",
 783                         .id             = 2,
 784                         .enable         = s5pv210_clk_mask1_ctrl,
 785                         .ctrlbit        = (1 << 4),
 786                 },
 787                 .sources = &clkset_group2,
 788                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 789                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 790         }, {
 791                 .clk            = {
 792                         .name           = "sclk_cam",
 793                         .id             = 0,
 794                         .enable         = s5pv210_clk_mask0_ctrl,
 795                         .ctrlbit        = (1 << 3),
 796                 },
 797                 .sources = &clkset_group2,
 798                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 799                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 800         }, {
 801                 .clk            = {
 802                         .name           = "sclk_cam",
 803                         .id             = 1,
 804                         .enable         = s5pv210_clk_mask0_ctrl,
 805                         .ctrlbit        = (1 << 4),
 806                 },
 807                 .sources = &clkset_group2,
 808                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 809                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 810         }, {
 811                 .clk            = {
 812                         .name           = "sclk_fimd",
 813                         .id             = -1,
 814                         .enable         = s5pv210_clk_mask0_ctrl,
 815                         .ctrlbit        = (1 << 5),
 816                 },
 817                 .sources = &clkset_group2,
 818                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 819                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 820         }, {
 821                 .clk            = {
 822                         .name           = "sclk_mmc",
 823                         .id             = 0,
 824                         .enable         = s5pv210_clk_mask0_ctrl,
 825                         .ctrlbit        = (1 << 8),
 826                 },
 827                 .sources = &clkset_group2,
 828                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 829                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 830         }, {
 831                 .clk            = {
 832                         .name           = "sclk_mmc",
 833                         .id             = 1,
 834                         .enable         = s5pv210_clk_mask0_ctrl,
 835                         .ctrlbit        = (1 << 9),
 836                 },
 837                 .sources = &clkset_group2,
 838                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 839                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 840         }, {
 841                 .clk            = {
 842                         .name           = "sclk_mmc",
 843                         .id             = 2,
 844                         .enable         = s5pv210_clk_mask0_ctrl,
 845                         .ctrlbit        = (1 << 10),
 846                 },
 847                 .sources = &clkset_group2,
 848                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 849                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 850         }, {
 851                 .clk            = {
 852                         .name           = "sclk_mmc",
 853                         .id             = 3,
 854                         .enable         = s5pv210_clk_mask0_ctrl,
 855                         .ctrlbit        = (1 << 11),
 856                 },
 857                 .sources = &clkset_group2,
 858                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 859                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 860         }, {
 861                 .clk            = {
 862                         .name           = "sclk_mfc",
 863                         .id             = -1,
 864                         .enable         = s5pv210_clk_ip0_ctrl,
 865                         .ctrlbit        = (1 << 16),
 866                 },
 867                 .sources = &clkset_group1,
 868                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 869                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 870         }, {
 871                 .clk            = {
 872                         .name           = "sclk_g2d",
 873                         .id             = -1,
 874                         .enable         = s5pv210_clk_ip0_ctrl,
 875                         .ctrlbit        = (1 << 12),
 876                 },
 877                 .sources = &clkset_group1,
 878                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 879                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 880         }, {
 881                 .clk            = {
 882                         .name           = "sclk_g3d",
 883                         .id             = -1,
 884                         .enable         = s5pv210_clk_ip0_ctrl,
 885                         .ctrlbit        = (1 << 8),
 886                 },
 887                 .sources = &clkset_group1,
 888                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 889                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 890         }, {
 891                 .clk            = {
 892                         .name           = "sclk_csis",
 893                         .id             = -1,
 894                         .enable         = s5pv210_clk_mask0_ctrl,
 895                         .ctrlbit        = (1 << 6),
 896                 },
 897                 .sources = &clkset_group2,
 898                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 899                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 900         }, {
 901                 .clk            = {
 902                         .name           = "sclk_spi",
 903                         .id             = 0,
 904                         .enable         = s5pv210_clk_mask0_ctrl,
 905                         .ctrlbit        = (1 << 16),
 906                 },
 907                 .sources = &clkset_group2,
 908                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
 909                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
 910         }, {
 911                 .clk            = {
 912                         .name           = "sclk_spi",
 913                         .id             = 1,
 914                         .enable         = s5pv210_clk_mask0_ctrl,
 915                         .ctrlbit        = (1 << 17),
 916                 },
 917                 .sources = &clkset_group2,
 918                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
 919                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
 920         }, {
 921                 .clk            = {
 922                         .name           = "sclk_pwi",
 923                         .id             = -1,
 924                         .enable         = s5pv210_clk_mask0_ctrl,
 925                         .ctrlbit        = (1 << 29),
 926                 },
 927                 .sources = &clkset_group2,
 928                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
 929                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
 930         }, {
 931                 .clk            = {
 932                         .name           = "sclk_pwm",
 933                         .id             = -1,
 934                         .enable         = s5pv210_clk_mask0_ctrl,
 935                         .ctrlbit        = (1 << 19),
 936                 },
 937                 .sources = &clkset_group2,
 938                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
 939                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
 940         },
 941 };
 942
 943 /* Clock initialisation code */
 944 static struct clksrc_clk *sysclks[] = {
 945         &clk_mout_apll,
 946         &clk_mout_epll,
 947         &clk_mout_mpll,
 948         &clk_armclk,
 949         &clk_hclk_msys,
 950         &clk_sclk_a2m,
 951         &clk_hclk_dsys,
 952         &clk_hclk_psys,
 953         &clk_pclk_msys,
 954         &clk_pclk_dsys,
 955         &clk_pclk_psys,
 956         &clk_vpllsrc,
 957         &clk_sclk_vpll,
 958         &clk_sclk_dac,
 959         &clk_sclk_pixel,
 960         &clk_sclk_hdmi,
 961 };
 962
 963 void __init_or_cpufreq s5pv210_setup_clocks(void)
 964 {
 965         struct clk *xtal_clk;
 966         unsigned long xtal;
 967         unsigned long vpllsrc;
 968         unsigned long armclk;
 969         unsigned long hclk_msys;
 970         unsigned long hclk_dsys;
 971         unsigned long hclk_psys;
 972         unsigned long pclk_msys;
 973         unsigned long pclk_dsys;
 974         unsigned long pclk_psys;
 975         unsigned long apll;
 976         unsigned long mpll;
 977         unsigned long epll;
 978         unsigned long vpll;
 979         unsigned int ptr;
 980         u32 clkdiv0, clkdiv1;
 981
 982         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
 983
 984         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 985         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
 986
 987         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
 988                                 __func__, clkdiv0, clkdiv1);
 989
 990         xtal_clk = clk_get(NULL, "xtal");
 991         BUG_ON(IS_ERR(xtal_clk));
 992
 993         xtal = clk_get_rate(xtal_clk);
 994         clk_put(xtal_clk);
 995
 996         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
 997
 998         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 999         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1000         epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
1001         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1002         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1003
1004         clk_fout_apll.rate = apll;
1005         clk_fout_mpll.rate = mpll;
1006         clk_fout_epll.rate = epll;
1007         clk_fout_vpll.rate = vpll;
1008
1009         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1010                         apll, mpll, epll, vpll);
1011
1012         armclk = clk_get_rate(&clk_armclk.clk);
1013         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1014         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1015         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1016         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1017         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1018         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1019
1020         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1021                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1022                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1023                         pclk_msys, pclk_dsys, pclk_psys);
1024
1025         clk_f.rate = armclk;
1026         clk_h.rate = hclk_psys;
1027         clk_p.rate = pclk_psys;
1028
1029         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1030                 s3c_set_clksrc(&clksrcs[ptr], true);
1031 }
1032
1033 static struct clk *clks[] __initdata = {
1034         &clk_sclk_hdmi27m,
1035         &clk_sclk_hdmiphy,
1036         &clk_sclk_usbphy0,
1037         &clk_sclk_usbphy1,
1038         &clk_pcmcdclk0,
1039         &clk_pcmcdclk1,
1040         &clk_pcmcdclk2,
1041 };
1042
1043 void __init s5pv210_register_clocks(void)
1044 {
1045         struct clk *clkp;
1046         int ret;
1047         int ptr;
1048
1049         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1050         if (ret > 0)
1051                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
1052
1053         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1054                 s3c_register_clksrc(sysclks[ptr], 1);
1055
1056         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1057         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1058
1059         clkp = init_clocks_disable;
1060         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
1061                 ret = s3c24xx_register_clock(clkp);
1062                 if (ret < 0) {
1063                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
1064                                clkp->name, ret);
1065                 }
1066                 (clkp->enable)(clkp, 0);
1067         }
1068
1069         s3c_pwmclk_init();
1070 }