arch/arm/mach-s5pv210/clock.c

   1 /* linux/arch/arm/mach-s5pv210/clock.c
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5PV210 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/map.h>
  24
  25 #include <plat/cpu-freq.h>
  26 #include <mach/regs-clock.h>
  27 #include <plat/clock.h>
  28 #include <plat/cpu.h>
  29 #include <plat/pll.h>
  30 #include <plat/s5p-clock.h>
  31 #include <plat/clock-clksrc.h>
  32 #include <plat/s5pv210.h>
  33
  34 static unsigned long xtal;
  35
  36 static struct clksrc_clk clk_mout_apll = {
  37         .clk    = {
  38                 .name           = "mout_apll",
  39         },
  40         .sources        = &clk_src_apll,
  41         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  42 };
  43
  44 static struct clksrc_clk clk_mout_epll = {
  45         .clk    = {
  46                 .name           = "mout_epll",
  47         },
  48         .sources        = &clk_src_epll,
  49         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
  50 };
  51
  52 static struct clksrc_clk clk_mout_mpll = {
  53         .clk = {
  54                 .name           = "mout_mpll",
  55         },
  56         .sources        = &clk_src_mpll,
  57         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
  58 };
  59
  60 static struct clk *clkset_armclk_list[] = {
  61         [0] = &clk_mout_apll.clk,
  62         [1] = &clk_mout_mpll.clk,
  63 };
  64
  65 static struct clksrc_sources clkset_armclk = {
  66         .sources        = clkset_armclk_list,
  67         .nr_sources     = ARRAY_SIZE(clkset_armclk_list),
  68 };
  69
  70 static struct clksrc_clk clk_armclk = {
  71         .clk    = {
  72                 .name           = "armclk",
  73         },
  74         .sources        = &clkset_armclk,
  75         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
  76         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
  77 };
  78
  79 static struct clksrc_clk clk_hclk_msys = {
  80         .clk    = {
  81                 .name           = "hclk_msys",
  82                 .parent         = &clk_armclk.clk,
  83         },
  84         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
  85 };
  86
  87 static struct clksrc_clk clk_pclk_msys = {
  88         .clk    = {
  89                 .name           = "pclk_msys",
  90                 .parent         = &clk_hclk_msys.clk,
  91         },
  92         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
  93 };
  94
  95 static struct clksrc_clk clk_sclk_a2m = {
  96         .clk    = {
  97                 .name           = "sclk_a2m",
  98                 .parent         = &clk_mout_apll.clk,
  99         },
 100         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
 101 };
 102
 103 static struct clk *clkset_hclk_sys_list[] = {
 104         [0] = &clk_mout_mpll.clk,
 105         [1] = &clk_sclk_a2m.clk,
 106 };
 107
 108 static struct clksrc_sources clkset_hclk_sys = {
 109         .sources        = clkset_hclk_sys_list,
 110         .nr_sources     = ARRAY_SIZE(clkset_hclk_sys_list),
 111 };
 112
 113 static struct clksrc_clk clk_hclk_dsys = {
 114         .clk    = {
 115                 .name   = "hclk_dsys",
 116         },
 117         .sources        = &clkset_hclk_sys,
 118         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
 119         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
 120 };
 121
 122 static struct clksrc_clk clk_pclk_dsys = {
 123         .clk    = {
 124                 .name   = "pclk_dsys",
 125                 .parent = &clk_hclk_dsys.clk,
 126         },
 127         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
 128 };
 129
 130 static struct clksrc_clk clk_hclk_psys = {
 131         .clk    = {
 132                 .name   = "hclk_psys",
 133         },
 134         .sources        = &clkset_hclk_sys,
 135         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
 136         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
 137 };
 138
 139 static struct clksrc_clk clk_pclk_psys = {
 140         .clk    = {
 141                 .name   = "pclk_psys",
 142                 .parent = &clk_hclk_psys.clk,
 143         },
 144         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
 145 };
 146
 147 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
 148 {
 149         return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
 150 }
 151
 152 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
 153 {
 154         return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
 155 }
 156
 157 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
 158 {
 159         return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
 160 }
 161
 162 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
 163 {
 164         return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
 165 }
 166
 167 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 168 {
 169         return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 170 }
 171
 172 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
 173 {
 174         return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
 175 }
 176
 177 static struct clk clk_sclk_hdmi27m = {
 178         .name           = "sclk_hdmi27m",
 179         .rate           = 27000000,
 180 };
 181
 182 static struct clk clk_sclk_hdmiphy = {
 183         .name           = "sclk_hdmiphy",
 184 };
 185
 186 static struct clk clk_sclk_usbphy0 = {
 187         .name           = "sclk_usbphy0",
 188 };
 189
 190 static struct clk clk_sclk_usbphy1 = {
 191         .name           = "sclk_usbphy1",
 192 };
 193
 194 static struct clk clk_pcmcdclk0 = {
 195         .name           = "pcmcdclk",
 196 };
 197
 198 static struct clk clk_pcmcdclk1 = {
 199         .name           = "pcmcdclk",
 200 };
 201
 202 static struct clk clk_pcmcdclk2 = {
 203         .name           = "pcmcdclk",
 204 };
 205
 206 static struct clk dummy_apb_pclk = {
 207         .name           = "apb_pclk",
 208         .id             = -1,
 209 };
 210
 211 static struct clk *clkset_vpllsrc_list[] = {
 212         [0] = &clk_fin_vpll,
 213         [1] = &clk_sclk_hdmi27m,
 214 };
 215
 216 static struct clksrc_sources clkset_vpllsrc = {
 217         .sources        = clkset_vpllsrc_list,
 218         .nr_sources     = ARRAY_SIZE(clkset_vpllsrc_list),
 219 };
 220
 221 static struct clksrc_clk clk_vpllsrc = {
 222         .clk    = {
 223                 .name           = "vpll_src",
 224                 .enable         = s5pv210_clk_mask0_ctrl,
 225                 .ctrlbit        = (1 << 7),
 226         },
 227         .sources        = &clkset_vpllsrc,
 228         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
 229 };
 230
 231 static struct clk *clkset_sclk_vpll_list[] = {
 232         [0] = &clk_vpllsrc.clk,
 233         [1] = &clk_fout_vpll,
 234 };
 235
 236 static struct clksrc_sources clkset_sclk_vpll = {
 237         .sources        = clkset_sclk_vpll_list,
 238         .nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
 239 };
 240
 241 static struct clksrc_clk clk_sclk_vpll = {
 242         .clk    = {
 243                 .name           = "sclk_vpll",
 244         },
 245         .sources        = &clkset_sclk_vpll,
 246         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
 247 };
 248
 249 static struct clk *clkset_moutdmc0src_list[] = {
 250         [0] = &clk_sclk_a2m.clk,
 251         [1] = &clk_mout_mpll.clk,
 252         [2] = NULL,
 253         [3] = NULL,
 254 };
 255
 256 static struct clksrc_sources clkset_moutdmc0src = {
 257         .sources        = clkset_moutdmc0src_list,
 258         .nr_sources     = ARRAY_SIZE(clkset_moutdmc0src_list),
 259 };
 260
 261 static struct clksrc_clk clk_mout_dmc0 = {
 262         .clk    = {
 263                 .name           = "mout_dmc0",
 264         },
 265         .sources        = &clkset_moutdmc0src,
 266         .reg_src        = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 267 };
 268
 269 static struct clksrc_clk clk_sclk_dmc0 = {
 270         .clk    = {
 271                 .name           = "sclk_dmc0",
 272                 .parent         = &clk_mout_dmc0.clk,
 273         },
 274         .reg_div        = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 275 };
 276
 277 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
 278 {
 279         return clk_get_rate(clk->parent) / 2;
 280 }
 281
 282 static struct clk_ops clk_hclk_imem_ops = {
 283         .get_rate       = s5pv210_clk_imem_get_rate,
 284 };
 285
 286 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
 287 {
 288         return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
 289 }
 290
 291 static struct clk_ops clk_fout_apll_ops = {
 292         .get_rate       = s5pv210_clk_fout_apll_get_rate,
 293 };
 294
 295 static struct clk init_clocks_off[] = {
 296         {
 297                 .name           = "dma",
 298                 .devname        = "s3c-pl330.0",
 299                 .parent         = &clk_hclk_psys.clk,
 300                 .enable         = s5pv210_clk_ip0_ctrl,
 301                 .ctrlbit        = (1 << 3),
 302         }, {
 303                 .name           = "dma",
 304                 .devname        = "s3c-pl330.1",
 305                 .parent         = &clk_hclk_psys.clk,
 306                 .enable         = s5pv210_clk_ip0_ctrl,
 307                 .ctrlbit        = (1 << 4),
 308         }, {
 309                 .name           = "rot",
 310                 .parent         = &clk_hclk_dsys.clk,
 311                 .enable         = s5pv210_clk_ip0_ctrl,
 312                 .ctrlbit        = (1<<29),
 313         }, {
 314                 .name           = "fimc",
 315                 .devname        = "s5pv210-fimc.0",
 316                 .parent         = &clk_hclk_dsys.clk,
 317                 .enable         = s5pv210_clk_ip0_ctrl,
 318                 .ctrlbit        = (1 << 24),
 319         }, {
 320                 .name           = "fimc",
 321                 .devname        = "s5pv210-fimc.1",
 322                 .parent         = &clk_hclk_dsys.clk,
 323                 .enable         = s5pv210_clk_ip0_ctrl,
 324                 .ctrlbit        = (1 << 25),
 325         }, {
 326                 .name           = "fimc",
 327                 .devname        = "s5pv210-fimc.2",
 328                 .parent         = &clk_hclk_dsys.clk,
 329                 .enable         = s5pv210_clk_ip0_ctrl,
 330                 .ctrlbit        = (1 << 26),
 331         }, {
 332                 .name           = "mfc",
 333                 .devname        = "s5p-mfc",
 334                 .parent         = &clk_pclk_psys.clk,
 335                 .enable         = s5pv210_clk_ip0_ctrl,
 336                 .ctrlbit        = (1 << 16),
 337         }, {
 338                 .name           = "otg",
 339                 .parent         = &clk_hclk_psys.clk,
 340                 .enable         = s5pv210_clk_ip1_ctrl,
 341                 .ctrlbit        = (1<<16),
 342         }, {
 343                 .name           = "usb-host",
 344                 .parent         = &clk_hclk_psys.clk,
 345                 .enable         = s5pv210_clk_ip1_ctrl,
 346                 .ctrlbit        = (1<<17),
 347         }, {
 348                 .name           = "lcd",
 349                 .parent         = &clk_hclk_dsys.clk,
 350                 .enable         = s5pv210_clk_ip1_ctrl,
 351                 .ctrlbit        = (1<<0),
 352         }, {
 353                 .name           = "cfcon",
 354                 .parent         = &clk_hclk_psys.clk,
 355                 .enable         = s5pv210_clk_ip1_ctrl,
 356                 .ctrlbit        = (1<<25),
 357         }, {
 358                 .name           = "hsmmc",
 359                 .devname        = "s3c-sdhci.0",
 360                 .parent         = &clk_hclk_psys.clk,
 361                 .enable         = s5pv210_clk_ip2_ctrl,
 362                 .ctrlbit        = (1<<16),
 363         }, {
 364                 .name           = "hsmmc",
 365                 .devname        = "s3c-sdhci.1",
 366                 .parent         = &clk_hclk_psys.clk,
 367                 .enable         = s5pv210_clk_ip2_ctrl,
 368                 .ctrlbit        = (1<<17),
 369         }, {
 370                 .name           = "hsmmc",
 371                 .devname        = "s3c-sdhci.2",
 372                 .parent         = &clk_hclk_psys.clk,
 373                 .enable         = s5pv210_clk_ip2_ctrl,
 374                 .ctrlbit        = (1<<18),
 375         }, {
 376                 .name           = "hsmmc",
 377                 .devname        = "s3c-sdhci.3",
 378                 .parent         = &clk_hclk_psys.clk,
 379                 .enable         = s5pv210_clk_ip2_ctrl,
 380                 .ctrlbit        = (1<<19),
 381         }, {
 382                 .name           = "systimer",
 383                 .parent         = &clk_pclk_psys.clk,
 384                 .enable         = s5pv210_clk_ip3_ctrl,
 385                 .ctrlbit        = (1<<16),
 386         }, {
 387                 .name           = "watchdog",
 388                 .parent         = &clk_pclk_psys.clk,
 389                 .enable         = s5pv210_clk_ip3_ctrl,
 390                 .ctrlbit        = (1<<22),
 391         }, {
 392                 .name           = "rtc",
 393                 .parent         = &clk_pclk_psys.clk,
 394                 .enable         = s5pv210_clk_ip3_ctrl,
 395                 .ctrlbit        = (1<<15),
 396         }, {
 397                 .name           = "i2c",
 398                 .devname        = "s3c2440-i2c.0",
 399                 .parent         = &clk_pclk_psys.clk,
 400                 .enable         = s5pv210_clk_ip3_ctrl,
 401                 .ctrlbit        = (1<<7),
 402         }, {
 403                 .name           = "i2c",
 404                 .devname        = "s3c2440-i2c.1",
 405                 .parent         = &clk_pclk_psys.clk,
 406                 .enable         = s5pv210_clk_ip3_ctrl,
 407                 .ctrlbit        = (1 << 10),
 408         }, {
 409                 .name           = "i2c",
 410                 .devname        = "s3c2440-i2c.2",
 411                 .parent         = &clk_pclk_psys.clk,
 412                 .enable         = s5pv210_clk_ip3_ctrl,
 413                 .ctrlbit        = (1<<9),
 414         }, {
 415                 .name           = "spi",
 416                 .devname        = "s3c64xx-spi.0",
 417                 .parent         = &clk_pclk_psys.clk,
 418                 .enable         = s5pv210_clk_ip3_ctrl,
 419                 .ctrlbit        = (1<<12),
 420         }, {
 421                 .name           = "spi",
 422                 .devname        = "s3c64xx-spi.1",
 423                 .parent         = &clk_pclk_psys.clk,
 424                 .enable         = s5pv210_clk_ip3_ctrl,
 425                 .ctrlbit        = (1<<13),
 426         }, {
 427                 .name           = "spi",
 428                 .devname        = "s3c64xx-spi.2",
 429                 .parent         = &clk_pclk_psys.clk,
 430                 .enable         = s5pv210_clk_ip3_ctrl,
 431                 .ctrlbit        = (1<<14),
 432         }, {
 433                 .name           = "timers",
 434                 .parent         = &clk_pclk_psys.clk,
 435                 .enable         = s5pv210_clk_ip3_ctrl,
 436                 .ctrlbit        = (1<<23),
 437         }, {
 438                 .name           = "adc",
 439                 .parent         = &clk_pclk_psys.clk,
 440                 .enable         = s5pv210_clk_ip3_ctrl,
 441                 .ctrlbit        = (1<<24),
 442         }, {
 443                 .name           = "keypad",
 444                 .parent         = &clk_pclk_psys.clk,
 445                 .enable         = s5pv210_clk_ip3_ctrl,
 446                 .ctrlbit        = (1<<21),
 447         }, {
 448                 .name           = "iis",
 449                 .devname        = "samsung-i2s.0",
 450                 .parent         = &clk_p,
 451                 .enable         = s5pv210_clk_ip3_ctrl,
 452                 .ctrlbit        = (1<<4),
 453         }, {
 454                 .name           = "iis",
 455                 .devname        = "samsung-i2s.1",
 456                 .parent         = &clk_p,
 457                 .enable         = s5pv210_clk_ip3_ctrl,
 458                 .ctrlbit        = (1 << 5),
 459         }, {
 460                 .name           = "iis",
 461                 .devname        = "samsung-i2s.2",
 462                 .parent         = &clk_p,
 463                 .enable         = s5pv210_clk_ip3_ctrl,
 464                 .ctrlbit        = (1 << 6),
 465         }, {
 466                 .name           = "spdif",
 467                 .parent         = &clk_p,
 468                 .enable         = s5pv210_clk_ip3_ctrl,
 469                 .ctrlbit        = (1 << 0),
 470         },
 471 };
 472
 473 static struct clk init_clocks[] = {
 474         {
 475                 .name           = "hclk_imem",
 476                 .parent         = &clk_hclk_msys.clk,
 477                 .ctrlbit        = (1 << 5),
 478                 .enable         = s5pv210_clk_ip0_ctrl,
 479                 .ops            = &clk_hclk_imem_ops,
 480         }, {
 481                 .name           = "uart",
 482                 .devname        = "s5pv210-uart.0",
 483                 .parent         = &clk_pclk_psys.clk,
 484                 .enable         = s5pv210_clk_ip3_ctrl,
 485                 .ctrlbit        = (1 << 17),
 486         }, {
 487                 .name           = "uart",
 488                 .devname        = "s5pv210-uart.1",
 489                 .parent         = &clk_pclk_psys.clk,
 490                 .enable         = s5pv210_clk_ip3_ctrl,
 491                 .ctrlbit        = (1 << 18),
 492         }, {
 493                 .name           = "uart",
 494                 .devname        = "s5pv210-uart.2",
 495                 .parent         = &clk_pclk_psys.clk,
 496                 .enable         = s5pv210_clk_ip3_ctrl,
 497                 .ctrlbit        = (1 << 19),
 498         }, {
 499                 .name           = "uart",
 500                 .devname        = "s5pv210-uart.3",
 501                 .parent         = &clk_pclk_psys.clk,
 502                 .enable         = s5pv210_clk_ip3_ctrl,
 503                 .ctrlbit        = (1 << 20),
 504         }, {
 505                 .name           = "sromc",
 506                 .parent         = &clk_hclk_psys.clk,
 507                 .enable         = s5pv210_clk_ip1_ctrl,
 508                 .ctrlbit        = (1 << 26),
 509         },
 510 };
 511
 512 static struct clk *clkset_uart_list[] = {
 513         [6] = &clk_mout_mpll.clk,
 514         [7] = &clk_mout_epll.clk,
 515 };
 516
 517 static struct clksrc_sources clkset_uart = {
 518         .sources        = clkset_uart_list,
 519         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 520 };
 521
 522 static struct clk *clkset_group1_list[] = {
 523         [0] = &clk_sclk_a2m.clk,
 524         [1] = &clk_mout_mpll.clk,
 525         [2] = &clk_mout_epll.clk,
 526         [3] = &clk_sclk_vpll.clk,
 527 };
 528
 529 static struct clksrc_sources clkset_group1 = {
 530         .sources        = clkset_group1_list,
 531         .nr_sources     = ARRAY_SIZE(clkset_group1_list),
 532 };
 533
 534 static struct clk *clkset_sclk_onenand_list[] = {
 535         [0] = &clk_hclk_psys.clk,
 536         [1] = &clk_hclk_dsys.clk,
 537 };
 538
 539 static struct clksrc_sources clkset_sclk_onenand = {
 540         .sources        = clkset_sclk_onenand_list,
 541         .nr_sources     = ARRAY_SIZE(clkset_sclk_onenand_list),
 542 };
 543
 544 static struct clk *clkset_sclk_dac_list[] = {
 545         [0] = &clk_sclk_vpll.clk,
 546         [1] = &clk_sclk_hdmiphy,
 547 };
 548
 549 static struct clksrc_sources clkset_sclk_dac = {
 550         .sources        = clkset_sclk_dac_list,
 551         .nr_sources     = ARRAY_SIZE(clkset_sclk_dac_list),
 552 };
 553
 554 static struct clksrc_clk clk_sclk_dac = {
 555         .clk            = {
 556                 .name           = "sclk_dac",
 557                 .enable         = s5pv210_clk_mask0_ctrl,
 558                 .ctrlbit        = (1 << 2),
 559         },
 560         .sources        = &clkset_sclk_dac,
 561         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
 562 };
 563
 564 static struct clksrc_clk clk_sclk_pixel = {
 565         .clk            = {
 566                 .name           = "sclk_pixel",
 567                 .parent         = &clk_sclk_vpll.clk,
 568         },
 569         .reg_div        = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
 570 };
 571
 572 static struct clk *clkset_sclk_hdmi_list[] = {
 573         [0] = &clk_sclk_pixel.clk,
 574         [1] = &clk_sclk_hdmiphy,
 575 };
 576
 577 static struct clksrc_sources clkset_sclk_hdmi = {
 578         .sources        = clkset_sclk_hdmi_list,
 579         .nr_sources     = ARRAY_SIZE(clkset_sclk_hdmi_list),
 580 };
 581
 582 static struct clksrc_clk clk_sclk_hdmi = {
 583         .clk            = {
 584                 .name           = "sclk_hdmi",
 585                 .enable         = s5pv210_clk_mask0_ctrl,
 586                 .ctrlbit        = (1 << 0),
 587         },
 588         .sources        = &clkset_sclk_hdmi,
 589         .reg_src        = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
 590 };
 591
 592 static struct clk *clkset_sclk_mixer_list[] = {
 593         [0] = &clk_sclk_dac.clk,
 594         [1] = &clk_sclk_hdmi.clk,
 595 };
 596
 597 static struct clksrc_sources clkset_sclk_mixer = {
 598         .sources        = clkset_sclk_mixer_list,
 599         .nr_sources     = ARRAY_SIZE(clkset_sclk_mixer_list),
 600 };
 601
 602 static struct clk *clkset_sclk_audio0_list[] = {
 603         [0] = &clk_ext_xtal_mux,
 604         [1] = &clk_pcmcdclk0,
 605         [2] = &clk_sclk_hdmi27m,
 606         [3] = &clk_sclk_usbphy0,
 607         [4] = &clk_sclk_usbphy1,
 608         [5] = &clk_sclk_hdmiphy,
 609         [6] = &clk_mout_mpll.clk,
 610         [7] = &clk_mout_epll.clk,
 611         [8] = &clk_sclk_vpll.clk,
 612 };
 613
 614 static struct clksrc_sources clkset_sclk_audio0 = {
 615         .sources        = clkset_sclk_audio0_list,
 616         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio0_list),
 617 };
 618
 619 static struct clksrc_clk clk_sclk_audio0 = {
 620         .clk            = {
 621                 .name           = "sclk_audio",
 622                 .devname        = "soc-audio.0",
 623                 .enable         = s5pv210_clk_mask0_ctrl,
 624                 .ctrlbit        = (1 << 24),
 625         },
 626         .sources = &clkset_sclk_audio0,
 627         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
 628         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
 629 };
 630
 631 static struct clk *clkset_sclk_audio1_list[] = {
 632         [0] = &clk_ext_xtal_mux,
 633         [1] = &clk_pcmcdclk1,
 634         [2] = &clk_sclk_hdmi27m,
 635         [3] = &clk_sclk_usbphy0,
 636         [4] = &clk_sclk_usbphy1,
 637         [5] = &clk_sclk_hdmiphy,
 638         [6] = &clk_mout_mpll.clk,
 639         [7] = &clk_mout_epll.clk,
 640         [8] = &clk_sclk_vpll.clk,
 641 };
 642
 643 static struct clksrc_sources clkset_sclk_audio1 = {
 644         .sources        = clkset_sclk_audio1_list,
 645         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio1_list),
 646 };
 647
 648 static struct clksrc_clk clk_sclk_audio1 = {
 649         .clk            = {
 650                 .name           = "sclk_audio",
 651                 .devname        = "soc-audio.1",
 652                 .enable         = s5pv210_clk_mask0_ctrl,
 653                 .ctrlbit        = (1 << 25),
 654         },
 655         .sources = &clkset_sclk_audio1,
 656         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
 657         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
 658 };
 659
 660 static struct clk *clkset_sclk_audio2_list[] = {
 661         [0] = &clk_ext_xtal_mux,
 662         [1] = &clk_pcmcdclk0,
 663         [2] = &clk_sclk_hdmi27m,
 664         [3] = &clk_sclk_usbphy0,
 665         [4] = &clk_sclk_usbphy1,
 666         [5] = &clk_sclk_hdmiphy,
 667         [6] = &clk_mout_mpll.clk,
 668         [7] = &clk_mout_epll.clk,
 669         [8] = &clk_sclk_vpll.clk,
 670 };
 671
 672 static struct clksrc_sources clkset_sclk_audio2 = {
 673         .sources        = clkset_sclk_audio2_list,
 674         .nr_sources     = ARRAY_SIZE(clkset_sclk_audio2_list),
 675 };
 676
 677 static struct clksrc_clk clk_sclk_audio2 = {
 678         .clk            = {
 679                 .name           = "sclk_audio",
 680                 .devname        = "soc-audio.2",
 681                 .enable         = s5pv210_clk_mask0_ctrl,
 682                 .ctrlbit        = (1 << 26),
 683         },
 684         .sources = &clkset_sclk_audio2,
 685         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
 686         .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
 687 };
 688
 689 static struct clk *clkset_sclk_spdif_list[] = {
 690         [0] = &clk_sclk_audio0.clk,
 691         [1] = &clk_sclk_audio1.clk,
 692         [2] = &clk_sclk_audio2.clk,
 693 };
 694
 695 static struct clksrc_sources clkset_sclk_spdif = {
 696         .sources        = clkset_sclk_spdif_list,
 697         .nr_sources     = ARRAY_SIZE(clkset_sclk_spdif_list),
 698 };
 699
 700 static struct clksrc_clk clk_sclk_spdif = {
 701         .clk            = {
 702                 .name           = "sclk_spdif",
 703                 .enable         = s5pv210_clk_mask0_ctrl,
 704                 .ctrlbit        = (1 << 27),
 705                 .ops            = &s5p_sclk_spdif_ops,
 706         },
 707         .sources = &clkset_sclk_spdif,
 708         .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
 709 };
 710
 711 static struct clk *clkset_group2_list[] = {
 712         [0] = &clk_ext_xtal_mux,
 713         [1] = &clk_xusbxti,
 714         [2] = &clk_sclk_hdmi27m,
 715         [3] = &clk_sclk_usbphy0,
 716         [4] = &clk_sclk_usbphy1,
 717         [5] = &clk_sclk_hdmiphy,
 718         [6] = &clk_mout_mpll.clk,
 719         [7] = &clk_mout_epll.clk,
 720         [8] = &clk_sclk_vpll.clk,
 721 };
 722
 723 static struct clksrc_sources clkset_group2 = {
 724         .sources        = clkset_group2_list,
 725         .nr_sources     = ARRAY_SIZE(clkset_group2_list),
 726 };
 727
 728 static struct clksrc_clk clksrcs[] = {
 729         {
 730                 .clk    = {
 731                         .name           = "sclk_dmc",
 732                 },
 733                 .sources = &clkset_group1,
 734                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
 735                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
 736         }, {
 737                 .clk    = {
 738                         .name           = "sclk_onenand",
 739                 },
 740                 .sources = &clkset_sclk_onenand,
 741                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
 742                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
 743         }, {
 744                 .clk    = {
 745                         .name           = "uclk1",
 746                         .devname        = "s5pv210-uart.0",
 747                         .enable         = s5pv210_clk_mask0_ctrl,
 748                         .ctrlbit        = (1 << 12),
 749                 },
 750                 .sources = &clkset_uart,
 751                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
 752                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
 753         }, {
 754                 .clk            = {
 755                         .name           = "uclk1",
 756                         .devname        = "s5pv210-uart.1",
 757                         .enable         = s5pv210_clk_mask0_ctrl,
 758                         .ctrlbit        = (1 << 13),
 759                 },
 760                 .sources = &clkset_uart,
 761                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
 762                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
 763         }, {
 764                 .clk            = {
 765                         .name           = "uclk1",
 766                         .devname        = "s5pv210-uart.2",
 767                         .enable         = s5pv210_clk_mask0_ctrl,
 768                         .ctrlbit        = (1 << 14),
 769                 },
 770                 .sources = &clkset_uart,
 771                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
 772                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
 773         }, {
 774                 .clk            = {
 775                         .name           = "uclk1",
 776                         .devname        = "s5pv210-uart.3",
 777                         .enable         = s5pv210_clk_mask0_ctrl,
 778                         .ctrlbit        = (1 << 15),
 779                 },
 780                 .sources = &clkset_uart,
 781                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
 782                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
 783         }, {
 784                 .clk    = {
 785                         .name           = "sclk_mixer",
 786                         .enable         = s5pv210_clk_mask0_ctrl,
 787                         .ctrlbit        = (1 << 1),
 788                 },
 789                 .sources = &clkset_sclk_mixer,
 790                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
 791         }, {
 792                 .clk    = {
 793                         .name           = "sclk_fimc",
 794                         .devname        = "s5pv210-fimc.0",
 795                         .enable         = s5pv210_clk_mask1_ctrl,
 796                         .ctrlbit        = (1 << 2),
 797                 },
 798                 .sources = &clkset_group2,
 799                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
 800                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
 801         }, {
 802                 .clk    = {
 803                         .name           = "sclk_fimc",
 804                         .devname        = "s5pv210-fimc.1",
 805                         .enable         = s5pv210_clk_mask1_ctrl,
 806                         .ctrlbit        = (1 << 3),
 807                 },
 808                 .sources = &clkset_group2,
 809                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
 810                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
 811         }, {
 812                 .clk    = {
 813                         .name           = "sclk_fimc",
 814                         .devname        = "s5pv210-fimc.2",
 815                         .enable         = s5pv210_clk_mask1_ctrl,
 816                         .ctrlbit        = (1 << 4),
 817                 },
 818                 .sources = &clkset_group2,
 819                 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
 820                 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
 821         }, {
 822                 .clk            = {
 823                         .name           = "sclk_cam0",
 824                         .enable         = s5pv210_clk_mask0_ctrl,
 825                         .ctrlbit        = (1 << 3),
 826                 },
 827                 .sources = &clkset_group2,
 828                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
 829                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
 830         }, {
 831                 .clk            = {
 832                         .name           = "sclk_cam1",
 833                         .enable         = s5pv210_clk_mask0_ctrl,
 834                         .ctrlbit        = (1 << 4),
 835                 },
 836                 .sources = &clkset_group2,
 837                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
 838                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
 839         }, {
 840                 .clk            = {
 841                         .name           = "sclk_fimd",
 842                         .enable         = s5pv210_clk_mask0_ctrl,
 843                         .ctrlbit        = (1 << 5),
 844                 },
 845                 .sources = &clkset_group2,
 846                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
 847                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
 848         }, {
 849                 .clk            = {
 850                         .name           = "sclk_mmc",
 851                         .devname        = "s3c-sdhci.0",
 852                         .enable         = s5pv210_clk_mask0_ctrl,
 853                         .ctrlbit        = (1 << 8),
 854                 },
 855                 .sources = &clkset_group2,
 856                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
 857                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
 858         }, {
 859                 .clk            = {
 860                         .name           = "sclk_mmc",
 861                         .devname        = "s3c-sdhci.1",
 862                         .enable         = s5pv210_clk_mask0_ctrl,
 863                         .ctrlbit        = (1 << 9),
 864                 },
 865                 .sources = &clkset_group2,
 866                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
 867                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
 868         }, {
 869                 .clk            = {
 870                         .name           = "sclk_mmc",
 871                         .devname        = "s3c-sdhci.2",
 872                         .enable         = s5pv210_clk_mask0_ctrl,
 873                         .ctrlbit        = (1 << 10),
 874                 },
 875                 .sources = &clkset_group2,
 876                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
 877                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
 878         }, {
 879                 .clk            = {
 880                         .name           = "sclk_mmc",
 881                         .devname        = "s3c-sdhci.3",
 882                         .enable         = s5pv210_clk_mask0_ctrl,
 883                         .ctrlbit        = (1 << 11),
 884                 },
 885                 .sources = &clkset_group2,
 886                 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
 887                 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
 888         }, {
 889                 .clk            = {
 890                         .name           = "sclk_mfc",
 891                         .devname        = "s5p-mfc",
 892                         .enable         = s5pv210_clk_ip0_ctrl,
 893                         .ctrlbit        = (1 << 16),
 894                 },
 895                 .sources = &clkset_group1,
 896                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
 897                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 898         }, {
 899                 .clk            = {
 900                         .name           = "sclk_g2d",
 901                         .enable         = s5pv210_clk_ip0_ctrl,
 902                         .ctrlbit        = (1 << 12),
 903                 },
 904                 .sources = &clkset_group1,
 905                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
 906                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
 907         }, {
 908                 .clk            = {
 909                         .name           = "sclk_g3d",
 910                         .enable         = s5pv210_clk_ip0_ctrl,
 911                         .ctrlbit        = (1 << 8),
 912                 },
 913                 .sources = &clkset_group1,
 914                 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
 915                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 916         }, {
 917                 .clk            = {
 918                         .name           = "sclk_csis",
 919                         .enable         = s5pv210_clk_mask0_ctrl,
 920                         .ctrlbit        = (1 << 6),
 921                 },
 922                 .sources = &clkset_group2,
 923                 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
 924                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
 925         }, {
 926                 .clk            = {
 927                         .name           = "sclk_spi",
 928                         .devname        = "s3c64xx-spi.0",
 929                         .enable         = s5pv210_clk_mask0_ctrl,
 930                         .ctrlbit        = (1 << 16),
 931                 },
 932                 .sources = &clkset_group2,
 933                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
 934                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
 935         }, {
 936                 .clk            = {
 937                         .name           = "sclk_spi",
 938                         .devname        = "s3c64xx-spi.1",
 939                         .enable         = s5pv210_clk_mask0_ctrl,
 940                         .ctrlbit        = (1 << 17),
 941                 },
 942                 .sources = &clkset_group2,
 943                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
 944                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
 945         }, {
 946                 .clk            = {
 947                         .name           = "sclk_pwi",
 948                         .enable         = s5pv210_clk_mask0_ctrl,
 949                         .ctrlbit        = (1 << 29),
 950                 },
 951                 .sources = &clkset_group2,
 952                 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
 953                 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
 954         }, {
 955                 .clk            = {
 956                         .name           = "sclk_pwm",
 957                         .enable         = s5pv210_clk_mask0_ctrl,
 958                         .ctrlbit        = (1 << 19),
 959                 },
 960                 .sources = &clkset_group2,
 961                 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
 962                 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
 963         },
 964 };
 965
 966 /* Clock initialisation code */
 967 static struct clksrc_clk *sysclks[] = {
 968         &clk_mout_apll,
 969         &clk_mout_epll,
 970         &clk_mout_mpll,
 971         &clk_armclk,
 972         &clk_hclk_msys,
 973         &clk_sclk_a2m,
 974         &clk_hclk_dsys,
 975         &clk_hclk_psys,
 976         &clk_pclk_msys,
 977         &clk_pclk_dsys,
 978         &clk_pclk_psys,
 979         &clk_vpllsrc,
 980         &clk_sclk_vpll,
 981         &clk_sclk_dac,
 982         &clk_sclk_pixel,
 983         &clk_sclk_hdmi,
 984         &clk_mout_dmc0,
 985         &clk_sclk_dmc0,
 986         &clk_sclk_audio0,
 987         &clk_sclk_audio1,
 988         &clk_sclk_audio2,
 989         &clk_sclk_spdif,
 990 };
 991
 992 static u32 epll_div[][6] = {
 993         {  48000000, 0, 48, 3, 3, 0 },
 994         {  96000000, 0, 48, 3, 2, 0 },
 995         { 144000000, 1, 72, 3, 2, 0 },
 996         { 192000000, 0, 48, 3, 1, 0 },
 997         { 288000000, 1, 72, 3, 1, 0 },
 998         {  32750000, 1, 65, 3, 4, 35127 },
 999         {  32768000, 1, 65, 3, 4, 35127 },
1000         {  45158400, 0, 45, 3, 3, 10355 },
1001         {  45000000, 0, 45, 3, 3, 10355 },
1002         {  45158000, 0, 45, 3, 3, 10355 },
1003         {  49125000, 0, 49, 3, 3, 9961 },
1004         {  49152000, 0, 49, 3, 3, 9961 },
1005         {  67737600, 1, 67, 3, 3, 48366 },
1006         {  67738000, 1, 67, 3, 3, 48366 },
1007         {  73800000, 1, 73, 3, 3, 47710 },
1008         {  73728000, 1, 73, 3, 3, 47710 },
1009         {  36000000, 1, 32, 3, 4, 0 },
1010         {  60000000, 1, 60, 3, 3, 0 },
1011         {  72000000, 1, 72, 3, 3, 0 },
1012         {  80000000, 1, 80, 3, 3, 0 },
1013         {  84000000, 0, 42, 3, 2, 0 },
1014         {  50000000, 0, 50, 3, 3, 0 },
1015 };
1016
1017 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1018 {
1019         unsigned int epll_con, epll_con_k;
1020         unsigned int i;
1021
1022         /* Return if nothing changed */
1023         if (clk->rate == rate)
1024                 return 0;
1025
1026         epll_con = __raw_readl(S5P_EPLL_CON);
1027         epll_con_k = __raw_readl(S5P_EPLL_CON1);
1028
1029         epll_con_k &= ~PLL46XX_KDIV_MASK;
1030         epll_con &= ~(1 << 27 |
1031                         PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1032                         PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1033                         PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1034
1035         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1036                 if (epll_div[i][0] == rate) {
1037                         epll_con_k |= epll_div[i][5] << 0;
1038                         epll_con |= (epll_div[i][1] << 27 |
1039                                         epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1040                                         epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1041                                         epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1042                         break;
1043                 }
1044         }
1045
1046         if (i == ARRAY_SIZE(epll_div)) {
1047                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1048                                 __func__);
1049                 return -EINVAL;
1050         }
1051
1052         __raw_writel(epll_con, S5P_EPLL_CON);
1053         __raw_writel(epll_con_k, S5P_EPLL_CON1);
1054
1055         printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1056                         clk->rate, rate);
1057
1058         clk->rate = rate;
1059
1060         return 0;
1061 }
1062
1063 static struct clk_ops s5pv210_epll_ops = {
1064         .set_rate = s5pv210_epll_set_rate,
1065         .get_rate = s5p_epll_get_rate,
1066 };
1067
1068 void __init_or_cpufreq s5pv210_setup_clocks(void)
1069 {
1070         struct clk *xtal_clk;
1071         unsigned long vpllsrc;
1072         unsigned long armclk;
1073         unsigned long hclk_msys;
1074         unsigned long hclk_dsys;
1075         unsigned long hclk_psys;
1076         unsigned long pclk_msys;
1077         unsigned long pclk_dsys;
1078         unsigned long pclk_psys;
1079         unsigned long apll;
1080         unsigned long mpll;
1081         unsigned long epll;
1082         unsigned long vpll;
1083         unsigned int ptr;
1084         u32 clkdiv0, clkdiv1;
1085
1086         /* Set functions for clk_fout_epll */
1087         clk_fout_epll.enable = s5p_epll_enable;
1088         clk_fout_epll.ops = &s5pv210_epll_ops;
1089
1090         printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1091
1092         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1093         clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1094
1095         printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1096                                 __func__, clkdiv0, clkdiv1);
1097
1098         xtal_clk = clk_get(NULL, "xtal");
1099         BUG_ON(IS_ERR(xtal_clk));
1100
1101         xtal = clk_get_rate(xtal_clk);
1102         clk_put(xtal_clk);
1103
1104         printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1105
1106         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1107         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1108         epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1109                                 __raw_readl(S5P_EPLL_CON1), pll_4600);
1110         vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1111         vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1112
1113         clk_fout_apll.ops = &clk_fout_apll_ops;
1114         clk_fout_mpll.rate = mpll;
1115         clk_fout_epll.rate = epll;
1116         clk_fout_vpll.rate = vpll;
1117
1118         printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1119                         apll, mpll, epll, vpll);
1120
1121         armclk = clk_get_rate(&clk_armclk.clk);
1122         hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1123         hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1124         hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1125         pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1126         pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1127         pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1128
1129         printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1130                          "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1131                         armclk, hclk_msys, hclk_dsys, hclk_psys,
1132                         pclk_msys, pclk_dsys, pclk_psys);
1133
1134         clk_f.rate = armclk;
1135         clk_h.rate = hclk_psys;
1136         clk_p.rate = pclk_psys;
1137
1138         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1139                 s3c_set_clksrc(&clksrcs[ptr], true);
1140 }
1141
1142 static struct clk *clks[] __initdata = {
1143         &clk_sclk_hdmi27m,
1144         &clk_sclk_hdmiphy,
1145         &clk_sclk_usbphy0,
1146         &clk_sclk_usbphy1,
1147         &clk_pcmcdclk0,
1148         &clk_pcmcdclk1,
1149         &clk_pcmcdclk2,
1150 };
1151
1152 void __init s5pv210_register_clocks(void)
1153 {
1154         int ptr;
1155
1156         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1157
1158         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1159                 s3c_register_clksrc(sysclks[ptr], 1);
1160
1161         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1162         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1163
1164         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1165         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1166
1167         s3c24xx_register_clock(&dummy_apb_pclk);
1168         s3c_pwmclk_init();
1169 }