1 /* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
6 * S5PC100 - GPIO register definitions
9 #ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
10 #define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
15 #define S5PC100_GPIO_BASE S5P_VA_GPIO
16 #define S5PC100_GPA0_BASE (S5PC100_GPIO_BASE + 0x0000)
17 #define S5PC100_GPA1_BASE (S5PC100_GPIO_BASE + 0x0020)
18 #define S5PC100_GPB_BASE (S5PC100_GPIO_BASE + 0x0040)
19 #define S5PC100_GPC_BASE (S5PC100_GPIO_BASE + 0x0060)
20 #define S5PC100_GPD_BASE (S5PC100_GPIO_BASE + 0x0080)
21 #define S5PC100_GPE0_BASE (S5PC100_GPIO_BASE + 0x00A0)
22 #define S5PC100_GPE1_BASE (S5PC100_GPIO_BASE + 0x00C0)
23 #define S5PC100_GPF0_BASE (S5PC100_GPIO_BASE + 0x00E0)
24 #define S5PC100_GPF1_BASE (S5PC100_GPIO_BASE + 0x0100)
25 #define S5PC100_GPF2_BASE (S5PC100_GPIO_BASE + 0x0120)
26 #define S5PC100_GPF3_BASE (S5PC100_GPIO_BASE + 0x0140)
27 #define S5PC100_GPG0_BASE (S5PC100_GPIO_BASE + 0x0160)
28 #define S5PC100_GPG1_BASE (S5PC100_GPIO_BASE + 0x0180)
29 #define S5PC100_GPG2_BASE (S5PC100_GPIO_BASE + 0x01A0)
30 #define S5PC100_GPG3_BASE (S5PC100_GPIO_BASE + 0x01C0)
31 #define S5PC100_GPH0_BASE (S5PC100_GPIO_BASE + 0x0C00)
32 #define S5PC100_GPH1_BASE (S5PC100_GPIO_BASE + 0x0C20)
33 #define S5PC100_GPH2_BASE (S5PC100_GPIO_BASE + 0x0C40)
34 #define S5PC100_GPH3_BASE (S5PC100_GPIO_BASE + 0x0C60)
35 #define S5PC100_GPI_BASE (S5PC100_GPIO_BASE + 0x01E0)
36 #define S5PC100_GPJ0_BASE (S5PC100_GPIO_BASE + 0x0200)
37 #define S5PC100_GPJ1_BASE (S5PC100_GPIO_BASE + 0x0220)
38 #define S5PC100_GPJ2_BASE (S5PC100_GPIO_BASE + 0x0240)
39 #define S5PC100_GPJ3_BASE (S5PC100_GPIO_BASE + 0x0260)
40 #define S5PC100_GPJ4_BASE (S5PC100_GPIO_BASE + 0x0280)
41 #define S5PC100_GPK0_BASE (S5PC100_GPIO_BASE + 0x02A0)
42 #define S5PC100_GPK1_BASE (S5PC100_GPIO_BASE + 0x02C0)
43 #define S5PC100_GPK2_BASE (S5PC100_GPIO_BASE + 0x02E0)
44 #define S5PC100_GPK3_BASE (S5PC100_GPIO_BASE + 0x0300)
45 #define S5PC100_GPL0_BASE (S5PC100_GPIO_BASE + 0x0320)
46 #define S5PC100_GPL1_BASE (S5PC100_GPIO_BASE + 0x0340)
47 #define S5PC100_GPL2_BASE (S5PC100_GPIO_BASE + 0x0360)
48 #define S5PC100_GPL3_BASE (S5PC100_GPIO_BASE + 0x0380)
49 #define S5PC100_GPL4_BASE (S5PC100_GPIO_BASE + 0x03A0)
51 #define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
52 #define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
54 #define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
55 #define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
57 #define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
58 #define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
60 #define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
61 #define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
63 #define eint_offset(irq) ((irq) < IRQ_EINT16_31 ? ((irq) - IRQ_EINT(0)) : \
64 (((irq) - S5P_EINT_BASE2)))
66 #define EINT_REG_NR(x) (eint_offset(x) >> 3)
68 #define eint_irq_to_bit(irq) (1 << (eint_offset(irq) & 0x7))
70 /* values for S5P_EXTINT0 */
71 #define S5P_EXTINT_LOWLEV (0x00)
72 #define S5P_EXTINT_HILEV (0x01)
73 #define S5P_EXTINT_FALLEDGE (0x02)
74 #define S5P_EXTINT_RISEEDGE (0x03)
75 #define S5P_EXTINT_BOTHEDGE (0x04)
77 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */