1 /* linux/arch/arm/mach-s5p64x0/gpio.c
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P64X0 - GPIOlib support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
19 #include <mach/regs-gpio.h>
21 #include <plat/gpio-core.h>
22 #include <plat/gpio-cfg.h>
23 #include <plat/gpio-cfg-helpers.h>
25 /* To be implemented S5P6450 GPIO */
28 * S5P6440 GPIO bank summary:
30 * Bank GPIOs Style SlpCon ExtInt Group
39 * N 16 2Bit No IRQ_EINT
43 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
44 * [2] BANK has two control registers, GPxCON0 and GPxCON1
47 static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
50 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
51 void __iomem *base = ourchip->base;
52 void __iomem *regcon = base;
72 s3c_gpio_lock(ourchip, flags);
74 con = __raw_readl(regcon);
75 con &= ~(0xf << con_4bit_shift(offset));
76 __raw_writel(con, regcon);
78 s3c_gpio_unlock(ourchip, flags);
83 static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
84 unsigned int offset, int value)
86 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
87 void __iomem *base = ourchip->base;
88 void __iomem *regcon = base;
92 unsigned con_offset = offset;
110 s3c_gpio_lock(ourchip, flags);
112 con = __raw_readl(regcon);
113 con &= ~(0xf << con_4bit_shift(con_offset));
114 con |= 0x1 << con_4bit_shift(con_offset);
116 dat = __raw_readl(base + GPIODAT_OFF);
120 dat &= ~(1 << offset);
122 __raw_writel(con, regcon);
123 __raw_writel(dat, base + GPIODAT_OFF);
125 s3c_gpio_unlock(ourchip, flags);
130 int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
131 unsigned int off, unsigned int cfg)
133 void __iomem *reg = chip->base;
145 shift = (off & 7) * 4;
149 shift = ((off + 1) & 7) * 4;
152 shift = ((off + 1) & 7) * 4;
156 if (s3c_gpio_is_cfg_special(cfg)) {
161 s3c_gpio_lock(chip, flags);
163 con = __raw_readl(reg);
164 con &= ~(0xf << shift);
166 __raw_writel(con, reg);
168 s3c_gpio_unlock(chip, flags);
173 static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = {
180 .set_config = s5p64x0_gpio_setcfg_4bit_rbank,
183 .set_config = s3c_gpio_setcfg_s3c24xx,
184 .get_config = s3c_gpio_getcfg_s3c24xx,
187 .set_config = s3c_gpio_setcfg_s3c24xx,
188 .get_config = s3c_gpio_getcfg_s3c24xx,
191 .set_config = s3c_gpio_setcfg_s3c24xx,
192 .get_config = s3c_gpio_getcfg_s3c24xx,
196 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
198 .base = S5P6440_GPA_BASE,
199 .config = &s5p64x0_gpio_cfgs[1],
201 .base = S5P6440_GPA(0),
202 .ngpio = S5P6440_GPIO_A_NR,
206 .base = S5P6440_GPB_BASE,
207 .config = &s5p64x0_gpio_cfgs[1],
209 .base = S5P6440_GPB(0),
210 .ngpio = S5P6440_GPIO_B_NR,
214 .base = S5P6440_GPC_BASE,
215 .config = &s5p64x0_gpio_cfgs[1],
217 .base = S5P6440_GPC(0),
218 .ngpio = S5P6440_GPIO_C_NR,
222 .base = S5P6440_GPG_BASE,
223 .config = &s5p64x0_gpio_cfgs[1],
225 .base = S5P6440_GPG(0),
226 .ngpio = S5P6440_GPIO_G_NR,
232 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
234 .base = S5P6440_GPH_BASE + 0x4,
235 .config = &s5p64x0_gpio_cfgs[1],
237 .base = S5P6440_GPH(0),
238 .ngpio = S5P6440_GPIO_H_NR,
244 static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = {
246 .base = S5P6440_GPR_BASE + 0x4,
247 .config = &s5p64x0_gpio_cfgs[2],
249 .base = S5P6440_GPR(0),
250 .ngpio = S5P6440_GPIO_R_NR,
256 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
258 .base = S5P6440_GPF_BASE,
259 .config = &s5p64x0_gpio_cfgs[5],
261 .base = S5P6440_GPF(0),
262 .ngpio = S5P6440_GPIO_F_NR,
266 .base = S5P6440_GPI_BASE,
267 .config = &s5p64x0_gpio_cfgs[3],
269 .base = S5P6440_GPI(0),
270 .ngpio = S5P6440_GPIO_I_NR,
274 .base = S5P6440_GPJ_BASE,
275 .config = &s5p64x0_gpio_cfgs[3],
277 .base = S5P6440_GPJ(0),
278 .ngpio = S5P6440_GPIO_J_NR,
282 .base = S5P6440_GPN_BASE,
283 .config = &s5p64x0_gpio_cfgs[4],
285 .base = S5P6440_GPN(0),
286 .ngpio = S5P6440_GPIO_N_NR,
290 .base = S5P6440_GPP_BASE,
291 .config = &s5p64x0_gpio_cfgs[5],
293 .base = S5P6440_GPP(0),
294 .ngpio = S5P6440_GPIO_P_NR,
300 void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
302 for (; nr_chips > 0; nr_chips--, chipcfg++) {
303 if (!chipcfg->set_config)
304 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
305 if (!chipcfg->get_config)
306 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
307 if (!chipcfg->set_pull)
308 chipcfg->set_pull = s3c_gpio_setpull_updown;
309 if (!chipcfg->get_pull)
310 chipcfg->get_pull = s3c_gpio_getpull_updown;
314 static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
317 for (; nr_chips > 0; nr_chips--, chip++) {
318 chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input;
319 chip->chip.direction_output =
320 s5p64x0_gpiolib_rbank_4bit2_output;
321 s3c_gpiolib_add(chip);
325 static int __init s5p6440_gpiolib_init(void)
327 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
328 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
330 s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs,
331 ARRAY_SIZE(s5p64x0_gpio_cfgs));
333 for (; nr_chips > 0; nr_chips--, chips++)
334 s3c_gpiolib_add(chips);
336 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
337 ARRAY_SIZE(s5p6440_gpio_4bit));
339 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
340 ARRAY_SIZE(s5p6440_gpio_4bit2));
342 s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2,
343 ARRAY_SIZE(s5p6440_gpio_rbank_4bit2));
347 arch_initcall(s5p6440_gpiolib_init);