1 /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * S5P6450 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
23 #include <mach/hardware.h>
25 #include <mach/regs-clock.h>
26 #include <mach/s5p64x0-clock.h>
28 #include <plat/cpu-freq.h>
29 #include <plat/clock.h>
32 #include <plat/s5p-clock.h>
33 #include <plat/clock-clksrc.h>
34 #include <plat/s5p6450.h>
36 static struct clksrc_clk clk_mout_dpll = {
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
45 static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
51 static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
53 unsigned int epll_con, epll_con_k;
56 if (clk->rate == rate) /* Return if nothing changed */
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
91 static struct clk_ops s5p6450_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6450_epll_set_rate,
96 static struct clksrc_clk clk_dout_epll = {
100 .parent = &clk_mout_epll.clk,
102 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
105 static struct clksrc_clk clk_mout_hclk_sel = {
107 .name = "mout_hclk_sel",
110 .sources = &clkset_hclk_low,
111 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
114 static struct clk *clkset_hclk_list[] = {
115 &clk_mout_hclk_sel.clk,
119 static struct clksrc_sources clkset_hclk = {
120 .sources = clkset_hclk_list,
121 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
124 static struct clksrc_clk clk_hclk = {
129 .sources = &clkset_hclk,
130 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
131 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
134 static struct clksrc_clk clk_pclk = {
138 .parent = &clk_hclk.clk,
140 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
142 static struct clksrc_clk clk_dout_pwm_ratio0 = {
144 .name = "clk_dout_pwm_ratio0",
146 .parent = &clk_mout_hclk_sel.clk,
148 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
151 static struct clksrc_clk clk_pclk_to_wdt_pwm = {
153 .name = "clk_pclk_to_wdt_pwm",
155 .parent = &clk_dout_pwm_ratio0.clk,
157 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
160 static struct clksrc_clk clk_hclk_low = {
162 .name = "clk_hclk_low",
165 .sources = &clkset_hclk_low,
166 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
167 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
170 static struct clksrc_clk clk_pclk_low = {
172 .name = "clk_pclk_low",
174 .parent = &clk_hclk_low.clk,
176 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
180 * The following clocks will be disabled during clock initialization. It is
181 * recommended to keep the following clocks disabled until the driver requests
182 * for enabling the clock.
184 static struct clk init_clocks_disable[] = {
188 .parent = &clk_hclk_low.clk,
189 .enable = s5p64x0_hclk0_ctrl,
194 .parent = &clk_hclk_low.clk,
195 .enable = s5p64x0_hclk0_ctrl,
196 .ctrlbit = (1 << 12),
200 .parent = &clk_hclk_low.clk,
201 .enable = s5p64x0_hclk0_ctrl,
202 .ctrlbit = (1 << 17),
206 .parent = &clk_hclk_low.clk,
207 .enable = s5p64x0_hclk0_ctrl,
208 .ctrlbit = (1 << 18),
212 .parent = &clk_hclk_low.clk,
213 .enable = s5p64x0_hclk0_ctrl,
214 .ctrlbit = (1 << 19),
218 .parent = &clk_hclk_low.clk,
219 .enable = s5p64x0_hclk0_ctrl,
220 .ctrlbit = (1 << 20),
225 .enable = s5p64x0_hclk1_ctrl,
230 .parent = &clk_pclk_low.clk,
231 .enable = s5p64x0_pclk_ctrl,
236 .parent = &clk_pclk_low.clk,
237 .enable = s5p64x0_pclk_ctrl,
238 .ctrlbit = (1 << 12),
242 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 17),
248 .parent = &clk_pclk_low.clk,
249 .enable = s5p64x0_pclk_ctrl,
250 .ctrlbit = (1 << 21),
254 .parent = &clk_pclk_low.clk,
255 .enable = s5p64x0_pclk_ctrl,
256 .ctrlbit = (1 << 22),
260 .parent = &clk_pclk_low.clk,
261 .enable = s5p64x0_pclk_ctrl,
262 .ctrlbit = (1 << 26),
266 .parent = &clk_pclk_low.clk,
267 .enable = s5p64x0_pclk_ctrl,
268 .ctrlbit = (1 << 15),
272 .parent = &clk_pclk_low.clk,
273 .enable = s5p64x0_pclk_ctrl,
274 .ctrlbit = (1 << 16),
278 .parent = &clk_pclk_low.clk,
279 .enable = s5p64x0_pclk_ctrl,
280 .ctrlbit = (1 << 27),
284 .parent = &clk_pclk.clk,
285 .enable = s5p64x0_pclk_ctrl,
286 .ctrlbit = (1 << 30),
291 * The following clocks will be enabled during clock initialization.
293 static struct clk init_clocks[] = {
297 .parent = &clk_hclk.clk,
298 .enable = s5p64x0_hclk0_ctrl,
303 .parent = &clk_hclk.clk,
304 .enable = s5p64x0_hclk0_ctrl,
305 .ctrlbit = (1 << 21),
309 .parent = &clk_pclk_low.clk,
310 .enable = s5p64x0_pclk_ctrl,
315 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl,
321 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl,
327 .parent = &clk_pclk_low.clk,
328 .enable = s5p64x0_pclk_ctrl,
333 .parent = &clk_pclk_to_wdt_pwm.clk,
334 .enable = s5p64x0_pclk_ctrl,
339 .parent = &clk_pclk_low.clk,
340 .enable = s5p64x0_pclk_ctrl,
341 .ctrlbit = (1 << 18),
345 static struct clk *clkset_uart_list[] = {
350 static struct clksrc_sources clkset_uart = {
351 .sources = clkset_uart_list,
352 .nr_sources = ARRAY_SIZE(clkset_uart_list),
355 static struct clk *clkset_mali_list[] = {
361 static struct clksrc_sources clkset_mali = {
362 .sources = clkset_mali_list,
363 .nr_sources = ARRAY_SIZE(clkset_mali_list),
366 static struct clk *clkset_group2_list[] = {
372 static struct clksrc_sources clkset_group2 = {
373 .sources = clkset_group2_list,
374 .nr_sources = ARRAY_SIZE(clkset_group2_list),
377 static struct clk *clkset_dispcon_list[] = {
384 static struct clksrc_sources clkset_dispcon = {
385 .sources = clkset_dispcon_list,
386 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
389 static struct clk *clkset_hsmmc44_list[] = {
397 static struct clksrc_sources clkset_hsmmc44 = {
398 .sources = clkset_hsmmc44_list,
399 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
402 static struct clk *clkset_sclk_audio0_list[] = {
403 [0] = &clk_dout_epll.clk,
404 [1] = &clk_dout_mpll.clk,
405 [2] = &clk_ext_xtal_mux,
410 static struct clksrc_sources clkset_sclk_audio0 = {
411 .sources = clkset_sclk_audio0_list,
412 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
415 static struct clksrc_clk clk_sclk_audio0 = {
419 .enable = s5p64x0_sclk_ctrl,
421 .parent = &clk_dout_epll.clk,
423 .sources = &clkset_sclk_audio0,
424 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
425 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
428 static struct clksrc_clk clksrcs[] = {
433 .ctrlbit = (1 << 24),
434 .enable = s5p64x0_sclk_ctrl,
436 .sources = &clkset_group2,
437 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
438 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
443 .ctrlbit = (1 << 25),
444 .enable = s5p64x0_sclk_ctrl,
446 .sources = &clkset_group2,
447 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
448 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
453 .ctrlbit = (1 << 26),
454 .enable = s5p64x0_sclk_ctrl,
456 .sources = &clkset_group2,
457 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
458 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
464 .enable = s5p64x0_sclk_ctrl,
466 .sources = &clkset_uart,
467 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
468 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
473 .ctrlbit = (1 << 20),
474 .enable = s5p64x0_sclk_ctrl,
476 .sources = &clkset_group2,
477 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
478 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
483 .ctrlbit = (1 << 21),
484 .enable = s5p64x0_sclk_ctrl,
486 .sources = &clkset_group2,
487 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
488 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
493 .ctrlbit = (1 << 10),
494 .enable = s5p64x0_sclk_ctrl,
496 .sources = &clkset_group2,
497 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
498 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
504 .enable = s5p64x0_sclk1_ctrl,
506 .sources = &clkset_mali,
507 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
508 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
513 .ctrlbit = (1 << 12),
514 .enable = s5p64x0_sclk_ctrl,
516 .sources = &clkset_mali,
517 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
518 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
524 .enable = s5p64x0_sclk_ctrl,
526 .sources = &clkset_group2,
527 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
528 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
531 .name = "sclk_camif",
534 .enable = s5p64x0_sclk_ctrl,
536 .sources = &clkset_group2,
537 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
538 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
541 .name = "sclk_dispcon",
544 .enable = s5p64x0_sclk1_ctrl,
546 .sources = &clkset_dispcon,
547 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
548 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
551 .name = "sclk_hsmmc44",
553 .ctrlbit = (1 << 30),
554 .enable = s5p64x0_sclk_ctrl,
556 .sources = &clkset_hsmmc44,
557 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
558 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
562 /* Clock initialization code */
563 static struct clksrc_clk *sysclks[] = {
571 &clk_dout_pwm_ratio0,
572 &clk_pclk_to_wdt_pwm,
580 void __init_or_cpufreq s5p6450_setup_clocks(void)
582 struct clk *xtal_clk;
587 unsigned long hclk_low;
589 unsigned long pclk_low;
597 /* Set S5P6450 functions for clk_fout_epll */
599 clk_fout_epll.enable = s5p_epll_enable;
600 clk_fout_epll.ops = &s5p6450_epll_ops;
602 clk_48m.enable = s5p64x0_clk48m_ctrl;
604 xtal_clk = clk_get(NULL, "ext_xtal");
605 BUG_ON(IS_ERR(xtal_clk));
607 xtal = clk_get_rate(xtal_clk);
610 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
611 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
612 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
613 __raw_readl(S5P64X0_EPLL_CON_K));
614 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
615 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
617 clk_fout_apll.rate = apll;
618 clk_fout_mpll.rate = mpll;
619 clk_fout_epll.rate = epll;
620 clk_fout_dpll.rate = dpll;
622 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
623 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
624 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
627 fclk = clk_get_rate(&clk_armclk.clk);
628 hclk = clk_get_rate(&clk_hclk.clk);
629 pclk = clk_get_rate(&clk_pclk.clk);
630 hclk_low = clk_get_rate(&clk_hclk_low.clk);
631 pclk_low = clk_get_rate(&clk_pclk_low.clk);
633 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
634 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
635 print_mhz(hclk), print_mhz(hclk_low),
636 print_mhz(pclk), print_mhz(pclk_low));
642 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
643 s3c_set_clksrc(&clksrcs[ptr], true);
646 void __init s5p6450_register_clocks(void)
652 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
653 s3c_register_clksrc(sysclks[ptr], 1);
655 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
656 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
658 clkp = init_clocks_disable;
659 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
661 ret = s3c24xx_register_clock(clkp);
663 printk(KERN_ERR "Failed to register clock %s (%d)\n",
666 (clkp->enable)(clkp, 0);