1 /* arch/arm/mach-s5p6440/gpio.c
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5P6440 - GPIOlib support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
17 #include <mach/gpio.h>
18 #include <mach/regs-gpio.h>
19 #include <plat/gpio-core.h>
20 #include <plat/gpio-cfg.h>
21 #include <plat/gpio-cfg-helpers.h>
25 * Bank GPIOs Style SlpCon ExtInt Group
34 * N 16 2Bit No IRQ_EINT
38 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
39 * [2] BANK has two control registers, GPxCON0 and GPxCON1
42 static int s5p6440_gpiolib_rbank_4bit2_input(struct gpio_chip *chip,
45 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
46 void __iomem *base = ourchip->base;
47 void __iomem *regcon = base;
66 con = __raw_readl(regcon);
67 con &= ~(0xf << con_4bit_shift(offset));
68 __raw_writel(con, regcon);
73 static int s5p6440_gpiolib_rbank_4bit2_output(struct gpio_chip *chip,
74 unsigned int offset, int value)
76 struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
77 void __iomem *base = ourchip->base;
78 void __iomem *regcon = base;
81 unsigned con_offset = offset;
99 con = __raw_readl(regcon);
100 con &= ~(0xf << con_4bit_shift(con_offset));
101 con |= 0x1 << con_4bit_shift(con_offset);
103 dat = __raw_readl(base + GPIODAT_OFF);
107 dat &= ~(1 << offset);
109 __raw_writel(con, regcon);
110 __raw_writel(dat, base + GPIODAT_OFF);
115 int s5p6440_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip,
116 unsigned int off, unsigned int cfg)
118 void __iomem *reg = chip->base;
129 shift = (off & 7) * 4;
133 shift = ((off + 1) & 7) * 4;
136 shift = ((off + 1) & 7) * 4;
140 if (s3c_gpio_is_cfg_special(cfg)) {
145 con = __raw_readl(reg);
146 con &= ~(0xf << shift);
148 __raw_writel(con, reg);
153 static struct s3c_gpio_cfg s5p6440_gpio_cfgs[] = {
160 .set_config = s5p6440_gpio_setcfg_4bit_rbank,
163 .set_config = s3c_gpio_setcfg_s3c24xx,
164 .get_config = s3c_gpio_getcfg_s3c24xx,
167 .set_config = s3c_gpio_setcfg_s3c24xx,
168 .get_config = s3c_gpio_getcfg_s3c24xx,
171 .set_config = s3c_gpio_setcfg_s3c24xx,
172 .get_config = s3c_gpio_getcfg_s3c24xx,
176 static struct s3c_gpio_chip s5p6440_gpio_4bit[] = {
178 .base = S5P6440_GPA_BASE,
179 .config = &s5p6440_gpio_cfgs[1],
181 .base = S5P6440_GPA(0),
182 .ngpio = S5P6440_GPIO_A_NR,
186 .base = S5P6440_GPB_BASE,
187 .config = &s5p6440_gpio_cfgs[1],
189 .base = S5P6440_GPB(0),
190 .ngpio = S5P6440_GPIO_B_NR,
194 .base = S5P6440_GPC_BASE,
195 .config = &s5p6440_gpio_cfgs[1],
197 .base = S5P6440_GPC(0),
198 .ngpio = S5P6440_GPIO_C_NR,
202 .base = S5P6440_GPG_BASE,
203 .config = &s5p6440_gpio_cfgs[1],
205 .base = S5P6440_GPG(0),
206 .ngpio = S5P6440_GPIO_G_NR,
212 static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = {
214 .base = S5P6440_GPH_BASE + 0x4,
215 .config = &s5p6440_gpio_cfgs[1],
217 .base = S5P6440_GPH(0),
218 .ngpio = S5P6440_GPIO_H_NR,
224 static struct s3c_gpio_chip gpio_rbank_4bit2[] = {
226 .base = S5P6440_GPR_BASE + 0x4,
227 .config = &s5p6440_gpio_cfgs[2],
229 .base = S5P6440_GPR(0),
230 .ngpio = S5P6440_GPIO_R_NR,
236 static struct s3c_gpio_chip s5p6440_gpio_2bit[] = {
238 .base = S5P6440_GPF_BASE,
239 .config = &s5p6440_gpio_cfgs[5],
241 .base = S5P6440_GPF(0),
242 .ngpio = S5P6440_GPIO_F_NR,
246 .base = S5P6440_GPI_BASE,
247 .config = &s5p6440_gpio_cfgs[3],
249 .base = S5P6440_GPI(0),
250 .ngpio = S5P6440_GPIO_I_NR,
254 .base = S5P6440_GPJ_BASE,
255 .config = &s5p6440_gpio_cfgs[3],
257 .base = S5P6440_GPJ(0),
258 .ngpio = S5P6440_GPIO_J_NR,
262 .base = S5P6440_GPN_BASE,
263 .config = &s5p6440_gpio_cfgs[4],
265 .base = S5P6440_GPN(0),
266 .ngpio = S5P6440_GPIO_N_NR,
270 .base = S5P6440_GPP_BASE,
271 .config = &s5p6440_gpio_cfgs[5],
273 .base = S5P6440_GPP(0),
274 .ngpio = S5P6440_GPIO_P_NR,
280 void __init s5p6440_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips)
282 for (; nr_chips > 0; nr_chips--, chipcfg++) {
283 if (!chipcfg->set_config)
284 chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit;
285 if (!chipcfg->get_config)
286 chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit;
287 if (!chipcfg->set_pull)
288 chipcfg->set_pull = s3c_gpio_setpull_updown;
289 if (!chipcfg->get_pull)
290 chipcfg->get_pull = s3c_gpio_getpull_updown;
294 static void __init s5p6440_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip,
297 for (; nr_chips > 0; nr_chips--, chip++) {
298 chip->chip.direction_input = s5p6440_gpiolib_rbank_4bit2_input;
299 chip->chip.direction_output =
300 s5p6440_gpiolib_rbank_4bit2_output;
301 s3c_gpiolib_add(chip);
305 static int __init s5p6440_gpiolib_init(void)
307 struct s3c_gpio_chip *chips = s5p6440_gpio_2bit;
308 int nr_chips = ARRAY_SIZE(s5p6440_gpio_2bit);
310 s5p6440_gpiolib_set_cfg(s5p6440_gpio_cfgs,
311 ARRAY_SIZE(s5p6440_gpio_cfgs));
313 for (; nr_chips > 0; nr_chips--, chips++)
314 s3c_gpiolib_add(chips);
316 samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit,
317 ARRAY_SIZE(s5p6440_gpio_4bit));
319 samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2,
320 ARRAY_SIZE(s5p6440_gpio_4bit2));
322 s5p6440_gpio_add_rbank_4bit2(gpio_rbank_4bit2,
323 ARRAY_SIZE(gpio_rbank_4bit2));
327 arch_initcall(s5p6440_gpiolib_init);