arch/arm/mach-s5p6440/clock.c

   1 /* linux/arch/arm/mach-s5p6440/clock.c
   2  *
   3  * Copyright (c) 2009 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5P6440 - Clock support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/init.h>
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/list.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/io.h>
  22
  23 #include <mach/hardware.h>
  24 #include <mach/map.h>
  25
  26 #include <plat/cpu-freq.h>
  27 #include <mach/regs-clock.h>
  28 #include <plat/clock.h>
  29 #include <plat/cpu.h>
  30 #include <plat/clock-clksrc.h>
  31 #include <plat/s5p-clock.h>
  32 #include <plat/pll.h>
  33 #include <plat/s5p6440.h>
  34
  35 /* APLL Mux output clock */
  36 static struct clksrc_clk clk_mout_apll = {
  37         .clk    = {
  38                 .name           = "mout_apll",
  39                 .id             = -1,
  40         },
  41         .sources        = &clk_src_apll,
  42         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
  43 };
  44
  45 static int s5p6440_epll_enable(struct clk *clk, int enable)
  46 {
  47         unsigned int ctrlbit = clk->ctrlbit;
  48         unsigned int epll_con = __raw_readl(S5P_EPLL_CON) & ~ctrlbit;
  49
  50         if (enable)
  51                 __raw_writel(epll_con | ctrlbit, S5P_EPLL_CON);
  52         else
  53                 __raw_writel(epll_con, S5P_EPLL_CON);
  54
  55         return 0;
  56 }
  57
  58 static unsigned long s5p6440_epll_get_rate(struct clk *clk)
  59 {
  60         return clk->rate;
  61 }
  62
  63 static u32 epll_div[][5] = {
  64         { 36000000,     0,      48, 1, 4 },
  65         { 48000000,     0,      32, 1, 3 },
  66         { 60000000,     0,      40, 1, 3 },
  67         { 72000000,     0,      48, 1, 3 },
  68         { 84000000,     0,      28, 1, 2 },
  69         { 96000000,     0,      32, 1, 2 },
  70         { 32768000,     45264,  43, 1, 4 },
  71         { 45158000,     6903,   30, 1, 3 },
  72         { 49152000,     50332,  32, 1, 3 },
  73         { 67738000,     10398,  45, 1, 3 },
  74         { 73728000,     9961,   49, 1, 3 }
  75 };
  76
  77 static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
  78 {
  79         unsigned int epll_con, epll_con_k;
  80         unsigned int i;
  81
  82         if (clk->rate == rate)  /* Return if nothing changed */
  83                 return 0;
  84
  85         epll_con = __raw_readl(S5P_EPLL_CON);
  86         epll_con_k = __raw_readl(S5P_EPLL_CON_K);
  87
  88         epll_con_k &= ~(PLL90XX_KDIV_MASK);
  89         epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
  90
  91         for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
  92                  if (epll_div[i][0] == rate) {
  93                         epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
  94                         epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
  95                                     (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
  96                                     (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
  97                         break;
  98                 }
  99         }
 100
 101         if (i == ARRAY_SIZE(epll_div)) {
 102                 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
 103                 return -EINVAL;
 104         }
 105
 106         __raw_writel(epll_con, S5P_EPLL_CON);
 107         __raw_writel(epll_con_k, S5P_EPLL_CON_K);
 108
 109         clk->rate = rate;
 110
 111         return 0;
 112 }
 113
 114 static struct clk_ops s5p6440_epll_ops = {
 115         .get_rate = s5p6440_epll_get_rate,
 116         .set_rate = s5p6440_epll_set_rate,
 117 };
 118
 119 static struct clksrc_clk clk_mout_epll = {
 120         .clk    = {
 121                 .name           = "mout_epll",
 122                 .id             = -1,
 123         },
 124         .sources        = &clk_src_epll,
 125         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 2, .size = 1 },
 126 };
 127
 128 static struct clksrc_clk clk_mout_mpll = {
 129         .clk = {
 130                 .name           = "mout_mpll",
 131                 .id             = -1,
 132         },
 133         .sources        = &clk_src_mpll,
 134         .reg_src        = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
 135 };
 136
 137 static struct clk clk_p_low = {
 138         .name           = "pclk_low",
 139         .id             = -1,
 140         .rate           = 0,
 141         .parent         = NULL,
 142         .ctrlbit        = 0,
 143         .ops            = &clk_ops_def_setrate,
 144 };
 145
 146 enum perf_level {
 147         L0 = 532*1000,
 148         L1 = 266*1000,
 149         L2 = 133*1000,
 150 };
 151
 152 static const u32 clock_table[][3] = {
 153         /*{ARM_CLK, DIVarm, DIVhclk}*/
 154         {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P_CLKDIV0_HCLK_SHIFT)},
 155         {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P_CLKDIV0_HCLK_SHIFT)},
 156         {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P_CLKDIV0_HCLK_SHIFT)},
 157 };
 158
 159 static unsigned long s5p6440_armclk_get_rate(struct clk *clk)
 160 {
 161         unsigned long rate = clk_get_rate(clk->parent);
 162         u32 clkdiv;
 163
 164         /* divisor mask starts at bit0, so no need to shift */
 165         clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
 166
 167         return rate / (clkdiv + 1);
 168 }
 169
 170 static unsigned long s5p6440_armclk_round_rate(struct clk *clk,
 171                                                 unsigned long rate)
 172 {
 173         u32 iter;
 174
 175         for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
 176                 if (rate > clock_table[iter][0])
 177                         return clock_table[iter-1][0];
 178         }
 179
 180         return clock_table[ARRAY_SIZE(clock_table) - 1][0];
 181 }
 182
 183 static int s5p6440_armclk_set_rate(struct clk *clk, unsigned long rate)
 184 {
 185         u32 round_tmp;
 186         u32 iter;
 187         u32 clk_div0_tmp;
 188         u32 cur_rate = clk->ops->get_rate(clk);
 189         unsigned long flags;
 190
 191         round_tmp = clk->ops->round_rate(clk, rate);
 192         if (round_tmp == cur_rate)
 193                 return 0;
 194
 195
 196         for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
 197                 if (round_tmp == clock_table[iter][0])
 198                         break;
 199         }
 200
 201         if (iter >= ARRAY_SIZE(clock_table))
 202                 iter = ARRAY_SIZE(clock_table) - 1;
 203
 204         local_irq_save(flags);
 205         if (cur_rate > round_tmp) {
 206                 /* Frequency Down */
 207                 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
 208                 clk_div0_tmp |= clock_table[iter][1];
 209                 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
 210
 211                 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
 212                                 ~(S5P_CLKDIV0_HCLK_MASK);
 213                 clk_div0_tmp |= clock_table[iter][2];
 214                 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
 215
 216
 217         } else {
 218                 /* Frequency Up */
 219                 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
 220                                 ~(S5P_CLKDIV0_HCLK_MASK);
 221                 clk_div0_tmp |= clock_table[iter][2];
 222                 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
 223
 224                 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
 225                 clk_div0_tmp |= clock_table[iter][1];
 226                 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
 227                 }
 228         local_irq_restore(flags);
 229
 230         clk->rate = clock_table[iter][0];
 231
 232         return 0;
 233 }
 234
 235 static struct clk_ops s5p6440_clkarm_ops = {
 236         .get_rate       = s5p6440_armclk_get_rate,
 237         .set_rate       = s5p6440_armclk_set_rate,
 238         .round_rate     = s5p6440_armclk_round_rate,
 239 };
 240
 241 static struct clksrc_clk clk_armclk = {
 242         .clk    = {
 243                 .name   = "armclk",
 244                 .id     = 1,
 245                 .parent = &clk_mout_apll.clk,
 246                 .ops    = &s5p6440_clkarm_ops,
 247         },
 248         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
 249 };
 250
 251 static struct clksrc_clk clk_dout_mpll = {
 252         .clk    = {
 253                 .name   = "dout_mpll",
 254                 .id     = -1,
 255                 .parent = &clk_mout_mpll.clk,
 256         },
 257         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
 258 };
 259
 260 static struct clksrc_clk clk_hclk = {
 261         .clk    = {
 262                 .name   = "clk_hclk",
 263                 .id     = -1,
 264                 .parent = &clk_armclk.clk,
 265         },
 266         .reg_div        = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
 267 };
 268
 269 static struct clksrc_clk clk_pclk = {
 270         .clk    = {
 271                 .name   = "clk_pclk",
 272                 .id     = -1,
 273                 .parent = &clk_hclk.clk,
 274         },
 275         .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
 276 };
 277
 278 static struct clk *clkset_hclklow_list[] = {
 279         &clk_mout_apll.clk,
 280         &clk_mout_mpll.clk,
 281 };
 282
 283 static struct clksrc_sources clkset_hclklow = {
 284         .sources        = clkset_hclklow_list,
 285         .nr_sources     = ARRAY_SIZE(clkset_hclklow_list),
 286 };
 287
 288 static struct clksrc_clk clk_hclk_low = {
 289         .clk = {
 290                 .name   = "hclk_low",
 291                 .id     = -1,
 292         },
 293         .sources        = &clkset_hclklow,
 294         .reg_src        = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
 295         .reg_div        = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
 296 };
 297
 298 int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
 299 {
 300         unsigned long flags;
 301         u32 val;
 302
 303         /* can't rely on clock lock, this register has other usages */
 304         local_irq_save(flags);
 305
 306         val = __raw_readl(S5P_OTHERS);
 307         if (enable)
 308                 val |= S5P_OTHERS_USB_SIG_MASK;
 309         else
 310                 val &= ~S5P_OTHERS_USB_SIG_MASK;
 311
 312         __raw_writel(val, S5P_OTHERS);
 313
 314         local_irq_restore(flags);
 315
 316         return 0;
 317 }
 318
 319 static int s5p6440_pclk_ctrl(struct clk *clk, int enable)
 320 {
 321         return s5p_gatectrl(S5P_CLK_GATE_PCLK, clk, enable);
 322 }
 323
 324 static int s5p6440_hclk0_ctrl(struct clk *clk, int enable)
 325 {
 326         return s5p_gatectrl(S5P_CLK_GATE_HCLK0, clk, enable);
 327 }
 328
 329 static int s5p6440_hclk1_ctrl(struct clk *clk, int enable)
 330 {
 331         return s5p_gatectrl(S5P_CLK_GATE_HCLK1, clk, enable);
 332 }
 333
 334 static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
 335 {
 336         return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
 337 }
 338
 339 static int s5p6440_mem_ctrl(struct clk *clk, int enable)
 340 {
 341         return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
 342 }
 343
 344 /*
 345  * The following clocks will be disabled during clock initialization. It is
 346  * recommended to keep the following clocks disabled until the driver requests
 347  * for enabling the clock.
 348  */
 349 static struct clk init_clocks_disable[] = {
 350         {
 351                 .name           = "nand",
 352                 .id             = -1,
 353                 .parent         = &clk_hclk.clk,
 354                 .enable         = s5p6440_mem_ctrl,
 355                 .ctrlbit        = S5P_CLKCON_MEM0_HCLK_NFCON,
 356         }, {
 357                 .name           = "adc",
 358                 .id             = -1,
 359                 .parent         = &clk_p_low,
 360                 .enable         = s5p6440_pclk_ctrl,
 361                 .ctrlbit        = S5P_CLKCON_PCLK_TSADC,
 362         }, {
 363                 .name           = "i2c",
 364                 .id             = -1,
 365                 .parent         = &clk_p_low,
 366                 .enable         = s5p6440_pclk_ctrl,
 367                 .ctrlbit        = S5P_CLKCON_PCLK_IIC0,
 368         }, {
 369                 .name           = "i2s_v40",
 370                 .id             = 0,
 371                 .parent         = &clk_p_low,
 372                 .enable         = s5p6440_pclk_ctrl,
 373                 .ctrlbit        = S5P_CLKCON_PCLK_IIS2,
 374         }, {
 375                 .name           = "spi",
 376                 .id             = 0,
 377                 .parent         = &clk_p_low,
 378                 .enable         = s5p6440_pclk_ctrl,
 379                 .ctrlbit        = S5P_CLKCON_PCLK_SPI0,
 380         }, {
 381                 .name           = "spi",
 382                 .id             = 1,
 383                 .parent         = &clk_p_low,
 384                 .enable         = s5p6440_pclk_ctrl,
 385                 .ctrlbit        = S5P_CLKCON_PCLK_SPI1,
 386         }, {
 387                 .name           = "sclk_spi_48",
 388                 .id             = 0,
 389                 .parent         = &clk_48m,
 390                 .enable         = s5p6440_sclk_ctrl,
 391                 .ctrlbit        = S5P_CLKCON_SCLK0_SPI0_48,
 392         }, {
 393                 .name           = "sclk_spi_48",
 394                 .id             = 1,
 395                 .parent         = &clk_48m,
 396                 .enable         = s5p6440_sclk_ctrl,
 397                 .ctrlbit        = S5P_CLKCON_SCLK0_SPI1_48,
 398         }, {
 399                 .name           = "mmc_48m",
 400                 .id             = 0,
 401                 .parent         = &clk_48m,
 402                 .enable         = s5p6440_sclk_ctrl,
 403                 .ctrlbit        = S5P_CLKCON_SCLK0_MMC0_48,
 404         }, {
 405                 .name           = "mmc_48m",
 406                 .id             = 1,
 407                 .parent         = &clk_48m,
 408                 .enable         = s5p6440_sclk_ctrl,
 409                 .ctrlbit        = S5P_CLKCON_SCLK0_MMC1_48,
 410         }, {
 411                 .name           = "mmc_48m",
 412                 .id             = 2,
 413                 .parent         = &clk_48m,
 414                 .enable         = s5p6440_sclk_ctrl,
 415                 .ctrlbit        = S5P_CLKCON_SCLK0_MMC2_48,
 416         }, {
 417                 .name           = "otg",
 418                 .id             = -1,
 419                 .parent         = &clk_hclk_low.clk,
 420                 .enable         = s5p6440_hclk0_ctrl,
 421                 .ctrlbit        = S5P_CLKCON_HCLK0_USB
 422         }, {
 423                 .name           = "post",
 424                 .id             = -1,
 425                 .parent         = &clk_hclk_low.clk,
 426                 .enable         = s5p6440_hclk0_ctrl,
 427                 .ctrlbit        = S5P_CLKCON_HCLK0_POST0
 428         }, {
 429                 .name           = "lcd",
 430                 .id             = -1,
 431                 .parent         = &clk_hclk_low.clk,
 432                 .enable         = s5p6440_hclk1_ctrl,
 433                 .ctrlbit        = S5P_CLKCON_HCLK1_DISPCON,
 434         }, {
 435                 .name           = "hsmmc",
 436                 .id             = 0,
 437                 .parent         = &clk_hclk_low.clk,
 438                 .enable         = s5p6440_hclk0_ctrl,
 439                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC0,
 440         }, {
 441                 .name           = "hsmmc",
 442                 .id             = 1,
 443                 .parent         = &clk_hclk_low.clk,
 444                 .enable         = s5p6440_hclk0_ctrl,
 445                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC1,
 446         }, {
 447                 .name           = "hsmmc",
 448                 .id             = 2,
 449                 .parent         = &clk_hclk_low.clk,
 450                 .enable         = s5p6440_hclk0_ctrl,
 451                 .ctrlbit        = S5P_CLKCON_HCLK0_HSMMC2,
 452         }, {
 453                 .name           = "rtc",
 454                 .id             = -1,
 455                 .parent         = &clk_p_low,
 456                 .enable         = s5p6440_pclk_ctrl,
 457                 .ctrlbit        = S5P_CLKCON_PCLK_RTC,
 458         }, {
 459                 .name           = "watchdog",
 460                 .id             = -1,
 461                 .parent         = &clk_p_low,
 462                 .enable         = s5p6440_pclk_ctrl,
 463                 .ctrlbit        = S5P_CLKCON_PCLK_WDT,
 464         }, {
 465                 .name           = "timers",
 466                 .id             = -1,
 467                 .parent         = &clk_p_low,
 468                 .enable         = s5p6440_pclk_ctrl,
 469                 .ctrlbit        = S5P_CLKCON_PCLK_PWM,
 470         }
 471 };
 472
 473 /*
 474  * The following clocks will be enabled during clock initialization.
 475  */
 476 static struct clk init_clocks[] = {
 477         {
 478                 .name           = "gpio",
 479                 .id             = -1,
 480                 .parent         = &clk_p_low,
 481                 .enable         = s5p6440_pclk_ctrl,
 482                 .ctrlbit        = S5P_CLKCON_PCLK_GPIO,
 483         }, {
 484                 .name           = "uart",
 485                 .id             = 0,
 486                 .parent         = &clk_p_low,
 487                 .enable         = s5p6440_pclk_ctrl,
 488                 .ctrlbit        = S5P_CLKCON_PCLK_UART0,
 489         }, {
 490                 .name           = "uart",
 491                 .id             = 1,
 492                 .parent         = &clk_p_low,
 493                 .enable         = s5p6440_pclk_ctrl,
 494                 .ctrlbit        = S5P_CLKCON_PCLK_UART1,
 495         }, {
 496                 .name           = "uart",
 497                 .id             = 2,
 498                 .parent         = &clk_p_low,
 499                 .enable         = s5p6440_pclk_ctrl,
 500                 .ctrlbit        = S5P_CLKCON_PCLK_UART2,
 501         }, {
 502                 .name           = "uart",
 503                 .id             = 3,
 504                 .parent         = &clk_p_low,
 505                 .enable         = s5p6440_pclk_ctrl,
 506                 .ctrlbit        = S5P_CLKCON_PCLK_UART3,
 507         }
 508 };
 509
 510 static struct clk clk_iis_cd_v40 = {
 511         .name           = "iis_cdclk_v40",
 512         .id             = -1,
 513 };
 514
 515 static struct clk clk_pcm_cd = {
 516         .name           = "pcm_cdclk",
 517         .id             = -1,
 518 };
 519
 520 static struct clk *clkset_spi_mmc_list[] = {
 521         &clk_mout_epll.clk,
 522         &clk_dout_mpll.clk,
 523         &clk_fin_epll,
 524 };
 525
 526 static struct clksrc_sources clkset_spi_mmc = {
 527         .sources        = clkset_spi_mmc_list,
 528         .nr_sources     = ARRAY_SIZE(clkset_spi_mmc_list),
 529 };
 530
 531 static struct clk *clkset_uart_list[] = {
 532         &clk_mout_epll.clk,
 533         &clk_dout_mpll.clk,
 534 };
 535
 536 static struct clksrc_sources clkset_uart = {
 537         .sources        = clkset_uart_list,
 538         .nr_sources     = ARRAY_SIZE(clkset_uart_list),
 539 };
 540
 541 static struct clksrc_clk clksrcs[] = {
 542         {
 543                 .clk    = {
 544                         .name           = "mmc_bus",
 545                         .id             = 0,
 546                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC0,
 547                         .enable         = s5p6440_sclk_ctrl,
 548                 },
 549                 .sources = &clkset_spi_mmc,
 550                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
 551                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
 552         }, {
 553                 .clk    = {
 554                         .name           = "mmc_bus",
 555                         .id             = 1,
 556                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC1,
 557                         .enable         = s5p6440_sclk_ctrl,
 558                 },
 559                 .sources = &clkset_spi_mmc,
 560                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
 561                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
 562         }, {
 563                 .clk    = {
 564                         .name           = "mmc_bus",
 565                         .id             = 2,
 566                         .ctrlbit        = S5P_CLKCON_SCLK0_MMC2,
 567                         .enable         = s5p6440_sclk_ctrl,
 568                 },
 569                 .sources = &clkset_spi_mmc,
 570                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
 571                 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
 572         }, {
 573                 .clk    = {
 574                         .name           = "uclk1",
 575                         .id             = -1,
 576                         .ctrlbit        = S5P_CLKCON_SCLK0_UART,
 577                         .enable         = s5p6440_sclk_ctrl,
 578                 },
 579                 .sources = &clkset_uart,
 580                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 13, .size = 1 },
 581                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
 582         }, {
 583                 .clk    = {
 584                         .name           = "spi_epll",
 585                         .id             = 0,
 586                         .ctrlbit        = S5P_CLKCON_SCLK0_SPI0,
 587                         .enable         = s5p6440_sclk_ctrl,
 588                 },
 589                 .sources = &clkset_spi_mmc,
 590                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
 591                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
 592         }, {
 593                 .clk    = {
 594                         .name           = "spi_epll",
 595                         .id             = 1,
 596                         .ctrlbit        = S5P_CLKCON_SCLK0_SPI1,
 597                         .enable         = s5p6440_sclk_ctrl,
 598                 },
 599                 .sources = &clkset_spi_mmc,
 600                 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
 601                 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
 602         }
 603 };
 604
 605 /* Clock initialisation code */
 606 static struct clksrc_clk *sysclks[] = {
 607         &clk_mout_apll,
 608         &clk_mout_epll,
 609         &clk_mout_mpll,
 610         &clk_dout_mpll,
 611         &clk_armclk,
 612         &clk_hclk,
 613         &clk_pclk,
 614         &clk_hclk_low,
 615 };
 616
 617 void __init_or_cpufreq s5p6440_setup_clocks(void)
 618 {
 619         struct clk *xtal_clk;
 620         unsigned long xtal;
 621         unsigned long fclk;
 622         unsigned long hclk;
 623         unsigned long hclk_low;
 624         unsigned long pclk;
 625         unsigned long pclk_low;
 626         unsigned long epll;
 627         unsigned long apll;
 628         unsigned long mpll;
 629         unsigned int ptr;
 630         u32 clkdiv0;
 631         u32 clkdiv3;
 632
 633         /* Set S5P6440 functions for clk_fout_epll */
 634         clk_fout_epll.enable = s5p6440_epll_enable;
 635         clk_fout_epll.ops = &s5p6440_epll_ops;
 636
 637         /* Set S5P6440 functions for arm clock */
 638         clk_48m.enable = s5p6440_clk48m_ctrl;
 639
 640         clkdiv0 = __raw_readl(S5P_CLK_DIV0);
 641         clkdiv3 = __raw_readl(S5P_CLK_DIV3);
 642
 643         xtal_clk = clk_get(NULL, "ext_xtal");
 644         BUG_ON(IS_ERR(xtal_clk));
 645
 646         xtal = clk_get_rate(xtal_clk);
 647         clk_put(xtal_clk);
 648
 649         epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
 650                                 __raw_readl(S5P_EPLL_CON_K));
 651         mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 652         apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
 653
 654         clk_fout_mpll.rate = mpll;
 655         clk_fout_epll.rate = epll;
 656         clk_fout_apll.rate = apll;
 657
 658         printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
 659                         " E=%ld.%ldMHz\n",
 660                         print_mhz(apll), print_mhz(mpll), print_mhz(epll));
 661
 662         fclk = clk_get_rate(&clk_armclk.clk);
 663         hclk = clk_get_rate(&clk_hclk.clk);
 664         pclk = clk_get_rate(&clk_pclk.clk);
 665         hclk_low = clk_get_rate(&clk_hclk_low.clk);
 666         pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
 667
 668         printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
 669                         " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
 670                         print_mhz(hclk), print_mhz(hclk_low),
 671                         print_mhz(pclk), print_mhz(pclk_low));
 672
 673         clk_f.rate = fclk;
 674         clk_h.rate = hclk;
 675         clk_p.rate = pclk;
 676         clk_p_low.rate = pclk_low;
 677
 678         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 679                 s3c_set_clksrc(&clksrcs[ptr], true);
 680 }
 681
 682 static struct clk *clks[] __initdata = {
 683         &clk_ext,
 684         &clk_iis_cd_v40,
 685         &clk_pcm_cd,
 686         &clk_p_low,
 687 };
 688
 689 void __init s5p6440_register_clocks(void)
 690 {
 691         struct clk *clkp;
 692         int ret;
 693         int ptr;
 694
 695         ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 696         if (ret > 0)
 697                 printk(KERN_ERR "Failed to register %u clocks\n", ret);
 698
 699         for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
 700                 s3c_register_clksrc(sysclks[ptr], 1);
 701
 702         s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
 703         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 704
 705         clkp = init_clocks_disable;
 706         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 707
 708                 ret = s3c24xx_register_clock(clkp);
 709                 if (ret < 0) {
 710                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 711                                clkp->name, ret);
 712                 }
 713                 (clkp->enable)(clkp, 0);
 714         }
 715
 716         s3c_pwmclk_init();
 717 }