1 /* linux/arch/arm/mach-s3c2410/s3c2440-clock.c
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
7 * S3C2440 Clock support
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/list.h>
28 #include <linux/errno.h>
29 #include <linux/err.h>
30 #include <linux/device.h>
31 #include <linux/sysdev.h>
32 #include <linux/interrupt.h>
33 #include <linux/ioport.h>
34 #include <linux/clk.h>
36 #include <asm/hardware.h>
37 #include <asm/atomic.h>
41 #include <asm/arch/regs-clock.h>
46 /* S3C2440 extended clock support */
48 static unsigned long s3c2440_camif_upll_round(struct clk *clk,
51 unsigned long parent_rate = clk_get_rate(clk->parent);
54 if (rate > parent_rate)
57 /* note, we remove the +/- 1 calculations for the divisor */
59 div = (parent_rate / rate) / 2;
66 return parent_rate / (div * 2);
69 static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
71 unsigned long parent_rate = clk_get_rate(clk->parent);
72 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
74 rate = s3c2440_camif_upll_round(clk, rate);
76 camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
78 if (rate != parent_rate) {
79 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
80 camdivn |= (((parent_rate / rate) / 2) - 1);
83 __raw_writel(camdivn, S3C2440_CAMDIVN);
88 /* Extra S3C2440 clocks */
90 static struct clk s3c2440_clk_cam = {
93 .enable = s3c24xx_clkcon_enable,
94 .ctrlbit = S3C2440_CLKCON_CAMERA,
97 static struct clk s3c2440_clk_cam_upll = {
100 .set_rate = s3c2440_camif_upll_setrate,
101 .round_rate = s3c2440_camif_upll_round,
104 static struct clk s3c2440_clk_ac97 = {
107 .enable = s3c24xx_clkcon_enable,
108 .ctrlbit = S3C2440_CLKCON_CAMERA,
111 static int s3c2440_clk_add(struct sys_device *sysdev)
113 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
117 printk("S3C2440: Clock Support, DVS %s\n",
118 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
120 clk_p = clk_get(NULL, "pclk");
121 clk_h = clk_get(NULL, "hclk");
123 if (IS_ERR(clk_p) || IS_ERR(clk_h)) {
124 printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
128 s3c2440_clk_cam.parent = clk_h;
129 s3c2440_clk_ac97.parent = clk_p;
130 s3c2440_clk_cam_upll.parent = clk_upll;
132 s3c24xx_register_clock(&s3c2440_clk_ac97);
133 s3c24xx_register_clock(&s3c2440_clk_cam);
134 s3c24xx_register_clock(&s3c2440_clk_cam_upll);
136 clk_disable(&s3c2440_clk_ac97);
137 clk_disable(&s3c2440_clk_cam);
142 static struct sysdev_driver s3c2440_clk_driver = {
143 .add = s3c2440_clk_add,
146 static __init int s3c24xx_clk_driver(void)
148 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
151 arch_initcall(s3c24xx_clk_driver);