arch/arm/mach-s3c2410/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright (c) 2003-2005 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/sysdev.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/dm9000.h>
  23 #include <linux/ata_platform.h>
  24
  25 #include <net/ax88796.h>
  26
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/irq.h>
  30
  31 #include <asm/arch/bast-map.h>
  32 #include <asm/arch/bast-irq.h>
  33 #include <asm/arch/bast-cpld.h>
  34
  35 #include <asm/hardware.h>
  36 #include <asm/io.h>
  37 #include <asm/irq.h>
  38 #include <asm/mach-types.h>
  39
  40 //#include <asm/debug-ll.h>
  41 #include <asm/plat-s3c/regs-serial.h>
  42 #include <asm/arch/regs-gpio.h>
  43 #include <asm/arch/regs-mem.h>
  44 #include <asm/arch/regs-lcd.h>
  45
  46 #include <asm/plat-s3c/nand.h>
  47 #include <asm/plat-s3c/iic.h>
  48 #include <asm/arch/fb.h>
  49
  50 #include <linux/mtd/mtd.h>
  51 #include <linux/mtd/nand.h>
  52 #include <linux/mtd/nand_ecc.h>
  53 #include <linux/mtd/partitions.h>
  54
  55 #include <linux/serial_8250.h>
  56
  57 #include <asm/plat-s3c24xx/clock.h>
  58 #include <asm/plat-s3c24xx/devs.h>
  59 #include <asm/plat-s3c24xx/cpu.h>
  60 #include "usb-simtec.h"
  61
  62 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
  63
  64 /* macros for virtual address mods for the io space entries */
  65 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  66 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  67 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  68 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  69
  70 /* macros to modify the physical addresses for io space */
  71
  72 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  73 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  74 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  75 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  76
  77 static struct map_desc bast_iodesc[] __initdata = {
  78   /* ISA IO areas */
  79   {
  80           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  81           .pfn          = PA_CS2(BAST_PA_ISAIO),
  82           .length       = SZ_16M,
  83           .type         = MT_DEVICE,
  84   }, {
  85           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  86           .pfn          = PA_CS3(BAST_PA_ISAIO),
  87           .length       = SZ_16M,
  88           .type         = MT_DEVICE,
  89   },
  90   /* bast CPLD control registers, and external interrupt controls */
  91   {
  92           .virtual      = (u32)BAST_VA_CTRL1,
  93           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
  94           .length       = SZ_1M,
  95           .type         = MT_DEVICE,
  96   }, {
  97           .virtual      = (u32)BAST_VA_CTRL2,
  98           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
  99           .length       = SZ_1M,
 100           .type         = MT_DEVICE,
 101   }, {
 102           .virtual      = (u32)BAST_VA_CTRL3,
 103           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 104           .length       = SZ_1M,
 105           .type         = MT_DEVICE,
 106   }, {
 107           .virtual      = (u32)BAST_VA_CTRL4,
 108           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 109           .length       = SZ_1M,
 110           .type         = MT_DEVICE,
 111   },
 112   /* PC104 IRQ mux */
 113   {
 114           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 115           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 116           .length       = SZ_1M,
 117           .type         = MT_DEVICE,
 118   }, {
 119           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 120           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 121           .length       = SZ_1M,
 122           .type         = MT_DEVICE,
 123   }, {
 124           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 125           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 126           .length       = SZ_1M,
 127           .type         = MT_DEVICE,
 128   },
 129
 130   /* peripheral space... one for each of fast/slow/byte/16bit */
 131   /* note, ide is only decoded in word space, even though some registers
 132    * are only 8bit */
 133
 134   /* slow, byte */
 135   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 136   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 137   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 138
 139   /* slow, word */
 140   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 141   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 142   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 143
 144   /* fast, byte */
 145   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 146   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 147   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 148
 149   /* fast, word */
 150   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 151   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 152   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 153 };
 154
 155 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 156 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 157 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 158
 159 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
 160         [0] = {
 161                 .name           = "uclk",
 162                 .divisor        = 1,
 163                 .min_baud       = 0,
 164                 .max_baud       = 0,
 165         },
 166         [1] = {
 167                 .name           = "pclk",
 168                 .divisor        = 1,
 169                 .min_baud       = 0,
 170                 .max_baud       = 0,
 171         }
 172 };
 173
 174
 175 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 176         [0] = {
 177                 .hwport      = 0,
 178                 .flags       = 0,
 179                 .ucon        = UCON,
 180                 .ulcon       = ULCON,
 181                 .ufcon       = UFCON,
 182                 .clocks      = bast_serial_clocks,
 183                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 184         },
 185         [1] = {
 186                 .hwport      = 1,
 187                 .flags       = 0,
 188                 .ucon        = UCON,
 189                 .ulcon       = ULCON,
 190                 .ufcon       = UFCON,
 191                 .clocks      = bast_serial_clocks,
 192                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 193         },
 194         /* port 2 is not actually used */
 195         [2] = {
 196                 .hwport      = 2,
 197                 .flags       = 0,
 198                 .ucon        = UCON,
 199                 .ulcon       = ULCON,
 200                 .ufcon       = UFCON,
 201                 .clocks      = bast_serial_clocks,
 202                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 203         }
 204 };
 205
 206 /* NOR Flash on BAST board */
 207
 208 static struct resource bast_nor_resource[] = {
 209         [0] = {
 210                 .start = S3C2410_CS1 + 0x4000000,
 211                 .end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
 212                 .flags = IORESOURCE_MEM,
 213         }
 214 };
 215
 216 static struct platform_device bast_device_nor = {
 217         .name           = "bast-nor",
 218         .id             = -1,
 219         .num_resources  = ARRAY_SIZE(bast_nor_resource),
 220         .resource       = bast_nor_resource,
 221 };
 222
 223 /* NAND Flash on BAST board */
 224
 225 #ifdef CONFIG_PM
 226 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 227 {
 228         /* ensure that an nRESET is not generated on resume. */
 229         s3c2410_gpio_setpin(S3C2410_GPA21, 1);
 230         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_OUT);
 231
 232         return 0;
 233 }
 234
 235 static int bast_pm_resume(struct sys_device *sd)
 236 {
 237         s3c2410_gpio_cfgpin(S3C2410_GPA21, S3C2410_GPA21_nRSTOUT);
 238         return 0;
 239 }
 240
 241 #else
 242 #define bast_pm_suspend NULL
 243 #define bast_pm_resume NULL
 244 #endif
 245
 246 static struct sysdev_class bast_pm_sysclass = {
 247         .name           = "mach-bast",
 248         .suspend        = bast_pm_suspend,
 249         .resume         = bast_pm_resume,
 250 };
 251
 252 static struct sys_device bast_pm_sysdev = {
 253         .cls            = &bast_pm_sysclass,
 254 };
 255
 256 static int smartmedia_map[] = { 0 };
 257 static int chip0_map[] = { 1 };
 258 static int chip1_map[] = { 2 };
 259 static int chip2_map[] = { 3 };
 260
 261 static struct mtd_partition bast_default_nand_part[] = {
 262         [0] = {
 263                 .name   = "Boot Agent",
 264                 .size   = SZ_16K,
 265                 .offset = 0,
 266         },
 267         [1] = {
 268                 .name   = "/boot",
 269                 .size   = SZ_4M - SZ_16K,
 270                 .offset = SZ_16K,
 271         },
 272         [2] = {
 273                 .name   = "user",
 274                 .offset = SZ_4M,
 275                 .size   = MTDPART_SIZ_FULL,
 276         }
 277 };
 278
 279 /* the bast has 4 selectable slots for nand-flash, the three
 280  * on-board chip areas, as well as the external SmartMedia
 281  * slot.
 282  *
 283  * Note, there is no current hot-plug support for the SmartMedia
 284  * socket.
 285 */
 286
 287 static struct s3c2410_nand_set bast_nand_sets[] = {
 288         [0] = {
 289                 .name           = "SmartMedia",
 290                 .nr_chips       = 1,
 291                 .nr_map         = smartmedia_map,
 292                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 293                 .partitions     = bast_default_nand_part,
 294         },
 295         [1] = {
 296                 .name           = "chip0",
 297                 .nr_chips       = 1,
 298                 .nr_map         = chip0_map,
 299                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 300                 .partitions     = bast_default_nand_part,
 301         },
 302         [2] = {
 303                 .name           = "chip1",
 304                 .nr_chips       = 1,
 305                 .nr_map         = chip1_map,
 306                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 307                 .partitions     = bast_default_nand_part,
 308         },
 309         [3] = {
 310                 .name           = "chip2",
 311                 .nr_chips       = 1,
 312                 .nr_map         = chip2_map,
 313                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 314                 .partitions     = bast_default_nand_part,
 315         }
 316 };
 317
 318 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 319 {
 320         unsigned int tmp;
 321
 322         slot = set->nr_map[slot] & 3;
 323
 324         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 325                  slot, set, set->nr_map);
 326
 327         tmp = __raw_readb(BAST_VA_CTRL2);
 328         tmp &= BAST_CPLD_CTLR2_IDERST;
 329         tmp |= slot;
 330         tmp |= BAST_CPLD_CTRL2_WNAND;
 331
 332         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 333
 334         __raw_writeb(tmp, BAST_VA_CTRL2);
 335 }
 336
 337 static struct s3c2410_platform_nand bast_nand_info = {
 338         .tacls          = 30,
 339         .twrph0         = 60,
 340         .twrph1         = 60,
 341         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 342         .sets           = bast_nand_sets,
 343         .select_chip    = bast_nand_select,
 344 };
 345
 346 /* DM9000 */
 347
 348 static struct resource bast_dm9k_resource[] = {
 349         [0] = {
 350                 .start = S3C2410_CS5 + BAST_PA_DM9000,
 351                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
 352                 .flags = IORESOURCE_MEM,
 353         },
 354         [1] = {
 355                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
 356                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
 357                 .flags = IORESOURCE_MEM,
 358         },
 359         [2] = {
 360                 .start = IRQ_DM9000,
 361                 .end   = IRQ_DM9000,
 362                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 363         }
 364
 365 };
 366
 367 /* for the moment we limit ourselves to 16bit IO until some
 368  * better IO routines can be written and tested
 369 */
 370
 371 static struct dm9000_plat_data bast_dm9k_platdata = {
 372         .flags          = DM9000_PLATF_16BITONLY,
 373 };
 374
 375 static struct platform_device bast_device_dm9k = {
 376         .name           = "dm9000",
 377         .id             = 0,
 378         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 379         .resource       = bast_dm9k_resource,
 380         .dev            = {
 381                 .platform_data = &bast_dm9k_platdata,
 382         }
 383 };
 384
 385 /* serial devices */
 386
 387 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 388 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 389 #define SERIAL_CLK   (1843200)
 390
 391 static struct plat_serial8250_port bast_sio_data[] = {
 392         [0] = {
 393                 .mapbase        = SERIAL_BASE + 0x2f8,
 394                 .irq            = IRQ_PCSERIAL1,
 395                 .flags          = SERIAL_FLAGS,
 396                 .iotype         = UPIO_MEM,
 397                 .regshift       = 0,
 398                 .uartclk        = SERIAL_CLK,
 399         },
 400         [1] = {
 401                 .mapbase        = SERIAL_BASE + 0x3f8,
 402                 .irq            = IRQ_PCSERIAL2,
 403                 .flags          = SERIAL_FLAGS,
 404                 .iotype         = UPIO_MEM,
 405                 .regshift       = 0,
 406                 .uartclk        = SERIAL_CLK,
 407         },
 408         { }
 409 };
 410
 411 static struct platform_device bast_sio = {
 412         .name                   = "serial8250",
 413         .id                     = PLAT8250_DEV_PLATFORM,
 414         .dev                    = {
 415                 .platform_data  = &bast_sio_data,
 416         },
 417 };
 418
 419 /* we have devices on the bus which cannot work much over the
 420  * standard 100KHz i2c bus frequency
 421 */
 422
 423 static struct s3c2410_platform_i2c bast_i2c_info = {
 424         .flags          = 0,
 425         .slave_addr     = 0x10,
 426         .bus_freq       = 100*1000,
 427         .max_freq       = 130*1000,
 428 };
 429
 430 /* Asix AX88796 10/100 ethernet controller */
 431
 432 static struct ax_plat_data bast_asix_platdata = {
 433         .flags          = AXFLG_MAC_FROMDEV,
 434         .wordlength     = 2,
 435         .dcr_val        = 0x48,
 436         .rcr_val        = 0x40,
 437 };
 438
 439 static struct resource bast_asix_resource[] = {
 440         [0] = {
 441                 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
 442                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
 443                 .flags = IORESOURCE_MEM,
 444         },
 445         [1] = {
 446                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 447                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 448                 .flags = IORESOURCE_MEM,
 449         },
 450         [2] = {
 451                 .start = IRQ_ASIX,
 452                 .end   = IRQ_ASIX,
 453                 .flags = IORESOURCE_IRQ
 454         }
 455 };
 456
 457 static struct platform_device bast_device_asix = {
 458         .name           = "ax88796",
 459         .id             = 0,
 460         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 461         .resource       = bast_asix_resource,
 462         .dev            = {
 463                 .platform_data = &bast_asix_platdata
 464         }
 465 };
 466
 467 /* Asix AX88796 10/100 ethernet controller parallel port */
 468
 469 static struct resource bast_asixpp_resource[] = {
 470         [0] = {
 471                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
 472                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
 473                 .flags = IORESOURCE_MEM,
 474         }
 475 };
 476
 477 static struct platform_device bast_device_axpp = {
 478         .name           = "ax88796-pp",
 479         .id             = 0,
 480         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 481         .resource       = bast_asixpp_resource,
 482 };
 483
 484 /* LCD/VGA controller */
 485
 486 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 487         {
 488                 .type           = S3C2410_LCDCON1_TFT,
 489                 .width          = 640,
 490                 .height         = 480,
 491
 492                 .pixclock       = 33333,
 493                 .xres           = 640,
 494                 .yres           = 480,
 495                 .bpp            = 4,
 496                 .left_margin    = 40,
 497                 .right_margin   = 20,
 498                 .hsync_len      = 88,
 499                 .upper_margin   = 30,
 500                 .lower_margin   = 32,
 501                 .vsync_len      = 3,
 502
 503                 .lcdcon5        = 0x00014b02,
 504         },
 505         {
 506                 .type           = S3C2410_LCDCON1_TFT,
 507                 .width          = 640,
 508                 .height         = 480,
 509
 510                 .pixclock       = 33333,
 511                 .xres           = 640,
 512                 .yres           = 480,
 513                 .bpp            = 8,
 514                 .left_margin    = 40,
 515                 .right_margin   = 20,
 516                 .hsync_len      = 88,
 517                 .upper_margin   = 30,
 518                 .lower_margin   = 32,
 519                 .vsync_len      = 3,
 520
 521                 .lcdcon5        = 0x00014b02,
 522         },
 523         {
 524                 .type           = S3C2410_LCDCON1_TFT,
 525                 .width          = 640,
 526                 .height         = 480,
 527
 528                 .pixclock       = 33333,
 529                 .xres           = 640,
 530                 .yres           = 480,
 531                 .bpp            = 16,
 532                 .left_margin    = 40,
 533                 .right_margin   = 20,
 534                 .hsync_len      = 88,
 535                 .upper_margin   = 30,
 536                 .lower_margin   = 32,
 537                 .vsync_len      = 3,
 538
 539                 .lcdcon5        = 0x00014b02,
 540         },
 541 };
 542
 543 /* LCD/VGA controller */
 544
 545 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 546
 547         .displays = bast_lcd_info,
 548         .num_displays = ARRAY_SIZE(bast_lcd_info),
 549         .default_display = 1,
 550 };
 551
 552
 553 /* Standard BAST devices */
 554
 555 static struct platform_device *bast_devices[] __initdata = {
 556         &s3c_device_usb,
 557         &s3c_device_lcd,
 558         &s3c_device_wdt,
 559         &s3c_device_i2c,
 560         &s3c_device_rtc,
 561         &s3c_device_nand,
 562         &bast_device_nor,
 563         &bast_device_dm9k,
 564         &bast_device_asix,
 565         &bast_device_axpp,
 566         &bast_sio,
 567 };
 568
 569 static struct clk *bast_clocks[] = {
 570         &s3c24xx_dclk0,
 571         &s3c24xx_dclk1,
 572         &s3c24xx_clkout0,
 573         &s3c24xx_clkout1,
 574         &s3c24xx_uclk,
 575 };
 576
 577 static void __init bast_map_io(void)
 578 {
 579         /* initialise the clocks */
 580
 581         s3c24xx_dclk0.parent = &clk_upll;
 582         s3c24xx_dclk0.rate   = 12*1000*1000;
 583
 584         s3c24xx_dclk1.parent = &clk_upll;
 585         s3c24xx_dclk1.rate   = 24*1000*1000;
 586
 587         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 588         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 589
 590         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 591
 592         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 593
 594         s3c_device_nand.dev.platform_data = &bast_nand_info;
 595         s3c_device_i2c.dev.platform_data = &bast_i2c_info;
 596
 597         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 598         s3c24xx_init_clocks(0);
 599         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 600
 601         usb_simtec_init();
 602 }
 603
 604 static void __init bast_init(void)
 605 {
 606         sysdev_class_register(&bast_pm_sysclass);
 607         sysdev_register(&bast_pm_sysdev);
 608
 609         s3c24xx_fb_set_platdata(&bast_fb_info);
 610         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 611 }
 612
 613 MACHINE_START(BAST, "Simtec-BAST")
 614         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 615         .phys_io        = S3C2410_PA_UART,
 616         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 617         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 618         .map_io         = bast_map_io,
 619         .init_irq       = s3c24xx_init_irq,
 620         .init_machine   = bast_init,
 621         .timer          = &s3c24xx_timer,
 622 MACHINE_END