arch/arm/mach-s3c2410/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright (c) 2003-2005,2008 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/list.h>
  17 #include <linux/timer.h>
  18 #include <linux/init.h>
  19 #include <linux/gpio.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/dm9000.h>
  24 #include <linux/ata_platform.h>
  25 #include <linux/i2c.h>
  26 #include <linux/io.h>
  27
  28 #include <net/ax88796.h>
  29
  30 #include <asm/mach/arch.h>
  31 #include <asm/mach/map.h>
  32 #include <asm/mach/irq.h>
  33
  34 #include <mach/bast-map.h>
  35 #include <mach/bast-irq.h>
  36 #include <mach/bast-cpld.h>
  37
  38 #include <mach/hardware.h>
  39 #include <asm/irq.h>
  40 #include <asm/mach-types.h>
  41
  42 //#include <asm/debug-ll.h>
  43 #include <plat/regs-serial.h>
  44 #include <mach/regs-gpio.h>
  45 #include <mach/regs-mem.h>
  46 #include <mach/regs-lcd.h>
  47
  48 #include <plat/hwmon.h>
  49 #include <plat/nand.h>
  50 #include <plat/iic.h>
  51 #include <mach/fb.h>
  52
  53 #include <linux/mtd/mtd.h>
  54 #include <linux/mtd/nand.h>
  55 #include <linux/mtd/nand_ecc.h>
  56 #include <linux/mtd/partitions.h>
  57
  58 #include <linux/serial_8250.h>
  59
  60 #include <plat/clock.h>
  61 #include <plat/devs.h>
  62 #include <plat/cpu.h>
  63 #include <plat/cpu-freq.h>
  64
  65 #include "usb-simtec.h"
  66 #include "nor-simtec.h"
  67
  68 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
  69
  70 /* macros for virtual address mods for the io space entries */
  71 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  72 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  73 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  74 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  75
  76 /* macros to modify the physical addresses for io space */
  77
  78 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  79 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  80 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  81 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  82
  83 static struct map_desc bast_iodesc[] __initdata = {
  84   /* ISA IO areas */
  85   {
  86           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
  87           .pfn          = PA_CS2(BAST_PA_ISAIO),
  88           .length       = SZ_16M,
  89           .type         = MT_DEVICE,
  90   }, {
  91           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
  92           .pfn          = PA_CS3(BAST_PA_ISAIO),
  93           .length       = SZ_16M,
  94           .type         = MT_DEVICE,
  95   },
  96   /* bast CPLD control registers, and external interrupt controls */
  97   {
  98           .virtual      = (u32)BAST_VA_CTRL1,
  99           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
 100           .length       = SZ_1M,
 101           .type         = MT_DEVICE,
 102   }, {
 103           .virtual      = (u32)BAST_VA_CTRL2,
 104           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
 105           .length       = SZ_1M,
 106           .type         = MT_DEVICE,
 107   }, {
 108           .virtual      = (u32)BAST_VA_CTRL3,
 109           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 110           .length       = SZ_1M,
 111           .type         = MT_DEVICE,
 112   }, {
 113           .virtual      = (u32)BAST_VA_CTRL4,
 114           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 115           .length       = SZ_1M,
 116           .type         = MT_DEVICE,
 117   },
 118   /* PC104 IRQ mux */
 119   {
 120           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 121           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 122           .length       = SZ_1M,
 123           .type         = MT_DEVICE,
 124   }, {
 125           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 126           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 127           .length       = SZ_1M,
 128           .type         = MT_DEVICE,
 129   }, {
 130           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 131           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 132           .length       = SZ_1M,
 133           .type         = MT_DEVICE,
 134   },
 135
 136   /* peripheral space... one for each of fast/slow/byte/16bit */
 137   /* note, ide is only decoded in word space, even though some registers
 138    * are only 8bit */
 139
 140   /* slow, byte */
 141   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 142   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 143   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 144
 145   /* slow, word */
 146   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 147   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 148   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 149
 150   /* fast, byte */
 151   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 152   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 153   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 154
 155   /* fast, word */
 156   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 157   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 158   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 159 };
 160
 161 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 162 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 163 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 164
 165 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
 166         [0] = {
 167                 .name           = "uclk",
 168                 .divisor        = 1,
 169                 .min_baud       = 0,
 170                 .max_baud       = 0,
 171         },
 172         [1] = {
 173                 .name           = "pclk",
 174                 .divisor        = 1,
 175                 .min_baud       = 0,
 176                 .max_baud       = 0,
 177         }
 178 };
 179
 180
 181 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 182         [0] = {
 183                 .hwport      = 0,
 184                 .flags       = 0,
 185                 .ucon        = UCON,
 186                 .ulcon       = ULCON,
 187                 .ufcon       = UFCON,
 188                 .clocks      = bast_serial_clocks,
 189                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 190         },
 191         [1] = {
 192                 .hwport      = 1,
 193                 .flags       = 0,
 194                 .ucon        = UCON,
 195                 .ulcon       = ULCON,
 196                 .ufcon       = UFCON,
 197                 .clocks      = bast_serial_clocks,
 198                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 199         },
 200         /* port 2 is not actually used */
 201         [2] = {
 202                 .hwport      = 2,
 203                 .flags       = 0,
 204                 .ucon        = UCON,
 205                 .ulcon       = ULCON,
 206                 .ufcon       = UFCON,
 207                 .clocks      = bast_serial_clocks,
 208                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 209         }
 210 };
 211
 212 /* NAND Flash on BAST board */
 213
 214 #ifdef CONFIG_PM
 215 static int bast_pm_suspend(struct sys_device *sd, pm_message_t state)
 216 {
 217         /* ensure that an nRESET is not generated on resume. */
 218         s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
 219         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
 220
 221         return 0;
 222 }
 223
 224 static int bast_pm_resume(struct sys_device *sd)
 225 {
 226         s3c2410_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
 227         return 0;
 228 }
 229
 230 #else
 231 #define bast_pm_suspend NULL
 232 #define bast_pm_resume NULL
 233 #endif
 234
 235 static struct sysdev_class bast_pm_sysclass = {
 236         .name           = "mach-bast",
 237         .suspend        = bast_pm_suspend,
 238         .resume         = bast_pm_resume,
 239 };
 240
 241 static struct sys_device bast_pm_sysdev = {
 242         .cls            = &bast_pm_sysclass,
 243 };
 244
 245 static int smartmedia_map[] = { 0 };
 246 static int chip0_map[] = { 1 };
 247 static int chip1_map[] = { 2 };
 248 static int chip2_map[] = { 3 };
 249
 250 static struct mtd_partition bast_default_nand_part[] = {
 251         [0] = {
 252                 .name   = "Boot Agent",
 253                 .size   = SZ_16K,
 254                 .offset = 0,
 255         },
 256         [1] = {
 257                 .name   = "/boot",
 258                 .size   = SZ_4M - SZ_16K,
 259                 .offset = SZ_16K,
 260         },
 261         [2] = {
 262                 .name   = "user",
 263                 .offset = SZ_4M,
 264                 .size   = MTDPART_SIZ_FULL,
 265         }
 266 };
 267
 268 /* the bast has 4 selectable slots for nand-flash, the three
 269  * on-board chip areas, as well as the external SmartMedia
 270  * slot.
 271  *
 272  * Note, there is no current hot-plug support for the SmartMedia
 273  * socket.
 274 */
 275
 276 static struct s3c2410_nand_set bast_nand_sets[] = {
 277         [0] = {
 278                 .name           = "SmartMedia",
 279                 .nr_chips       = 1,
 280                 .nr_map         = smartmedia_map,
 281                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 282                 .partitions     = bast_default_nand_part,
 283         },
 284         [1] = {
 285                 .name           = "chip0",
 286                 .nr_chips       = 1,
 287                 .nr_map         = chip0_map,
 288                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 289                 .partitions     = bast_default_nand_part,
 290         },
 291         [2] = {
 292                 .name           = "chip1",
 293                 .nr_chips       = 1,
 294                 .nr_map         = chip1_map,
 295                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 296                 .partitions     = bast_default_nand_part,
 297         },
 298         [3] = {
 299                 .name           = "chip2",
 300                 .nr_chips       = 1,
 301                 .nr_map         = chip2_map,
 302                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 303                 .partitions     = bast_default_nand_part,
 304         }
 305 };
 306
 307 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 308 {
 309         unsigned int tmp;
 310
 311         slot = set->nr_map[slot] & 3;
 312
 313         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 314                  slot, set, set->nr_map);
 315
 316         tmp = __raw_readb(BAST_VA_CTRL2);
 317         tmp &= BAST_CPLD_CTLR2_IDERST;
 318         tmp |= slot;
 319         tmp |= BAST_CPLD_CTRL2_WNAND;
 320
 321         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 322
 323         __raw_writeb(tmp, BAST_VA_CTRL2);
 324 }
 325
 326 static struct s3c2410_platform_nand bast_nand_info = {
 327         .tacls          = 30,
 328         .twrph0         = 60,
 329         .twrph1         = 60,
 330         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 331         .sets           = bast_nand_sets,
 332         .select_chip    = bast_nand_select,
 333 };
 334
 335 /* DM9000 */
 336
 337 static struct resource bast_dm9k_resource[] = {
 338         [0] = {
 339                 .start = S3C2410_CS5 + BAST_PA_DM9000,
 340                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
 341                 .flags = IORESOURCE_MEM,
 342         },
 343         [1] = {
 344                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
 345                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
 346                 .flags = IORESOURCE_MEM,
 347         },
 348         [2] = {
 349                 .start = IRQ_DM9000,
 350                 .end   = IRQ_DM9000,
 351                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
 352         }
 353
 354 };
 355
 356 /* for the moment we limit ourselves to 16bit IO until some
 357  * better IO routines can be written and tested
 358 */
 359
 360 static struct dm9000_plat_data bast_dm9k_platdata = {
 361         .flags          = DM9000_PLATF_16BITONLY,
 362 };
 363
 364 static struct platform_device bast_device_dm9k = {
 365         .name           = "dm9000",
 366         .id             = 0,
 367         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 368         .resource       = bast_dm9k_resource,
 369         .dev            = {
 370                 .platform_data = &bast_dm9k_platdata,
 371         }
 372 };
 373
 374 /* serial devices */
 375
 376 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 377 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 378 #define SERIAL_CLK   (1843200)
 379
 380 static struct plat_serial8250_port bast_sio_data[] = {
 381         [0] = {
 382                 .mapbase        = SERIAL_BASE + 0x2f8,
 383                 .irq            = IRQ_PCSERIAL1,
 384                 .flags          = SERIAL_FLAGS,
 385                 .iotype         = UPIO_MEM,
 386                 .regshift       = 0,
 387                 .uartclk        = SERIAL_CLK,
 388         },
 389         [1] = {
 390                 .mapbase        = SERIAL_BASE + 0x3f8,
 391                 .irq            = IRQ_PCSERIAL2,
 392                 .flags          = SERIAL_FLAGS,
 393                 .iotype         = UPIO_MEM,
 394                 .regshift       = 0,
 395                 .uartclk        = SERIAL_CLK,
 396         },
 397         { }
 398 };
 399
 400 static struct platform_device bast_sio = {
 401         .name                   = "serial8250",
 402         .id                     = PLAT8250_DEV_PLATFORM,
 403         .dev                    = {
 404                 .platform_data  = &bast_sio_data,
 405         },
 406 };
 407
 408 /* we have devices on the bus which cannot work much over the
 409  * standard 100KHz i2c bus frequency
 410 */
 411
 412 static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
 413         .flags          = 0,
 414         .slave_addr     = 0x10,
 415         .frequency      = 100*1000,
 416 };
 417
 418 /* Asix AX88796 10/100 ethernet controller */
 419
 420 static struct ax_plat_data bast_asix_platdata = {
 421         .flags          = AXFLG_MAC_FROMDEV,
 422         .wordlength     = 2,
 423         .dcr_val        = 0x48,
 424         .rcr_val        = 0x40,
 425 };
 426
 427 static struct resource bast_asix_resource[] = {
 428         [0] = {
 429                 .start = S3C2410_CS5 + BAST_PA_ASIXNET,
 430                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20) - 1,
 431                 .flags = IORESOURCE_MEM,
 432         },
 433         [1] = {
 434                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 435                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20),
 436                 .flags = IORESOURCE_MEM,
 437         },
 438         [2] = {
 439                 .start = IRQ_ASIX,
 440                 .end   = IRQ_ASIX,
 441                 .flags = IORESOURCE_IRQ
 442         }
 443 };
 444
 445 static struct platform_device bast_device_asix = {
 446         .name           = "ax88796",
 447         .id             = 0,
 448         .num_resources  = ARRAY_SIZE(bast_asix_resource),
 449         .resource       = bast_asix_resource,
 450         .dev            = {
 451                 .platform_data = &bast_asix_platdata
 452         }
 453 };
 454
 455 /* Asix AX88796 10/100 ethernet controller parallel port */
 456
 457 static struct resource bast_asixpp_resource[] = {
 458         [0] = {
 459                 .start = S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20),
 460                 .end   = S3C2410_CS5 + BAST_PA_ASIXNET + (0x1b * 0x20) - 1,
 461                 .flags = IORESOURCE_MEM,
 462         }
 463 };
 464
 465 static struct platform_device bast_device_axpp = {
 466         .name           = "ax88796-pp",
 467         .id             = 0,
 468         .num_resources  = ARRAY_SIZE(bast_asixpp_resource),
 469         .resource       = bast_asixpp_resource,
 470 };
 471
 472 /* LCD/VGA controller */
 473
 474 static struct s3c2410fb_display __initdata bast_lcd_info[] = {
 475         {
 476                 .type           = S3C2410_LCDCON1_TFT,
 477                 .width          = 640,
 478                 .height         = 480,
 479
 480                 .pixclock       = 33333,
 481                 .xres           = 640,
 482                 .yres           = 480,
 483                 .bpp            = 4,
 484                 .left_margin    = 40,
 485                 .right_margin   = 20,
 486                 .hsync_len      = 88,
 487                 .upper_margin   = 30,
 488                 .lower_margin   = 32,
 489                 .vsync_len      = 3,
 490
 491                 .lcdcon5        = 0x00014b02,
 492         },
 493         {
 494                 .type           = S3C2410_LCDCON1_TFT,
 495                 .width          = 640,
 496                 .height         = 480,
 497
 498                 .pixclock       = 33333,
 499                 .xres           = 640,
 500                 .yres           = 480,
 501                 .bpp            = 8,
 502                 .left_margin    = 40,
 503                 .right_margin   = 20,
 504                 .hsync_len      = 88,
 505                 .upper_margin   = 30,
 506                 .lower_margin   = 32,
 507                 .vsync_len      = 3,
 508
 509                 .lcdcon5        = 0x00014b02,
 510         },
 511         {
 512                 .type           = S3C2410_LCDCON1_TFT,
 513                 .width          = 640,
 514                 .height         = 480,
 515
 516                 .pixclock       = 33333,
 517                 .xres           = 640,
 518                 .yres           = 480,
 519                 .bpp            = 16,
 520                 .left_margin    = 40,
 521                 .right_margin   = 20,
 522                 .hsync_len      = 88,
 523                 .upper_margin   = 30,
 524                 .lower_margin   = 32,
 525                 .vsync_len      = 3,
 526
 527                 .lcdcon5        = 0x00014b02,
 528         },
 529 };
 530
 531 /* LCD/VGA controller */
 532
 533 static struct s3c2410fb_mach_info __initdata bast_fb_info = {
 534
 535         .displays = bast_lcd_info,
 536         .num_displays = ARRAY_SIZE(bast_lcd_info),
 537         .default_display = 1,
 538 };
 539
 540 /* I2C devices fitted. */
 541
 542 static struct i2c_board_info bast_i2c_devs[] __initdata = {
 543         {
 544                 I2C_BOARD_INFO("tlv320aic23", 0x1a),
 545         }, {
 546                 I2C_BOARD_INFO("simtec-pmu", 0x6b),
 547         }, {
 548                 I2C_BOARD_INFO("ch7013", 0x75),
 549         },
 550 };
 551
 552 static struct s3c_hwmon_pdata bast_hwmon_info = {
 553         /* LCD contrast (0-6.6V) */
 554         .in[0] = &(struct s3c_hwmon_chcfg) {
 555                 .name           = "lcd-contrast",
 556                 .mult           = 3300,
 557                 .div            = 512,
 558         },
 559         /* LED current feedback */
 560         .in[1] = &(struct s3c_hwmon_chcfg) {
 561                 .name           = "led-feedback",
 562                 .mult           = 3300,
 563                 .div            = 1024,
 564         },
 565         /* LCD feedback (0-6.6V) */
 566         .in[2] = &(struct s3c_hwmon_chcfg) {
 567                 .name           = "lcd-feedback",
 568                 .mult           = 3300,
 569                 .div            = 512,
 570         },
 571         /* Vcore (1.8-2.0V), Vref 3.3V  */
 572         .in[3] = &(struct s3c_hwmon_chcfg) {
 573                 .name           = "vcore",
 574                 .mult           = 3300,
 575                 .div            = 1024,
 576         },
 577 };
 578
 579 /* Standard BAST devices */
 580 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 581
 582 static struct platform_device *bast_devices[] __initdata = {
 583         &s3c_device_usb,
 584         &s3c_device_lcd,
 585         &s3c_device_wdt,
 586         &s3c_device_i2c0,
 587         &s3c_device_rtc,
 588         &s3c_device_nand,
 589         &s3c_device_adc,
 590         &s3c_device_hwmon,
 591         &bast_device_dm9k,
 592         &bast_device_asix,
 593         &bast_device_axpp,
 594         &bast_sio,
 595 };
 596
 597 static struct clk *bast_clocks[] __initdata = {
 598         &s3c24xx_dclk0,
 599         &s3c24xx_dclk1,
 600         &s3c24xx_clkout0,
 601         &s3c24xx_clkout1,
 602         &s3c24xx_uclk,
 603 };
 604
 605 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
 606         .refresh        = 7800, /* 7.8usec */
 607         .auto_io        = 1,
 608         .need_io        = 1,
 609 };
 610
 611 static void __init bast_map_io(void)
 612 {
 613         /* initialise the clocks */
 614
 615         s3c24xx_dclk0.parent = &clk_upll;
 616         s3c24xx_dclk0.rate   = 12*1000*1000;
 617
 618         s3c24xx_dclk1.parent = &clk_upll;
 619         s3c24xx_dclk1.rate   = 24*1000*1000;
 620
 621         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 622         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 623
 624         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 625
 626         s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
 627
 628         s3c_device_nand.dev.platform_data = &bast_nand_info;
 629         s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
 630
 631         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 632         s3c24xx_init_clocks(0);
 633         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 634 }
 635
 636 static void __init bast_init(void)
 637 {
 638         sysdev_class_register(&bast_pm_sysclass);
 639         sysdev_register(&bast_pm_sysdev);
 640
 641         s3c_i2c0_set_platdata(&bast_i2c_info);
 642         s3c24xx_fb_set_platdata(&bast_fb_info);
 643         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 644
 645         i2c_register_board_info(0, bast_i2c_devs,
 646                                 ARRAY_SIZE(bast_i2c_devs));
 647
 648         usb_simtec_init();
 649         nor_simtec_init();
 650
 651         s3c_cpufreq_setboard(&bast_cpufreq);
 652 }
 653
 654 MACHINE_START(BAST, "Simtec-BAST")
 655         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 656         .phys_io        = S3C2410_PA_UART,
 657         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 658         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 659         .map_io         = bast_map_io,
 660         .init_irq       = s3c24xx_init_irq,
 661         .init_machine   = bast_init,
 662         .timer          = &s3c24xx_timer,
 663 MACHINE_END