2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <linux/sysdev.h>
25 #include <asm/mach/map.h>
26 #include <mach/hardware.h>
27 #include <mach/gpio.h>
28 #include <mach/pxa3xx-regs.h>
29 #include <mach/reset.h>
30 #include <mach/ohci.h>
33 #include <mach/regs-intc.h>
34 #include <mach/smemc.h>
41 /* Crystal clock: 13MHz */
42 #define BASE_CLK 13000000
44 /* Ring Oscillator Clock: 60MHz */
45 #define RO_CLK 60000000
47 #define ACCR_D0CS (1 << 26)
48 #define ACCR_PCCE (1 << 11)
50 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
51 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
53 /* crystal frequency to static memory controller multiplier (SMCFS) */
54 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
56 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
57 static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
60 * Get the clock frequency as reflected by CCSR and the turbo flag.
61 * We assume these values have been applied via a fcs.
62 * If info is not 0 we also display the current settings.
64 unsigned int pxa3xx_get_clk_frequency_khz(int info)
66 unsigned long acsr, xclkcfg;
67 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
69 /* Read XCLKCFG register turbo bit */
70 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
76 xn = (acsr >> 8) & 0x7;
77 hss = (acsr >> 14) & 0x3;
82 ro = acsr & ACCR_D0CS;
84 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
85 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
88 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
89 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
91 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
92 XL / 1000000, (XL % 1000000) / 10000, xl);
93 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
94 XN / 1000000, (XN % 1000000) / 10000, xn,
96 pr_info("HSIO bus clock: %d.%02dMHz\n",
97 HSS / 1000000, (HSS % 1000000) / 10000);
103 void pxa3xx_clear_reset_status(unsigned int mask)
105 /* RESET_STATUS_* has a 1:1 mapping with ARSR */
110 * Return the current AC97 clock frequency.
112 static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
114 unsigned long rate = 312000000;
115 unsigned long ac97_div;
119 /* This may loose precision for some rates but won't for the
120 * standard 24.576MHz.
122 rate /= (ac97_div >> 12) & 0x7fff;
123 rate *= (ac97_div & 0xfff);
129 * Return the current HSIO bus clock frequency
131 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
134 unsigned int hss, hsio_clk;
138 hss = (acsr >> 14) & 0x3;
139 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
144 void clk_pxa3xx_cken_enable(struct clk *clk)
146 unsigned long mask = 1ul << (clk->cken & 0x1f);
154 void clk_pxa3xx_cken_disable(struct clk *clk)
156 unsigned long mask = 1ul << (clk->cken & 0x1f);
164 const struct clkops clk_pxa3xx_cken_ops = {
165 .enable = clk_pxa3xx_cken_enable,
166 .disable = clk_pxa3xx_cken_disable,
169 static const struct clkops clk_pxa3xx_hsio_ops = {
170 .enable = clk_pxa3xx_cken_enable,
171 .disable = clk_pxa3xx_cken_disable,
172 .getrate = clk_pxa3xx_hsio_getrate,
175 static const struct clkops clk_pxa3xx_ac97_ops = {
176 .enable = clk_pxa3xx_cken_enable,
177 .disable = clk_pxa3xx_cken_disable,
178 .getrate = clk_pxa3xx_ac97_getrate,
181 static void clk_pout_enable(struct clk *clk)
186 static void clk_pout_disable(struct clk *clk)
191 static const struct clkops clk_pout_ops = {
192 .enable = clk_pout_enable,
193 .disable = clk_pout_disable,
196 static void clk_dummy_enable(struct clk *clk)
200 static void clk_dummy_disable(struct clk *clk)
204 static const struct clkops clk_dummy_ops = {
205 .enable = clk_dummy_enable,
206 .disable = clk_dummy_disable,
209 static struct clk clk_pxa3xx_pout = {
210 .ops = &clk_pout_ops,
215 static struct clk clk_dummy = {
216 .ops = &clk_dummy_ops,
219 static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
220 static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
221 static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
222 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
223 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
224 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
225 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
226 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
227 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
228 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
229 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
230 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
231 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
232 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
233 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
234 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
235 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
236 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
237 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
239 static struct clk_lookup pxa3xx_clkregs[] = {
240 INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
241 /* Power I2C clock is always on */
242 INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
243 INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
244 INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
245 INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
246 INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
247 INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
248 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
249 INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
250 INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
251 INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
252 INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
253 INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
254 INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
255 INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
256 INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
257 INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
258 INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
259 INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
260 INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
261 INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
262 INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
267 #define ISRAM_START 0x5c000000
268 #define ISRAM_SIZE SZ_256K
270 static void __iomem *sram;
271 static unsigned long wakeup_src;
273 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
274 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
276 enum { SLEEP_SAVE_CKENA,
283 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
290 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
298 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
299 * memory controller has to be reinitialised, so we place some code
300 * in the SRAM to perform this function.
302 * We disable FIQs across the standby - otherwise, we might receive a
303 * FIQ while the SDRAM is unavailable.
305 static void pxa3xx_cpu_standby(unsigned int pwrmode)
307 extern const char pm_enter_standby_start[], pm_enter_standby_end[];
308 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
310 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
311 pm_enter_standby_end - pm_enter_standby_start);
315 AD2D0ER = wakeup_src;
329 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
330 * PXA3xx development kits assumes that the resuming process continues
331 * with the address stored within the first 4 bytes of SDRAM. The PSPR
332 * register is used privately by BootROM and OBM, and _must_ be set to
333 * 0x5c014000 for the moment.
335 static void pxa3xx_cpu_pm_suspend(void)
337 volatile unsigned long *p = (volatile void *)0xc0000000;
338 unsigned long saved_data = *p;
340 extern void pxa3xx_cpu_suspend(void);
341 extern void pxa3xx_cpu_resume(void);
343 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
344 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
345 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
347 /* clear and setup wakeup source */
353 PCFR |= (1u << 13); /* L1_DIS */
354 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
358 /* overwrite with the resume address */
359 *p = virt_to_phys(pxa3xx_cpu_resume);
361 pxa3xx_cpu_suspend();
368 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
371 * Don't sleep if no wakeup sources are defined
373 if (wakeup_src == 0) {
374 printk(KERN_ERR "Not suspending: no wakeup sources\n");
379 case PM_SUSPEND_STANDBY:
380 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
384 pxa3xx_cpu_pm_suspend();
389 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
391 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
394 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
395 .save_count = SLEEP_SAVE_COUNT,
396 .save = pxa3xx_cpu_pm_save,
397 .restore = pxa3xx_cpu_pm_restore,
398 .valid = pxa3xx_cpu_pm_valid,
399 .enter = pxa3xx_cpu_pm_enter,
402 static void __init pxa3xx_init_pm(void)
404 sram = ioremap(ISRAM_START, ISRAM_SIZE);
406 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
411 * Since we copy wakeup code into the SRAM, we need to ensure
412 * that it is preserved over the low power modes. Note: bit 8
413 * is undocumented in the developer manual, but must be set.
415 AD1R |= ADXR_L2 | ADXR_R0;
416 AD2R |= ADXR_L2 | ADXR_R0;
417 AD3R |= ADXR_L2 | ADXR_R0;
420 * Clear the resume enable registers.
427 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
430 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
432 unsigned long flags, mask = 0;
436 mask = ADXER_MFP_WSSP3;
449 mask = ADXER_MFP_WAC97;
455 mask = ADXER_MFP_WSSP2;
458 mask = ADXER_MFP_WI2C;
461 mask = ADXER_MFP_WUART3;
464 mask = ADXER_MFP_WUART2;
467 mask = ADXER_MFP_WUART1;
470 mask = ADXER_MFP_WMMC1;
473 mask = ADXER_MFP_WSSP1;
479 mask = ADXER_MFP_WSSP4;
488 mask = ADXER_MFP_WMMC2;
491 mask = ADXER_MFP_WFLASH;
497 mask = ADXER_WEXTWAKE0;
500 mask = ADXER_WEXTWAKE1;
503 mask = ADXER_MFP_GEN12;
509 local_irq_save(flags);
514 local_irq_restore(flags);
519 static inline void pxa3xx_init_pm(void) {}
520 #define pxa3xx_set_wake NULL
523 static void pxa_ack_ext_wakeup(unsigned int irq)
525 PECR |= PECR_IS(irq - IRQ_WAKEUP0);
528 static void pxa_mask_ext_wakeup(unsigned int irq)
530 ICMR2 &= ~(1 << ((irq - PXA_IRQ(0)) & 0x1f));
531 PECR &= ~PECR_IE(irq - IRQ_WAKEUP0);
534 static void pxa_unmask_ext_wakeup(unsigned int irq)
536 ICMR2 |= 1 << ((irq - PXA_IRQ(0)) & 0x1f);
537 PECR |= PECR_IE(irq - IRQ_WAKEUP0);
540 static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
542 if (flow_type & IRQ_TYPE_EDGE_RISING)
543 PWER |= 1 << (irq - IRQ_WAKEUP0);
545 if (flow_type & IRQ_TYPE_EDGE_FALLING)
546 PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);
551 static struct irq_chip pxa_ext_wakeup_chip = {
553 .ack = pxa_ack_ext_wakeup,
554 .mask = pxa_mask_ext_wakeup,
555 .unmask = pxa_unmask_ext_wakeup,
556 .set_type = pxa_set_ext_wakeup_type,
559 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
563 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
564 set_irq_chip(irq, &pxa_ext_wakeup_chip);
565 set_irq_handler(irq, handle_edge_irq);
566 set_irq_flags(irq, IRQF_VALID);
569 pxa_ext_wakeup_chip.set_wake = fn;
572 void __init pxa3xx_init_irq(void)
574 /* enable CP6 access */
576 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
578 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
580 pxa_init_irq(56, pxa3xx_set_wake);
581 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
582 pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
585 static struct map_desc pxa3xx_io_desc[] __initdata = {
587 .virtual = SMEMC_VIRT,
588 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
589 .length = 0x00200000,
594 void __init pxa3xx_map_io(void)
597 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
598 pxa3xx_get_clk_frequency_khz(1);
602 * device registration specific to PXA3xx.
605 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
607 pxa_register_device(&pxa3xx_device_i2c_power, info);
610 static struct platform_device *devices[] __initdata = {
614 &pxa_device_asoc_ssp1,
615 &pxa_device_asoc_ssp2,
616 &pxa_device_asoc_ssp3,
617 &pxa_device_asoc_ssp4,
618 &pxa_device_asoc_platform,
629 static struct sys_device pxa3xx_sysdev[] = {
631 .cls = &pxa_irq_sysclass,
633 .cls = &pxa3xx_mfp_sysclass,
635 .cls = &pxa_gpio_sysclass,
639 static int __init pxa3xx_init(void)
643 if (cpu_is_pxa3xx()) {
648 * clear RDH bit every time after reset
650 * Note: the last 3 bits DxS are write-1-to-clear so carefully
651 * preserve them here in case they will be referenced later
653 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
655 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
657 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
662 for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
663 ret = sysdev_register(&pxa3xx_sysdev[i]);
665 pr_err("failed to register sysdev[%d]\n", i);
668 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
674 postcore_initcall(pxa3xx_init);