2 * linux/arch/arm/mach-pxa/pxa25x.c
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA21x/25x/26x variants.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
24 #include <linux/sysdev.h>
26 #include <asm/hardware.h>
27 #include <asm/arch/irqs.h>
28 #include <asm/arch/pxa-regs.h>
29 #include <asm/arch/pxa2xx-regs.h>
30 #include <asm/arch/mfp-pxa25x.h>
31 #include <asm/arch/pm.h>
32 #include <asm/arch/dma.h>
39 * Various clock factors driven by the CCCR register.
42 /* Crystal Frequency to Memory Frequency Multiplier (L) */
43 static unsigned char L_clk_mult[32] = { 0, 27, 32, 36, 40, 45, 0, };
45 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
46 static unsigned char M_clk_mult[4] = { 0, 1, 2, 4 };
48 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
49 /* Note: we store the value N * 2 here. */
50 static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
53 #define BASE_CLK 3686400
56 * Get the clock frequency as reflected by CCCR and the turbo flag.
57 * We assume these values have been applied via a fcs.
58 * If info is not 0 we also display the current settings.
60 unsigned int pxa25x_get_clk_frequency_khz(int info)
62 unsigned long cccr, turbo;
63 unsigned int l, L, m, M, n2, N;
66 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo) );
68 l = L_clk_mult[(cccr >> 0) & 0x1f];
69 m = M_clk_mult[(cccr >> 5) & 0x03];
70 n2 = N2_clk_mult[(cccr >> 7) & 0x07];
79 printk( KERN_INFO "Memory clock: %d.%02dMHz (*%d)\n",
80 L / 1000000, (L % 1000000) / 10000, l );
82 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
83 M / 1000000, (M % 1000000) / 10000, m );
85 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
86 N / 1000000, (N % 1000000) / 10000, n2 / 2, (n2 % 2) * 5,
87 (turbo & 1) ? "" : "in" );
90 return (turbo & 1) ? (N/1000) : (M/1000);
94 * Return the current memory clock frequency in units of 10kHz
96 unsigned int pxa25x_get_memclk_frequency_10khz(void)
98 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
101 static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
103 return pxa25x_get_memclk_frequency_10khz() * 10000;
106 static const struct clkops clk_pxa25x_lcd_ops = {
107 .enable = clk_cken_enable,
108 .disable = clk_cken_disable,
109 .getrate = clk_pxa25x_lcd_getrate,
112 static unsigned long gpio12_config_32k[] = {
116 static unsigned long gpio12_config_gpio[] = {
120 static void clk_gpio12_enable(struct clk *clk)
122 pxa2xx_mfp_config(gpio12_config_32k, 1);
125 static void clk_gpio12_disable(struct clk *clk)
127 pxa2xx_mfp_config(gpio12_config_gpio, 1);
130 static const struct clkops clk_pxa25x_gpio12_ops = {
131 .enable = clk_gpio12_enable,
132 .disable = clk_gpio12_disable,
136 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
137 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
138 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
140 static struct clk pxa25x_hwuart_clk =
141 INIT_CKEN("UARTCLK", HWUART, 14745600, 1, &pxa_device_hwuart.dev)
145 * PXA 2xx clock declarations. Order is important (see aliases below)
146 * Please be careful not to disrupt the ordering.
148 static struct clk pxa25x_clks[] = {
149 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
150 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
151 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
152 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
153 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa25x_device_udc.dev),
154 INIT_CLK("GPIO12_CLK", &clk_pxa25x_gpio12_ops, 32768, 0, NULL),
155 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
156 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
158 INIT_CKEN("SSPCLK", SSP, 3686400, 0, &pxa25x_device_ssp.dev),
159 INIT_CKEN("SSPCLK", NSSP, 3686400, 0, &pxa25x_device_nssp.dev),
160 INIT_CKEN("SSPCLK", ASSP, 3686400, 0, &pxa25x_device_assp.dev),
161 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, &pxa25x_device_pwm0.dev),
162 INIT_CKEN("PWMCLK", PWM1, 3686400, 0, &pxa25x_device_pwm1.dev),
164 INIT_CKEN("AC97CLK", AC97, 24576000, 0, NULL),
167 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
169 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
172 static struct clk gpio7_clk = INIT_CKOTHER("GPIO7_CK", &pxa25x_clks[4], NULL);
176 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
177 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
180 * List of global PXA peripheral registers to preserve.
181 * More ones like CP and general purpose register values are preserved
182 * with the stack pointer in sleep.S.
184 enum { SLEEP_SAVE_PGSR0, SLEEP_SAVE_PGSR1, SLEEP_SAVE_PGSR2,
186 SLEEP_SAVE_GAFR0_L, SLEEP_SAVE_GAFR0_U,
187 SLEEP_SAVE_GAFR1_L, SLEEP_SAVE_GAFR1_U,
188 SLEEP_SAVE_GAFR2_L, SLEEP_SAVE_GAFR2_U,
198 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
200 SAVE(PGSR0); SAVE(PGSR1); SAVE(PGSR2);
202 SAVE(GAFR0_L); SAVE(GAFR0_U);
203 SAVE(GAFR1_L); SAVE(GAFR1_U);
204 SAVE(GAFR2_L); SAVE(GAFR2_U);
209 /* Clear GPIO transition detect bits */
210 GEDR0 = GEDR0; GEDR1 = GEDR1; GEDR2 = GEDR2;
213 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
215 /* ensure not to come back here if it wasn't intended */
218 /* restore registers */
219 RESTORE(GAFR0_L); RESTORE(GAFR0_U);
220 RESTORE(GAFR1_L); RESTORE(GAFR1_U);
221 RESTORE(GAFR2_L); RESTORE(GAFR2_U);
222 RESTORE(PGSR0); RESTORE(PGSR1); RESTORE(PGSR2);
224 PSSR = PSSR_RDH | PSSR_PH;
230 static void pxa25x_cpu_pm_enter(suspend_state_t state)
232 /* Clear reset status */
233 RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
237 /* set resume return address */
238 PSPR = virt_to_phys(pxa_cpu_resume);
239 pxa25x_cpu_suspend(PWRMODE_SLEEP);
244 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
245 .save_count = SLEEP_SAVE_COUNT,
246 .valid = suspend_valid_only_mem,
247 .save = pxa25x_cpu_pm_save,
248 .restore = pxa25x_cpu_pm_restore,
249 .enter = pxa25x_cpu_pm_enter,
252 static void __init pxa25x_init_pm(void)
254 pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
257 static inline void pxa25x_init_pm(void) {}
260 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
263 static int pxa25x_set_wake(unsigned int irq, unsigned int on)
265 int gpio = IRQ_TO_GPIO(irq);
268 if (gpio >= 0 && gpio < 85)
269 return gpio_set_wake(gpio, on);
271 if (irq == IRQ_RTCAlrm) {
287 void __init pxa25x_init_irq(void)
289 pxa_init_irq(32, pxa25x_set_wake);
290 pxa_init_gpio(85, pxa25x_set_wake);
293 static struct platform_device *pxa25x_devices[] __initdata = {
307 static struct sys_device pxa25x_sysdev[] = {
309 .cls = &pxa_irq_sysclass,
311 .cls = &pxa_gpio_sysclass,
315 static int __init pxa25x_init(void)
319 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
321 clks_register(&pxa25x_hwuart_clk, 1);
323 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
324 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
326 if ((ret = pxa_init_dma(16)))
331 for (i = 0; i < ARRAY_SIZE(pxa25x_sysdev); i++) {
332 ret = sysdev_register(&pxa25x_sysdev[i]);
334 pr_err("failed to register sysdev[%d]\n", i);
337 ret = platform_add_devices(pxa25x_devices,
338 ARRAY_SIZE(pxa25x_devices));
343 /* Only add HWUART for PXA255/26x; PXA210/250/27x do not have it. */
345 ret = platform_device_register(&pxa_device_hwuart);
347 clks_register(&gpio7_clk, 1);
352 postcore_initcall(pxa25x_init);