2 * interrupt controller support for CSR SiRFprimaII
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
6 * Licensed under GPLv2 or later.
9 #include <linux/init.h>
11 #include <linux/irq.h>
12 #include <mach/hardware.h>
13 #include <asm/mach/irq.h>
15 #include <linux/of_address.h>
16 #include <linux/irqdomain.h>
18 #define SIRFSOC_INT_RISC_MASK0 0x0018
19 #define SIRFSOC_INT_RISC_MASK1 0x001C
20 #define SIRFSOC_INT_RISC_LEVEL0 0x0020
21 #define SIRFSOC_INT_RISC_LEVEL1 0x0024
23 void __iomem *sirfsoc_intc_base;
26 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
28 struct irq_chip_generic *gc;
29 struct irq_chip_type *ct;
31 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
34 ct->chip.irq_mask = irq_gc_mask_clr_bit;
35 ct->chip.irq_unmask = irq_gc_mask_set_bit;
36 ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
38 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
41 static __init void sirfsoc_irq_init(void)
43 sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
44 sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
46 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
47 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
49 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
50 writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
53 static struct of_device_id intc_ids[] = {
54 { .compatible = "sirf,prima2-intc" },
58 void __init sirfsoc_of_irq_init(void)
60 struct device_node *np;
62 np = of_find_matching_node(NULL, intc_ids);
64 panic("unable to find compatible intc node in dtb\n");
66 sirfsoc_intc_base = of_iomap(np, 0);
67 if (!sirfsoc_intc_base)
68 panic("unable to map intc cpu registers\n");
70 irq_domain_add_simple(np, 0);