arch/arm/mach-orion5x/common.c

   1 /*
   2  * arch/arm/mach-orion5x/common.c
   3  *
   4  * Core functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/dma-mapping.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/mbus.h>
  19 #include <linux/mv643xx_i2c.h>
  20 #include <linux/ata_platform.h>
  21 #include <net/dsa.h>
  22 #include <asm/page.h>
  23 #include <asm/setup.h>
  24 #include <asm/timex.h>
  25 #include <asm/mach/arch.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/time.h>
  28 #include <mach/bridge-regs.h>
  29 #include <mach/hardware.h>
  30 #include <mach/orion5x.h>
  31 #include <plat/orion_nand.h>
  32 #include <plat/ehci-orion.h>
  33 #include <plat/time.h>
  34 #include <plat/common.h>
  35 #include "common.h"
  36
  37 /*****************************************************************************
  38  * I/O Address Mapping
  39  ****************************************************************************/
  40 static struct map_desc orion5x_io_desc[] __initdata = {
  41         {
  42                 .virtual        = ORION5X_REGS_VIRT_BASE,
  43                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
  44                 .length         = ORION5X_REGS_SIZE,
  45                 .type           = MT_DEVICE,
  46         }, {
  47                 .virtual        = ORION5X_PCIE_IO_VIRT_BASE,
  48                 .pfn            = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
  49                 .length         = ORION5X_PCIE_IO_SIZE,
  50                 .type           = MT_DEVICE,
  51         }, {
  52                 .virtual        = ORION5X_PCI_IO_VIRT_BASE,
  53                 .pfn            = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
  54                 .length         = ORION5X_PCI_IO_SIZE,
  55                 .type           = MT_DEVICE,
  56         }, {
  57                 .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
  58                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
  59                 .length         = ORION5X_PCIE_WA_SIZE,
  60                 .type           = MT_DEVICE,
  61         },
  62 };
  63
  64 void __init orion5x_map_io(void)
  65 {
  66         iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
  67 }
  68
  69
  70 /*****************************************************************************
  71  * EHCI0
  72  ****************************************************************************/
  73 void __init orion5x_ehci0_init(void)
  74 {
  75         orion_ehci_init(&orion5x_mbus_dram_info,
  76                         ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL,
  77                         EHCI_PHY_ORION);
  78 }
  79
  80
  81 /*****************************************************************************
  82  * EHCI1
  83  ****************************************************************************/
  84 void __init orion5x_ehci1_init(void)
  85 {
  86         orion_ehci_1_init(&orion5x_mbus_dram_info,
  87                           ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
  88 }
  89
  90
  91 /*****************************************************************************
  92  * GE00
  93  ****************************************************************************/
  94 void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
  95 {
  96         orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
  97                         ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
  98                         IRQ_ORION5X_ETH_ERR, orion5x_tclk);
  99 }
 100
 101
 102 /*****************************************************************************
 103  * Ethernet switch
 104  ****************************************************************************/
 105 void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
 106 {
 107         orion_ge00_switch_init(d, irq);
 108 }
 109
 110
 111 /*****************************************************************************
 112  * I2C
 113  ****************************************************************************/
 114 void __init orion5x_i2c_init(void)
 115 {
 116         orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
 117
 118 }
 119
 120
 121 /*****************************************************************************
 122  * SATA
 123  ****************************************************************************/
 124 void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
 125 {
 126         orion_sata_init(sata_data, &orion5x_mbus_dram_info,
 127                         ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
 128 }
 129
 130
 131 /*****************************************************************************
 132  * SPI
 133  ****************************************************************************/
 134 void __init orion5x_spi_init()
 135 {
 136         orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
 137 }
 138
 139
 140 /*****************************************************************************
 141  * UART0
 142  ****************************************************************************/
 143 void __init orion5x_uart0_init(void)
 144 {
 145         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 146                          IRQ_ORION5X_UART0, orion5x_tclk);
 147 }
 148
 149 /*****************************************************************************
 150  * UART1
 151  ****************************************************************************/
 152 void __init orion5x_uart1_init(void)
 153 {
 154         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 155                          IRQ_ORION5X_UART1, orion5x_tclk);
 156 }
 157
 158 /*****************************************************************************
 159  * XOR engine
 160  ****************************************************************************/
 161 void __init orion5x_xor_init(void)
 162 {
 163         orion_xor0_init(&orion5x_mbus_dram_info,
 164                         ORION5X_XOR_PHYS_BASE,
 165                         ORION5X_XOR_PHYS_BASE + 0x200,
 166                         IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
 167 }
 168
 169 /*****************************************************************************
 170  * Cryptographic Engines and Security Accelerator (CESA)
 171  ****************************************************************************/
 172 static void __init orion5x_crypto_init(void)
 173 {
 174         int ret;
 175
 176         ret = orion5x_setup_sram_win();
 177         if (ret)
 178                 return;
 179
 180         orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
 181                           SZ_8K, IRQ_ORION5X_CESA);
 182 }
 183
 184 /*****************************************************************************
 185  * Watchdog
 186  ****************************************************************************/
 187 void __init orion5x_wdt_init(void)
 188 {
 189         orion_wdt_init(orion5x_tclk);
 190 }
 191
 192
 193 /*****************************************************************************
 194  * Time handling
 195  ****************************************************************************/
 196 void __init orion5x_init_early(void)
 197 {
 198         orion_time_set_base(TIMER_VIRT_BASE);
 199 }
 200
 201 int orion5x_tclk;
 202
 203 int __init orion5x_find_tclk(void)
 204 {
 205         u32 dev, rev;
 206
 207         orion5x_pcie_id(&dev, &rev);
 208         if (dev == MV88F6183_DEV_ID &&
 209             (readl(MPP_RESET_SAMPLE) & 0x00000200) == 0)
 210                 return 133333333;
 211
 212         return 166666667;
 213 }
 214
 215 static void orion5x_timer_init(void)
 216 {
 217         orion5x_tclk = orion5x_find_tclk();
 218
 219         orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 220                         IRQ_ORION5X_BRIDGE, orion5x_tclk);
 221 }
 222
 223 struct sys_timer orion5x_timer = {
 224         .init = orion5x_timer_init,
 225 };
 226
 227
 228 /*****************************************************************************
 229  * General
 230  ****************************************************************************/
 231 /*
 232  * Identify device ID and rev from PCIe configuration header space '0'.
 233  */
 234 static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
 235 {
 236         orion5x_pcie_id(dev, rev);
 237
 238         if (*dev == MV88F5281_DEV_ID) {
 239                 if (*rev == MV88F5281_REV_D2) {
 240                         *dev_name = "MV88F5281-D2";
 241                 } else if (*rev == MV88F5281_REV_D1) {
 242                         *dev_name = "MV88F5281-D1";
 243                 } else if (*rev == MV88F5281_REV_D0) {
 244                         *dev_name = "MV88F5281-D0";
 245                 } else {
 246                         *dev_name = "MV88F5281-Rev-Unsupported";
 247                 }
 248         } else if (*dev == MV88F5182_DEV_ID) {
 249                 if (*rev == MV88F5182_REV_A2) {
 250                         *dev_name = "MV88F5182-A2";
 251                 } else {
 252                         *dev_name = "MV88F5182-Rev-Unsupported";
 253                 }
 254         } else if (*dev == MV88F5181_DEV_ID) {
 255                 if (*rev == MV88F5181_REV_B1) {
 256                         *dev_name = "MV88F5181-Rev-B1";
 257                 } else if (*rev == MV88F5181L_REV_A1) {
 258                         *dev_name = "MV88F5181L-Rev-A1";
 259                 } else {
 260                         *dev_name = "MV88F5181(L)-Rev-Unsupported";
 261                 }
 262         } else if (*dev == MV88F6183_DEV_ID) {
 263                 if (*rev == MV88F6183_REV_B0) {
 264                         *dev_name = "MV88F6183-Rev-B0";
 265                 } else {
 266                         *dev_name = "MV88F6183-Rev-Unsupported";
 267                 }
 268         } else {
 269                 *dev_name = "Device-Unknown";
 270         }
 271 }
 272
 273 void __init orion5x_init(void)
 274 {
 275         char *dev_name;
 276         u32 dev, rev;
 277
 278         orion5x_id(&dev, &rev, &dev_name);
 279         printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
 280
 281         /*
 282          * Setup Orion address map
 283          */
 284         orion5x_setup_cpu_mbus_bridge();
 285
 286         /*
 287          * Don't issue "Wait for Interrupt" instruction if we are
 288          * running on D0 5281 silicon.
 289          */
 290         if (dev == MV88F5281_DEV_ID && rev == MV88F5281_REV_D0) {
 291                 printk(KERN_INFO "Orion: Applying 5281 D0 WFI workaround.\n");
 292                 disable_hlt();
 293         }
 294
 295         /*
 296          * The 5082/5181l/5182/6082/6082l/6183 have crypto
 297          * while 5180n/5181/5281 don't have crypto.
 298          */
 299         if ((dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0) ||
 300             dev == MV88F5182_DEV_ID || dev == MV88F6183_DEV_ID)
 301                 orion5x_crypto_init();
 302
 303         /*
 304          * Register watchdog driver
 305          */
 306         orion5x_wdt_init();
 307 }
 308
 309 /*
 310  * Many orion-based systems have buggy bootloader implementations.
 311  * This is a common fixup for bogus memory tags.
 312  */
 313 void __init tag_fixup_mem32(struct tag *t, char **from,
 314                             struct meminfo *meminfo)
 315 {
 316         for (; t->hdr.size; t = tag_next(t))
 317                 if (t->hdr.tag == ATAG_MEM &&
 318                     (!t->u.mem.size || t->u.mem.size & ~PAGE_MASK ||
 319                      t->u.mem.start & ~PAGE_MASK)) {
 320                         printk(KERN_WARNING
 321                                "Clearing invalid memory bank %dKB@0x%08x\n",
 322                                t->u.mem.size / 1024, t->u.mem.start);
 323                         t->hdr.tag = 0;
 324                 }
 325 }