arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39
  40 #include <asm/mach/time.h>
  41 #include <plat/dmtimer.h>
  42 #include <asm/localtimer.h>
  43 #include <asm/sched_clock.h>
  44 #include <plat/common.h>
  45 #include <plat/omap_hwmod.h>
  46 #include <plat/omap_device.h>
  47
  48 /* Parent clocks, eventually these will come from the clock framework */
  49
  50 #define OMAP2_MPU_SOURCE        "sys_ck"
  51 #define OMAP3_MPU_SOURCE        OMAP2_MPU_SOURCE
  52 #define OMAP4_MPU_SOURCE        "sys_clkin_ck"
  53 #define OMAP2_32K_SOURCE        "func_32k_ck"
  54 #define OMAP3_32K_SOURCE        "omap_32k_fck"
  55 #define OMAP4_32K_SOURCE        "sys_32k_ck"
  56
  57 #ifdef CONFIG_OMAP_32K_TIMER
  58 #define OMAP2_CLKEV_SOURCE      OMAP2_32K_SOURCE
  59 #define OMAP3_CLKEV_SOURCE      OMAP3_32K_SOURCE
  60 #define OMAP4_CLKEV_SOURCE      OMAP4_32K_SOURCE
  61 #define OMAP3_SECURE_TIMER      12
  62 #else
  63 #define OMAP2_CLKEV_SOURCE      OMAP2_MPU_SOURCE
  64 #define OMAP3_CLKEV_SOURCE      OMAP3_MPU_SOURCE
  65 #define OMAP4_CLKEV_SOURCE      OMAP4_MPU_SOURCE
  66 #define OMAP3_SECURE_TIMER      1
  67 #endif
  68
  69 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
  70 #define MAX_GPTIMER_ID          12
  71
  72 u32 sys_timer_reserved;
  73
  74 /* Clockevent code */
  75
  76 static struct omap_dm_timer clkev;
  77 static struct clock_event_device clockevent_gpt;
  78
  79 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  80 {
  81         struct clock_event_device *evt = &clockevent_gpt;
  82
  83         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  84
  85         evt->event_handler(evt);
  86         return IRQ_HANDLED;
  87 }
  88
  89 static struct irqaction omap2_gp_timer_irq = {
  90         .name           = "gp timer",
  91         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
  92         .handler        = omap2_gp_timer_interrupt,
  93 };
  94
  95 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  96                                          struct clock_event_device *evt)
  97 {
  98         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
  99                                                 0xffffffff - cycles, 1);
 100
 101         return 0;
 102 }
 103
 104 static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
 105                                     struct clock_event_device *evt)
 106 {
 107         u32 period;
 108
 109         __omap_dm_timer_stop(&clkev, 1, clkev.rate);
 110
 111         switch (mode) {
 112         case CLOCK_EVT_MODE_PERIODIC:
 113                 period = clkev.rate / HZ;
 114                 period -= 1;
 115                 /* Looks like we need to first set the load value separately */
 116                 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
 117                                         0xffffffff - period, 1);
 118                 __omap_dm_timer_load_start(&clkev,
 119                                         OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 120                                                 0xffffffff - period, 1);
 121                 break;
 122         case CLOCK_EVT_MODE_ONESHOT:
 123                 break;
 124         case CLOCK_EVT_MODE_UNUSED:
 125         case CLOCK_EVT_MODE_SHUTDOWN:
 126         case CLOCK_EVT_MODE_RESUME:
 127                 break;
 128         }
 129 }
 130
 131 static struct clock_event_device clockevent_gpt = {
 132         .name           = "gp timer",
 133         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 134         .shift          = 32,
 135         .set_next_event = omap2_gp_timer_set_next_event,
 136         .set_mode       = omap2_gp_timer_set_mode,
 137 };
 138
 139 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 140                                                 int gptimer_id,
 141                                                 const char *fck_source)
 142 {
 143         char name[10]; /* 10 = sizeof("gptXX_Xck0") */
 144         struct omap_hwmod *oh;
 145         size_t size;
 146         int res = 0;
 147
 148         sprintf(name, "timer%d", gptimer_id);
 149         omap_hwmod_setup_one(name);
 150         oh = omap_hwmod_lookup(name);
 151         if (!oh)
 152                 return -ENODEV;
 153
 154         timer->irq = oh->mpu_irqs[0].irq;
 155         timer->phys_base = oh->slaves[0]->addr->pa_start;
 156         size = oh->slaves[0]->addr->pa_end - timer->phys_base;
 157
 158         /* Static mapping, never released */
 159         timer->io_base = ioremap(timer->phys_base, size);
 160         if (!timer->io_base)
 161                 return -ENXIO;
 162
 163         /* After the dmtimer is using hwmod these clocks won't be needed */
 164         sprintf(name, "gpt%d_fck", gptimer_id);
 165         timer->fclk = clk_get(NULL, name);
 166         if (IS_ERR(timer->fclk))
 167                 return -ENODEV;
 168
 169         sprintf(name, "gpt%d_ick", gptimer_id);
 170         timer->iclk = clk_get(NULL, name);
 171         if (IS_ERR(timer->iclk)) {
 172                 clk_put(timer->fclk);
 173                 return -ENODEV;
 174         }
 175
 176         omap_hwmod_enable(oh);
 177
 178         sys_timer_reserved |= (1 << (gptimer_id - 1));
 179
 180         if (gptimer_id != 12) {
 181                 struct clk *src;
 182
 183                 src = clk_get(NULL, fck_source);
 184                 if (IS_ERR(src)) {
 185                         res = -EINVAL;
 186                 } else {
 187                         res = __omap_dm_timer_set_source(timer->fclk, src);
 188                         if (IS_ERR_VALUE(res))
 189                                 pr_warning("%s: timer%i cannot set source\n",
 190                                                 __func__, gptimer_id);
 191                         clk_put(src);
 192                 }
 193         }
 194         __omap_dm_timer_init_regs(timer);
 195         __omap_dm_timer_reset(timer, 1, 1);
 196         timer->posted = 1;
 197
 198         timer->rate = clk_get_rate(timer->fclk);
 199
 200         timer->reserved = 1;
 201
 202         return res;
 203 }
 204
 205 static void __init omap2_gp_clockevent_init(int gptimer_id,
 206                                                 const char *fck_source)
 207 {
 208         int res;
 209
 210         res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
 211         BUG_ON(res);
 212
 213         omap2_gp_timer_irq.dev_id = (void *)&clkev;
 214         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 215
 216         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 217
 218         clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
 219                                      clockevent_gpt.shift);
 220         clockevent_gpt.max_delta_ns =
 221                 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
 222         clockevent_gpt.min_delta_ns =
 223                 clockevent_delta2ns(3, &clockevent_gpt);
 224                 /* Timer internal resynch latency. */
 225
 226         clockevent_gpt.cpumask = cpumask_of(0);
 227         clockevents_register_device(&clockevent_gpt);
 228
 229         pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
 230                 gptimer_id, clkev.rate);
 231 }
 232
 233 /* Clocksource code */
 234
 235 #ifdef CONFIG_OMAP_32K_TIMER
 236 /*
 237  * When 32k-timer is enabled, don't use GPTimer for clocksource
 238  * instead, just leave default clocksource which uses the 32k
 239  * sync counter.  See clocksource setup in plat-omap/counter_32k.c
 240  */
 241
 242 static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
 243 {
 244         omap_init_clocksource_32k();
 245 }
 246
 247 #else
 248
 249 static struct omap_dm_timer clksrc;
 250
 251 /*
 252  * clocksource
 253  */
 254 static DEFINE_CLOCK_DATA(cd);
 255 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 256 {
 257         return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1);
 258 }
 259
 260 static struct clocksource clocksource_gpt = {
 261         .name           = "gp timer",
 262         .rating         = 300,
 263         .read           = clocksource_read_cycles,
 264         .mask           = CLOCKSOURCE_MASK(32),
 265         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 266 };
 267
 268 static void notrace dmtimer_update_sched_clock(void)
 269 {
 270         u32 cyc;
 271
 272         cyc = __omap_dm_timer_read_counter(&clksrc, 1);
 273
 274         update_sched_clock(&cd, cyc, (u32)~0);
 275 }
 276
 277 unsigned long long notrace sched_clock(void)
 278 {
 279         u32 cyc = 0;
 280
 281         if (clksrc.reserved)
 282                 cyc = __omap_dm_timer_read_counter(&clksrc, 1);
 283
 284         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 285 }
 286
 287 /* Setup free-running counter for clocksource */
 288 static void __init omap2_gp_clocksource_init(int gptimer_id,
 289                                                 const char *fck_source)
 290 {
 291         int res;
 292
 293         res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
 294         BUG_ON(res);
 295
 296         pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
 297                 gptimer_id, clksrc.rate);
 298
 299         __omap_dm_timer_load_start(&clksrc,
 300                         OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1);
 301         init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
 302
 303         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 304                 pr_err("Could not register clocksource %s\n",
 305                         clocksource_gpt.name);
 306 }
 307 #endif
 308
 309 #define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src,                  \
 310                                 clksrc_nr, clksrc_src)                  \
 311 static void __init omap##name##_timer_init(void)                        \
 312 {                                                                       \
 313         omap2_gp_clockevent_init((clkev_nr), clkev_src);                \
 314         omap2_gp_clocksource_init((clksrc_nr), clksrc_src);             \
 315 }
 316
 317 #define OMAP_SYS_TIMER(name)                                            \
 318 struct sys_timer omap##name##_timer = {                                 \
 319         .init   = omap##name##_timer_init,                              \
 320 };
 321
 322 #ifdef CONFIG_ARCH_OMAP2
 323 OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
 324 OMAP_SYS_TIMER(2)
 325 #endif
 326
 327 #ifdef CONFIG_ARCH_OMAP3
 328 OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
 329 OMAP_SYS_TIMER(3)
 330 OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 331                         2, OMAP3_MPU_SOURCE)
 332 OMAP_SYS_TIMER(3_secure)
 333 #endif
 334
 335 #ifdef CONFIG_ARCH_OMAP4
 336 static void __init omap4_timer_init(void)
 337 {
 338 #ifdef CONFIG_LOCAL_TIMERS
 339         twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
 340         BUG_ON(!twd_base);
 341 #endif
 342         omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
 343         omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
 344 }
 345 OMAP_SYS_TIMER(4)
 346 #endif
 347
 348 /**
 349  * omap2_dm_timer_set_src - change the timer input clock source
 350  * @pdev:       timer platform device pointer
 351  * @source:     array index of parent clock source
 352  */
 353 static int omap2_dm_timer_set_src(struct platform_device *pdev, int source)
 354 {
 355         int ret;
 356         struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
 357         struct clk *fclk, *parent;
 358         char *parent_name = NULL;
 359
 360         fclk = clk_get(&pdev->dev, "fck");
 361         if (IS_ERR_OR_NULL(fclk)) {
 362                 dev_err(&pdev->dev, "%s: %d: clk_get() FAILED\n",
 363                                 __func__, __LINE__);
 364                 return -EINVAL;
 365         }
 366
 367         switch (source) {
 368         case OMAP_TIMER_SRC_SYS_CLK:
 369                 parent_name = "sys_ck";
 370                 break;
 371
 372         case OMAP_TIMER_SRC_32_KHZ:
 373                 parent_name = "32k_ck";
 374                 break;
 375
 376         case OMAP_TIMER_SRC_EXT_CLK:
 377                 if (pdata->timer_ip_version == OMAP_TIMER_IP_VERSION_1) {
 378                         parent_name = "alt_ck";
 379                         break;
 380                 }
 381                 dev_err(&pdev->dev, "%s: %d: invalid clk src.\n",
 382                         __func__, __LINE__);
 383                 clk_put(fclk);
 384                 return -EINVAL;
 385         }
 386
 387         parent = clk_get(&pdev->dev, parent_name);
 388         if (IS_ERR_OR_NULL(parent)) {
 389                 dev_err(&pdev->dev, "%s: %d: clk_get() %s FAILED\n",
 390                         __func__, __LINE__, parent_name);
 391                 clk_put(fclk);
 392                 return -EINVAL;
 393         }
 394
 395         ret = clk_set_parent(fclk, parent);
 396         if (IS_ERR_VALUE(ret)) {
 397                 dev_err(&pdev->dev, "%s: clk_set_parent() to %s FAILED\n",
 398                         __func__, parent_name);
 399                 ret = -EINVAL;
 400         }
 401
 402         clk_put(parent);
 403         clk_put(fclk);
 404
 405         return ret;
 406 }
 407
 408 struct omap_device_pm_latency omap2_dmtimer_latency[] = {
 409         {
 410                 .deactivate_func = omap_device_idle_hwmods,
 411                 .activate_func   = omap_device_enable_hwmods,
 412                 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
 413         },
 414 };
 415
 416 /**
 417  * omap_timer_init - build and register timer device with an
 418  * associated timer hwmod
 419  * @oh: timer hwmod pointer to be used to build timer device
 420  * @user:       parameter that can be passed from calling hwmod API
 421  *
 422  * Called by omap_hwmod_for_each_by_class to register each of the timer
 423  * devices present in the system. The number of timer devices is known
 424  * by parsing through the hwmod database for a given class name. At the
 425  * end of function call memory is allocated for timer device and it is
 426  * registered to the framework ready to be proved by the driver.
 427  */
 428 static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
 429 {
 430         int id;
 431         int ret = 0;
 432         char *name = "omap_timer";
 433         struct dmtimer_platform_data *pdata;
 434         struct omap_device *od;
 435         struct omap_timer_capability_dev_attr *timer_dev_attr;
 436
 437         pr_debug("%s: %s\n", __func__, oh->name);
 438
 439         /* on secure device, do not register secure timer */
 440         timer_dev_attr = oh->dev_attr;
 441         if (omap_type() != OMAP2_DEVICE_TYPE_GP && timer_dev_attr)
 442                 if (timer_dev_attr->timer_capability == OMAP_TIMER_SECURE)
 443                         return ret;
 444
 445         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
 446         if (!pdata) {
 447                 pr_err("%s: No memory for [%s]\n", __func__, oh->name);
 448                 return -ENOMEM;
 449         }
 450
 451         /*
 452          * Extract the IDs from name field in hwmod database
 453          * and use the same for constructing ids' for the
 454          * timer devices. In a way, we are avoiding usage of
 455          * static variable witin the function to do the same.
 456          * CAUTION: We have to be careful and make sure the
 457          * name in hwmod database does not change in which case
 458          * we might either make corresponding change here or
 459          * switch back static variable mechanism.
 460          */
 461         sscanf(oh->name, "timer%2d", &id);
 462
 463         pdata->set_timer_src = omap2_dm_timer_set_src;
 464         pdata->timer_ip_version = oh->class->rev;
 465
 466         od = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
 467                         omap2_dmtimer_latency,
 468                         ARRAY_SIZE(omap2_dmtimer_latency),
 469                         0);
 470
 471         if (IS_ERR(od)) {
 472                 pr_err("%s: Can't build omap_device for %s: %s.\n",
 473                         __func__, name, oh->name);
 474                 ret = -EINVAL;
 475         }
 476
 477         kfree(pdata);
 478
 479         return ret;
 480 }
 481
 482 /**
 483  * omap2_dm_timer_init - top level regular device initialization
 484  *
 485  * Uses dedicated hwmod api to parse through hwmod database for
 486  * given class name and then build and register the timer device.
 487  */
 488 static int __init omap2_dm_timer_init(void)
 489 {
 490         int ret;
 491
 492         ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
 493         if (unlikely(ret)) {
 494                 pr_err("%s: device registration failed.\n", __func__);
 495                 return -EINVAL;
 496         }
 497
 498         return 0;
 499 }
 500 arch_initcall(omap2_dm_timer_init);