arch/arm/mach-omap2/sram34xx.S

   1 /*
   2  * linux/arch/arm/mach-omap3/sram.S
   3  *
   4  * Omap3 specific functions that need to be run in internal SRAM
   5  *
   6  * (C) Copyright 2007
   7  * Texas Instruments Inc.
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * (C) Copyright 2004
  11  * Texas Instruments, <www.ti.com>
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29 #include <linux/linkage.h>
  30 #include <asm/assembler.h>
  31 #include <mach/hardware.h>
  32
  33 #include <mach/io.h>
  34
  35 #include "sdrc.h"
  36 #include "cm.h"
  37
  38         .text
  39
  40 /*
  41  * Change frequency of core dpll
  42  * r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
  43  */
  44 ENTRY(omap3_sram_configure_core_dpll)
  45         stmfd   sp!, {r1-r12, lr}       @ store regs to stack
  46         cmp     r3, #0x2
  47         blne    configure_sdrc
  48         cmp     r3, #0x2
  49         blne    lock_dll
  50         cmp     r3, #0x1
  51         blne    unlock_dll
  52         bl      sdram_in_selfrefresh    @ put the SDRAM in self refresh
  53         bl      configure_core_dpll
  54         bl      enable_sdrc
  55         cmp     r3, #0x1
  56         blne    wait_dll_unlock
  57         cmp     r3, #0x2
  58         blne    wait_dll_lock
  59         cmp     r3, #0x1
  60         blne    configure_sdrc
  61         mov     r0, #0                  @ return value
  62         ldmfd   sp!, {r1-r12, pc}       @ restore regs and return
  63 unlock_dll:
  64         ldr     r4, omap3_sdrc_dlla_ctrl
  65         ldr     r5, [r4]
  66         orr     r5, r5, #0x4
  67         str     r5, [r4]
  68         bx      lr
  69 lock_dll:
  70         ldr     r4, omap3_sdrc_dlla_ctrl
  71         ldr     r5, [r4]
  72         bic     r5, r5, #0x4
  73         str     r5, [r4]
  74         bx      lr
  75 sdram_in_selfrefresh:
  76         mov     r5, #0x0                @ Move 0 to R5
  77         mcr     p15, 0, r5, c7, c10, 5  @ memory barrier
  78         ldr     r4, omap3_sdrc_power    @ read the SDRC_POWER register
  79         ldr     r5, [r4]                @ read the contents of SDRC_POWER
  80         orr     r5, r5, #0x40           @ enable self refresh on idle req
  81         str     r5, [r4]                @ write back to SDRC_POWER register
  82         ldr     r4, omap3_cm_iclken1_core       @ read the CM_ICLKEN1_CORE reg
  83         ldr     r5, [r4]
  84         bic     r5, r5, #0x2            @ disable iclk bit for SRDC
  85         str     r5, [r4]
  86 wait_sdrc_idle:
  87         ldr     r4, omap3_cm_idlest1_core
  88         ldr     r5, [r4]
  89         and     r5, r5, #0x2            @ check for SDRC idle
  90         cmp     r5, #2
  91         bne     wait_sdrc_idle
  92         bx      lr
  93 configure_core_dpll:
  94         ldr     r4, omap3_cm_clksel1_pll
  95         ldr     r5, [r4]
  96         ldr     r6, core_m2_mask_val    @ modify m2 for core dpll
  97         and     r5, r5, r6
  98         orr     r5, r5, r3, lsl #0x1B   @ r3 contains the M2 val
  99         str     r5, [r4]
 100         mov     r5, #0x800              @ wait for the clock to stabilise
 101         cmp     r3, #2
 102         bne     wait_clk_stable
 103         bx      lr
 104 wait_clk_stable:
 105         subs    r5, r5, #1
 106         bne     wait_clk_stable
 107         nop
 108         nop
 109         nop
 110         nop
 111         nop
 112         nop
 113         nop
 114         nop
 115         nop
 116         nop
 117         bx      lr
 118 enable_sdrc:
 119         ldr     r4, omap3_cm_iclken1_core
 120         ldr     r5, [r4]
 121         orr     r5, r5, #0x2            @ enable iclk bit for SDRC
 122         str     r5, [r4]
 123 wait_sdrc_idle1:
 124         ldr     r4, omap3_cm_idlest1_core
 125         ldr     r5, [r4]
 126         and     r5, r5, #0x2
 127         cmp     r5, #0
 128         bne     wait_sdrc_idle1
 129         ldr     r4, omap3_sdrc_power
 130         ldr     r5, [r4]
 131         bic     r5, r5, #0x40
 132         str     r5, [r4]
 133         bx      lr
 134 wait_dll_lock:
 135         ldr     r4, omap3_sdrc_dlla_status
 136         ldr     r5, [r4]
 137         and     r5, r5, #0x4
 138         cmp     r5, #0x4
 139         bne     wait_dll_lock
 140         bx      lr
 141 wait_dll_unlock:
 142         ldr     r4, omap3_sdrc_dlla_status
 143         ldr     r5, [r4]
 144         and     r5, r5, #0x4
 145         cmp     r5, #0x0
 146         bne     wait_dll_unlock
 147         bx      lr
 148 configure_sdrc:
 149         ldr     r4, omap3_sdrc_rfr_ctrl
 150         str     r0, [r4]
 151         ldr     r4, omap3_sdrc_actim_ctrla
 152         str     r1, [r4]
 153         ldr     r4, omap3_sdrc_actim_ctrlb
 154         str     r2, [r4]
 155         bx      lr
 156
 157 omap3_sdrc_power:
 158         .word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
 159 omap3_cm_clksel1_pll:
 160         .word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
 161 omap3_cm_idlest1_core:
 162         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
 163 omap3_cm_iclken1_core:
 164         .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
 165 omap3_sdrc_rfr_ctrl:
 166         .word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
 167 omap3_sdrc_actim_ctrla:
 168         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
 169 omap3_sdrc_actim_ctrlb:
 170         .word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
 171 omap3_sdrc_dlla_status:
 172         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
 173 omap3_sdrc_dlla_ctrl:
 174         .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
 175 core_m2_mask_val:
 176         .word 0x07FFFFFF
 177
 178 ENTRY(omap3_sram_configure_core_dpll_sz)
 179         .word   . - omap3_sram_configure_core_dpll