arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_reg.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/delay.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/slab.h>
  28 #include <linux/serial_8250.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/console.h>
  31
  32 #ifdef CONFIG_SERIAL_OMAP
  33 #include <plat/omap-serial.h>
  34 #endif
  35
  36 #include <plat/common.h>
  37 #include <plat/board.h>
  38 #include <plat/clock.h>
  39 #include <plat/dma.h>
  40 #include <plat/omap_hwmod.h>
  41 #include <plat/omap_device.h>
  42
  43 #include "prm2xxx_3xxx.h"
  44 #include "pm.h"
  45 #include "cm2xxx_3xxx.h"
  46 #include "prm-regbits-34xx.h"
  47 #include "control.h"
  48 #include "mux.h"
  49
  50 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  51 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  52
  53 #define UART_ERRATA_FIFO_FULL_ABORT     (0x1 << 0)
  54 #define UART_ERRATA_i202_MDR1_ACCESS    (0x1 << 1)
  55
  56 /*
  57  * NOTE: By default the serial timeout is disabled as it causes lost characters
  58  * over the serial ports. This means that the UART clocks will stay on until
  59  * disabled via sysfs. This also causes that any deeper omap sleep states are
  60  * blocked.
  61  */
  62 #define DEFAULT_TIMEOUT (10 * HZ)
  63
  64 #define MAX_UART_HWMOD_NAME_LEN         16
  65
  66 struct omap_uart_state {
  67         int num;
  68         int can_sleep;
  69         struct timer_list timer;
  70         u32 timeout;
  71
  72         void __iomem *wk_st;
  73         void __iomem *wk_en;
  74         u32 wk_mask;
  75         u32 padconf;
  76         u32 padconf2;
  77         u32 dma_enabled;
  78
  79         struct clk *ick;
  80         struct clk *fck;
  81         int clocked;
  82
  83         int irq;
  84         int regshift;
  85         int irqflags;
  86         void __iomem *membase;
  87         resource_size_t mapbase;
  88
  89         struct list_head node;
  90         struct omap_hwmod *oh;
  91         struct platform_device *pdev;
  92
  93         u32 errata;
  94 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  95         int context_valid;
  96
  97         /* Registers to be saved/restored for OFF-mode */
  98         u16 dll;
  99         u16 dlh;
 100         u16 ier;
 101         u16 sysc;
 102         u16 scr;
 103         u16 wer;
 104         u16 mcr;
 105 #endif
 106 };
 107
 108 static LIST_HEAD(uart_list);
 109 static u8 num_uarts;
 110
 111 static inline unsigned int __serial_read_reg(struct uart_port *up,
 112                                              int offset)
 113 {
 114         offset <<= up->regshift;
 115         return (unsigned int)__raw_readb(up->membase + offset);
 116 }
 117
 118 static inline unsigned int serial_read_reg(struct omap_uart_state *uart,
 119                                            int offset)
 120 {
 121         offset <<= uart->regshift;
 122         return (unsigned int)__raw_readb(uart->membase + offset);
 123 }
 124
 125 static inline void __serial_write_reg(struct uart_port *up, int offset,
 126                 int value)
 127 {
 128         offset <<= up->regshift;
 129         __raw_writeb(value, up->membase + offset);
 130 }
 131
 132 static inline void serial_write_reg(struct omap_uart_state *uart, int offset,
 133                                     int value)
 134 {
 135         offset <<= uart->regshift;
 136         __raw_writeb(value, uart->membase + offset);
 137 }
 138
 139 /*
 140  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 141  * properly. Note that the TX watermark initialization may not be needed
 142  * once the 8250.c watermark handling code is merged.
 143  */
 144
 145 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 146 {
 147         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 148         serial_write_reg(uart, UART_OMAP_SCR, 0x08);
 149         serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
 150 }
 151
 152 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 153
 154 /*
 155  * Work Around for Errata i202 (3430 - 1.12, 3630 - 1.6)
 156  * The access to uart register after MDR1 Access
 157  * causes UART to corrupt data.
 158  *
 159  * Need a delay =
 160  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 161  * give 10 times as much
 162  */
 163 static void omap_uart_mdr1_errataset(struct omap_uart_state *uart, u8 mdr1_val,
 164                 u8 fcr_val)
 165 {
 166         u8 timeout = 255;
 167
 168         serial_write_reg(uart, UART_OMAP_MDR1, mdr1_val);
 169         udelay(2);
 170         serial_write_reg(uart, UART_FCR, fcr_val | UART_FCR_CLEAR_XMIT |
 171                         UART_FCR_CLEAR_RCVR);
 172         /*
 173          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 174          * TX_FIFO_E bit is 1.
 175          */
 176         while (UART_LSR_THRE != (serial_read_reg(uart, UART_LSR) &
 177                                 (UART_LSR_THRE | UART_LSR_DR))) {
 178                 timeout--;
 179                 if (!timeout) {
 180                         /* Should *never* happen. we warn and carry on */
 181                         dev_crit(&uart->pdev->dev, "Errata i202: timedout %x\n",
 182                         serial_read_reg(uart, UART_LSR));
 183                         break;
 184                 }
 185                 udelay(1);
 186         }
 187 }
 188
 189 static void omap_uart_save_context(struct omap_uart_state *uart)
 190 {
 191         u16 lcr = 0;
 192
 193         if (!enable_off_mode)
 194                 return;
 195
 196         lcr = serial_read_reg(uart, UART_LCR);
 197         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 198         uart->dll = serial_read_reg(uart, UART_DLL);
 199         uart->dlh = serial_read_reg(uart, UART_DLM);
 200         serial_write_reg(uart, UART_LCR, lcr);
 201         uart->ier = serial_read_reg(uart, UART_IER);
 202         uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC);
 203         uart->scr = serial_read_reg(uart, UART_OMAP_SCR);
 204         uart->wer = serial_read_reg(uart, UART_OMAP_WER);
 205         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 206         uart->mcr = serial_read_reg(uart, UART_MCR);
 207         serial_write_reg(uart, UART_LCR, lcr);
 208
 209         uart->context_valid = 1;
 210 }
 211
 212 static void omap_uart_restore_context(struct omap_uart_state *uart)
 213 {
 214         u16 efr = 0;
 215
 216         if (!enable_off_mode)
 217                 return;
 218
 219         if (!uart->context_valid)
 220                 return;
 221
 222         uart->context_valid = 0;
 223
 224         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 225                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0);
 226         else
 227                 serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
 228
 229         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 230         efr = serial_read_reg(uart, UART_EFR);
 231         serial_write_reg(uart, UART_EFR, UART_EFR_ECB);
 232         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 233         serial_write_reg(uart, UART_IER, 0x0);
 234         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 235         serial_write_reg(uart, UART_DLL, uart->dll);
 236         serial_write_reg(uart, UART_DLM, uart->dlh);
 237         serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */
 238         serial_write_reg(uart, UART_IER, uart->ier);
 239         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A);
 240         serial_write_reg(uart, UART_MCR, uart->mcr);
 241         serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B);
 242         serial_write_reg(uart, UART_EFR, efr);
 243         serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8);
 244         serial_write_reg(uart, UART_OMAP_SCR, uart->scr);
 245         serial_write_reg(uart, UART_OMAP_WER, uart->wer);
 246         serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc);
 247
 248         if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS)
 249                 omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1);
 250         else
 251                 /* UART 16x mode */
 252                 serial_write_reg(uart, UART_OMAP_MDR1,
 253                                 UART_OMAP_MDR1_16X_MODE);
 254 }
 255 #else
 256 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 257 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 258 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 259
 260 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 261 {
 262         if (uart->clocked)
 263                 return;
 264
 265         omap_device_enable(uart->pdev);
 266         uart->clocked = 1;
 267         omap_uart_restore_context(uart);
 268 }
 269
 270 #ifdef CONFIG_PM
 271
 272 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 273 {
 274         if (!uart->clocked)
 275                 return;
 276
 277         omap_uart_save_context(uart);
 278         uart->clocked = 0;
 279         omap_device_idle(uart->pdev);
 280 }
 281
 282 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 283 {
 284         /* Set wake-enable bit */
 285         if (uart->wk_en && uart->wk_mask) {
 286                 u32 v = __raw_readl(uart->wk_en);
 287                 v |= uart->wk_mask;
 288                 __raw_writel(v, uart->wk_en);
 289         }
 290
 291         /* Ensure IOPAD wake-enables are set */
 292         if (cpu_is_omap34xx()) {
 293                 if (uart->padconf) {
 294                         u16 v = omap_ctrl_readw(uart->padconf);
 295                         v |= OMAP3_PADCONF_WAKEUPENABLE0;
 296                         omap_ctrl_writew(v, uart->padconf);
 297                 }
 298                 if (uart->padconf2) {
 299                         u16 v = omap_ctrl_readw(uart->padconf2);
 300                         v |= OMAP3_PADCONF_WAKEUPENABLE0;
 301                         omap_ctrl_writew(v, uart->padconf2);
 302                 }
 303         }
 304 }
 305
 306 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 307 {
 308         /* Clear wake-enable bit */
 309         if (uart->wk_en && uart->wk_mask) {
 310                 u32 v = __raw_readl(uart->wk_en);
 311                 v &= ~uart->wk_mask;
 312                 __raw_writel(v, uart->wk_en);
 313         }
 314
 315         /* Ensure IOPAD wake-enables are cleared */
 316         if (cpu_is_omap34xx()) {
 317                 if (uart->padconf) {
 318                         u16 v = omap_ctrl_readw(uart->padconf);
 319                         v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 320                         omap_ctrl_writew(v, uart->padconf);
 321                 }
 322                 if (uart->padconf2) {
 323                         u16 v = omap_ctrl_readw(uart->padconf2);
 324                         v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 325                         omap_ctrl_writew(v, uart->padconf2);
 326                 }
 327         }
 328 }
 329
 330 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 331                                                int enable)
 332 {
 333         u8 idlemode;
 334
 335         if (enable) {
 336                 /**
 337                  * Errata 2.15: [UART]:Cannot Acknowledge Idle Requests
 338                  * in Smartidle Mode When Configured for DMA Operations.
 339                  */
 340                 if (uart->dma_enabled)
 341                         idlemode = HWMOD_IDLEMODE_FORCE;
 342                 else
 343                         idlemode = HWMOD_IDLEMODE_SMART;
 344         } else {
 345                 idlemode = HWMOD_IDLEMODE_NO;
 346         }
 347
 348         omap_hwmod_set_slave_idlemode(uart->oh, idlemode);
 349 }
 350
 351 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 352 {
 353         omap_uart_enable_clocks(uart);
 354
 355         omap_uart_smart_idle_enable(uart, 0);
 356         uart->can_sleep = 0;
 357         if (uart->timeout)
 358                 mod_timer(&uart->timer, jiffies + uart->timeout);
 359         else
 360                 del_timer(&uart->timer);
 361 }
 362
 363 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 364 {
 365         if (device_may_wakeup(&uart->pdev->dev))
 366                 omap_uart_enable_wakeup(uart);
 367         else
 368                 omap_uart_disable_wakeup(uart);
 369
 370         if (!uart->clocked)
 371                 return;
 372
 373         omap_uart_smart_idle_enable(uart, 1);
 374         uart->can_sleep = 1;
 375         del_timer(&uart->timer);
 376 }
 377
 378 static void omap_uart_idle_timer(unsigned long data)
 379 {
 380         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 381
 382         omap_uart_allow_sleep(uart);
 383 }
 384
 385 void omap_uart_prepare_idle(int num)
 386 {
 387         struct omap_uart_state *uart;
 388
 389         list_for_each_entry(uart, &uart_list, node) {
 390                 if (num == uart->num && uart->can_sleep) {
 391                         omap_uart_disable_clocks(uart);
 392                         return;
 393                 }
 394         }
 395 }
 396
 397 void omap_uart_resume_idle(int num)
 398 {
 399         struct omap_uart_state *uart;
 400
 401         list_for_each_entry(uart, &uart_list, node) {
 402                 if (num == uart->num && uart->can_sleep) {
 403                         omap_uart_enable_clocks(uart);
 404
 405                         /* Check for IO pad wakeup */
 406                         if (cpu_is_omap34xx()) {
 407                                 u16 p = 0;
 408                                 if (uart->padconf)
 409                                         p |= omap_ctrl_readw(uart->padconf);
 410                                 if (uart->padconf2)
 411                                         p |= omap_ctrl_readw(uart->padconf2);
 412
 413                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 414                                         omap_uart_block_sleep(uart);
 415                         }
 416
 417                         /* Check for normal UART wakeup */
 418                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 419                                 omap_uart_block_sleep(uart);
 420                         return;
 421                 }
 422         }
 423 }
 424
 425 void omap_uart_prepare_suspend(void)
 426 {
 427         struct omap_uart_state *uart;
 428
 429         list_for_each_entry(uart, &uart_list, node) {
 430                 omap_uart_allow_sleep(uart);
 431         }
 432 }
 433
 434 int omap_uart_can_sleep(void)
 435 {
 436         struct omap_uart_state *uart;
 437         int can_sleep = 1;
 438
 439         list_for_each_entry(uart, &uart_list, node) {
 440                 if (!uart->clocked)
 441                         continue;
 442
 443                 if (!uart->can_sleep) {
 444                         can_sleep = 0;
 445                         continue;
 446                 }
 447
 448                 /* This UART can now safely sleep. */
 449                 omap_uart_allow_sleep(uart);
 450         }
 451
 452         return can_sleep;
 453 }
 454
 455 /**
 456  * omap_uart_interrupt()
 457  *
 458  * This handler is used only to detect that *any* UART interrupt has
 459  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 460  * any UART interrupt will trigger the inactivity timer so the
 461  * UART will not idle or sleep for its timeout period.
 462  *
 463  **/
 464 /* static int first_interrupt; */
 465 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 466 {
 467         struct omap_uart_state *uart = dev_id;
 468
 469         omap_uart_block_sleep(uart);
 470
 471         return IRQ_NONE;
 472 }
 473
 474 static void omap_uart_idle_init(struct omap_uart_state *uart)
 475 {
 476         int ret;
 477
 478         uart->can_sleep = 0;
 479         uart->timeout = DEFAULT_TIMEOUT;
 480         setup_timer(&uart->timer, omap_uart_idle_timer,
 481                     (unsigned long) uart);
 482         if (uart->timeout)
 483                 mod_timer(&uart->timer, jiffies + uart->timeout);
 484         omap_uart_smart_idle_enable(uart, 0);
 485
 486         if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
 487                 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD;
 488                 u32 wk_mask = 0;
 489                 u32 padconf = 0;
 490                 u32 padconf2 = 0;
 491
 492                 /* XXX These PRM accesses do not belong here */
 493                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 494                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 495                 switch (uart->num) {
 496                 case 0:
 497                         wk_mask = OMAP3430_ST_UART1_MASK;
 498                         padconf = 0x182;
 499                         padconf2 = 0x180;
 500                         break;
 501                 case 1:
 502                         wk_mask = OMAP3430_ST_UART2_MASK;
 503                         padconf = 0x17a;
 504                         break;
 505                 case 2:
 506                         wk_mask = OMAP3430_ST_UART3_MASK;
 507                         padconf = 0x19e;
 508                         break;
 509                 case 3:
 510                         wk_mask = OMAP3630_ST_UART4_MASK;
 511                         padconf = 0x0d2;
 512                         break;
 513                 }
 514                 uart->wk_mask = wk_mask;
 515                 uart->padconf = padconf;
 516                 uart->padconf2 = padconf2;
 517         } else if (cpu_is_omap24xx()) {
 518                 u32 wk_mask = 0;
 519                 u32 wk_en = PM_WKEN1, wk_st = PM_WKST1;
 520
 521                 switch (uart->num) {
 522                 case 0:
 523                         wk_mask = OMAP24XX_ST_UART1_MASK;
 524                         break;
 525                 case 1:
 526                         wk_mask = OMAP24XX_ST_UART2_MASK;
 527                         break;
 528                 case 2:
 529                         wk_en = OMAP24XX_PM_WKEN2;
 530                         wk_st = OMAP24XX_PM_WKST2;
 531                         wk_mask = OMAP24XX_ST_UART3_MASK;
 532                         break;
 533                 }
 534                 uart->wk_mask = wk_mask;
 535                 if (cpu_is_omap2430()) {
 536                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en);
 537                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st);
 538                 } else if (cpu_is_omap2420()) {
 539                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en);
 540                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st);
 541                 }
 542         } else {
 543                 uart->wk_en = NULL;
 544                 uart->wk_st = NULL;
 545                 uart->wk_mask = 0;
 546                 uart->padconf = 0;
 547                 uart->padconf2 = 0;
 548         }
 549
 550         uart->irqflags |= IRQF_SHARED;
 551         ret = request_threaded_irq(uart->irq, NULL, omap_uart_interrupt,
 552                                    IRQF_SHARED, "serial idle", (void *)uart);
 553         WARN_ON(ret);
 554 }
 555
 556 void omap_uart_enable_irqs(int enable)
 557 {
 558         int ret;
 559         struct omap_uart_state *uart;
 560
 561         list_for_each_entry(uart, &uart_list, node) {
 562                 if (enable) {
 563                         pm_runtime_put_sync(&uart->pdev->dev);
 564                         ret = request_threaded_irq(uart->irq, NULL,
 565                                                    omap_uart_interrupt,
 566                                                    IRQF_SHARED,
 567                                                    "serial idle",
 568                                                    (void *)uart);
 569                 } else {
 570                         pm_runtime_get_noresume(&uart->pdev->dev);
 571                         free_irq(uart->irq, (void *)uart);
 572                 }
 573         }
 574 }
 575
 576 static ssize_t sleep_timeout_show(struct device *dev,
 577                                   struct device_attribute *attr,
 578                                   char *buf)
 579 {
 580         struct platform_device *pdev = to_platform_device(dev);
 581         struct omap_device *odev = to_omap_device(pdev);
 582         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 583
 584         return sprintf(buf, "%u\n", uart->timeout / HZ);
 585 }
 586
 587 static ssize_t sleep_timeout_store(struct device *dev,
 588                                    struct device_attribute *attr,
 589                                    const char *buf, size_t n)
 590 {
 591         struct platform_device *pdev = to_platform_device(dev);
 592         struct omap_device *odev = to_omap_device(pdev);
 593         struct omap_uart_state *uart = odev->hwmods[0]->dev_attr;
 594         unsigned int value;
 595
 596         if (sscanf(buf, "%u", &value) != 1) {
 597                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
 598                 return -EINVAL;
 599         }
 600
 601         uart->timeout = value * HZ;
 602         if (uart->timeout)
 603                 mod_timer(&uart->timer, jiffies + uart->timeout);
 604         else
 605                 /* A zero value means disable timeout feature */
 606                 omap_uart_block_sleep(uart);
 607
 608         return n;
 609 }
 610
 611 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 612                 sleep_timeout_store);
 613 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 614 #else
 615 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 616 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 617 {
 618         /* Needed to enable UART clocks when built without CONFIG_PM */
 619         omap_uart_enable_clocks(uart);
 620 }
 621 #define DEV_CREATE_FILE(dev, attr)
 622 #endif /* CONFIG_PM */
 623
 624 #ifndef CONFIG_SERIAL_OMAP
 625 /*
 626  * Override the default 8250 read handler: mem_serial_in()
 627  * Empty RX fifo read causes an abort on omap3630 and omap4
 628  * This function makes sure that an empty rx fifo is not read on these silicons
 629  * (OMAP1/2/3430 are not affected)
 630  */
 631 static unsigned int serial_in_override(struct uart_port *up, int offset)
 632 {
 633         if (UART_RX == offset) {
 634                 unsigned int lsr;
 635                 lsr = __serial_read_reg(up, UART_LSR);
 636                 if (!(lsr & UART_LSR_DR))
 637                         return -EPERM;
 638         }
 639
 640         return __serial_read_reg(up, offset);
 641 }
 642
 643 static void serial_out_override(struct uart_port *up, int offset, int value)
 644 {
 645         unsigned int status, tmout = 10000;
 646
 647         status = __serial_read_reg(up, UART_LSR);
 648         while (!(status & UART_LSR_THRE)) {
 649                 /* Wait up to 10ms for the character(s) to be sent. */
 650                 if (--tmout == 0)
 651                         break;
 652                 udelay(1);
 653                 status = __serial_read_reg(up, UART_LSR);
 654         }
 655         __serial_write_reg(up, offset, value);
 656 }
 657 #endif
 658
 659 static int __init omap_serial_early_init(void)
 660 {
 661         int i = 0;
 662
 663         do {
 664                 char oh_name[MAX_UART_HWMOD_NAME_LEN];
 665                 struct omap_hwmod *oh;
 666                 struct omap_uart_state *uart;
 667
 668                 snprintf(oh_name, MAX_UART_HWMOD_NAME_LEN,
 669                          "uart%d", i + 1);
 670                 oh = omap_hwmod_lookup(oh_name);
 671                 if (!oh)
 672                         break;
 673
 674                 uart = kzalloc(sizeof(struct omap_uart_state), GFP_KERNEL);
 675                 if (WARN_ON(!uart))
 676                         return -ENODEV;
 677
 678                 uart->oh = oh;
 679                 uart->num = i++;
 680                 list_add_tail(&uart->node, &uart_list);
 681                 num_uarts++;
 682
 683                 /*
 684                  * NOTE: omap_hwmod_setup*() has not yet been called,
 685                  *       so no hwmod functions will work yet.
 686                  */
 687
 688                 /*
 689                  * During UART early init, device need to be probed
 690                  * to determine SoC specific init before omap_device
 691                  * is ready.  Therefore, don't allow idle here
 692                  */
 693                 uart->oh->flags |= HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET;
 694         } while (1);
 695
 696         return 0;
 697 }
 698 core_initcall(omap_serial_early_init);
 699
 700 /**
 701  * omap_serial_init_port() - initialize single serial port
 702  * @bdata: port specific board data pointer
 703  *
 704  * This function initialies serial driver for given port only.
 705  * Platforms can call this function instead of omap_serial_init()
 706  * if they don't plan to use all available UARTs as serial ports.
 707  *
 708  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 709  * use only one of the two.
 710  */
 711 void __init omap_serial_init_port(struct omap_board_data *bdata)
 712 {
 713         struct omap_uart_state *uart;
 714         struct omap_hwmod *oh;
 715         struct platform_device *pdev;
 716         void *pdata = NULL;
 717         u32 pdata_size = 0;
 718         char *name;
 719 #ifndef CONFIG_SERIAL_OMAP
 720         struct plat_serial8250_port ports[2] = {
 721                 {},
 722                 {.flags = 0},
 723         };
 724         struct plat_serial8250_port *p = &ports[0];
 725 #else
 726         struct omap_uart_port_info omap_up;
 727 #endif
 728
 729         if (WARN_ON(!bdata))
 730                 return;
 731         if (WARN_ON(bdata->id < 0))
 732                 return;
 733         if (WARN_ON(bdata->id >= num_uarts))
 734                 return;
 735
 736         list_for_each_entry(uart, &uart_list, node)
 737                 if (bdata->id == uart->num)
 738                         break;
 739
 740         oh = uart->oh;
 741         uart->dma_enabled = 0;
 742 #ifndef CONFIG_SERIAL_OMAP
 743         name = "serial8250";
 744
 745         /*
 746          * !! 8250 driver does not use standard IORESOURCE* It
 747          * has it's own custom pdata that can be taken from
 748          * the hwmod resource data.  But, this needs to be
 749          * done after the build.
 750          *
 751          * ?? does it have to be done before the register ??
 752          * YES, because platform_device_data_add() copies
 753          * pdata, it does not use a pointer.
 754          */
 755         p->flags = UPF_BOOT_AUTOCONF;
 756         p->iotype = UPIO_MEM;
 757         p->regshift = 2;
 758         p->uartclk = OMAP24XX_BASE_BAUD * 16;
 759         p->irq = oh->mpu_irqs[0].irq;
 760         p->mapbase = oh->slaves[0]->addr->pa_start;
 761         p->membase = omap_hwmod_get_mpu_rt_va(oh);
 762         p->irqflags = IRQF_SHARED;
 763         p->private_data = uart;
 764
 765         /*
 766          * omap44xx, ti816x: Never read empty UART fifo
 767          * omap3xxx: Never read empty UART fifo on UARTs
 768          * with IP rev >=0x52
 769          */
 770         uart->regshift = p->regshift;
 771         uart->membase = p->membase;
 772         if (cpu_is_omap44xx() || cpu_is_ti816x())
 773                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 774         else if ((serial_read_reg(uart, UART_OMAP_MVER) & 0xFF)
 775                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV)
 776                 uart->errata |= UART_ERRATA_FIFO_FULL_ABORT;
 777
 778         if (uart->errata & UART_ERRATA_FIFO_FULL_ABORT) {
 779                 p->serial_in = serial_in_override;
 780                 p->serial_out = serial_out_override;
 781         }
 782
 783         pdata = &ports[0];
 784         pdata_size = 2 * sizeof(struct plat_serial8250_port);
 785 #else
 786
 787         name = DRIVER_NAME;
 788
 789         omap_up.dma_enabled = uart->dma_enabled;
 790         omap_up.uartclk = OMAP24XX_BASE_BAUD * 16;
 791         omap_up.mapbase = oh->slaves[0]->addr->pa_start;
 792         omap_up.membase = omap_hwmod_get_mpu_rt_va(oh);
 793         omap_up.irqflags = IRQF_SHARED;
 794         omap_up.flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
 795
 796         pdata = &omap_up;
 797         pdata_size = sizeof(struct omap_uart_port_info);
 798 #endif
 799
 800         if (WARN_ON(!oh))
 801                 return;
 802
 803         pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
 804                                  NULL, 0, false);
 805         WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
 806              name, oh->name);
 807
 808         omap_device_disable_idle_on_suspend(pdev);
 809         oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
 810
 811         uart->irq = oh->mpu_irqs[0].irq;
 812         uart->regshift = 2;
 813         uart->mapbase = oh->slaves[0]->addr->pa_start;
 814         uart->membase = omap_hwmod_get_mpu_rt_va(oh);
 815         uart->pdev = pdev;
 816
 817         oh->dev_attr = uart;
 818
 819         console_lock(); /* in case the earlycon is on the UART */
 820
 821         /*
 822          * Because of early UART probing, UART did not get idled
 823          * on init.  Now that omap_device is ready, ensure full idle
 824          * before doing omap_device_enable().
 825          */
 826         omap_hwmod_idle(uart->oh);
 827
 828         omap_device_enable(uart->pdev);
 829         omap_uart_idle_init(uart);
 830         omap_uart_reset(uart);
 831         omap_hwmod_enable_wakeup(uart->oh);
 832         omap_device_idle(uart->pdev);
 833
 834         /*
 835          * Need to block sleep long enough for interrupt driven
 836          * driver to start.  Console driver is in polling mode
 837          * so device needs to be kept enabled while polling driver
 838          * is in use.
 839          */
 840         if (uart->timeout)
 841                 uart->timeout = (30 * HZ);
 842         omap_uart_block_sleep(uart);
 843         uart->timeout = DEFAULT_TIMEOUT;
 844
 845         console_unlock();
 846
 847         if ((cpu_is_omap34xx() && (uart->padconf || uart->padconf2)) ||
 848             (uart->wk_en && uart->wk_mask)) {
 849                 device_init_wakeup(&pdev->dev, true);
 850                 DEV_CREATE_FILE(&pdev->dev, &dev_attr_sleep_timeout);
 851         }
 852
 853         /* Enable the MDR1 errata for OMAP3 */
 854         if (cpu_is_omap34xx() && !cpu_is_ti816x())
 855                 uart->errata |= UART_ERRATA_i202_MDR1_ACCESS;
 856 }
 857
 858 /**
 859  * omap_serial_init() - initialize all supported serial ports
 860  *
 861  * Initializes all available UARTs as serial ports. Platforms
 862  * can call this function when they want to have default behaviour
 863  * for serial ports (e.g initialize them all as serial ports).
 864  */
 865 void __init omap_serial_init(void)
 866 {
 867         struct omap_uart_state *uart;
 868         struct omap_board_data bdata;
 869
 870         list_for_each_entry(uart, &uart_list, node) {
 871                 bdata.id = uart->num;
 872                 bdata.flags = 0;
 873                 bdata.pads = NULL;
 874                 bdata.pads_cnt = 0;
 875                 omap_serial_init_port(&bdata);
 876
 877         }
 878 }