arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_8250.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/delay.h>
  27
  28 #include <plat/common.h>
  29 #include <plat/board.h>
  30 #include <plat/clock.h>
  31 #include <plat/control.h>
  32
  33 #include "prm.h"
  34 #include "pm.h"
  35 #include "prm-regbits-34xx.h"
  36
  37 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  38 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  39
  40 /*
  41  * NOTE: By default the serial timeout is disabled as it causes lost characters
  42  * over the serial ports. This means that the UART clocks will stay on until
  43  * disabled via sysfs. This also causes that any deeper omap sleep states are
  44  * blocked.
  45  */
  46 #define DEFAULT_TIMEOUT 0
  47
  48 struct omap_uart_state {
  49         int num;
  50         int can_sleep;
  51         struct timer_list timer;
  52         u32 timeout;
  53
  54         void __iomem *wk_st;
  55         void __iomem *wk_en;
  56         u32 wk_mask;
  57         u32 padconf;
  58
  59         struct clk *ick;
  60         struct clk *fck;
  61         int clocked;
  62
  63         struct plat_serial8250_port *p;
  64         struct list_head node;
  65         struct platform_device pdev;
  66
  67 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  68         int context_valid;
  69
  70         /* Registers to be saved/restored for OFF-mode */
  71         u16 dll;
  72         u16 dlh;
  73         u16 ier;
  74         u16 sysc;
  75         u16 scr;
  76         u16 wer;
  77         u16 mcr;
  78 #endif
  79 };
  80
  81 static LIST_HEAD(uart_list);
  82
  83 static struct plat_serial8250_port serial_platform_data0[] = {
  84         {
  85                 .irq            = 72,
  86                 .flags          = UPF_BOOT_AUTOCONF,
  87                 .iotype         = UPIO_MEM,
  88                 .regshift       = 2,
  89                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  90         }, {
  91                 .flags          = 0
  92         }
  93 };
  94
  95 static struct plat_serial8250_port serial_platform_data1[] = {
  96         {
  97                 .irq            = 73,
  98                 .flags          = UPF_BOOT_AUTOCONF,
  99                 .iotype         = UPIO_MEM,
 100                 .regshift       = 2,
 101                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 102         }, {
 103                 .flags          = 0
 104         }
 105 };
 106
 107 static struct plat_serial8250_port serial_platform_data2[] = {
 108         {
 109                 .irq            = 74,
 110                 .flags          = UPF_BOOT_AUTOCONF,
 111                 .iotype         = UPIO_MEM,
 112                 .regshift       = 2,
 113                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 114         }, {
 115                 .flags          = 0
 116         }
 117 };
 118
 119 static struct plat_serial8250_port serial_platform_data3[] = {
 120         {
 121                 .irq            = 70,
 122                 .flags          = UPF_BOOT_AUTOCONF,
 123                 .iotype         = UPIO_MEM,
 124                 .regshift       = 2,
 125                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 126         }, {
 127                 .flags          = 0
 128         }
 129 };
 130
 131 void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
 132 {
 133         serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
 134         serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
 135         serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
 136         serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
 137 }
 138
 139 static inline unsigned int __serial_read_reg(struct uart_port *up,
 140                                            int offset)
 141 {
 142         offset <<= up->regshift;
 143         return (unsigned int)__raw_readb(up->membase + offset);
 144 }
 145
 146 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 147                                            int offset)
 148 {
 149         offset <<= up->regshift;
 150         return (unsigned int)__raw_readb(up->membase + offset);
 151 }
 152
 153 static inline void __serial_write_reg(struct uart_port *up, int offset,
 154                 int value)
 155 {
 156         offset <<= up->regshift;
 157         __raw_writeb(value, up->membase + offset);
 158 }
 159
 160 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 161                                     int value)
 162 {
 163         offset <<= p->regshift;
 164         __raw_writeb(value, p->membase + offset);
 165 }
 166
 167 /*
 168  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 169  * properly. Note that the TX watermark initialization may not be needed
 170  * once the 8250.c watermark handling code is merged.
 171  */
 172 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 173 {
 174         struct plat_serial8250_port *p = uart->p;
 175
 176         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
 177         serial_write_reg(p, UART_OMAP_SCR, 0x08);
 178         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
 179         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 180 }
 181
 182 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 183
 184 static void omap_uart_save_context(struct omap_uart_state *uart)
 185 {
 186         u16 lcr = 0;
 187         struct plat_serial8250_port *p = uart->p;
 188
 189         if (!enable_off_mode)
 190                 return;
 191
 192         lcr = serial_read_reg(p, UART_LCR);
 193         serial_write_reg(p, UART_LCR, 0xBF);
 194         uart->dll = serial_read_reg(p, UART_DLL);
 195         uart->dlh = serial_read_reg(p, UART_DLM);
 196         serial_write_reg(p, UART_LCR, lcr);
 197         uart->ier = serial_read_reg(p, UART_IER);
 198         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
 199         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
 200         uart->wer = serial_read_reg(p, UART_OMAP_WER);
 201         serial_write_reg(p, UART_LCR, 0x80);
 202         uart->mcr = serial_read_reg(p, UART_MCR);
 203         serial_write_reg(p, UART_LCR, lcr);
 204
 205         uart->context_valid = 1;
 206 }
 207
 208 static void omap_uart_restore_context(struct omap_uart_state *uart)
 209 {
 210         u16 efr = 0;
 211         struct plat_serial8250_port *p = uart->p;
 212
 213         if (!enable_off_mode)
 214                 return;
 215
 216         if (!uart->context_valid)
 217                 return;
 218
 219         uart->context_valid = 0;
 220
 221         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
 222         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 223         efr = serial_read_reg(p, UART_EFR);
 224         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
 225         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 226         serial_write_reg(p, UART_IER, 0x0);
 227         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 228         serial_write_reg(p, UART_DLL, uart->dll);
 229         serial_write_reg(p, UART_DLM, uart->dlh);
 230         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 231         serial_write_reg(p, UART_IER, uart->ier);
 232         serial_write_reg(p, UART_LCR, 0x80);
 233         serial_write_reg(p, UART_MCR, uart->mcr);
 234         serial_write_reg(p, UART_FCR, 0xA1);
 235         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 236         serial_write_reg(p, UART_EFR, efr);
 237         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
 238         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
 239         serial_write_reg(p, UART_OMAP_WER, uart->wer);
 240         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
 241         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
 242 }
 243 #else
 244 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 245 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 246 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 247
 248 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 249 {
 250         if (uart->clocked)
 251                 return;
 252
 253         clk_enable(uart->ick);
 254         clk_enable(uart->fck);
 255         uart->clocked = 1;
 256         omap_uart_restore_context(uart);
 257 }
 258
 259 #ifdef CONFIG_PM
 260
 261 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 262 {
 263         if (!uart->clocked)
 264                 return;
 265
 266         omap_uart_save_context(uart);
 267         uart->clocked = 0;
 268         clk_disable(uart->ick);
 269         clk_disable(uart->fck);
 270 }
 271
 272 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 273 {
 274         /* Set wake-enable bit */
 275         if (uart->wk_en && uart->wk_mask) {
 276                 u32 v = __raw_readl(uart->wk_en);
 277                 v |= uart->wk_mask;
 278                 __raw_writel(v, uart->wk_en);
 279         }
 280
 281         /* Ensure IOPAD wake-enables are set */
 282         if (cpu_is_omap34xx() && uart->padconf) {
 283                 u16 v = omap_ctrl_readw(uart->padconf);
 284                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 285                 omap_ctrl_writew(v, uart->padconf);
 286         }
 287 }
 288
 289 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 290 {
 291         /* Clear wake-enable bit */
 292         if (uart->wk_en && uart->wk_mask) {
 293                 u32 v = __raw_readl(uart->wk_en);
 294                 v &= ~uart->wk_mask;
 295                 __raw_writel(v, uart->wk_en);
 296         }
 297
 298         /* Ensure IOPAD wake-enables are cleared */
 299         if (cpu_is_omap34xx() && uart->padconf) {
 300                 u16 v = omap_ctrl_readw(uart->padconf);
 301                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 302                 omap_ctrl_writew(v, uart->padconf);
 303         }
 304 }
 305
 306 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 307                                           int enable)
 308 {
 309         struct plat_serial8250_port *p = uart->p;
 310         u16 sysc;
 311
 312         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
 313         if (enable)
 314                 sysc |= 0x2 << 3;
 315         else
 316                 sysc |= 0x1 << 3;
 317
 318         serial_write_reg(p, UART_OMAP_SYSC, sysc);
 319 }
 320
 321 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 322 {
 323         omap_uart_enable_clocks(uart);
 324
 325         omap_uart_smart_idle_enable(uart, 0);
 326         uart->can_sleep = 0;
 327         if (uart->timeout)
 328                 mod_timer(&uart->timer, jiffies + uart->timeout);
 329         else
 330                 del_timer(&uart->timer);
 331 }
 332
 333 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 334 {
 335         if (device_may_wakeup(&uart->pdev.dev))
 336                 omap_uart_enable_wakeup(uart);
 337         else
 338                 omap_uart_disable_wakeup(uart);
 339
 340         if (!uart->clocked)
 341                 return;
 342
 343         omap_uart_smart_idle_enable(uart, 1);
 344         uart->can_sleep = 1;
 345         del_timer(&uart->timer);
 346 }
 347
 348 static void omap_uart_idle_timer(unsigned long data)
 349 {
 350         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 351
 352         omap_uart_allow_sleep(uart);
 353 }
 354
 355 void omap_uart_prepare_idle(int num)
 356 {
 357         struct omap_uart_state *uart;
 358
 359         list_for_each_entry(uart, &uart_list, node) {
 360                 if (num == uart->num && uart->can_sleep) {
 361                         omap_uart_disable_clocks(uart);
 362                         return;
 363                 }
 364         }
 365 }
 366
 367 void omap_uart_resume_idle(int num)
 368 {
 369         struct omap_uart_state *uart;
 370
 371         list_for_each_entry(uart, &uart_list, node) {
 372                 if (num == uart->num) {
 373                         omap_uart_enable_clocks(uart);
 374
 375                         /* Check for IO pad wakeup */
 376                         if (cpu_is_omap34xx() && uart->padconf) {
 377                                 u16 p = omap_ctrl_readw(uart->padconf);
 378
 379                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 380                                         omap_uart_block_sleep(uart);
 381                         }
 382
 383                         /* Check for normal UART wakeup */
 384                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 385                                 omap_uart_block_sleep(uart);
 386                         return;
 387                 }
 388         }
 389 }
 390
 391 void omap_uart_prepare_suspend(void)
 392 {
 393         struct omap_uart_state *uart;
 394
 395         list_for_each_entry(uart, &uart_list, node) {
 396                 omap_uart_allow_sleep(uart);
 397         }
 398 }
 399
 400 int omap_uart_can_sleep(void)
 401 {
 402         struct omap_uart_state *uart;
 403         int can_sleep = 1;
 404
 405         list_for_each_entry(uart, &uart_list, node) {
 406                 if (!uart->clocked)
 407                         continue;
 408
 409                 if (!uart->can_sleep) {
 410                         can_sleep = 0;
 411                         continue;
 412                 }
 413
 414                 /* This UART can now safely sleep. */
 415                 omap_uart_allow_sleep(uart);
 416         }
 417
 418         return can_sleep;
 419 }
 420
 421 /**
 422  * omap_uart_interrupt()
 423  *
 424  * This handler is used only to detect that *any* UART interrupt has
 425  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 426  * any UART interrupt will trigger the inactivity timer so the
 427  * UART will not idle or sleep for its timeout period.
 428  *
 429  **/
 430 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 431 {
 432         struct omap_uart_state *uart = dev_id;
 433
 434         omap_uart_block_sleep(uart);
 435
 436         return IRQ_NONE;
 437 }
 438
 439 static void omap_uart_idle_init(struct omap_uart_state *uart)
 440 {
 441         struct plat_serial8250_port *p = uart->p;
 442         int ret;
 443
 444         uart->can_sleep = 0;
 445         uart->timeout = DEFAULT_TIMEOUT;
 446         setup_timer(&uart->timer, omap_uart_idle_timer,
 447                     (unsigned long) uart);
 448         if (uart->timeout)
 449                 mod_timer(&uart->timer, jiffies + uart->timeout);
 450         omap_uart_smart_idle_enable(uart, 0);
 451
 452         if (cpu_is_omap34xx()) {
 453                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
 454                 u32 wk_mask = 0;
 455                 u32 padconf = 0;
 456
 457                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 458                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 459                 switch (uart->num) {
 460                 case 0:
 461                         wk_mask = OMAP3430_ST_UART1_MASK;
 462                         padconf = 0x182;
 463                         break;
 464                 case 1:
 465                         wk_mask = OMAP3430_ST_UART2_MASK;
 466                         padconf = 0x17a;
 467                         break;
 468                 case 2:
 469                         wk_mask = OMAP3430_ST_UART3_MASK;
 470                         padconf = 0x19e;
 471                         break;
 472                 }
 473                 uart->wk_mask = wk_mask;
 474                 uart->padconf = padconf;
 475         } else if (cpu_is_omap24xx()) {
 476                 u32 wk_mask = 0;
 477
 478                 if (cpu_is_omap2430()) {
 479                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 480                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
 481                 } else if (cpu_is_omap2420()) {
 482                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 483                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
 484                 }
 485                 switch (uart->num) {
 486                 case 0:
 487                         wk_mask = OMAP24XX_ST_UART1_MASK;
 488                         break;
 489                 case 1:
 490                         wk_mask = OMAP24XX_ST_UART2_MASK;
 491                         break;
 492                 case 2:
 493                         wk_mask = OMAP24XX_ST_UART3_MASK;
 494                         break;
 495                 }
 496                 uart->wk_mask = wk_mask;
 497         } else {
 498                 uart->wk_en = NULL;
 499                 uart->wk_st = NULL;
 500                 uart->wk_mask = 0;
 501                 uart->padconf = 0;
 502         }
 503
 504         p->irqflags |= IRQF_SHARED;
 505         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
 506                           "serial idle", (void *)uart);
 507         WARN_ON(ret);
 508 }
 509
 510 void omap_uart_enable_irqs(int enable)
 511 {
 512         int ret;
 513         struct omap_uart_state *uart;
 514
 515         list_for_each_entry(uart, &uart_list, node) {
 516                 if (enable)
 517                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
 518                                 IRQF_SHARED, "serial idle", (void *)uart);
 519                 else
 520                         free_irq(uart->p->irq, (void *)uart);
 521         }
 522 }
 523
 524 static ssize_t sleep_timeout_show(struct device *dev,
 525                                   struct device_attribute *attr,
 526                                   char *buf)
 527 {
 528         struct platform_device *pdev = container_of(dev,
 529                                         struct platform_device, dev);
 530         struct omap_uart_state *uart = container_of(pdev,
 531                                         struct omap_uart_state, pdev);
 532
 533         return sprintf(buf, "%u\n", uart->timeout / HZ);
 534 }
 535
 536 static ssize_t sleep_timeout_store(struct device *dev,
 537                                    struct device_attribute *attr,
 538                                    const char *buf, size_t n)
 539 {
 540         struct platform_device *pdev = container_of(dev,
 541                                         struct platform_device, dev);
 542         struct omap_uart_state *uart = container_of(pdev,
 543                                         struct omap_uart_state, pdev);
 544         unsigned int value;
 545
 546         if (sscanf(buf, "%u", &value) != 1) {
 547                 dev_err(dev, "sleep_timeout_store: Invalid value\n");
 548                 return -EINVAL;
 549         }
 550
 551         uart->timeout = value * HZ;
 552         if (uart->timeout)
 553                 mod_timer(&uart->timer, jiffies + uart->timeout);
 554         else
 555                 /* A zero value means disable timeout feature */
 556                 omap_uart_block_sleep(uart);
 557
 558         return n;
 559 }
 560
 561 static DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show,
 562                 sleep_timeout_store);
 563 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 564 #else
 565 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 566 #define DEV_CREATE_FILE(dev, attr)
 567 #endif /* CONFIG_PM */
 568
 569 static struct omap_uart_state omap_uart[] = {
 570         {
 571                 .pdev = {
 572                         .name                   = "serial8250",
 573                         .id                     = PLAT8250_DEV_PLATFORM,
 574                         .dev                    = {
 575                                 .platform_data  = serial_platform_data0,
 576                         },
 577                 },
 578         }, {
 579                 .pdev = {
 580                         .name                   = "serial8250",
 581                         .id                     = PLAT8250_DEV_PLATFORM1,
 582                         .dev                    = {
 583                                 .platform_data  = serial_platform_data1,
 584                         },
 585                 },
 586         }, {
 587                 .pdev = {
 588                         .name                   = "serial8250",
 589                         .id                     = PLAT8250_DEV_PLATFORM2,
 590                         .dev                    = {
 591                                 .platform_data  = serial_platform_data2,
 592                         },
 593                 },
 594         },
 595 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 596         {
 597                 .pdev = {
 598                         .name                   = "serial8250",
 599                         .id                     = 3,
 600                         .dev                    = {
 601                                 .platform_data  = serial_platform_data3,
 602                         },
 603                 },
 604         },
 605 #endif
 606 };
 607
 608 /*
 609  * Override the default 8250 read handler: mem_serial_in()
 610  * Empty RX fifo read causes an abort on omap3630 and omap4
 611  * This function makes sure that an empty rx fifo is not read on these silicons
 612  * (OMAP1/2/3430 are not affected)
 613  */
 614 static unsigned int serial_in_override(struct uart_port *up, int offset)
 615 {
 616         if (UART_RX == offset) {
 617                 unsigned int lsr;
 618                 lsr = __serial_read_reg(up, UART_LSR);
 619                 if (!(lsr & UART_LSR_DR))
 620                         return -EPERM;
 621         }
 622
 623         return __serial_read_reg(up, offset);
 624 }
 625
 626 static void serial_out_override(struct uart_port *up, int offset, int value)
 627 {
 628         unsigned int status, tmout = 10000;
 629
 630         status = __serial_read_reg(up, UART_LSR);
 631         while (!(status & UART_LSR_THRE)) {
 632                 /* Wait up to 10ms for the character(s) to be sent. */
 633                 if (--tmout == 0)
 634                         break;
 635                 udelay(1);
 636                 status = __serial_read_reg(up, UART_LSR);
 637         }
 638         __serial_write_reg(up, offset, value);
 639 }
 640 void __init omap_serial_early_init(void)
 641 {
 642         int i, nr_ports;
 643         char name[16];
 644
 645         if (!(cpu_is_omap3630() || cpu_is_omap4430()))
 646                 nr_ports = 3;
 647         else
 648                 nr_ports = ARRAY_SIZE(omap_uart);
 649
 650         /*
 651          * Make sure the serial ports are muxed on at this point.
 652          * You have to mux them off in device drivers later on
 653          * if not needed.
 654          */
 655
 656         for (i = 0; i < nr_ports; i++) {
 657                 struct omap_uart_state *uart = &omap_uart[i];
 658                 struct platform_device *pdev = &uart->pdev;
 659                 struct device *dev = &pdev->dev;
 660                 struct plat_serial8250_port *p = dev->platform_data;
 661
 662                 /* Don't map zero-based physical address */
 663                 if (p->mapbase == 0) {
 664                         dev_warn(dev, "no physical address for uart#%d,"
 665                                  " so skipping early_init...\n", i);
 666                         continue;
 667                 }
 668                 /*
 669                  * Module 4KB + L4 interconnect 4KB
 670                  * Static mapping, never released
 671                  */
 672                 p->membase = ioremap(p->mapbase, SZ_8K);
 673                 if (!p->membase) {
 674                         dev_err(dev, "ioremap failed for uart%i\n", i + 1);
 675                         continue;
 676                 }
 677
 678                 sprintf(name, "uart%d_ick", i + 1);
 679                 uart->ick = clk_get(NULL, name);
 680                 if (IS_ERR(uart->ick)) {
 681                         dev_err(dev, "Could not get uart%d_ick\n", i + 1);
 682                         uart->ick = NULL;
 683                 }
 684
 685                 sprintf(name, "uart%d_fck", i+1);
 686                 uart->fck = clk_get(NULL, name);
 687                 if (IS_ERR(uart->fck)) {
 688                         dev_err(dev, "Could not get uart%d_fck\n", i + 1);
 689                         uart->fck = NULL;
 690                 }
 691
 692                 /* FIXME: Remove this once the clkdev is ready */
 693                 if (!cpu_is_omap44xx()) {
 694                         if (!uart->ick || !uart->fck)
 695                                 continue;
 696                 }
 697
 698                 uart->num = i;
 699                 p->private_data = uart;
 700                 uart->p = p;
 701
 702                 if (cpu_is_omap44xx())
 703                         p->irq += 32;
 704         }
 705 }
 706
 707 /**
 708  * omap_serial_init_port() - initialize single serial port
 709  * @port: serial port number (0-3)
 710  *
 711  * This function initialies serial driver for given @port only.
 712  * Platforms can call this function instead of omap_serial_init()
 713  * if they don't plan to use all available UARTs as serial ports.
 714  *
 715  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 716  * use only one of the two.
 717  */
 718 void __init omap_serial_init_port(int port)
 719 {
 720         struct omap_uart_state *uart;
 721         struct platform_device *pdev;
 722         struct device *dev;
 723
 724         BUG_ON(port < 0);
 725         BUG_ON(port >= ARRAY_SIZE(omap_uart));
 726
 727         uart = &omap_uart[port];
 728         pdev = &uart->pdev;
 729         dev = &pdev->dev;
 730
 731         /* Don't proceed if there's no clocks available */
 732         if (unlikely(!uart->ick || !uart->fck)) {
 733                 WARN(1, "%s: can't init uart%d, no clocks available\n",
 734                      kobject_name(&dev->kobj), port);
 735                 return;
 736         }
 737
 738         omap_uart_enable_clocks(uart);
 739
 740         omap_uart_reset(uart);
 741         omap_uart_idle_init(uart);
 742
 743         list_add_tail(&uart->node, &uart_list);
 744
 745         if (WARN_ON(platform_device_register(pdev)))
 746                 return;
 747
 748         if ((cpu_is_omap34xx() && uart->padconf) ||
 749             (uart->wk_en && uart->wk_mask)) {
 750                 device_init_wakeup(dev, true);
 751                 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
 752         }
 753
 754         /*
 755          * omap44xx: Never read empty UART fifo
 756          * omap3xxx: Never read empty UART fifo on UARTs
 757          * with IP rev >=0x52
 758          */
 759         if (cpu_is_omap44xx()) {
 760                 uart->p->serial_in = serial_in_override;
 761                 uart->p->serial_out = serial_out_override;
 762         } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
 763                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
 764                 uart->p->serial_in = serial_in_override;
 765                 uart->p->serial_out = serial_out_override;
 766         }
 767 }
 768
 769 /**
 770  * omap_serial_init() - intialize all supported serial ports
 771  *
 772  * Initializes all available UARTs as serial ports. Platforms
 773  * can call this function when they want to have default behaviour
 774  * for serial ports (e.g initialize them all as serial ports).
 775  */
 776 void __init omap_serial_init(void)
 777 {
 778         int i, nr_ports;
 779
 780         if (!(cpu_is_omap3630() || cpu_is_omap4430()))
 781                 nr_ports = 3;
 782         else
 783                 nr_ports = ARRAY_SIZE(omap_uart);
 784
 785         for (i = 0; i < nr_ports; i++)
 786                 omap_serial_init_port(i);
 787 }