arch/arm/mach-omap2/serial.c

   1 /*
   2  * arch/arm/mach-omap2/serial.c
   3  *
   4  * OMAP2 serial support.
   5  *
   6  * Copyright (C) 2005-2008 Nokia Corporation
   7  * Author: Paul Mundt <paul.mundt@nokia.com>
   8  *
   9  * Major rework for PM support by Kevin Hilman
  10  *
  11  * Based off of arch/arm/mach-omap/omap1/serial.c
  12  *
  13  * Copyright (C) 2009 Texas Instruments
  14  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com
  15  *
  16  * This file is subject to the terms and conditions of the GNU General Public
  17  * License. See the file "COPYING" in the main directory of this archive
  18  * for more details.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/serial_8250.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26 #include <linux/delay.h>
  27
  28 #include <plat/common.h>
  29 #include <plat/board.h>
  30 #include <plat/clock.h>
  31 #include <plat/control.h>
  32
  33 #include "prm.h"
  34 #include "pm.h"
  35 #include "prm-regbits-34xx.h"
  36
  37 #define UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV     0x52
  38 #define UART_OMAP_WER           0x17    /* Wake-up enable register */
  39
  40 /*
  41  * NOTE: By default the serial timeout is disabled as it causes lost characters
  42  * over the serial ports. This means that the UART clocks will stay on until
  43  * disabled via sysfs. This also causes that any deeper omap sleep states are
  44  * blocked.
  45  */
  46 #define DEFAULT_TIMEOUT 0
  47
  48 struct omap_uart_state {
  49         int num;
  50         int can_sleep;
  51         struct timer_list timer;
  52         u32 timeout;
  53
  54         void __iomem *wk_st;
  55         void __iomem *wk_en;
  56         u32 wk_mask;
  57         u32 padconf;
  58
  59         struct clk *ick;
  60         struct clk *fck;
  61         int clocked;
  62
  63         struct plat_serial8250_port *p;
  64         struct list_head node;
  65         struct platform_device pdev;
  66
  67 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
  68         int context_valid;
  69
  70         /* Registers to be saved/restored for OFF-mode */
  71         u16 dll;
  72         u16 dlh;
  73         u16 ier;
  74         u16 sysc;
  75         u16 scr;
  76         u16 wer;
  77 #endif
  78 };
  79
  80 static LIST_HEAD(uart_list);
  81
  82 static struct plat_serial8250_port serial_platform_data0[] = {
  83         {
  84                 .irq            = 72,
  85                 .flags          = UPF_BOOT_AUTOCONF,
  86                 .iotype         = UPIO_MEM,
  87                 .regshift       = 2,
  88                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
  89         }, {
  90                 .flags          = 0
  91         }
  92 };
  93
  94 static struct plat_serial8250_port serial_platform_data1[] = {
  95         {
  96                 .irq            = 73,
  97                 .flags          = UPF_BOOT_AUTOCONF,
  98                 .iotype         = UPIO_MEM,
  99                 .regshift       = 2,
 100                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 101         }, {
 102                 .flags          = 0
 103         }
 104 };
 105
 106 static struct plat_serial8250_port serial_platform_data2[] = {
 107         {
 108                 .irq            = 74,
 109                 .flags          = UPF_BOOT_AUTOCONF,
 110                 .iotype         = UPIO_MEM,
 111                 .regshift       = 2,
 112                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 113         }, {
 114                 .flags          = 0
 115         }
 116 };
 117
 118 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 119 static struct plat_serial8250_port serial_platform_data3[] = {
 120         {
 121                 .irq            = 70,
 122                 .flags          = UPF_BOOT_AUTOCONF,
 123                 .iotype         = UPIO_MEM,
 124                 .regshift       = 2,
 125                 .uartclk        = OMAP24XX_BASE_BAUD * 16,
 126         }, {
 127                 .flags          = 0
 128         }
 129 };
 130
 131 static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
 132 {
 133         serial_platform_data3[0].mapbase = omap2_globals->uart4_phys;
 134 }
 135 #else
 136 static inline void omap2_set_globals_uart4(struct omap_globals *omap2_globals)
 137 {
 138 }
 139 #endif
 140
 141 void __init omap2_set_globals_uart(struct omap_globals *omap2_globals)
 142 {
 143         serial_platform_data0[0].mapbase = omap2_globals->uart1_phys;
 144         serial_platform_data1[0].mapbase = omap2_globals->uart2_phys;
 145         serial_platform_data2[0].mapbase = omap2_globals->uart3_phys;
 146         if (cpu_is_omap3630() || cpu_is_omap44xx())
 147                 omap2_set_globals_uart4(omap2_globals);
 148 }
 149
 150 static inline unsigned int __serial_read_reg(struct uart_port *up,
 151                                            int offset)
 152 {
 153         offset <<= up->regshift;
 154         return (unsigned int)__raw_readb(up->membase + offset);
 155 }
 156
 157 static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
 158                                            int offset)
 159 {
 160         offset <<= up->regshift;
 161         return (unsigned int)__raw_readb(up->membase + offset);
 162 }
 163
 164 static inline void __serial_write_reg(struct uart_port *up, int offset,
 165                 int value)
 166 {
 167         offset <<= up->regshift;
 168         __raw_writeb(value, up->membase + offset);
 169 }
 170
 171 static inline void serial_write_reg(struct plat_serial8250_port *p, int offset,
 172                                     int value)
 173 {
 174         offset <<= p->regshift;
 175         __raw_writeb(value, p->membase + offset);
 176 }
 177
 178 /*
 179  * Internal UARTs need to be initialized for the 8250 autoconfig to work
 180  * properly. Note that the TX watermark initialization may not be needed
 181  * once the 8250.c watermark handling code is merged.
 182  */
 183 static inline void __init omap_uart_reset(struct omap_uart_state *uart)
 184 {
 185         struct plat_serial8250_port *p = uart->p;
 186
 187         serial_write_reg(p, UART_OMAP_MDR1, 0x07);
 188         serial_write_reg(p, UART_OMAP_SCR, 0x08);
 189         serial_write_reg(p, UART_OMAP_MDR1, 0x00);
 190         serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
 191 }
 192
 193 #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
 194
 195 static void omap_uart_save_context(struct omap_uart_state *uart)
 196 {
 197         u16 lcr = 0;
 198         struct plat_serial8250_port *p = uart->p;
 199
 200         if (!enable_off_mode)
 201                 return;
 202
 203         lcr = serial_read_reg(p, UART_LCR);
 204         serial_write_reg(p, UART_LCR, 0xBF);
 205         uart->dll = serial_read_reg(p, UART_DLL);
 206         uart->dlh = serial_read_reg(p, UART_DLM);
 207         serial_write_reg(p, UART_LCR, lcr);
 208         uart->ier = serial_read_reg(p, UART_IER);
 209         uart->sysc = serial_read_reg(p, UART_OMAP_SYSC);
 210         uart->scr = serial_read_reg(p, UART_OMAP_SCR);
 211         uart->wer = serial_read_reg(p, UART_OMAP_WER);
 212
 213         uart->context_valid = 1;
 214 }
 215
 216 static void omap_uart_restore_context(struct omap_uart_state *uart)
 217 {
 218         u16 efr = 0;
 219         struct plat_serial8250_port *p = uart->p;
 220
 221         if (!enable_off_mode)
 222                 return;
 223
 224         if (!uart->context_valid)
 225                 return;
 226
 227         uart->context_valid = 0;
 228
 229         serial_write_reg(p, UART_OMAP_MDR1, 0x7);
 230         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 231         efr = serial_read_reg(p, UART_EFR);
 232         serial_write_reg(p, UART_EFR, UART_EFR_ECB);
 233         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 234         serial_write_reg(p, UART_IER, 0x0);
 235         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 236         serial_write_reg(p, UART_DLL, uart->dll);
 237         serial_write_reg(p, UART_DLM, uart->dlh);
 238         serial_write_reg(p, UART_LCR, 0x0); /* Operational mode */
 239         serial_write_reg(p, UART_IER, uart->ier);
 240         serial_write_reg(p, UART_FCR, 0xA1);
 241         serial_write_reg(p, UART_LCR, 0xBF); /* Config B mode */
 242         serial_write_reg(p, UART_EFR, efr);
 243         serial_write_reg(p, UART_LCR, UART_LCR_WLEN8);
 244         serial_write_reg(p, UART_OMAP_SCR, uart->scr);
 245         serial_write_reg(p, UART_OMAP_WER, uart->wer);
 246         serial_write_reg(p, UART_OMAP_SYSC, uart->sysc);
 247         serial_write_reg(p, UART_OMAP_MDR1, 0x00); /* UART 16x mode */
 248 }
 249 #else
 250 static inline void omap_uart_save_context(struct omap_uart_state *uart) {}
 251 static inline void omap_uart_restore_context(struct omap_uart_state *uart) {}
 252 #endif /* CONFIG_PM && CONFIG_ARCH_OMAP3 */
 253
 254 static inline void omap_uart_enable_clocks(struct omap_uart_state *uart)
 255 {
 256         if (uart->clocked)
 257                 return;
 258
 259         clk_enable(uart->ick);
 260         clk_enable(uart->fck);
 261         uart->clocked = 1;
 262         omap_uart_restore_context(uart);
 263 }
 264
 265 #ifdef CONFIG_PM
 266
 267 static inline void omap_uart_disable_clocks(struct omap_uart_state *uart)
 268 {
 269         if (!uart->clocked)
 270                 return;
 271
 272         omap_uart_save_context(uart);
 273         uart->clocked = 0;
 274         clk_disable(uart->ick);
 275         clk_disable(uart->fck);
 276 }
 277
 278 static void omap_uart_enable_wakeup(struct omap_uart_state *uart)
 279 {
 280         /* Set wake-enable bit */
 281         if (uart->wk_en && uart->wk_mask) {
 282                 u32 v = __raw_readl(uart->wk_en);
 283                 v |= uart->wk_mask;
 284                 __raw_writel(v, uart->wk_en);
 285         }
 286
 287         /* Ensure IOPAD wake-enables are set */
 288         if (cpu_is_omap34xx() && uart->padconf) {
 289                 u16 v = omap_ctrl_readw(uart->padconf);
 290                 v |= OMAP3_PADCONF_WAKEUPENABLE0;
 291                 omap_ctrl_writew(v, uart->padconf);
 292         }
 293 }
 294
 295 static void omap_uart_disable_wakeup(struct omap_uart_state *uart)
 296 {
 297         /* Clear wake-enable bit */
 298         if (uart->wk_en && uart->wk_mask) {
 299                 u32 v = __raw_readl(uart->wk_en);
 300                 v &= ~uart->wk_mask;
 301                 __raw_writel(v, uart->wk_en);
 302         }
 303
 304         /* Ensure IOPAD wake-enables are cleared */
 305         if (cpu_is_omap34xx() && uart->padconf) {
 306                 u16 v = omap_ctrl_readw(uart->padconf);
 307                 v &= ~OMAP3_PADCONF_WAKEUPENABLE0;
 308                 omap_ctrl_writew(v, uart->padconf);
 309         }
 310 }
 311
 312 static void omap_uart_smart_idle_enable(struct omap_uart_state *uart,
 313                                           int enable)
 314 {
 315         struct plat_serial8250_port *p = uart->p;
 316         u16 sysc;
 317
 318         sysc = serial_read_reg(p, UART_OMAP_SYSC) & 0x7;
 319         if (enable)
 320                 sysc |= 0x2 << 3;
 321         else
 322                 sysc |= 0x1 << 3;
 323
 324         serial_write_reg(p, UART_OMAP_SYSC, sysc);
 325 }
 326
 327 static void omap_uart_block_sleep(struct omap_uart_state *uart)
 328 {
 329         omap_uart_enable_clocks(uart);
 330
 331         omap_uart_smart_idle_enable(uart, 0);
 332         uart->can_sleep = 0;
 333         if (uart->timeout)
 334                 mod_timer(&uart->timer, jiffies + uart->timeout);
 335         else
 336                 del_timer(&uart->timer);
 337 }
 338
 339 static void omap_uart_allow_sleep(struct omap_uart_state *uart)
 340 {
 341         if (device_may_wakeup(&uart->pdev.dev))
 342                 omap_uart_enable_wakeup(uart);
 343         else
 344                 omap_uart_disable_wakeup(uart);
 345
 346         if (!uart->clocked)
 347                 return;
 348
 349         omap_uart_smart_idle_enable(uart, 1);
 350         uart->can_sleep = 1;
 351         del_timer(&uart->timer);
 352 }
 353
 354 static void omap_uart_idle_timer(unsigned long data)
 355 {
 356         struct omap_uart_state *uart = (struct omap_uart_state *)data;
 357
 358         omap_uart_allow_sleep(uart);
 359 }
 360
 361 void omap_uart_prepare_idle(int num)
 362 {
 363         struct omap_uart_state *uart;
 364
 365         list_for_each_entry(uart, &uart_list, node) {
 366                 if (num == uart->num && uart->can_sleep) {
 367                         omap_uart_disable_clocks(uart);
 368                         return;
 369                 }
 370         }
 371 }
 372
 373 void omap_uart_resume_idle(int num)
 374 {
 375         struct omap_uart_state *uart;
 376
 377         list_for_each_entry(uart, &uart_list, node) {
 378                 if (num == uart->num) {
 379                         omap_uart_enable_clocks(uart);
 380
 381                         /* Check for IO pad wakeup */
 382                         if (cpu_is_omap34xx() && uart->padconf) {
 383                                 u16 p = omap_ctrl_readw(uart->padconf);
 384
 385                                 if (p & OMAP3_PADCONF_WAKEUPEVENT0)
 386                                         omap_uart_block_sleep(uart);
 387                         }
 388
 389                         /* Check for normal UART wakeup */
 390                         if (__raw_readl(uart->wk_st) & uart->wk_mask)
 391                                 omap_uart_block_sleep(uart);
 392                         return;
 393                 }
 394         }
 395 }
 396
 397 void omap_uart_prepare_suspend(void)
 398 {
 399         struct omap_uart_state *uart;
 400
 401         list_for_each_entry(uart, &uart_list, node) {
 402                 omap_uart_allow_sleep(uart);
 403         }
 404 }
 405
 406 int omap_uart_can_sleep(void)
 407 {
 408         struct omap_uart_state *uart;
 409         int can_sleep = 1;
 410
 411         list_for_each_entry(uart, &uart_list, node) {
 412                 if (!uart->clocked)
 413                         continue;
 414
 415                 if (!uart->can_sleep) {
 416                         can_sleep = 0;
 417                         continue;
 418                 }
 419
 420                 /* This UART can now safely sleep. */
 421                 omap_uart_allow_sleep(uart);
 422         }
 423
 424         return can_sleep;
 425 }
 426
 427 /**
 428  * omap_uart_interrupt()
 429  *
 430  * This handler is used only to detect that *any* UART interrupt has
 431  * occurred.  It does _nothing_ to handle the interrupt.  Rather,
 432  * any UART interrupt will trigger the inactivity timer so the
 433  * UART will not idle or sleep for its timeout period.
 434  *
 435  **/
 436 static irqreturn_t omap_uart_interrupt(int irq, void *dev_id)
 437 {
 438         struct omap_uart_state *uart = dev_id;
 439
 440         omap_uart_block_sleep(uart);
 441
 442         return IRQ_NONE;
 443 }
 444
 445 static void omap_uart_idle_init(struct omap_uart_state *uart)
 446 {
 447         struct plat_serial8250_port *p = uart->p;
 448         int ret;
 449
 450         uart->can_sleep = 0;
 451         uart->timeout = DEFAULT_TIMEOUT;
 452         setup_timer(&uart->timer, omap_uart_idle_timer,
 453                     (unsigned long) uart);
 454         if (uart->timeout)
 455                 mod_timer(&uart->timer, jiffies + uart->timeout);
 456         omap_uart_smart_idle_enable(uart, 0);
 457
 458         if (cpu_is_omap34xx()) {
 459                 u32 mod = (uart->num == 2) ? OMAP3430_PER_MOD : CORE_MOD;
 460                 u32 wk_mask = 0;
 461                 u32 padconf = 0;
 462
 463                 uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1);
 464                 uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1);
 465                 switch (uart->num) {
 466                 case 0:
 467                         wk_mask = OMAP3430_ST_UART1_MASK;
 468                         padconf = 0x182;
 469                         break;
 470                 case 1:
 471                         wk_mask = OMAP3430_ST_UART2_MASK;
 472                         padconf = 0x17a;
 473                         break;
 474                 case 2:
 475                         wk_mask = OMAP3430_ST_UART3_MASK;
 476                         padconf = 0x19e;
 477                         break;
 478                 }
 479                 uart->wk_mask = wk_mask;
 480                 uart->padconf = padconf;
 481         } else if (cpu_is_omap24xx()) {
 482                 u32 wk_mask = 0;
 483
 484                 if (cpu_is_omap2430()) {
 485                         uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 486                         uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, PM_WKST1);
 487                 } else if (cpu_is_omap2420()) {
 488                         uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKEN1);
 489                         uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, PM_WKST1);
 490                 }
 491                 switch (uart->num) {
 492                 case 0:
 493                         wk_mask = OMAP24XX_ST_UART1_MASK;
 494                         break;
 495                 case 1:
 496                         wk_mask = OMAP24XX_ST_UART2_MASK;
 497                         break;
 498                 case 2:
 499                         wk_mask = OMAP24XX_ST_UART3_MASK;
 500                         break;
 501                 }
 502                 uart->wk_mask = wk_mask;
 503         } else {
 504                 uart->wk_en = 0;
 505                 uart->wk_st = 0;
 506                 uart->wk_mask = 0;
 507                 uart->padconf = 0;
 508         }
 509
 510         p->irqflags |= IRQF_SHARED;
 511         ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
 512                           "serial idle", (void *)uart);
 513         WARN_ON(ret);
 514 }
 515
 516 void omap_uart_enable_irqs(int enable)
 517 {
 518         int ret;
 519         struct omap_uart_state *uart;
 520
 521         list_for_each_entry(uart, &uart_list, node) {
 522                 if (enable)
 523                         ret = request_irq(uart->p->irq, omap_uart_interrupt,
 524                                 IRQF_SHARED, "serial idle", (void *)uart);
 525                 else
 526                         free_irq(uart->p->irq, (void *)uart);
 527         }
 528 }
 529
 530 static ssize_t sleep_timeout_show(struct device *dev,
 531                                   struct device_attribute *attr,
 532                                   char *buf)
 533 {
 534         struct platform_device *pdev = container_of(dev,
 535                                         struct platform_device, dev);
 536         struct omap_uart_state *uart = container_of(pdev,
 537                                         struct omap_uart_state, pdev);
 538
 539         return sprintf(buf, "%u\n", uart->timeout / HZ);
 540 }
 541
 542 static ssize_t sleep_timeout_store(struct device *dev,
 543                                    struct device_attribute *attr,
 544                                    const char *buf, size_t n)
 545 {
 546         struct platform_device *pdev = container_of(dev,
 547                                         struct platform_device, dev);
 548         struct omap_uart_state *uart = container_of(pdev,
 549                                         struct omap_uart_state, pdev);
 550         unsigned int value;
 551
 552         if (sscanf(buf, "%u", &value) != 1) {
 553                 printk(KERN_ERR "sleep_timeout_store: Invalid value\n");
 554                 return -EINVAL;
 555         }
 556
 557         uart->timeout = value * HZ;
 558         if (uart->timeout)
 559                 mod_timer(&uart->timer, jiffies + uart->timeout);
 560         else
 561                 /* A zero value means disable timeout feature */
 562                 omap_uart_block_sleep(uart);
 563
 564         return n;
 565 }
 566
 567 DEVICE_ATTR(sleep_timeout, 0644, sleep_timeout_show, sleep_timeout_store);
 568 #define DEV_CREATE_FILE(dev, attr) WARN_ON(device_create_file(dev, attr))
 569 #else
 570 static inline void omap_uart_idle_init(struct omap_uart_state *uart) {}
 571 #define DEV_CREATE_FILE(dev, attr)
 572 #endif /* CONFIG_PM */
 573
 574 static struct omap_uart_state omap_uart[] = {
 575         {
 576                 .pdev = {
 577                         .name                   = "serial8250",
 578                         .id                     = PLAT8250_DEV_PLATFORM,
 579                         .dev                    = {
 580                                 .platform_data  = serial_platform_data0,
 581                         },
 582                 },
 583         }, {
 584                 .pdev = {
 585                         .name                   = "serial8250",
 586                         .id                     = PLAT8250_DEV_PLATFORM1,
 587                         .dev                    = {
 588                                 .platform_data  = serial_platform_data1,
 589                         },
 590                 },
 591         }, {
 592                 .pdev = {
 593                         .name                   = "serial8250",
 594                         .id                     = PLAT8250_DEV_PLATFORM2,
 595                         .dev                    = {
 596                                 .platform_data  = serial_platform_data2,
 597                         },
 598                 },
 599         },
 600 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 601         {
 602                 .pdev = {
 603                         .name                   = "serial8250",
 604                         .id                     = 3,
 605                         .dev                    = {
 606                                 .platform_data  = serial_platform_data3,
 607                         },
 608                 },
 609         },
 610 #endif
 611 };
 612
 613 /*
 614  * Override the default 8250 read handler: mem_serial_in()
 615  * Empty RX fifo read causes an abort on omap3630 and omap4
 616  * This function makes sure that an empty rx fifo is not read on these silicons
 617  * (OMAP1/2/3430 are not affected)
 618  */
 619 static unsigned int serial_in_override(struct uart_port *up, int offset)
 620 {
 621         if (UART_RX == offset) {
 622                 unsigned int lsr;
 623                 lsr = __serial_read_reg(up, UART_LSR);
 624                 if (!(lsr & UART_LSR_DR))
 625                         return -EPERM;
 626         }
 627
 628         return __serial_read_reg(up, offset);
 629 }
 630
 631 static void serial_out_override(struct uart_port *up, int offset, int value)
 632 {
 633         unsigned int status, tmout = 10000;
 634
 635         status = __serial_read_reg(up, UART_LSR);
 636         while (!(status & UART_LSR_THRE)) {
 637                 /* Wait up to 10ms for the character(s) to be sent. */
 638                 if (--tmout == 0)
 639                         break;
 640                 udelay(1);
 641                 status = __serial_read_reg(up, UART_LSR);
 642         }
 643         __serial_write_reg(up, offset, value);
 644 }
 645 void __init omap_serial_early_init(void)
 646 {
 647         int i;
 648         char name[16];
 649
 650         /*
 651          * Make sure the serial ports are muxed on at this point.
 652          * You have to mux them off in device drivers later on
 653          * if not needed.
 654          */
 655
 656         for (i = 0; i < ARRAY_SIZE(omap_uart); i++) {
 657                 struct omap_uart_state *uart = &omap_uart[i];
 658                 struct platform_device *pdev = &uart->pdev;
 659                 struct device *dev = &pdev->dev;
 660                 struct plat_serial8250_port *p = dev->platform_data;
 661
 662                 /*
 663                  * Module 4KB + L4 interconnect 4KB
 664                  * Static mapping, never released
 665                  */
 666                 p->membase = ioremap(p->mapbase, SZ_8K);
 667                 if (!p->membase) {
 668                         printk(KERN_ERR "ioremap failed for uart%i\n", i + 1);
 669                         continue;
 670                 }
 671
 672                 sprintf(name, "uart%d_ick", i+1);
 673                 uart->ick = clk_get(NULL, name);
 674                 if (IS_ERR(uart->ick)) {
 675                         printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
 676                         uart->ick = NULL;
 677                 }
 678
 679                 sprintf(name, "uart%d_fck", i+1);
 680                 uart->fck = clk_get(NULL, name);
 681                 if (IS_ERR(uart->fck)) {
 682                         printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
 683                         uart->fck = NULL;
 684                 }
 685
 686                 /* FIXME: Remove this once the clkdev is ready */
 687                 if (!cpu_is_omap44xx()) {
 688                         if (!uart->ick || !uart->fck)
 689                                 continue;
 690                 }
 691
 692                 uart->num = i;
 693                 p->private_data = uart;
 694                 uart->p = p;
 695
 696                 if (cpu_is_omap44xx())
 697                         p->irq += 32;
 698         }
 699 }
 700
 701 /**
 702  * omap_serial_init_port() - initialize single serial port
 703  * @port: serial port number (0-3)
 704  *
 705  * This function initialies serial driver for given @port only.
 706  * Platforms can call this function instead of omap_serial_init()
 707  * if they don't plan to use all available UARTs as serial ports.
 708  *
 709  * Don't mix calls to omap_serial_init_port() and omap_serial_init(),
 710  * use only one of the two.
 711  */
 712 void __init omap_serial_init_port(int port)
 713 {
 714         struct omap_uart_state *uart;
 715         struct platform_device *pdev;
 716         struct device *dev;
 717
 718         BUG_ON(port < 0);
 719         BUG_ON(port >= ARRAY_SIZE(omap_uart));
 720
 721         uart = &omap_uart[port];
 722         pdev = &uart->pdev;
 723         dev = &pdev->dev;
 724
 725         omap_uart_enable_clocks(uart);
 726
 727         omap_uart_reset(uart);
 728         omap_uart_idle_init(uart);
 729
 730         list_add_tail(&uart->node, &uart_list);
 731
 732         if (WARN_ON(platform_device_register(pdev)))
 733                 return;
 734
 735         if ((cpu_is_omap34xx() && uart->padconf) ||
 736             (uart->wk_en && uart->wk_mask)) {
 737                 device_init_wakeup(dev, true);
 738                 DEV_CREATE_FILE(dev, &dev_attr_sleep_timeout);
 739         }
 740
 741         /*
 742          * omap44xx: Never read empty UART fifo
 743          * omap3xxx: Never read empty UART fifo on UARTs
 744          * with IP rev >=0x52
 745          */
 746         if (cpu_is_omap44xx()) {
 747                 uart->p->serial_in = serial_in_override;
 748                 uart->p->serial_out = serial_out_override;
 749         } else if ((serial_read_reg(uart->p, UART_OMAP_MVER) & 0xFF)
 750                         >= UART_OMAP_NO_EMPTY_FIFO_READ_IP_REV) {
 751                 uart->p->serial_in = serial_in_override;
 752                 uart->p->serial_out = serial_out_override;
 753         }
 754 }
 755
 756 /**
 757  * omap_serial_init() - intialize all supported serial ports
 758  *
 759  * Initializes all available UARTs as serial ports. Platforms
 760  * can call this function when they want to have default behaviour
 761  * for serial ports (e.g initialize them all as serial ports).
 762  */
 763 void __init omap_serial_init(void)
 764 {
 765         int i, nr_ports;
 766
 767         if (!(cpu_is_omap3630() || cpu_is_omap4430()))
 768                 nr_ports = 3;
 769         else
 770                 nr_ports = ARRAY_SIZE(omap_uart);
 771
 772         for (i = 0; i < nr_ports; i++)
 773                 omap_serial_init_port(i);
 774 }