arch/arm/mach-omap2/prm44xx.c

   1 /*
   2  * OMAP4 PRM module functions
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/common.h>
  21 #include <plat/cpu.h>
  22 #include <plat/prcm.h>
  23
  24 #include "vp.h"
  25 #include "prm44xx.h"
  26 #include "prm-regbits-44xx.h"
  27 #include "prcm44xx.h"
  28 #include "prminst44xx.h"
  29
  30 /* PRM low-level functions */
  31
  32 /* Read a register in a CM/PRM instance in the PRM module */
  33 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
  34 {
  35         return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg));
  36 }
  37
  38 /* Write into a register in a CM/PRM instance in the PRM module */
  39 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
  40 {
  41         __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg));
  42 }
  43
  44 /* Read-modify-write a register in a PRM module. Caller must lock */
  45 u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
  46 {
  47         u32 v;
  48
  49         v = omap4_prm_read_inst_reg(inst, reg);
  50         v &= ~mask;
  51         v |= bits;
  52         omap4_prm_write_inst_reg(v, inst, reg);
  53
  54         return v;
  55 }
  56
  57 /* PRM VP */
  58
  59 /*
  60  * struct omap4_vp - OMAP4 VP register access description.
  61  * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
  62  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
  63  */
  64 struct omap4_vp {
  65         u32 irqstatus_mpu;
  66         u32 tranxdone_status;
  67 };
  68
  69 static struct omap4_vp omap4_vp[] = {
  70         [OMAP4_VP_VDD_MPU_ID] = {
  71                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
  72                 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
  73         },
  74         [OMAP4_VP_VDD_IVA_ID] = {
  75                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  76                 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
  77         },
  78         [OMAP4_VP_VDD_CORE_ID] = {
  79                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  80                 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
  81         },
  82 };
  83
  84 u32 omap4_prm_vp_check_txdone(u8 vp_id)
  85 {
  86         struct omap4_vp *vp = &omap4_vp[vp_id];
  87         u32 irqstatus;
  88
  89         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
  90                                                 OMAP4430_PRM_OCP_SOCKET_INST,
  91                                                 vp->irqstatus_mpu);
  92         return irqstatus & vp->tranxdone_status;
  93 }
  94
  95 void omap4_prm_vp_clear_txdone(u8 vp_id)
  96 {
  97         struct omap4_vp *vp = &omap4_vp[vp_id];
  98
  99         omap4_prminst_write_inst_reg(vp->tranxdone_status,
 100                                      OMAP4430_PRM_PARTITION,
 101                                      OMAP4430_PRM_OCP_SOCKET_INST,
 102                                      vp->irqstatus_mpu);
 103 };
 104
 105 u32 omap4_prm_vcvp_read(u8 offset)
 106 {
 107         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 108                                            OMAP4430_PRM_DEVICE_INST, offset);
 109 }
 110
 111 void omap4_prm_vcvp_write(u32 val, u8 offset)
 112 {
 113         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
 114                                      OMAP4430_PRM_DEVICE_INST, offset);
 115 }
 116
 117 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 118 {
 119         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 120                                                OMAP4430_PRM_PARTITION,
 121                                                OMAP4430_PRM_DEVICE_INST,
 122                                                offset);
 123 }