arch/arm/mach-omap2/prm.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
   2 #define __ARCH_ARM_MACH_OMAP2_PRM_H
   3
   4 /*
   5  * OMAP2/3 Power/Reset Management (PRM) register definitions
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "prcm-common.h"
  18
  19 #ifndef __ASSEMBLER__
  20 #define OMAP_PRM_REGADDR(module, reg)                                   \
  21         (void __iomem *)IO_ADDRESS(OMAP2_PRM_BASE + (module) + (reg))
  22 #else
  23 #define OMAP2420_PRM_REGADDR(module, reg)                               \
  24                         IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
  25 #define OMAP2430_PRM_REGADDR(module, reg)                               \
  26                         IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
  27 #define OMAP34XX_PRM_REGADDR(module, reg)                               \
  28                         IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
  29 #endif
  30
  31 /*
  32  * Architecture-specific global PRM registers
  33  * Use __raw_{read,write}l() with these registers.
  34  *
  35  * With a few exceptions, these are the register names beginning with
  36  * PRCM_* on 24xx, and PRM_* on 34xx.  (The exceptions are the
  37  * IRQSTATUS and IRQENABLE bits.)
  38  *
  39  */
  40
  41 #define OMAP24XX_PRCM_REVISION          OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
  42 #define OMAP24XX_PRCM_SYSCONFIG         OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
  43
  44 #define OMAP24XX_PRCM_IRQSTATUS_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
  45 #define OMAP24XX_PRCM_IRQENABLE_MPU     OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
  46
  47 #define OMAP24XX_PRCM_VOLTCTRL          OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
  48 #define OMAP24XX_PRCM_VOLTST            OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
  49 #define OMAP24XX_PRCM_CLKSRC_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
  50 #define OMAP24XX_PRCM_CLKOUT_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
  51 #define OMAP24XX_PRCM_CLKEMUL_CTRL      OMAP_PRM_REGADDR(OCP_MOD, 0x0078)
  52 #define OMAP24XX_PRCM_CLKCFG_CTRL       OMAP_PRM_REGADDR(OCP_MOD, 0x0080)
  53 #define OMAP24XX_PRCM_CLKCFG_STATUS     OMAP_PRM_REGADDR(OCP_MOD, 0x0084)
  54 #define OMAP24XX_PRCM_VOLTSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0090)
  55 #define OMAP24XX_PRCM_CLKSSETUP         OMAP_PRM_REGADDR(OCP_MOD, 0x0094)
  56 #define OMAP24XX_PRCM_POLCTRL           OMAP_PRM_REGADDR(OCP_MOD, 0x0098)
  57
  58 #define OMAP3430_PRM_REVISION           OMAP_PRM_REGADDR(OCP_MOD, 0x0004)
  59 #define OMAP3430_PRM_SYSCONFIG          OMAP_PRM_REGADDR(OCP_MOD, 0x0014)
  60
  61 #define OMAP3430_PRM_IRQSTATUS_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
  62 #define OMAP3430_PRM_IRQENABLE_MPU      OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
  63
  64
  65 #define OMAP3430_PRM_VC_SMPS_SA         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
  66 #define OMAP3430_PRM_VC_SMPS_VOL_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
  67 #define OMAP3430_PRM_VC_SMPS_CMD_RA     OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
  68 #define OMAP3430_PRM_VC_CMD_VAL_0       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
  69 #define OMAP3430_PRM_VC_CMD_VAL_1       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
  70 #define OMAP3430_PRM_VC_CH_CONF         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
  71 #define OMAP3430_PRM_VC_I2C_CFG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
  72 #define OMAP3430_PRM_VC_BYPASS_VAL      OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
  73 #define OMAP3430_PRM_RSTCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
  74 #define OMAP3430_PRM_RSTTIME            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
  75 #define OMAP3430_PRM_RSTST              OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
  76 #define OMAP3430_PRM_VOLTCTRL           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
  77 #define OMAP3430_PRM_SRAM_PCHARGE       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
  78 #define OMAP3430_PRM_CLKSRC_CTRL        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
  79 #define OMAP3430_PRM_VOLTSETUP1         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
  80 #define OMAP3430_PRM_VOLTOFFSET         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
  81 #define OMAP3430_PRM_CLKSETUP           OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
  82 #define OMAP3430_PRM_POLCTRL            OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
  83 #define OMAP3430_PRM_VOLTSETUP2         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
  84 #define OMAP3430_PRM_VP1_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
  85 #define OMAP3430_PRM_VP1_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
  86 #define OMAP3430_PRM_VP1_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
  87 #define OMAP3430_PRM_VP1_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
  88 #define OMAP3430_PRM_VP1_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
  89 #define OMAP3430_PRM_VP1_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
  90 #define OMAP3430_PRM_VP2_CONFIG         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
  91 #define OMAP3430_PRM_VP2_VSTEPMIN       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
  92 #define OMAP3430_PRM_VP2_VSTEPMAX       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
  93 #define OMAP3430_PRM_VP2_VLIMITTO       OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
  94 #define OMAP3430_PRM_VP2_VOLTAGE        OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
  95 #define OMAP3430_PRM_VP2_STATUS         OMAP_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
  96
  97 #define OMAP3430_PRM_CLKSEL             OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
  98 #define OMAP3430_PRM_CLKOUT_CTRL        OMAP_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
  99
 100 /*
 101  * Module specific PRM registers from PRM_BASE + domain offset
 102  *
 103  * Use prm_{read,write}_mod_reg() with these registers.
 104  *
 105  * With a few exceptions, these are the register names beginning with
 106  * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
 107  * and IRQENABLE bits.)
 108  *
 109  */
 110
 111 /* Registers appearing on both 24xx and 34xx */
 112
 113 #define RM_RSTCTRL                                      0x0050
 114 #define RM_RSTTIME                                      0x0054
 115 #define RM_RSTST                                        0x0058
 116
 117 #define PM_WKEN                                         0x00a0
 118 #define PM_WKEN1                                        PM_WKEN
 119 #define PM_WKST                                         0x00b0
 120 #define PM_WKST1                                        PM_WKST
 121 #define PM_WKDEP                                        0x00c8
 122 #define PM_EVGENCTRL                                    0x00d4
 123 #define PM_EVGENONTIM                                   0x00d8
 124 #define PM_EVGENOFFTIM                                  0x00dc
 125 #define PM_PWSTCTRL                                     0x00e0
 126 #define PM_PWSTST                                       0x00e4
 127
 128 #define OMAP3430_PM_MPUGRPSEL                           0x00a4
 129 #define OMAP3430_PM_MPUGRPSEL1                          OMAP3430_PM_MPUGRPSEL
 130
 131 #define OMAP3430_PM_IVAGRPSEL                           0x00a8
 132 #define OMAP3430_PM_IVAGRPSEL1                          OMAP3430_PM_IVAGRPSEL
 133
 134 #define OMAP3430_PM_PREPWSTST                           0x00e8
 135
 136 #define OMAP3430_PRM_IRQSTATUS_IVA2                     0x00f8
 137 #define OMAP3430_PRM_IRQENABLE_IVA2                     0x00fc
 138
 139
 140 /* Architecture-specific registers */
 141
 142 #define OMAP24XX_PM_WKEN2                               0x00a4
 143 #define OMAP24XX_PM_WKST2                               0x00b4
 144
 145 #define OMAP24XX_PRCM_IRQSTATUS_DSP                     0x00f0  /* IVA mod */
 146 #define OMAP24XX_PRCM_IRQENABLE_DSP                     0x00f4  /* IVA mod */
 147 #define OMAP24XX_PRCM_IRQSTATUS_IVA                     0x00f8
 148 #define OMAP24XX_PRCM_IRQENABLE_IVA                     0x00fc
 149
 150 #ifndef __ASSEMBLER__
 151
 152 /* Power/reset management domain register get/set */
 153
 154 static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx)
 155 {
 156         __raw_writel(val, OMAP_PRM_REGADDR(module, idx));
 157 }
 158
 159 static inline u32 prm_read_mod_reg(s16 module, s16 idx)
 160 {
 161         return __raw_readl(OMAP_PRM_REGADDR(module, idx));
 162 }
 163
 164 #endif
 165
 166 /*
 167  * Bits common to specific registers
 168  *
 169  * The 3430 register and bit names are generally used,
 170  * since they tend to make more sense
 171  */
 172
 173 /* PM_EVGENONTIM_MPU */
 174 /* Named PM_EVEGENONTIM_MPU on the 24XX */
 175 #define OMAP_ONTIMEVAL_SHIFT                            0
 176 #define OMAP_ONTIMEVAL_MASK                             (0xffffffff << 0)
 177
 178 /* PM_EVGENOFFTIM_MPU */
 179 /* Named PM_EVEGENOFFTIM_MPU on the 24XX */
 180 #define OMAP_OFFTIMEVAL_SHIFT                           0
 181 #define OMAP_OFFTIMEVAL_MASK                            (0xffffffff << 0)
 182
 183 /* PRM_CLKSETUP and PRCM_VOLTSETUP */
 184 /* Named PRCM_CLKSSETUP on the 24XX */
 185 #define OMAP_SETUP_TIME_SHIFT                           0
 186 #define OMAP_SETUP_TIME_MASK                            (0xffff << 0)
 187
 188 /* PRM_CLKSRC_CTRL */
 189 /* Named PRCM_CLKSRC_CTRL on the 24XX */
 190 #define OMAP_SYSCLKDIV_SHIFT                            6
 191 #define OMAP_SYSCLKDIV_MASK                             (0x3 << 6)
 192 #define OMAP_AUTOEXTCLKMODE_SHIFT                       3
 193 #define OMAP_AUTOEXTCLKMODE_MASK                        (0x3 << 3)
 194 #define OMAP_SYSCLKSEL_SHIFT                            0
 195 #define OMAP_SYSCLKSEL_MASK                             (0x3 << 0)
 196
 197 /* PM_EVGENCTRL_MPU */
 198 #define OMAP_OFFLOADMODE_SHIFT                          3
 199 #define OMAP_OFFLOADMODE_MASK                           (0x3 << 3)
 200 #define OMAP_ONLOADMODE_SHIFT                           1
 201 #define OMAP_ONLOADMODE_MASK                            (0x3 << 1)
 202 #define OMAP_ENABLE                                     (1 << 0)
 203
 204 /* PRM_RSTTIME */
 205 /* Named RM_RSTTIME_WKUP on the 24xx */
 206 #define OMAP_RSTTIME2_SHIFT                             8
 207 #define OMAP_RSTTIME2_MASK                              (0x1f << 8)
 208 #define OMAP_RSTTIME1_SHIFT                             0
 209 #define OMAP_RSTTIME1_MASK                              (0xff << 0)
 210
 211
 212 /* PRM_RSTCTRL */
 213 /* Named RM_RSTCTRL_WKUP on the 24xx */
 214 /* 2420 calls RST_DPLL3 'RST_DPLL' */
 215 #define OMAP_RST_DPLL3                                  (1 << 2)
 216 #define OMAP_RST_GS                                     (1 << 1)
 217
 218
 219 /*
 220  * Bits common to module-shared registers
 221  *
 222  * Not all registers of a particular type support all of these bits -
 223  * check TRM if you are unsure
 224  */
 225
 226 /*
 227  * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
 228  *
 229  * 2430: PM_PWSTST_MDM
 230  *
 231  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 232  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 233  *       PM_PWSTST_NEON
 234  */
 235 #define OMAP_INTRANSITION                               (1 << 20)
 236
 237
 238 /*
 239  * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
 240  *
 241  * 2430: PM_PWSTST_MDM
 242  *
 243  * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 244  *       PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 245  *       PM_PWSTST_NEON
 246  */
 247 #define OMAP_POWERSTATEST_SHIFT                         0
 248 #define OMAP_POWERSTATEST_MASK                          (0x3 << 0)
 249
 250 /*
 251  * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
 252  *       called 'COREWKUP_RST'
 253  *
 254  * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
 255  *       RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
 256  */
 257 #define OMAP_COREDOMAINWKUP_RST                         (1 << 3)
 258
 259 /*
 260  * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
 261  *
 262  * 2430: RM_RSTST_MDM
 263  *
 264  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 265  */
 266 #define OMAP_DOMAINWKUP_RST                             (1 << 2)
 267
 268 /*
 269  * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
 270  *       On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
 271  *
 272  * 2430: RM_RSTST_MDM
 273  *
 274  * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 275  */
 276 #define OMAP_GLOBALWARM_RST                             (1 << 1)
 277 #define OMAP_GLOBALCOLD_RST                             (1 << 0)
 278
 279 /*
 280  * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
 281  *       2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
 282  *
 283  * 2430: PM_WKDEP_MDM
 284  *
 285  * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
 286  *       PM_WKDEP_PER
 287  */
 288 #define OMAP_EN_WKUP                                    (1 << 4)
 289
 290 /*
 291  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 292  *       PM_PWSTCTRL_DSP
 293  *
 294  * 2430: PM_PWSTCTRL_MDM
 295  *
 296  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 297  *       PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 298  *       PM_PWSTCTRL_NEON
 299  */
 300 #define OMAP_LOGICRETSTATE                              (1 << 2)
 301
 302 /*
 303  * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 304  *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
 305  *
 306  * 2430: PM_PWSTCTRL_MDM shared bits
 307  *
 308  * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
 309  *       PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 310  *       PM_PWSTCTRL_NEON shared bits
 311  */
 312 #define OMAP_POWERSTATE_SHIFT                           0
 313 #define OMAP_POWERSTATE_MASK                            (0x3 << 0)
 314
 315
 316 #endif