2 * linux/arch/arm/mach-omap2/prcm.c
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
6 * Copyright (C) 2005 Nokia Corporation
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <plat/common.h>
27 #include <plat/prcm.h>
28 #include <plat/irqs.h>
31 #include "clock2xxx.h"
35 #include "prm-regbits-24xx.h"
36 #include "prm-regbits-44xx.h"
39 static void __iomem *prm_base;
40 static void __iomem *cm_base;
41 static void __iomem *cm2_base;
43 #define MAX_MODULE_ENABLE_WAIT 100000
45 struct omap3_prcm_regs {
61 u32 iva2_cm_clken_pll;
69 u32 usbhost_cm_fclken;
78 u32 usbhost_cm_iclken;
79 u32 iva2_cm_autiidle2;
81 u32 iva2_cm_clkstctrl;
83 u32 core_cm_clkstctrl;
88 u32 neon_cm_clkstctrl;
89 u32 usbhost_cm_clkstctrl;
90 u32 core_cm_autoidle1;
91 u32 core_cm_autoidle2;
92 u32 core_cm_autoidle3;
97 u32 usbhost_cm_autoidle;
102 u32 usbhost_cm_sleepdep;
110 u32 usbhost_pm_wkdep;
111 u32 core_pm_mpugrpsel1;
112 u32 iva2_pm_ivagrpsel1;
113 u32 core_pm_mpugrpsel3;
114 u32 core_pm_ivagrpsel3;
115 u32 wkup_pm_mpugrpsel;
116 u32 wkup_pm_ivagrpsel;
117 u32 per_pm_mpugrpsel;
118 u32 per_pm_ivagrpsel;
122 static struct omap3_prcm_regs prcm_context;
124 u32 omap_prcm_get_reset_sources(void)
126 /* XXX This presumably needs modification for 34XX */
127 if (cpu_is_omap24xx() || cpu_is_omap34xx())
128 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
129 if (cpu_is_omap44xx())
130 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
134 EXPORT_SYMBOL(omap_prcm_get_reset_sources);
136 /* Resets clock rates and reboots the system. Only called from system.h */
137 void omap_prcm_arch_reset(char mode, const char *cmd)
141 if (cpu_is_omap24xx()) {
142 omap2xxx_clk_prepare_for_reboot();
144 prcm_offs = WKUP_MOD;
145 } else if (cpu_is_omap34xx()) {
146 prcm_offs = OMAP3430_GR_MOD;
147 omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
148 } else if (cpu_is_omap44xx())
149 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
153 if (cpu_is_omap24xx() || cpu_is_omap34xx())
154 prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
156 if (cpu_is_omap44xx())
157 prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
158 prcm_offs, OMAP4_RM_RSTCTRL);
161 static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
164 return __raw_readl(base + module + reg);
167 static inline void __omap_prcm_write(u32 value, void __iomem *base,
171 __raw_writel(value, base + module + reg);
174 /* Read a register in a PRM module */
175 u32 prm_read_mod_reg(s16 module, u16 idx)
177 return __omap_prcm_read(prm_base, module, idx);
180 /* Write into a register in a PRM module */
181 void prm_write_mod_reg(u32 val, s16 module, u16 idx)
183 __omap_prcm_write(val, prm_base, module, idx);
186 /* Read-modify-write a register in a PRM module. Caller must lock */
187 u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
191 v = prm_read_mod_reg(module, idx);
194 prm_write_mod_reg(v, module, idx);
199 /* Read a PRM register, AND it, and shift the result down to bit 0 */
200 u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
204 v = prm_read_mod_reg(domain, idx);
211 /* Read a PRM register, AND it, and shift the result down to bit 0 */
212 u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
216 v = __raw_readl(reg);
223 /* Read-modify-write a register in a PRM module. Caller must lock */
224 u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
228 v = __raw_readl(reg);
231 __raw_writel(v, reg);
235 /* Read a register in a CM module */
236 u32 cm_read_mod_reg(s16 module, u16 idx)
238 return __omap_prcm_read(cm_base, module, idx);
241 /* Write into a register in a CM module */
242 void cm_write_mod_reg(u32 val, s16 module, u16 idx)
244 __omap_prcm_write(val, cm_base, module, idx);
247 /* Read-modify-write a register in a CM module. Caller must lock */
248 u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
252 v = cm_read_mod_reg(module, idx);
255 cm_write_mod_reg(v, module, idx);
261 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
262 * @reg: physical address of module IDLEST register
263 * @mask: value to mask against to determine if the module is active
264 * @idlest: idle state indicator (0 or 1) for the clock
265 * @name: name of the clock (for printk)
267 * Returns 1 if the module indicated readiness in time, or 0 if it
268 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
270 int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
282 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
283 MAX_MODULE_ENABLE_WAIT, i);
285 if (i < MAX_MODULE_ENABLE_WAIT)
286 pr_debug("cm: Module associated with clock %s ready after %d "
289 pr_err("cm: Module associated with clock %s didn't enable in "
290 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
292 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
295 void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
297 /* Static mapping, never released */
298 if (omap2_globals->prm) {
299 prm_base = ioremap(omap2_globals->prm, SZ_8K);
302 if (omap2_globals->cm) {
303 cm_base = ioremap(omap2_globals->cm, SZ_8K);
306 if (omap2_globals->cm2) {
307 cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
312 #ifdef CONFIG_ARCH_OMAP3
313 void omap3_prcm_save_context(void)
315 prcm_context.iva2_cm_clksel1 =
316 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
317 prcm_context.iva2_cm_clksel2 =
318 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
319 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
320 prcm_context.sgx_cm_clksel =
321 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
322 prcm_context.dss_cm_clksel =
323 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
324 prcm_context.cam_cm_clksel =
325 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
326 prcm_context.per_cm_clksel =
327 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
328 prcm_context.emu_cm_clksel =
329 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
330 prcm_context.emu_cm_clkstctrl =
331 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
332 prcm_context.pll_cm_autoidle2 =
333 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
334 prcm_context.pll_cm_clksel4 =
335 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
336 prcm_context.pll_cm_clksel5 =
337 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
338 prcm_context.pll_cm_clken2 =
339 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
340 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
341 prcm_context.iva2_cm_fclken =
342 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
343 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
344 OMAP3430_CM_CLKEN_PLL);
345 prcm_context.core_cm_fclken1 =
346 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
347 prcm_context.core_cm_fclken3 =
348 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
349 prcm_context.sgx_cm_fclken =
350 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
351 prcm_context.wkup_cm_fclken =
352 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
353 prcm_context.dss_cm_fclken =
354 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
355 prcm_context.cam_cm_fclken =
356 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
357 prcm_context.per_cm_fclken =
358 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
359 prcm_context.usbhost_cm_fclken =
360 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
361 prcm_context.core_cm_iclken1 =
362 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
363 prcm_context.core_cm_iclken2 =
364 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
365 prcm_context.core_cm_iclken3 =
366 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
367 prcm_context.sgx_cm_iclken =
368 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
369 prcm_context.wkup_cm_iclken =
370 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
371 prcm_context.dss_cm_iclken =
372 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
373 prcm_context.cam_cm_iclken =
374 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
375 prcm_context.per_cm_iclken =
376 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
377 prcm_context.usbhost_cm_iclken =
378 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
379 prcm_context.iva2_cm_autiidle2 =
380 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
381 prcm_context.mpu_cm_autoidle2 =
382 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
383 prcm_context.iva2_cm_clkstctrl =
384 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
385 prcm_context.mpu_cm_clkstctrl =
386 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
387 prcm_context.core_cm_clkstctrl =
388 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
389 prcm_context.sgx_cm_clkstctrl =
390 cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
392 prcm_context.dss_cm_clkstctrl =
393 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
394 prcm_context.cam_cm_clkstctrl =
395 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
396 prcm_context.per_cm_clkstctrl =
397 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
398 prcm_context.neon_cm_clkstctrl =
399 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
400 prcm_context.usbhost_cm_clkstctrl =
401 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
403 prcm_context.core_cm_autoidle1 =
404 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
405 prcm_context.core_cm_autoidle2 =
406 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
407 prcm_context.core_cm_autoidle3 =
408 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
409 prcm_context.wkup_cm_autoidle =
410 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
411 prcm_context.dss_cm_autoidle =
412 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
413 prcm_context.cam_cm_autoidle =
414 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
415 prcm_context.per_cm_autoidle =
416 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
417 prcm_context.usbhost_cm_autoidle =
418 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
419 prcm_context.sgx_cm_sleepdep =
420 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
421 prcm_context.dss_cm_sleepdep =
422 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
423 prcm_context.cam_cm_sleepdep =
424 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
425 prcm_context.per_cm_sleepdep =
426 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
427 prcm_context.usbhost_cm_sleepdep =
428 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
429 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
430 OMAP3_CM_CLKOUT_CTRL_OFFSET);
431 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
432 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
433 prcm_context.sgx_pm_wkdep =
434 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
435 prcm_context.dss_pm_wkdep =
436 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
437 prcm_context.cam_pm_wkdep =
438 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
439 prcm_context.per_pm_wkdep =
440 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
441 prcm_context.neon_pm_wkdep =
442 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
443 prcm_context.usbhost_pm_wkdep =
444 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
445 prcm_context.core_pm_mpugrpsel1 =
446 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
447 prcm_context.iva2_pm_ivagrpsel1 =
448 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
449 prcm_context.core_pm_mpugrpsel3 =
450 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
451 prcm_context.core_pm_ivagrpsel3 =
452 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
453 prcm_context.wkup_pm_mpugrpsel =
454 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
455 prcm_context.wkup_pm_ivagrpsel =
456 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
457 prcm_context.per_pm_mpugrpsel =
458 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
459 prcm_context.per_pm_ivagrpsel =
460 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
461 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
465 void omap3_prcm_restore_context(void)
467 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
469 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
471 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
472 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
474 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
476 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
478 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
480 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
482 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
484 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
486 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
487 OMAP3430ES2_CM_CLKSEL4);
488 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
489 OMAP3430ES2_CM_CLKSEL5);
490 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
491 OMAP3430ES2_CM_CLKEN2);
492 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
493 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
495 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
496 OMAP3430_CM_CLKEN_PLL);
497 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
498 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
499 OMAP3430ES2_CM_FCLKEN3);
500 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
502 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
503 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
505 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
507 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
509 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
510 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
511 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
512 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
513 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
514 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
516 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
517 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
519 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
521 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
523 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
524 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
525 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
527 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
528 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
530 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
532 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
534 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
536 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
538 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
540 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
542 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
544 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
545 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
546 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
548 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
550 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
552 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
553 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
555 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
557 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
559 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
560 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
561 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
562 OMAP3430_CM_SLEEPDEP);
563 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
564 OMAP3430_CM_SLEEPDEP);
565 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
566 OMAP3430_CM_SLEEPDEP);
567 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
568 OMAP3430_CM_SLEEPDEP);
569 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
570 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
571 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
572 OMAP3_CM_CLKOUT_CTRL_OFFSET);
573 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
574 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
575 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
577 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
579 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
581 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
583 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
585 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
586 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
587 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
588 OMAP3430_PM_MPUGRPSEL1);
589 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
590 OMAP3430_PM_IVAGRPSEL1);
591 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
592 OMAP3430ES2_PM_MPUGRPSEL3);
593 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
594 OMAP3430ES2_PM_IVAGRPSEL3);
595 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
596 OMAP3430_PM_MPUGRPSEL);
597 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
598 OMAP3430_PM_IVAGRPSEL);
599 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
600 OMAP3430_PM_MPUGRPSEL);
601 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
602 OMAP3430_PM_IVAGRPSEL);
603 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);