arch/arm/mach-omap2/powerdomains44xx_data.c

   1 /*
   2  * OMAP4 Power domains framework
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2011 Nokia Corporation
   6  *
   7  * Abhijit Pagare (abhijitpagare@ti.com)
   8  * Benoit Cousson (b-cousson@ti.com)
   9  * Paul Walmsley (paul@pwsan.com)
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <linux/kernel.h>
  23 #include <linux/init.h>
  24
  25 #include "powerdomain.h"
  26
  27 #include "prcm-common.h"
  28 #include "prcm44xx.h"
  29 #include "prm-regbits-44xx.h"
  30 #include "prm44xx.h"
  31 #include "prcm_mpu44xx.h"
  32
  33 /* core_44xx_pwrdm: CORE power domain */
  34 static struct powerdomain core_44xx_pwrdm = {
  35         .name             = "core_pwrdm",
  36         .prcm_offs        = OMAP4430_PRM_CORE_INST,
  37         .prcm_partition   = OMAP4430_PRM_PARTITION,
  38         .pwrsts           = PWRSTS_RET_ON,
  39         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  40         .banks            = 5,
  41         .pwrsts_mem_ret = {
  42                 [0] = PWRSTS_OFF,       /* core_nret_bank */
  43                 [1] = PWRSTS_RET,       /* core_ocmram */
  44                 [2] = PWRSTS_RET,       /* core_other_bank */
  45                 [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
  46                 [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
  47         },
  48         .pwrsts_mem_on  = {
  49                 [0] = PWRSTS_ON,        /* core_nret_bank */
  50                 [1] = PWRSTS_ON,        /* core_ocmram */
  51                 [2] = PWRSTS_ON,        /* core_other_bank */
  52                 [3] = PWRSTS_ON,        /* ducati_l2ram */
  53                 [4] = PWRSTS_ON,        /* ducati_unicache */
  54         },
  55         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  56 };
  57
  58 /* gfx_44xx_pwrdm: 3D accelerator power domain */
  59 static struct powerdomain gfx_44xx_pwrdm = {
  60         .name             = "gfx_pwrdm",
  61         .prcm_offs        = OMAP4430_PRM_GFX_INST,
  62         .prcm_partition   = OMAP4430_PRM_PARTITION,
  63         .pwrsts           = PWRSTS_OFF_ON,
  64         .banks            = 1,
  65         .pwrsts_mem_ret = {
  66                 [0] = PWRSTS_OFF,       /* gfx_mem */
  67         },
  68         .pwrsts_mem_on  = {
  69                 [0] = PWRSTS_ON,        /* gfx_mem */
  70         },
  71         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  72 };
  73
  74 /* abe_44xx_pwrdm: Audio back end power domain */
  75 static struct powerdomain abe_44xx_pwrdm = {
  76         .name             = "abe_pwrdm",
  77         .prcm_offs        = OMAP4430_PRM_ABE_INST,
  78         .prcm_partition   = OMAP4430_PRM_PARTITION,
  79         .pwrsts           = PWRSTS_OFF_RET_ON,
  80         .pwrsts_logic_ret = PWRSTS_OFF,
  81         .banks            = 2,
  82         .pwrsts_mem_ret = {
  83                 [0] = PWRSTS_RET,       /* aessmem */
  84                 [1] = PWRSTS_OFF,       /* periphmem */
  85         },
  86         .pwrsts_mem_on  = {
  87                 [0] = PWRSTS_ON,        /* aessmem */
  88                 [1] = PWRSTS_ON,        /* periphmem */
  89         },
  90         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
  91 };
  92
  93 /* dss_44xx_pwrdm: Display subsystem power domain */
  94 static struct powerdomain dss_44xx_pwrdm = {
  95         .name             = "dss_pwrdm",
  96         .prcm_offs        = OMAP4430_PRM_DSS_INST,
  97         .prcm_partition   = OMAP4430_PRM_PARTITION,
  98         .pwrsts           = PWRSTS_OFF_RET_ON,
  99         .pwrsts_logic_ret = PWRSTS_OFF,
 100         .banks            = 1,
 101         .pwrsts_mem_ret = {
 102                 [0] = PWRSTS_OFF,       /* dss_mem */
 103         },
 104         .pwrsts_mem_on  = {
 105                 [0] = PWRSTS_ON,        /* dss_mem */
 106         },
 107         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 108 };
 109
 110 /* tesla_44xx_pwrdm: Tesla processor power domain */
 111 static struct powerdomain tesla_44xx_pwrdm = {
 112         .name             = "tesla_pwrdm",
 113         .prcm_offs        = OMAP4430_PRM_TESLA_INST,
 114         .prcm_partition   = OMAP4430_PRM_PARTITION,
 115         .pwrsts           = PWRSTS_OFF_RET_ON,
 116         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 117         .banks            = 3,
 118         .pwrsts_mem_ret = {
 119                 [0] = PWRSTS_RET,       /* tesla_edma */
 120                 [1] = PWRSTS_OFF_RET,   /* tesla_l1 */
 121                 [2] = PWRSTS_OFF_RET,   /* tesla_l2 */
 122         },
 123         .pwrsts_mem_on  = {
 124                 [0] = PWRSTS_ON,        /* tesla_edma */
 125                 [1] = PWRSTS_ON,        /* tesla_l1 */
 126                 [2] = PWRSTS_ON,        /* tesla_l2 */
 127         },
 128         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 129 };
 130
 131 /* wkup_44xx_pwrdm: Wake-up power domain */
 132 static struct powerdomain wkup_44xx_pwrdm = {
 133         .name             = "wkup_pwrdm",
 134         .prcm_offs        = OMAP4430_PRM_WKUP_INST,
 135         .prcm_partition   = OMAP4430_PRM_PARTITION,
 136         .pwrsts           = PWRSTS_ON,
 137         .banks            = 1,
 138         .pwrsts_mem_ret = {
 139                 [0] = PWRSTS_OFF,       /* wkup_bank */
 140         },
 141         .pwrsts_mem_on  = {
 142                 [0] = PWRSTS_ON,        /* wkup_bank */
 143         },
 144 };
 145
 146 /* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
 147 static struct powerdomain cpu0_44xx_pwrdm = {
 148         .name             = "cpu0_pwrdm",
 149         .prcm_offs        = OMAP4430_PRCM_MPU_CPU0_INST,
 150         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
 151         .pwrsts           = PWRSTS_OFF_RET_ON,
 152         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 153         .banks            = 1,
 154         .pwrsts_mem_ret = {
 155                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
 156         },
 157         .pwrsts_mem_on  = {
 158                 [0] = PWRSTS_ON,        /* cpu0_l1 */
 159         },
 160 };
 161
 162 /* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
 163 static struct powerdomain cpu1_44xx_pwrdm = {
 164         .name             = "cpu1_pwrdm",
 165         .prcm_offs        = OMAP4430_PRCM_MPU_CPU1_INST,
 166         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
 167         .pwrsts           = PWRSTS_OFF_RET_ON,
 168         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 169         .banks            = 1,
 170         .pwrsts_mem_ret = {
 171                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
 172         },
 173         .pwrsts_mem_on  = {
 174                 [0] = PWRSTS_ON,        /* cpu1_l1 */
 175         },
 176 };
 177
 178 /* emu_44xx_pwrdm: Emulation power domain */
 179 static struct powerdomain emu_44xx_pwrdm = {
 180         .name             = "emu_pwrdm",
 181         .prcm_offs        = OMAP4430_PRM_EMU_INST,
 182         .prcm_partition   = OMAP4430_PRM_PARTITION,
 183         .pwrsts           = PWRSTS_OFF_ON,
 184         .banks            = 1,
 185         .pwrsts_mem_ret = {
 186                 [0] = PWRSTS_OFF,       /* emu_bank */
 187         },
 188         .pwrsts_mem_on  = {
 189                 [0] = PWRSTS_ON,        /* emu_bank */
 190         },
 191 };
 192
 193 /* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
 194 static struct powerdomain mpu_44xx_pwrdm = {
 195         .name             = "mpu_pwrdm",
 196         .prcm_offs        = OMAP4430_PRM_MPU_INST,
 197         .prcm_partition   = OMAP4430_PRM_PARTITION,
 198         .pwrsts           = PWRSTS_RET_ON,
 199         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 200         .banks            = 3,
 201         .pwrsts_mem_ret = {
 202                 [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
 203                 [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
 204                 [2] = PWRSTS_RET,       /* mpu_ram */
 205         },
 206         .pwrsts_mem_on  = {
 207                 [0] = PWRSTS_ON,        /* mpu_l1 */
 208                 [1] = PWRSTS_ON,        /* mpu_l2 */
 209                 [2] = PWRSTS_ON,        /* mpu_ram */
 210         },
 211 };
 212
 213 /* ivahd_44xx_pwrdm: IVA-HD power domain */
 214 static struct powerdomain ivahd_44xx_pwrdm = {
 215         .name             = "ivahd_pwrdm",
 216         .prcm_offs        = OMAP4430_PRM_IVAHD_INST,
 217         .prcm_partition   = OMAP4430_PRM_PARTITION,
 218         .pwrsts           = PWRSTS_OFF_RET_ON,
 219         .pwrsts_logic_ret = PWRSTS_OFF,
 220         .banks            = 4,
 221         .pwrsts_mem_ret = {
 222                 [0] = PWRSTS_OFF,       /* hwa_mem */
 223                 [1] = PWRSTS_OFF_RET,   /* sl2_mem */
 224                 [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
 225                 [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
 226         },
 227         .pwrsts_mem_on  = {
 228                 [0] = PWRSTS_ON,        /* hwa_mem */
 229                 [1] = PWRSTS_ON,        /* sl2_mem */
 230                 [2] = PWRSTS_ON,        /* tcm1_mem */
 231                 [3] = PWRSTS_ON,        /* tcm2_mem */
 232         },
 233         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 234 };
 235
 236 /* cam_44xx_pwrdm: Camera subsystem power domain */
 237 static struct powerdomain cam_44xx_pwrdm = {
 238         .name             = "cam_pwrdm",
 239         .prcm_offs        = OMAP4430_PRM_CAM_INST,
 240         .prcm_partition   = OMAP4430_PRM_PARTITION,
 241         .pwrsts           = PWRSTS_OFF_ON,
 242         .banks            = 1,
 243         .pwrsts_mem_ret = {
 244                 [0] = PWRSTS_OFF,       /* cam_mem */
 245         },
 246         .pwrsts_mem_on  = {
 247                 [0] = PWRSTS_ON,        /* cam_mem */
 248         },
 249         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 250 };
 251
 252 /* l3init_44xx_pwrdm: L3 initators pheripherals power domain  */
 253 static struct powerdomain l3init_44xx_pwrdm = {
 254         .name             = "l3init_pwrdm",
 255         .prcm_offs        = OMAP4430_PRM_L3INIT_INST,
 256         .prcm_partition   = OMAP4430_PRM_PARTITION,
 257         .pwrsts           = PWRSTS_RET_ON,
 258         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 259         .banks            = 1,
 260         .pwrsts_mem_ret = {
 261                 [0] = PWRSTS_OFF,       /* l3init_bank1 */
 262         },
 263         .pwrsts_mem_on  = {
 264                 [0] = PWRSTS_ON,        /* l3init_bank1 */
 265         },
 266         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 267 };
 268
 269 /* l4per_44xx_pwrdm: Target peripherals power domain */
 270 static struct powerdomain l4per_44xx_pwrdm = {
 271         .name             = "l4per_pwrdm",
 272         .prcm_offs        = OMAP4430_PRM_L4PER_INST,
 273         .prcm_partition   = OMAP4430_PRM_PARTITION,
 274         .pwrsts           = PWRSTS_RET_ON,
 275         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 276         .banks            = 2,
 277         .pwrsts_mem_ret = {
 278                 [0] = PWRSTS_OFF,       /* nonretained_bank */
 279                 [1] = PWRSTS_RET,       /* retained_bank */
 280         },
 281         .pwrsts_mem_on  = {
 282                 [0] = PWRSTS_ON,        /* nonretained_bank */
 283                 [1] = PWRSTS_ON,        /* retained_bank */
 284         },
 285         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 286 };
 287
 288 /*
 289  * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
 290  * domain
 291  */
 292 static struct powerdomain always_on_core_44xx_pwrdm = {
 293         .name             = "always_on_core_pwrdm",
 294         .prcm_offs        = OMAP4430_PRM_ALWAYS_ON_INST,
 295         .prcm_partition   = OMAP4430_PRM_PARTITION,
 296         .pwrsts           = PWRSTS_ON,
 297 };
 298
 299 /* cefuse_44xx_pwrdm: Customer efuse controller power domain */
 300 static struct powerdomain cefuse_44xx_pwrdm = {
 301         .name             = "cefuse_pwrdm",
 302         .prcm_offs        = OMAP4430_PRM_CEFUSE_INST,
 303         .prcm_partition   = OMAP4430_PRM_PARTITION,
 304         .pwrsts           = PWRSTS_OFF_ON,
 305         .flags            = PWRDM_HAS_LOWPOWERSTATECHANGE,
 306 };
 307
 308 /*
 309  * The following power domains are not under SW control
 310  *
 311  * always_on_iva
 312  * always_on_mpu
 313  * stdefuse
 314  */
 315
 316 /* As powerdomains are added or removed above, this list must also be changed */
 317 static struct powerdomain *powerdomains_omap44xx[] __initdata = {
 318         &core_44xx_pwrdm,
 319         &gfx_44xx_pwrdm,
 320         &abe_44xx_pwrdm,
 321         &dss_44xx_pwrdm,
 322         &tesla_44xx_pwrdm,
 323         &wkup_44xx_pwrdm,
 324         &cpu0_44xx_pwrdm,
 325         &cpu1_44xx_pwrdm,
 326         &emu_44xx_pwrdm,
 327         &mpu_44xx_pwrdm,
 328         &ivahd_44xx_pwrdm,
 329         &cam_44xx_pwrdm,
 330         &l3init_44xx_pwrdm,
 331         &l4per_44xx_pwrdm,
 332         &always_on_core_44xx_pwrdm,
 333         &cefuse_44xx_pwrdm,
 334         NULL
 335 };
 336
 337 void __init omap44xx_powerdomains_init(void)
 338 {
 339         pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
 340         pwrdm_register_pwrdms(powerdomains_omap44xx);
 341         pwrdm_complete_init();
 342 }