arch/arm/mach-omap2/powerdomains34xx.h

   1 /*
   2  * OMAP3 powerdomain definitions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  *
   7  * Written by Paul Walmsley
   8  * Debugging and integration fixes by Jouni Högander
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  16 #define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
  17
  18 /*
  19  * N.B. If powerdomains are added or removed from this file, update
  20  * the array in mach-omap2/powerdomains.h.
  21  */
  22
  23 #include <plat/powerdomain.h>
  24
  25 #include "prcm-common.h"
  26 #include "prm.h"
  27 #include "prm-regbits-34xx.h"
  28 #include "cm.h"
  29 #include "cm-regbits-34xx.h"
  30
  31 /*
  32  * 34XX-specific powerdomains, dependencies
  33  */
  34
  35 #ifdef CONFIG_ARCH_OMAP3
  36
  37 /*
  38  * Powerdomains
  39  */
  40
  41 static struct powerdomain iva2_pwrdm = {
  42         .name             = "iva2_pwrdm",
  43         .prcm_offs        = OMAP3430_IVA2_MOD,
  44         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  45         .pwrsts           = PWRSTS_OFF_RET_ON,
  46         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  47         .banks            = 4,
  48         .pwrsts_mem_ret   = {
  49                 [0] = PWRSTS_OFF_RET,
  50                 [1] = PWRSTS_OFF_RET,
  51                 [2] = PWRSTS_OFF_RET,
  52                 [3] = PWRSTS_OFF_RET,
  53         },
  54         .pwrsts_mem_on    = {
  55                 [0] = PWRDM_POWER_ON,
  56                 [1] = PWRDM_POWER_ON,
  57                 [2] = PWRSTS_OFF_ON,
  58                 [3] = PWRDM_POWER_ON,
  59         },
  60 };
  61
  62 static struct powerdomain mpu_3xxx_pwrdm = {
  63         .name             = "mpu_pwrdm",
  64         .prcm_offs        = MPU_MOD,
  65         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
  66         .pwrsts           = PWRSTS_OFF_RET_ON,
  67         .pwrsts_logic_ret = PWRSTS_OFF_RET,
  68         .flags            = PWRDM_HAS_MPU_QUIRK,
  69         .banks            = 1,
  70         .pwrsts_mem_ret   = {
  71                 [0] = PWRSTS_OFF_RET,
  72         },
  73         .pwrsts_mem_on    = {
  74                 [0] = PWRSTS_OFF_ON,
  75         },
  76 };
  77
  78 static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
  79         .name             = "core_pwrdm",
  80         .prcm_offs        = CORE_MOD,
  81         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
  82                                            CHIP_IS_OMAP3430ES2 |
  83                                            CHIP_IS_OMAP3430ES3_0),
  84         .pwrsts           = PWRSTS_OFF_RET_ON,
  85         .banks            = 2,
  86         .pwrsts_mem_ret   = {
  87                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
  88                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
  89         },
  90         .pwrsts_mem_on    = {
  91                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
  92                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
  93         },
  94 };
  95
  96 static struct powerdomain core_3xxx_es3_1_pwrdm = {
  97         .name             = "core_pwrdm",
  98         .prcm_offs        = CORE_MOD,
  99         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1),
 100         .pwrsts           = PWRSTS_OFF_RET_ON,
 101         .flags            = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
 102         .banks            = 2,
 103         .pwrsts_mem_ret   = {
 104                 [0] = PWRSTS_OFF_RET,    /* MEM1RETSTATE */
 105                 [1] = PWRSTS_OFF_RET,    /* MEM2RETSTATE */
 106         },
 107         .pwrsts_mem_on    = {
 108                 [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
 109                 [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
 110         },
 111 };
 112
 113 static struct powerdomain dss_pwrdm = {
 114         .name             = "dss_pwrdm",
 115         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 116         .prcm_offs        = OMAP3430_DSS_MOD,
 117         .pwrsts           = PWRSTS_OFF_RET_ON,
 118         .pwrsts_logic_ret = PWRDM_POWER_RET,
 119         .banks            = 1,
 120         .pwrsts_mem_ret   = {
 121                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 122         },
 123         .pwrsts_mem_on    = {
 124                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 125         },
 126 };
 127
 128 /*
 129  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 130  * possible SGX powerstate, the SGX device itself does not support
 131  * retention.
 132  */
 133 static struct powerdomain sgx_pwrdm = {
 134         .name             = "sgx_pwrdm",
 135         .prcm_offs        = OMAP3430ES2_SGX_MOD,
 136         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 137         /* XXX This is accurate for 3430 SGX, but what about GFX? */
 138         .pwrsts           = PWRSTS_OFF_ON,
 139         .pwrsts_logic_ret = PWRDM_POWER_RET,
 140         .banks            = 1,
 141         .pwrsts_mem_ret   = {
 142                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 143         },
 144         .pwrsts_mem_on    = {
 145                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 146         },
 147 };
 148
 149 static struct powerdomain cam_pwrdm = {
 150         .name             = "cam_pwrdm",
 151         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 152         .prcm_offs        = OMAP3430_CAM_MOD,
 153         .pwrsts           = PWRSTS_OFF_RET_ON,
 154         .pwrsts_logic_ret = PWRDM_POWER_RET,
 155         .banks            = 1,
 156         .pwrsts_mem_ret   = {
 157                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 158         },
 159         .pwrsts_mem_on    = {
 160                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 161         },
 162 };
 163
 164 static struct powerdomain per_pwrdm = {
 165         .name             = "per_pwrdm",
 166         .prcm_offs        = OMAP3430_PER_MOD,
 167         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 168         .pwrsts           = PWRSTS_OFF_RET_ON,
 169         .pwrsts_logic_ret = PWRSTS_OFF_RET,
 170         .banks            = 1,
 171         .pwrsts_mem_ret   = {
 172                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 173         },
 174         .pwrsts_mem_on    = {
 175                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 176         },
 177 };
 178
 179 static struct powerdomain emu_pwrdm = {
 180         .name           = "emu_pwrdm",
 181         .prcm_offs      = OMAP3430_EMU_MOD,
 182         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 183 };
 184
 185 static struct powerdomain neon_pwrdm = {
 186         .name             = "neon_pwrdm",
 187         .prcm_offs        = OMAP3430_NEON_MOD,
 188         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 189         .pwrsts           = PWRSTS_OFF_RET_ON,
 190         .pwrsts_logic_ret = PWRDM_POWER_RET,
 191 };
 192
 193 static struct powerdomain usbhost_pwrdm = {
 194         .name             = "usbhost_pwrdm",
 195         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
 196         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 197         .pwrsts           = PWRSTS_OFF_RET_ON,
 198         .pwrsts_logic_ret = PWRDM_POWER_RET,
 199         /*
 200          * REVISIT: Enabling usb host save and restore mechanism seems to
 201          * leave the usb host domain permanently in ACTIVE mode after
 202          * changing the usb host power domain state from OFF to active once.
 203          * Disabling for now.
 204          */
 205         /*.flags          = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
 206         .banks            = 1,
 207         .pwrsts_mem_ret   = {
 208                 [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
 209         },
 210         .pwrsts_mem_on    = {
 211                 [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
 212         },
 213 };
 214
 215 static struct powerdomain dpll1_pwrdm = {
 216         .name           = "dpll1_pwrdm",
 217         .prcm_offs      = MPU_MOD,
 218         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 219 };
 220
 221 static struct powerdomain dpll2_pwrdm = {
 222         .name           = "dpll2_pwrdm",
 223         .prcm_offs      = OMAP3430_IVA2_MOD,
 224         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 225 };
 226
 227 static struct powerdomain dpll3_pwrdm = {
 228         .name           = "dpll3_pwrdm",
 229         .prcm_offs      = PLL_MOD,
 230         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 231 };
 232
 233 static struct powerdomain dpll4_pwrdm = {
 234         .name           = "dpll4_pwrdm",
 235         .prcm_offs      = PLL_MOD,
 236         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 237 };
 238
 239 static struct powerdomain dpll5_pwrdm = {
 240         .name           = "dpll5_pwrdm",
 241         .prcm_offs      = PLL_MOD,
 242         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 243 };
 244
 245
 246 #endif    /* CONFIG_ARCH_OMAP3 */
 247
 248
 249 #endif