arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/suspend.h>
  35
  36 #include <plat/sram.h>
  37 #include "clockdomain.h"
  38 #include "powerdomain.h"
  39 #include <plat/serial.h>
  40 #include <plat/sdrc.h>
  41 #include <plat/prcm.h>
  42 #include <plat/gpmc.h>
  43 #include <plat/dma.h>
  44
  45 #include "cm2xxx_3xxx.h"
  46 #include "cm-regbits-34xx.h"
  47 #include "prm-regbits-34xx.h"
  48
  49 #include "prm2xxx_3xxx.h"
  50 #include "pm.h"
  51 #include "sdrc.h"
  52 #include "control.h"
  53
  54 #ifdef CONFIG_SUSPEND
  55 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  56 static inline bool is_suspending(void)
  57 {
  58         return (suspend_state != PM_SUSPEND_ON);
  59 }
  60 #else
  61 static inline bool is_suspending(void)
  62 {
  63         return false;
  64 }
  65 #endif
  66
  67 /* pm34xx errata defined in pm.h */
  68 u16 pm34xx_errata;
  69
  70 struct power_state {
  71         struct powerdomain *pwrdm;
  72         u32 next_state;
  73 #ifdef CONFIG_SUSPEND
  74         u32 saved_state;
  75 #endif
  76         struct list_head node;
  77 };
  78
  79 static LIST_HEAD(pwrst_list);
  80
  81 static int (*_omap_save_secure_sram)(u32 *addr);
  82 void (*omap3_do_wfi_sram)(void);
  83
  84 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  85 static struct powerdomain *core_pwrdm, *per_pwrdm;
  86 static struct powerdomain *cam_pwrdm;
  87
  88 static inline void omap3_per_save_context(void)
  89 {
  90         omap_gpio_save_context();
  91 }
  92
  93 static inline void omap3_per_restore_context(void)
  94 {
  95         omap_gpio_restore_context();
  96 }
  97
  98 static void omap3_enable_io_chain(void)
  99 {
 100         int timeout = 0;
 101
 102         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 103                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 104                                      PM_WKEN);
 105                 /* Do a readback to assure write has been done */
 106                 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 107
 108                 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 109                          OMAP3430_ST_IO_CHAIN_MASK)) {
 110                         timeout++;
 111                         if (timeout > 1000) {
 112                                 printk(KERN_ERR "Wake up daisy chain "
 113                                        "activation failed.\n");
 114                                 return;
 115                         }
 116                         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 117                                              WKUP_MOD, PM_WKEN);
 118                 }
 119         }
 120 }
 121
 122 static void omap3_disable_io_chain(void)
 123 {
 124         if (omap_rev() >= OMAP3430_REV_ES3_1)
 125                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 126                                        PM_WKEN);
 127 }
 128
 129 static void omap3_core_save_context(void)
 130 {
 131         omap3_ctrl_save_padconf();
 132
 133         /*
 134          * Force write last pad into memory, as this can fail in some
 135          * cases according to errata 1.157, 1.185
 136          */
 137         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 138                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 139
 140         /* Save the Interrupt controller context */
 141         omap_intc_save_context();
 142         /* Save the GPMC context */
 143         omap3_gpmc_save_context();
 144         /* Save the system control module context, padconf already save above*/
 145         omap3_control_save_context();
 146         omap_dma_global_context_save();
 147 }
 148
 149 static void omap3_core_restore_context(void)
 150 {
 151         /* Restore the control module context, padconf restored by h/w */
 152         omap3_control_restore_context();
 153         /* Restore the GPMC context */
 154         omap3_gpmc_restore_context();
 155         /* Restore the interrupt controller context */
 156         omap_intc_restore_context();
 157         omap_dma_global_context_restore();
 158 }
 159
 160 /*
 161  * FIXME: This function should be called before entering off-mode after
 162  * OMAP3 secure services have been accessed. Currently it is only called
 163  * once during boot sequence, but this works as we are not using secure
 164  * services.
 165  */
 166 static void omap3_save_secure_ram_context(void)
 167 {
 168         u32 ret;
 169         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 170
 171         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 172                 /*
 173                  * MPU next state must be set to POWER_ON temporarily,
 174                  * otherwise the WFI executed inside the ROM code
 175                  * will hang the system.
 176                  */
 177                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 178                 ret = _omap_save_secure_sram((u32 *)
 179                                 __pa(omap3_secure_ram_storage));
 180                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 181                 /* Following is for error tracking, it should not happen */
 182                 if (ret) {
 183                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 184                                 ret);
 185                         while (1)
 186                                 ;
 187                 }
 188         }
 189 }
 190
 191 /*
 192  * PRCM Interrupt Handler Helper Function
 193  *
 194  * The purpose of this function is to clear any wake-up events latched
 195  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 196  * may occur whilst attempting to clear a PM_WKST_x register and thus
 197  * set another bit in this register. A while loop is used to ensure
 198  * that any peripheral wake-up events occurring while attempting to
 199  * clear the PM_WKST_x are detected and cleared.
 200  */
 201 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 202 {
 203         u32 wkst, fclk, iclk, clken;
 204         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 205         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 206         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 207         u16 grpsel_off = (regs == 3) ?
 208                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 209         int c = 0;
 210
 211         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 212         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 213         if (wkst) {
 214                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 215                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 216                 while (wkst) {
 217                         clken = wkst;
 218                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 219                         /*
 220                          * For USBHOST, we don't know whether HOST1 or
 221                          * HOST2 woke us up, so enable both f-clocks
 222                          */
 223                         if (module == OMAP3430ES2_USBHOST_MOD)
 224                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 225                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 226                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 227                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 228                         c++;
 229                 }
 230                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 231                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 232         }
 233
 234         return c;
 235 }
 236
 237 static int _prcm_int_handle_wakeup(void)
 238 {
 239         int c;
 240
 241         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 242         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 243         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 244         if (omap_rev() > OMAP3430_REV_ES1_0) {
 245                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 246                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 247         }
 248
 249         return c;
 250 }
 251
 252 /*
 253  * PRCM Interrupt Handler
 254  *
 255  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 256  * interrupts from the PRCM for the MPU. These bits must be cleared in
 257  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 258  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 259  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 260  * register indicates that a wake-up event is pending for the MPU and
 261  * this bit can only be cleared if the all the wake-up events latched
 262  * in the various PM_WKST_x registers have been cleared. The interrupt
 263  * handler is implemented using a do-while loop so that if a wake-up
 264  * event occurred during the processing of the prcm interrupt handler
 265  * (setting a bit in the corresponding PM_WKST_x register and thus
 266  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 267  * this would be handled.
 268  */
 269 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 270 {
 271         u32 irqenable_mpu, irqstatus_mpu;
 272         int c = 0;
 273
 274         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 275                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 276         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 277                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 278         irqstatus_mpu &= irqenable_mpu;
 279
 280         do {
 281                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 282                                      OMAP3430_IO_ST_MASK)) {
 283                         c = _prcm_int_handle_wakeup();
 284
 285                         /*
 286                          * Is the MPU PRCM interrupt handler racing with the
 287                          * IVA2 PRCM interrupt handler ?
 288                          */
 289                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 290                              "but no wakeup sources are marked\n");
 291                 } else {
 292                         /* XXX we need to expand our PRCM interrupt handler */
 293                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 294                              "no code to handle it (%08x)\n", irqstatus_mpu);
 295                 }
 296
 297                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 298                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 299
 300                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 301                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 302                 irqstatus_mpu &= irqenable_mpu;
 303
 304         } while (irqstatus_mpu);
 305
 306         return IRQ_HANDLED;
 307 }
 308
 309 static void omap34xx_save_context(u32 *save)
 310 {
 311         u32 val;
 312
 313         /* Read Auxiliary Control Register */
 314         asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
 315         *save++ = 1;
 316         *save++ = val;
 317
 318         /* Read L2 AUX ctrl register */
 319         asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
 320         *save++ = 1;
 321         *save++ = val;
 322 }
 323
 324 static int omap34xx_do_sram_idle(unsigned long save_state)
 325 {
 326         omap34xx_cpu_suspend(save_state);
 327         return 0;
 328 }
 329
 330 void omap_sram_idle(void)
 331 {
 332         /* Variable to tell what needs to be saved and restored
 333          * in omap_sram_idle*/
 334         /* save_state = 0 => Nothing to save and restored */
 335         /* save_state = 1 => Only L1 and logic lost */
 336         /* save_state = 2 => Only L2 lost */
 337         /* save_state = 3 => L1, L2 and logic lost */
 338         int save_state = 0;
 339         int mpu_next_state = PWRDM_POWER_ON;
 340         int per_next_state = PWRDM_POWER_ON;
 341         int core_next_state = PWRDM_POWER_ON;
 342         int per_going_off;
 343         int core_prev_state, per_prev_state;
 344         u32 sdrc_pwr = 0;
 345
 346         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 347         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 348         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 349         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 350
 351         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 352         switch (mpu_next_state) {
 353         case PWRDM_POWER_ON:
 354         case PWRDM_POWER_RET:
 355                 /* No need to save context */
 356                 save_state = 0;
 357                 break;
 358         case PWRDM_POWER_OFF:
 359                 save_state = 3;
 360                 break;
 361         default:
 362                 /* Invalid state */
 363                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 364                 return;
 365         }
 366
 367         /* NEON control */
 368         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 369                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 370
 371         /* Enable IO-PAD and IO-CHAIN wakeups */
 372         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 373         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 374         if (omap3_has_io_wakeup() &&
 375             (per_next_state < PWRDM_POWER_ON ||
 376              core_next_state < PWRDM_POWER_ON)) {
 377                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 378                 omap3_enable_io_chain();
 379         }
 380
 381         /* Block console output in case it is on one of the OMAP UARTs */
 382         if (!is_suspending())
 383                 if (per_next_state < PWRDM_POWER_ON ||
 384                     core_next_state < PWRDM_POWER_ON)
 385                         if (!console_trylock())
 386                                 goto console_still_active;
 387
 388         pwrdm_pre_transition();
 389
 390         /* PER */
 391         if (per_next_state < PWRDM_POWER_ON) {
 392                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 393                 omap_uart_prepare_idle(2);
 394                 omap_uart_prepare_idle(3);
 395                 omap2_gpio_prepare_for_idle(per_going_off);
 396                 if (per_next_state == PWRDM_POWER_OFF)
 397                                 omap3_per_save_context();
 398         }
 399
 400         /* CORE */
 401         if (core_next_state < PWRDM_POWER_ON) {
 402                 omap_uart_prepare_idle(0);
 403                 omap_uart_prepare_idle(1);
 404                 if (core_next_state == PWRDM_POWER_OFF) {
 405                         omap3_core_save_context();
 406                         omap3_cm_save_context();
 407                 }
 408         }
 409
 410         omap3_intc_prepare_idle();
 411
 412         /*
 413         * On EMU/HS devices ROM code restores a SRDC value
 414         * from scratchpad which has automatic self refresh on timeout
 415         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 416         * Hence store/restore the SDRC_POWER register here.
 417         */
 418         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 419             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 420             core_next_state == PWRDM_POWER_OFF)
 421                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 422
 423         /*
 424          * omap3_arm_context is the location where some ARM context
 425          * get saved. The rest is placed on the stack, and restored
 426          * from there before resuming.
 427          */
 428         if (save_state)
 429                 omap34xx_save_context(omap3_arm_context);
 430         if (save_state == 1 || save_state == 3)
 431                 cpu_suspend(save_state, omap34xx_do_sram_idle);
 432         else
 433                 omap34xx_do_sram_idle(save_state);
 434
 435         /* Restore normal SDRC POWER settings */
 436         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 437             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 438             core_next_state == PWRDM_POWER_OFF)
 439                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 440
 441         /* CORE */
 442         if (core_next_state < PWRDM_POWER_ON) {
 443                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 444                 if (core_prev_state == PWRDM_POWER_OFF) {
 445                         omap3_core_restore_context();
 446                         omap3_cm_restore_context();
 447                         omap3_sram_restore_context();
 448                         omap2_sms_restore_context();
 449                 }
 450                 omap_uart_resume_idle(0);
 451                 omap_uart_resume_idle(1);
 452                 if (core_next_state == PWRDM_POWER_OFF)
 453                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 454                                                OMAP3430_GR_MOD,
 455                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 456         }
 457         omap3_intc_resume_idle();
 458
 459         pwrdm_post_transition();
 460
 461         /* PER */
 462         if (per_next_state < PWRDM_POWER_ON) {
 463                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 464                 omap2_gpio_resume_after_idle();
 465                 if (per_prev_state == PWRDM_POWER_OFF)
 466                         omap3_per_restore_context();
 467                 omap_uart_resume_idle(2);
 468                 omap_uart_resume_idle(3);
 469         }
 470
 471         if (!is_suspending())
 472                 console_unlock();
 473
 474 console_still_active:
 475         /* Disable IO-PAD and IO-CHAIN wakeup */
 476         if (omap3_has_io_wakeup() &&
 477             (per_next_state < PWRDM_POWER_ON ||
 478              core_next_state < PWRDM_POWER_ON)) {
 479                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 480                                              PM_WKEN);
 481                 omap3_disable_io_chain();
 482         }
 483
 484         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 485 }
 486
 487 int omap3_can_sleep(void)
 488 {
 489         if (!omap_uart_can_sleep())
 490                 return 0;
 491         return 1;
 492 }
 493
 494 static void omap3_pm_idle(void)
 495 {
 496         local_irq_disable();
 497         local_fiq_disable();
 498
 499         if (!omap3_can_sleep())
 500                 goto out;
 501
 502         if (omap_irq_pending() || need_resched())
 503                 goto out;
 504
 505         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 506         trace_cpu_idle(1, smp_processor_id());
 507
 508         omap_sram_idle();
 509
 510         trace_power_end(smp_processor_id());
 511         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 512
 513 out:
 514         local_fiq_enable();
 515         local_irq_enable();
 516 }
 517
 518 #ifdef CONFIG_SUSPEND
 519 static int omap3_pm_suspend(void)
 520 {
 521         struct power_state *pwrst;
 522         int state, ret = 0;
 523
 524         /* Read current next_pwrsts */
 525         list_for_each_entry(pwrst, &pwrst_list, node)
 526                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 527         /* Set ones wanted by suspend */
 528         list_for_each_entry(pwrst, &pwrst_list, node) {
 529                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 530                         goto restore;
 531                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 532                         goto restore;
 533         }
 534
 535         omap_uart_prepare_suspend();
 536         omap3_intc_suspend();
 537
 538         omap_sram_idle();
 539
 540 restore:
 541         /* Restore next_pwrsts */
 542         list_for_each_entry(pwrst, &pwrst_list, node) {
 543                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 544                 if (state > pwrst->next_state) {
 545                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 546                                "target state %d\n",
 547                                pwrst->pwrdm->name, pwrst->next_state);
 548                         ret = -1;
 549                 }
 550                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 551         }
 552         if (ret)
 553                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 554         else
 555                 printk(KERN_INFO "Successfully put all powerdomains "
 556                        "to target state\n");
 557
 558         return ret;
 559 }
 560
 561 static int omap3_pm_enter(suspend_state_t unused)
 562 {
 563         int ret = 0;
 564
 565         switch (suspend_state) {
 566         case PM_SUSPEND_STANDBY:
 567         case PM_SUSPEND_MEM:
 568                 ret = omap3_pm_suspend();
 569                 break;
 570         default:
 571                 ret = -EINVAL;
 572         }
 573
 574         return ret;
 575 }
 576
 577 /* Hooks to enable / disable UART interrupts during suspend */
 578 static int omap3_pm_begin(suspend_state_t state)
 579 {
 580         disable_hlt();
 581         suspend_state = state;
 582         omap_uart_enable_irqs(0);
 583         return 0;
 584 }
 585
 586 static void omap3_pm_end(void)
 587 {
 588         suspend_state = PM_SUSPEND_ON;
 589         omap_uart_enable_irqs(1);
 590         enable_hlt();
 591         return;
 592 }
 593
 594 static const struct platform_suspend_ops omap_pm_ops = {
 595         .begin          = omap3_pm_begin,
 596         .end            = omap3_pm_end,
 597         .enter          = omap3_pm_enter,
 598         .valid          = suspend_valid_only_mem,
 599 };
 600 #endif /* CONFIG_SUSPEND */
 601
 602
 603 /**
 604  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 605  *                   retention
 606  *
 607  * In cases where IVA2 is activated by bootcode, it may prevent
 608  * full-chip retention or off-mode because it is not idle.  This
 609  * function forces the IVA2 into idle state so it can go
 610  * into retention/off and thus allow full-chip retention/off.
 611  *
 612  **/
 613 static void __init omap3_iva_idle(void)
 614 {
 615         /* ensure IVA2 clock is disabled */
 616         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 617
 618         /* if no clock activity, nothing else to do */
 619         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 620               OMAP3430_CLKACTIVITY_IVA2_MASK))
 621                 return;
 622
 623         /* Reset IVA2 */
 624         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 625                           OMAP3430_RST2_IVA2_MASK |
 626                           OMAP3430_RST3_IVA2_MASK,
 627                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 628
 629         /* Enable IVA2 clock */
 630         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 631                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 632
 633         /* Set IVA2 boot mode to 'idle' */
 634         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 635                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 636
 637         /* Un-reset IVA2 */
 638         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 639
 640         /* Disable IVA2 clock */
 641         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 642
 643         /* Reset IVA2 */
 644         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 645                           OMAP3430_RST2_IVA2_MASK |
 646                           OMAP3430_RST3_IVA2_MASK,
 647                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 648 }
 649
 650 static void __init omap3_d2d_idle(void)
 651 {
 652         u16 mask, padconf;
 653
 654         /* In a stand alone OMAP3430 where there is not a stacked
 655          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 656          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 657          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 658         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 659         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 660         padconf |= mask;
 661         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 662
 663         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 664         padconf |= mask;
 665         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 666
 667         /* reset modem */
 668         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 669                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 670                           CORE_MOD, OMAP2_RM_RSTCTRL);
 671         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 672 }
 673
 674 static void __init prcm_setup_regs(void)
 675 {
 676         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 677                                         OMAP3630_EN_UART4_MASK : 0;
 678         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 679                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 680
 681         /* XXX This should be handled by hwmod code or SCM init code */
 682         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 683
 684         /*
 685          * Enable control of expternal oscillator through
 686          * sys_clkreq. In the long run clock framework should
 687          * take care of this.
 688          */
 689         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 690                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 691                              OMAP3430_GR_MOD,
 692                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 693
 694         /* setup wakup source */
 695         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 696                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 697                           WKUP_MOD, PM_WKEN);
 698         /* No need to write EN_IO, that is always enabled */
 699         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 700                           OMAP3430_GRPSEL_GPT1_MASK |
 701                           OMAP3430_GRPSEL_GPT12_MASK,
 702                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 703         /* For some reason IO doesn't generate wakeup event even if
 704          * it is selected to mpu wakeup goup */
 705         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 706                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 707
 708         /* Enable PM_WKEN to support DSS LPR */
 709         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 710                                 OMAP3430_DSS_MOD, PM_WKEN);
 711
 712         /* Enable wakeups in PER */
 713         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 714                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 715                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 716                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 717                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 718                           OMAP3430_EN_MCBSP4_MASK,
 719                           OMAP3430_PER_MOD, PM_WKEN);
 720         /* and allow them to wake up MPU */
 721         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 722                           OMAP3430_GRPSEL_GPIO2_MASK |
 723                           OMAP3430_GRPSEL_GPIO3_MASK |
 724                           OMAP3430_GRPSEL_GPIO4_MASK |
 725                           OMAP3430_GRPSEL_GPIO5_MASK |
 726                           OMAP3430_GRPSEL_GPIO6_MASK |
 727                           OMAP3430_GRPSEL_UART3_MASK |
 728                           OMAP3430_GRPSEL_MCBSP2_MASK |
 729                           OMAP3430_GRPSEL_MCBSP3_MASK |
 730                           OMAP3430_GRPSEL_MCBSP4_MASK,
 731                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 732
 733         /* Don't attach IVA interrupts */
 734         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 735         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 736         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 737         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 738
 739         /* Clear any pending 'reset' flags */
 740         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 741         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 742         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 743         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 744         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 745         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 746         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 747
 748         /* Clear any pending PRCM interrupts */
 749         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 750
 751         omap3_iva_idle();
 752         omap3_d2d_idle();
 753 }
 754
 755 void omap3_pm_off_mode_enable(int enable)
 756 {
 757         struct power_state *pwrst;
 758         u32 state;
 759
 760         if (enable)
 761                 state = PWRDM_POWER_OFF;
 762         else
 763                 state = PWRDM_POWER_RET;
 764
 765         list_for_each_entry(pwrst, &pwrst_list, node) {
 766                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 767                                 pwrst->pwrdm == core_pwrdm &&
 768                                 state == PWRDM_POWER_OFF) {
 769                         pwrst->next_state = PWRDM_POWER_RET;
 770                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 771                                 __func__);
 772                 } else {
 773                         pwrst->next_state = state;
 774                 }
 775                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 776         }
 777 }
 778
 779 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 780 {
 781         struct power_state *pwrst;
 782
 783         list_for_each_entry(pwrst, &pwrst_list, node) {
 784                 if (pwrst->pwrdm == pwrdm)
 785                         return pwrst->next_state;
 786         }
 787         return -EINVAL;
 788 }
 789
 790 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 791 {
 792         struct power_state *pwrst;
 793
 794         list_for_each_entry(pwrst, &pwrst_list, node) {
 795                 if (pwrst->pwrdm == pwrdm) {
 796                         pwrst->next_state = state;
 797                         return 0;
 798                 }
 799         }
 800         return -EINVAL;
 801 }
 802
 803 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 804 {
 805         struct power_state *pwrst;
 806
 807         if (!pwrdm->pwrsts)
 808                 return 0;
 809
 810         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 811         if (!pwrst)
 812                 return -ENOMEM;
 813         pwrst->pwrdm = pwrdm;
 814         pwrst->next_state = PWRDM_POWER_RET;
 815         list_add(&pwrst->node, &pwrst_list);
 816
 817         if (pwrdm_has_hdwr_sar(pwrdm))
 818                 pwrdm_enable_hdwr_sar(pwrdm);
 819
 820         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 821 }
 822
 823 /*
 824  * Enable hw supervised mode for all clockdomains if it's
 825  * supported. Initiate sleep transition for other clockdomains, if
 826  * they are not used
 827  */
 828 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 829 {
 830         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 831                 clkdm_allow_idle(clkdm);
 832         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 833                  atomic_read(&clkdm->usecount) == 0)
 834                 clkdm_sleep(clkdm);
 835         return 0;
 836 }
 837
 838 /*
 839  * Push functions to SRAM
 840  *
 841  * The minimum set of functions is pushed to SRAM for execution:
 842  * - omap3_do_wfi for erratum i581 WA,
 843  * - save_secure_ram_context for security extensions.
 844  */
 845 void omap_push_sram_idle(void)
 846 {
 847         omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
 848
 849         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 850                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 851                                 save_secure_ram_context_sz);
 852 }
 853
 854 static void __init pm_errata_configure(void)
 855 {
 856         if (cpu_is_omap3630()) {
 857                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 858                 /* Enable the l2 cache toggling in sleep logic */
 859                 enable_omap3630_toggle_l2_on_restore();
 860                 if (omap_rev() < OMAP3630_REV_ES1_2)
 861                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 862         }
 863 }
 864
 865 static int __init omap3_pm_init(void)
 866 {
 867         struct power_state *pwrst, *tmp;
 868         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 869         int ret;
 870
 871         if (!cpu_is_omap34xx())
 872                 return -ENODEV;
 873
 874         pm_errata_configure();
 875
 876         /* XXX prcm_setup_regs needs to be before enabling hw
 877          * supervised mode for powerdomains */
 878         prcm_setup_regs();
 879
 880         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 881                           (irq_handler_t)prcm_interrupt_handler,
 882                           IRQF_DISABLED, "prcm", NULL);
 883         if (ret) {
 884                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 885                        INT_34XX_PRCM_MPU_IRQ);
 886                 goto err1;
 887         }
 888
 889         ret = pwrdm_for_each(pwrdms_setup, NULL);
 890         if (ret) {
 891                 printk(KERN_ERR "Failed to setup powerdomains\n");
 892                 goto err2;
 893         }
 894
 895         (void) clkdm_for_each(clkdms_setup, NULL);
 896
 897         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 898         if (mpu_pwrdm == NULL) {
 899                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 900                 goto err2;
 901         }
 902
 903         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 904         per_pwrdm = pwrdm_lookup("per_pwrdm");
 905         core_pwrdm = pwrdm_lookup("core_pwrdm");
 906         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 907
 908         neon_clkdm = clkdm_lookup("neon_clkdm");
 909         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 910         per_clkdm = clkdm_lookup("per_clkdm");
 911         core_clkdm = clkdm_lookup("core_clkdm");
 912
 913 #ifdef CONFIG_SUSPEND
 914         suspend_set_ops(&omap_pm_ops);
 915 #endif /* CONFIG_SUSPEND */
 916
 917         pm_idle = omap3_pm_idle;
 918         omap3_idle_init();
 919
 920         /*
 921          * RTA is disabled during initialization as per erratum i608
 922          * it is safer to disable RTA by the bootloader, but we would like
 923          * to be doubly sure here and prevent any mishaps.
 924          */
 925         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 926                 omap3630_ctrl_disable_rta();
 927
 928         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 929         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 930                 omap3_secure_ram_storage =
 931                         kmalloc(0x803F, GFP_KERNEL);
 932                 if (!omap3_secure_ram_storage)
 933                         printk(KERN_ERR "Memory allocation failed when"
 934                                         "allocating for secure sram context\n");
 935
 936                 local_irq_disable();
 937                 local_fiq_disable();
 938
 939                 omap_dma_global_context_save();
 940                 omap3_save_secure_ram_context();
 941                 omap_dma_global_context_restore();
 942
 943                 local_irq_enable();
 944                 local_fiq_enable();
 945         }
 946
 947         omap3_save_scratchpad_contents();
 948 err1:
 949         return ret;
 950 err2:
 951         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 952         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 953                 list_del(&pwrst->node);
 954                 kfree(pwrst);
 955         }
 956         return ret;
 957 }
 958
 959 late_initcall(omap3_pm_init);