arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29
  30 #include <plat/sram.h>
  31 #include <plat/clockdomain.h>
  32 #include <plat/powerdomain.h>
  33 #include <plat/control.h>
  34 #include <plat/serial.h>
  35 #include <plat/sdrc.h>
  36 #include <plat/prcm.h>
  37 #include <plat/gpmc.h>
  38 #include <plat/dma.h>
  39 #include <plat/dmtimer.h>
  40
  41 #include <asm/tlbflush.h>
  42
  43 #include "cm.h"
  44 #include "cm-regbits-34xx.h"
  45 #include "prm-regbits-34xx.h"
  46
  47 #include "prm.h"
  48 #include "pm.h"
  49 #include "sdrc.h"
  50
  51 #define SDRC_POWER_AUTOCOUNT_SHIFT 8
  52 #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT)
  53 #define SDRC_POWER_CLKCTRL_SHIFT 4
  54 #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT)
  55 #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT)
  56
  57 /* Scratchpad offsets */
  58 #define OMAP343X_TABLE_ADDRESS_OFFSET      0x31
  59 #define OMAP343X_TABLE_VALUE_OFFSET        0x30
  60 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0x32
  61
  62 u32 enable_off_mode;
  63 u32 sleep_while_idle;
  64 u32 wakeup_timer_seconds;
  65
  66 struct power_state {
  67         struct powerdomain *pwrdm;
  68         u32 next_state;
  69 #ifdef CONFIG_SUSPEND
  70         u32 saved_state;
  71 #endif
  72         struct list_head node;
  73 };
  74
  75 static LIST_HEAD(pwrst_list);
  76
  77 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  78
  79 static int (*_omap_save_secure_sram)(u32 *addr);
  80
  81 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  82 static struct powerdomain *core_pwrdm, *per_pwrdm;
  83
  84 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
  85
  86 static inline void omap3_per_save_context(void)
  87 {
  88         omap_gpio_save_context();
  89 }
  90
  91 static inline void omap3_per_restore_context(void)
  92 {
  93         omap_gpio_restore_context();
  94 }
  95
  96 static void omap3_core_save_context(void)
  97 {
  98         u32 control_padconf_off;
  99
 100         /* Save the padconf registers */
 101         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 102         control_padconf_off |= START_PADCONF_SAVE;
 103         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 104         /* wait for the save to complete */
 105         while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 106                         & PADCONF_SAVE_DONE)
 107                 ;
 108         /* Save the Interrupt controller context */
 109         omap_intc_save_context();
 110         /* Save the GPMC context */
 111         omap3_gpmc_save_context();
 112         /* Save the system control module context, padconf already save above*/
 113         omap3_control_save_context();
 114         omap_dma_global_context_save();
 115 }
 116
 117 static void omap3_core_restore_context(void)
 118 {
 119         /* Restore the control module context, padconf restored by h/w */
 120         omap3_control_restore_context();
 121         /* Restore the GPMC context */
 122         omap3_gpmc_restore_context();
 123         /* Restore the interrupt controller context */
 124         omap_intc_restore_context();
 125         omap_dma_global_context_restore();
 126 }
 127
 128 /*
 129  * FIXME: This function should be called before entering off-mode after
 130  * OMAP3 secure services have been accessed. Currently it is only called
 131  * once during boot sequence, but this works as we are not using secure
 132  * services.
 133  */
 134 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 135 {
 136         u32 ret;
 137
 138         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 139                 /*
 140                  * MPU next state must be set to POWER_ON temporarily,
 141                  * otherwise the WFI executed inside the ROM code
 142                  * will hang the system.
 143                  */
 144                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 145                 ret = _omap_save_secure_sram((u32 *)
 146                                 __pa(omap3_secure_ram_storage));
 147                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 148                 /* Following is for error tracking, it should not happen */
 149                 if (ret) {
 150                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 151                                 ret);
 152                         while (1)
 153                                 ;
 154                 }
 155         }
 156 }
 157
 158 /*
 159  * PRCM Interrupt Handler Helper Function
 160  *
 161  * The purpose of this function is to clear any wake-up events latched
 162  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 163  * may occur whilst attempting to clear a PM_WKST_x register and thus
 164  * set another bit in this register. A while loop is used to ensure
 165  * that any peripheral wake-up events occurring while attempting to
 166  * clear the PM_WKST_x are detected and cleared.
 167  */
 168 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 169 {
 170         u32 wkst, fclk, iclk, clken;
 171         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 172         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 173         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 174         u16 grpsel_off = (regs == 3) ?
 175                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 176         int c = 0;
 177
 178         wkst = prm_read_mod_reg(module, wkst_off);
 179         wkst &= prm_read_mod_reg(module, grpsel_off);
 180         if (wkst) {
 181                 iclk = cm_read_mod_reg(module, iclk_off);
 182                 fclk = cm_read_mod_reg(module, fclk_off);
 183                 while (wkst) {
 184                         clken = wkst;
 185                         cm_set_mod_reg_bits(clken, module, iclk_off);
 186                         /*
 187                          * For USBHOST, we don't know whether HOST1 or
 188                          * HOST2 woke us up, so enable both f-clocks
 189                          */
 190                         if (module == OMAP3430ES2_USBHOST_MOD)
 191                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 192                         cm_set_mod_reg_bits(clken, module, fclk_off);
 193                         prm_write_mod_reg(wkst, module, wkst_off);
 194                         wkst = prm_read_mod_reg(module, wkst_off);
 195                         c++;
 196                 }
 197                 cm_write_mod_reg(iclk, module, iclk_off);
 198                 cm_write_mod_reg(fclk, module, fclk_off);
 199         }
 200
 201         return c;
 202 }
 203
 204 static int _prcm_int_handle_wakeup(void)
 205 {
 206         int c;
 207
 208         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 209         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 210         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 211         if (omap_rev() > OMAP3430_REV_ES1_0) {
 212                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 213                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 214         }
 215
 216         return c;
 217 }
 218
 219 /*
 220  * PRCM Interrupt Handler
 221  *
 222  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 223  * interrupts from the PRCM for the MPU. These bits must be cleared in
 224  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 225  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 226  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 227  * register indicates that a wake-up event is pending for the MPU and
 228  * this bit can only be cleared if the all the wake-up events latched
 229  * in the various PM_WKST_x registers have been cleared. The interrupt
 230  * handler is implemented using a do-while loop so that if a wake-up
 231  * event occurred during the processing of the prcm interrupt handler
 232  * (setting a bit in the corresponding PM_WKST_x register and thus
 233  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 234  * this would be handled.
 235  */
 236 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 237 {
 238         u32 irqstatus_mpu;
 239         int c = 0;
 240
 241         do {
 242                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 243                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 244
 245                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 246                         c = _prcm_int_handle_wakeup();
 247
 248                         /*
 249                          * Is the MPU PRCM interrupt handler racing with the
 250                          * IVA2 PRCM interrupt handler ?
 251                          */
 252                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 253                              "but no wakeup sources are marked\n");
 254                 } else {
 255                         /* XXX we need to expand our PRCM interrupt handler */
 256                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 257                              "no code to handle it (%08x)\n", irqstatus_mpu);
 258                 }
 259
 260                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 261                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 262
 263         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 264
 265         return IRQ_HANDLED;
 266 }
 267
 268 static void restore_control_register(u32 val)
 269 {
 270         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 271 }
 272
 273 /* Function to restore the table entry that was modified for enabling MMU */
 274 static void restore_table_entry(void)
 275 {
 276         u32 *scratchpad_address;
 277         u32 previous_value, control_reg_value;
 278         u32 *address;
 279
 280         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 281
 282         /* Get address of entry that was modified */
 283         address = (u32 *)__raw_readl(scratchpad_address +
 284                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 285         /* Get the previous value which needs to be restored */
 286         previous_value = __raw_readl(scratchpad_address +
 287                                      OMAP343X_TABLE_VALUE_OFFSET);
 288         address = __va(address);
 289         *address = previous_value;
 290         flush_tlb_all();
 291         control_reg_value = __raw_readl(scratchpad_address
 292                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 293         /* This will enable caches and prediction */
 294         restore_control_register(control_reg_value);
 295 }
 296
 297 static void omap_sram_idle(void)
 298 {
 299         /* Variable to tell what needs to be saved and restored
 300          * in omap_sram_idle*/
 301         /* save_state = 0 => Nothing to save and restored */
 302         /* save_state = 1 => Only L1 and logic lost */
 303         /* save_state = 2 => Only L2 lost */
 304         /* save_state = 3 => L1, L2 and logic lost */
 305         int save_state = 0;
 306         int mpu_next_state = PWRDM_POWER_ON;
 307         int per_next_state = PWRDM_POWER_ON;
 308         int core_next_state = PWRDM_POWER_ON;
 309         int core_prev_state, per_prev_state;
 310         u32 sdrc_pwr = 0;
 311
 312         if (!_omap_sram_idle)
 313                 return;
 314
 315         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 316         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 317         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 318         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 319
 320         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 321         switch (mpu_next_state) {
 322         case PWRDM_POWER_ON:
 323         case PWRDM_POWER_RET:
 324                 /* No need to save context */
 325                 save_state = 0;
 326                 break;
 327         case PWRDM_POWER_OFF:
 328                 save_state = 3;
 329                 break;
 330         default:
 331                 /* Invalid state */
 332                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 333                 return;
 334         }
 335         pwrdm_pre_transition();
 336
 337         /* NEON control */
 338         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 339                 set_pwrdm_state(neon_pwrdm, mpu_next_state);
 340
 341         /* CORE & PER */
 342         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 343         if (core_next_state < PWRDM_POWER_ON) {
 344                 omap2_gpio_prepare_for_retention();
 345                 omap_uart_prepare_idle(0);
 346                 omap_uart_prepare_idle(1);
 347                 /* PER changes only with core */
 348                 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 349                 if (per_next_state < PWRDM_POWER_ON) {
 350                         omap_uart_prepare_idle(2);
 351                         if (per_next_state == PWRDM_POWER_OFF)
 352                                 omap3_per_save_context();
 353                 }
 354                 if (core_next_state == PWRDM_POWER_OFF) {
 355                         omap3_core_save_context();
 356                         omap3_prcm_save_context();
 357                 }
 358                 /* Enable IO-PAD wakeup */
 359                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 360         }
 361
 362         /*
 363          * Force SDRAM controller to self-refresh mode after timeout on
 364          * autocount. This is needed on ES3.0 to avoid SDRAM controller
 365          * hang-ups.
 366          */
 367         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 368             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 369             core_next_state == PWRDM_POWER_OFF) {
 370                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 371                 sdrc_write_reg((sdrc_pwr &
 372                         ~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) |
 373                         (1 << SDRC_POWER_AUTOCOUNT_SHIFT) |
 374                         SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER);
 375         }
 376
 377         /*
 378          * omap3_arm_context is the location where ARM registers
 379          * get saved. The restore path then reads from this
 380          * location and restores them back.
 381          */
 382         _omap_sram_idle(omap3_arm_context, save_state);
 383         cpu_init();
 384
 385         /* Restore normal SDRAM settings */
 386         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 387             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 388             core_next_state == PWRDM_POWER_OFF)
 389                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 390
 391         /* Restore table entry modified during MMU restoration */
 392         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 393                 restore_table_entry();
 394
 395         if (core_next_state < PWRDM_POWER_ON) {
 396                 if (per_next_state < PWRDM_POWER_ON)
 397                         omap_uart_resume_idle(2);
 398                 omap_uart_resume_idle(1);
 399                 omap_uart_resume_idle(0);
 400
 401                 /* Disable IO-PAD wakeup */
 402                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 403                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 404                 if (core_prev_state == PWRDM_POWER_OFF) {
 405                         omap3_core_restore_context();
 406                         omap3_prcm_restore_context();
 407                         omap3_sram_restore_context();
 408                         omap2_sms_restore_context();
 409                 }
 410                 if (per_next_state < PWRDM_POWER_ON) {
 411                         per_prev_state =
 412                                 pwrdm_read_prev_pwrst(per_pwrdm);
 413                         if (per_prev_state == PWRDM_POWER_OFF)
 414                                 omap3_per_restore_context();
 415                 }
 416                 omap2_gpio_resume_after_retention();
 417         }
 418
 419         pwrdm_post_transition();
 420
 421 }
 422
 423 /*
 424  * Check if functional clocks are enabled before entering
 425  * sleep. This function could be behind CONFIG_PM_DEBUG
 426  * when all drivers are configuring their sysconfig registers
 427  * properly and using their clocks properly.
 428  */
 429 static int omap3_fclks_active(void)
 430 {
 431         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 432                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 433
 434         fck_core1 = cm_read_mod_reg(CORE_MOD,
 435                                     CM_FCLKEN1);
 436         if (omap_rev() > OMAP3430_REV_ES1_0) {
 437                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 438                                             OMAP3430ES2_CM_FCLKEN3);
 439                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 440                                           CM_FCLKEN);
 441                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 442                                               CM_FCLKEN);
 443         } else
 444                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 445                                           OMAP3430ES2_CM_FCLKEN3);
 446         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 447                                   CM_FCLKEN);
 448         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 449                                   CM_FCLKEN);
 450         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 451                                   CM_FCLKEN);
 452
 453         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 454         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 455         fck_per &= ~OMAP3430_EN_UART3;
 456
 457         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 458             fck_cam | fck_per | fck_usbhost)
 459                 return 1;
 460         return 0;
 461 }
 462
 463 static int omap3_can_sleep(void)
 464 {
 465         if (!sleep_while_idle)
 466                 return 0;
 467         if (!omap_uart_can_sleep())
 468                 return 0;
 469         if (omap3_fclks_active())
 470                 return 0;
 471         return 1;
 472 }
 473
 474 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 475  * RET are supported. Function is assuming that clkdm doesn't have
 476  * hw_sup mode enabled. */
 477 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 478 {
 479         u32 cur_state;
 480         int sleep_switch = 0;
 481         int ret = 0;
 482
 483         if (pwrdm == NULL || IS_ERR(pwrdm))
 484                 return -EINVAL;
 485
 486         while (!(pwrdm->pwrsts & (1 << state))) {
 487                 if (state == PWRDM_POWER_OFF)
 488                         return ret;
 489                 state--;
 490         }
 491
 492         cur_state = pwrdm_read_next_pwrst(pwrdm);
 493         if (cur_state == state)
 494                 return ret;
 495
 496         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 497                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 498                 sleep_switch = 1;
 499                 pwrdm_wait_transition(pwrdm);
 500         }
 501
 502         ret = pwrdm_set_next_pwrst(pwrdm, state);
 503         if (ret) {
 504                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 505                        pwrdm->name);
 506                 goto err;
 507         }
 508
 509         if (sleep_switch) {
 510                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 511                 pwrdm_wait_transition(pwrdm);
 512                 pwrdm_state_switch(pwrdm);
 513         }
 514
 515 err:
 516         return ret;
 517 }
 518
 519 static void omap3_pm_idle(void)
 520 {
 521         local_irq_disable();
 522         local_fiq_disable();
 523
 524         if (!omap3_can_sleep())
 525                 goto out;
 526
 527         if (omap_irq_pending())
 528                 goto out;
 529
 530         omap_sram_idle();
 531
 532 out:
 533         local_fiq_enable();
 534         local_irq_enable();
 535 }
 536
 537 #ifdef CONFIG_SUSPEND
 538 static suspend_state_t suspend_state;
 539
 540 static void omap2_pm_wakeup_on_timer(u32 seconds)
 541 {
 542         u32 tick_rate, cycles;
 543
 544         if (!seconds)
 545                 return;
 546
 547         tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
 548         cycles = tick_rate * seconds;
 549         omap_dm_timer_stop(gptimer_wakeup);
 550         omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
 551
 552         pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n",
 553                 seconds, cycles, tick_rate);
 554 }
 555
 556 static int omap3_pm_prepare(void)
 557 {
 558         disable_hlt();
 559         return 0;
 560 }
 561
 562 static int omap3_pm_suspend(void)
 563 {
 564         struct power_state *pwrst;
 565         int state, ret = 0;
 566
 567         if (wakeup_timer_seconds)
 568                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds);
 569
 570         /* Read current next_pwrsts */
 571         list_for_each_entry(pwrst, &pwrst_list, node)
 572                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 573         /* Set ones wanted by suspend */
 574         list_for_each_entry(pwrst, &pwrst_list, node) {
 575                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 576                         goto restore;
 577                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 578                         goto restore;
 579         }
 580
 581         omap_uart_prepare_suspend();
 582         omap_sram_idle();
 583
 584 restore:
 585         /* Restore next_pwrsts */
 586         list_for_each_entry(pwrst, &pwrst_list, node) {
 587                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 588                 if (state > pwrst->next_state) {
 589                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 590                                "target state %d\n",
 591                                pwrst->pwrdm->name, pwrst->next_state);
 592                         ret = -1;
 593                 }
 594                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 595         }
 596         if (ret)
 597                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 598         else
 599                 printk(KERN_INFO "Successfully put all powerdomains "
 600                        "to target state\n");
 601
 602         return ret;
 603 }
 604
 605 static int omap3_pm_enter(suspend_state_t unused)
 606 {
 607         int ret = 0;
 608
 609         switch (suspend_state) {
 610         case PM_SUSPEND_STANDBY:
 611         case PM_SUSPEND_MEM:
 612                 ret = omap3_pm_suspend();
 613                 break;
 614         default:
 615                 ret = -EINVAL;
 616         }
 617
 618         return ret;
 619 }
 620
 621 static void omap3_pm_finish(void)
 622 {
 623         enable_hlt();
 624 }
 625
 626 /* Hooks to enable / disable UART interrupts during suspend */
 627 static int omap3_pm_begin(suspend_state_t state)
 628 {
 629         suspend_state = state;
 630         omap_uart_enable_irqs(0);
 631         return 0;
 632 }
 633
 634 static void omap3_pm_end(void)
 635 {
 636         suspend_state = PM_SUSPEND_ON;
 637         omap_uart_enable_irqs(1);
 638         return;
 639 }
 640
 641 static struct platform_suspend_ops omap_pm_ops = {
 642         .begin          = omap3_pm_begin,
 643         .end            = omap3_pm_end,
 644         .prepare        = omap3_pm_prepare,
 645         .enter          = omap3_pm_enter,
 646         .finish         = omap3_pm_finish,
 647         .valid          = suspend_valid_only_mem,
 648 };
 649 #endif /* CONFIG_SUSPEND */
 650
 651
 652 /**
 653  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 654  *                   retention
 655  *
 656  * In cases where IVA2 is activated by bootcode, it may prevent
 657  * full-chip retention or off-mode because it is not idle.  This
 658  * function forces the IVA2 into idle state so it can go
 659  * into retention/off and thus allow full-chip retention/off.
 660  *
 661  **/
 662 static void __init omap3_iva_idle(void)
 663 {
 664         /* ensure IVA2 clock is disabled */
 665         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 666
 667         /* if no clock activity, nothing else to do */
 668         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 669               OMAP3430_CLKACTIVITY_IVA2_MASK))
 670                 return;
 671
 672         /* Reset IVA2 */
 673         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 674                           OMAP3430_RST2_IVA2 |
 675                           OMAP3430_RST3_IVA2,
 676                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 677
 678         /* Enable IVA2 clock */
 679         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 680                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 681
 682         /* Set IVA2 boot mode to 'idle' */
 683         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 684                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 685
 686         /* Un-reset IVA2 */
 687         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 688
 689         /* Disable IVA2 clock */
 690         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 691
 692         /* Reset IVA2 */
 693         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 694                           OMAP3430_RST2_IVA2 |
 695                           OMAP3430_RST3_IVA2,
 696                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 697 }
 698
 699 static void __init omap3_d2d_idle(void)
 700 {
 701         u16 mask, padconf;
 702
 703         /* In a stand alone OMAP3430 where there is not a stacked
 704          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 705          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 706          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 707         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 708         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 709         padconf |= mask;
 710         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 711
 712         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 713         padconf |= mask;
 714         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 715
 716         /* reset modem */
 717         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 718                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 719                           CORE_MOD, RM_RSTCTRL);
 720         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 721 }
 722
 723 static void __init prcm_setup_regs(void)
 724 {
 725         /* XXX Reset all wkdeps. This should be done when initializing
 726          * powerdomains */
 727         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 728         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 729         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 730         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 731         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 732         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 733         if (omap_rev() > OMAP3430_REV_ES1_0) {
 734                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 735                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 736         } else
 737                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 738
 739         /*
 740          * Enable interface clock autoidle for all modules.
 741          * Note that in the long run this should be done by clockfw
 742          */
 743         cm_write_mod_reg(
 744                 OMAP3430_AUTO_MODEM |
 745                 OMAP3430ES2_AUTO_MMC3 |
 746                 OMAP3430ES2_AUTO_ICR |
 747                 OMAP3430_AUTO_AES2 |
 748                 OMAP3430_AUTO_SHA12 |
 749                 OMAP3430_AUTO_DES2 |
 750                 OMAP3430_AUTO_MMC2 |
 751                 OMAP3430_AUTO_MMC1 |
 752                 OMAP3430_AUTO_MSPRO |
 753                 OMAP3430_AUTO_HDQ |
 754                 OMAP3430_AUTO_MCSPI4 |
 755                 OMAP3430_AUTO_MCSPI3 |
 756                 OMAP3430_AUTO_MCSPI2 |
 757                 OMAP3430_AUTO_MCSPI1 |
 758                 OMAP3430_AUTO_I2C3 |
 759                 OMAP3430_AUTO_I2C2 |
 760                 OMAP3430_AUTO_I2C1 |
 761                 OMAP3430_AUTO_UART2 |
 762                 OMAP3430_AUTO_UART1 |
 763                 OMAP3430_AUTO_GPT11 |
 764                 OMAP3430_AUTO_GPT10 |
 765                 OMAP3430_AUTO_MCBSP5 |
 766                 OMAP3430_AUTO_MCBSP1 |
 767                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 768                 OMAP3430_AUTO_MAILBOXES |
 769                 OMAP3430_AUTO_OMAPCTRL |
 770                 OMAP3430ES1_AUTO_FSHOSTUSB |
 771                 OMAP3430_AUTO_HSOTGUSB |
 772                 OMAP3430_AUTO_SAD2D |
 773                 OMAP3430_AUTO_SSI,
 774                 CORE_MOD, CM_AUTOIDLE1);
 775
 776         cm_write_mod_reg(
 777                 OMAP3430_AUTO_PKA |
 778                 OMAP3430_AUTO_AES1 |
 779                 OMAP3430_AUTO_RNG |
 780                 OMAP3430_AUTO_SHA11 |
 781                 OMAP3430_AUTO_DES1,
 782                 CORE_MOD, CM_AUTOIDLE2);
 783
 784         if (omap_rev() > OMAP3430_REV_ES1_0) {
 785                 cm_write_mod_reg(
 786                         OMAP3430_AUTO_MAD2D |
 787                         OMAP3430ES2_AUTO_USBTLL,
 788                         CORE_MOD, CM_AUTOIDLE3);
 789         }
 790
 791         cm_write_mod_reg(
 792                 OMAP3430_AUTO_WDT2 |
 793                 OMAP3430_AUTO_WDT1 |
 794                 OMAP3430_AUTO_GPIO1 |
 795                 OMAP3430_AUTO_32KSYNC |
 796                 OMAP3430_AUTO_GPT12 |
 797                 OMAP3430_AUTO_GPT1 ,
 798                 WKUP_MOD, CM_AUTOIDLE);
 799
 800         cm_write_mod_reg(
 801                 OMAP3430_AUTO_DSS,
 802                 OMAP3430_DSS_MOD,
 803                 CM_AUTOIDLE);
 804
 805         cm_write_mod_reg(
 806                 OMAP3430_AUTO_CAM,
 807                 OMAP3430_CAM_MOD,
 808                 CM_AUTOIDLE);
 809
 810         cm_write_mod_reg(
 811                 OMAP3430_AUTO_GPIO6 |
 812                 OMAP3430_AUTO_GPIO5 |
 813                 OMAP3430_AUTO_GPIO4 |
 814                 OMAP3430_AUTO_GPIO3 |
 815                 OMAP3430_AUTO_GPIO2 |
 816                 OMAP3430_AUTO_WDT3 |
 817                 OMAP3430_AUTO_UART3 |
 818                 OMAP3430_AUTO_GPT9 |
 819                 OMAP3430_AUTO_GPT8 |
 820                 OMAP3430_AUTO_GPT7 |
 821                 OMAP3430_AUTO_GPT6 |
 822                 OMAP3430_AUTO_GPT5 |
 823                 OMAP3430_AUTO_GPT4 |
 824                 OMAP3430_AUTO_GPT3 |
 825                 OMAP3430_AUTO_GPT2 |
 826                 OMAP3430_AUTO_MCBSP4 |
 827                 OMAP3430_AUTO_MCBSP3 |
 828                 OMAP3430_AUTO_MCBSP2,
 829                 OMAP3430_PER_MOD,
 830                 CM_AUTOIDLE);
 831
 832         if (omap_rev() > OMAP3430_REV_ES1_0) {
 833                 cm_write_mod_reg(
 834                         OMAP3430ES2_AUTO_USBHOST,
 835                         OMAP3430ES2_USBHOST_MOD,
 836                         CM_AUTOIDLE);
 837         }
 838
 839         /*
 840          * Set all plls to autoidle. This is needed until autoidle is
 841          * enabled by clockfw
 842          */
 843         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 844                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 845         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 846                          MPU_MOD,
 847                          CM_AUTOIDLE2);
 848         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 849                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 850                          PLL_MOD,
 851                          CM_AUTOIDLE);
 852         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 853                          PLL_MOD,
 854                          CM_AUTOIDLE2);
 855
 856         /*
 857          * Enable control of expternal oscillator through
 858          * sys_clkreq. In the long run clock framework should
 859          * take care of this.
 860          */
 861         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 862                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 863                              OMAP3430_GR_MOD,
 864                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 865
 866         /* setup wakup source */
 867         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 868                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 869                           WKUP_MOD, PM_WKEN);
 870         /* No need to write EN_IO, that is always enabled */
 871         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 872                           OMAP3430_EN_GPT12,
 873                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 874         /* For some reason IO doesn't generate wakeup event even if
 875          * it is selected to mpu wakeup goup */
 876         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 877                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 878
 879         /* Enable wakeups in PER */
 880         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 881                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 882                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 883                           OMAP3430_PER_MOD, PM_WKEN);
 884         /* and allow them to wake up MPU */
 885         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 886                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 887                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 888                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 889
 890         /* Don't attach IVA interrupts */
 891         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 892         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 893         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 894         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 895
 896         /* Clear any pending 'reset' flags */
 897         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 898         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 899         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 900         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 901         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 902         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 903         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 904
 905         /* Clear any pending PRCM interrupts */
 906         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 907
 908         /* Don't attach IVA interrupts */
 909         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 910         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 911         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 912         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 913
 914         /* Clear any pending 'reset' flags */
 915         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 916         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 917         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 918         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 919         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 920         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 921         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 922
 923         /* Clear any pending PRCM interrupts */
 924         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 925
 926         omap3_iva_idle();
 927         omap3_d2d_idle();
 928 }
 929
 930 void omap3_pm_off_mode_enable(int enable)
 931 {
 932         struct power_state *pwrst;
 933         u32 state;
 934
 935         if (enable)
 936                 state = PWRDM_POWER_OFF;
 937         else
 938                 state = PWRDM_POWER_RET;
 939
 940         list_for_each_entry(pwrst, &pwrst_list, node) {
 941                 pwrst->next_state = state;
 942                 set_pwrdm_state(pwrst->pwrdm, state);
 943         }
 944 }
 945
 946 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 947 {
 948         struct power_state *pwrst;
 949
 950         list_for_each_entry(pwrst, &pwrst_list, node) {
 951                 if (pwrst->pwrdm == pwrdm)
 952                         return pwrst->next_state;
 953         }
 954         return -EINVAL;
 955 }
 956
 957 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 958 {
 959         struct power_state *pwrst;
 960
 961         list_for_each_entry(pwrst, &pwrst_list, node) {
 962                 if (pwrst->pwrdm == pwrdm) {
 963                         pwrst->next_state = state;
 964                         return 0;
 965                 }
 966         }
 967         return -EINVAL;
 968 }
 969
 970 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 971 {
 972         struct power_state *pwrst;
 973
 974         if (!pwrdm->pwrsts)
 975                 return 0;
 976
 977         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 978         if (!pwrst)
 979                 return -ENOMEM;
 980         pwrst->pwrdm = pwrdm;
 981         pwrst->next_state = PWRDM_POWER_RET;
 982         list_add(&pwrst->node, &pwrst_list);
 983
 984         if (pwrdm_has_hdwr_sar(pwrdm))
 985                 pwrdm_enable_hdwr_sar(pwrdm);
 986
 987         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 988 }
 989
 990 /*
 991  * Enable hw supervised mode for all clockdomains if it's
 992  * supported. Initiate sleep transition for other clockdomains, if
 993  * they are not used
 994  */
 995 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 996 {
 997         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 998                 omap2_clkdm_allow_idle(clkdm);
 999         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1000                  atomic_read(&clkdm->usecount) == 0)
1001                 omap2_clkdm_sleep(clkdm);
1002         return 0;
1003 }
1004
1005 void omap_push_sram_idle(void)
1006 {
1007         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1008                                         omap34xx_cpu_suspend_sz);
1009         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1010                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1011                                 save_secure_ram_context_sz);
1012 }
1013
1014 static int __init omap3_pm_init(void)
1015 {
1016         struct power_state *pwrst, *tmp;
1017         int ret;
1018
1019         if (!cpu_is_omap34xx())
1020                 return -ENODEV;
1021
1022         printk(KERN_ERR "Power Management for TI OMAP3.\n");
1023
1024         /* XXX prcm_setup_regs needs to be before enabling hw
1025          * supervised mode for powerdomains */
1026         prcm_setup_regs();
1027
1028         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1029                           (irq_handler_t)prcm_interrupt_handler,
1030                           IRQF_DISABLED, "prcm", NULL);
1031         if (ret) {
1032                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1033                        INT_34XX_PRCM_MPU_IRQ);
1034                 goto err1;
1035         }
1036
1037         ret = pwrdm_for_each(pwrdms_setup, NULL);
1038         if (ret) {
1039                 printk(KERN_ERR "Failed to setup powerdomains\n");
1040                 goto err2;
1041         }
1042
1043         (void) clkdm_for_each(clkdms_setup, NULL);
1044
1045         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1046         if (mpu_pwrdm == NULL) {
1047                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1048                 goto err2;
1049         }
1050
1051         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1052         per_pwrdm = pwrdm_lookup("per_pwrdm");
1053         core_pwrdm = pwrdm_lookup("core_pwrdm");
1054
1055         omap_push_sram_idle();
1056 #ifdef CONFIG_SUSPEND
1057         suspend_set_ops(&omap_pm_ops);
1058 #endif /* CONFIG_SUSPEND */
1059
1060         pm_idle = omap3_pm_idle;
1061
1062         pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
1063         /*
1064          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
1065          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
1066          * waking up PER with every CORE wakeup - see
1067          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
1068         */
1069         pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
1070
1071         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1072                 omap3_secure_ram_storage =
1073                         kmalloc(0x803F, GFP_KERNEL);
1074                 if (!omap3_secure_ram_storage)
1075                         printk(KERN_ERR "Memory allocation failed when"
1076                                         "allocating for secure sram context\n");
1077
1078                 local_irq_disable();
1079                 local_fiq_disable();
1080
1081                 omap_dma_global_context_save();
1082                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1083                 omap_dma_global_context_restore();
1084
1085                 local_irq_enable();
1086                 local_fiq_enable();
1087         }
1088
1089         omap3_save_scratchpad_contents();
1090 err1:
1091         return ret;
1092 err2:
1093         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1094         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1095                 list_del(&pwrst->node);
1096                 kfree(pwrst);
1097         }
1098         return ret;
1099 }
1100
1101 late_initcall(omap3_pm_init);