arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32
  33 #include <plat/sram.h>
  34 #include <plat/clockdomain.h>
  35 #include <plat/powerdomain.h>
  36 #include <plat/serial.h>
  37 #include <plat/sdrc.h>
  38 #include <plat/prcm.h>
  39 #include <plat/gpmc.h>
  40 #include <plat/dma.h>
  41
  42 #include <asm/tlbflush.h>
  43
  44 #include "cm.h"
  45 #include "cm-regbits-34xx.h"
  46 #include "prm-regbits-34xx.h"
  47
  48 #include "prm.h"
  49 #include "pm.h"
  50 #include "sdrc.h"
  51 #include "control.h"
  52
  53 #ifdef CONFIG_SUSPEND
  54 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  55 static inline bool is_suspending(void)
  56 {
  57         return (suspend_state != PM_SUSPEND_ON);
  58 }
  59 #else
  60 static inline bool is_suspending(void)
  61 {
  62         return false;
  63 }
  64 #endif
  65
  66 /* Scratchpad offsets */
  67 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
  68 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
  69 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
  70
  71 /* pm34xx errata defined in pm.h */
  72 u16 pm34xx_errata;
  73
  74 struct power_state {
  75         struct powerdomain *pwrdm;
  76         u32 next_state;
  77 #ifdef CONFIG_SUSPEND
  78         u32 saved_state;
  79 #endif
  80         struct list_head node;
  81 };
  82
  83 static LIST_HEAD(pwrst_list);
  84
  85 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  86
  87 static int (*_omap_save_secure_sram)(u32 *addr);
  88
  89 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  90 static struct powerdomain *core_pwrdm, *per_pwrdm;
  91 static struct powerdomain *cam_pwrdm;
  92
  93 static inline void omap3_per_save_context(void)
  94 {
  95         omap_gpio_save_context();
  96 }
  97
  98 static inline void omap3_per_restore_context(void)
  99 {
 100         omap_gpio_restore_context();
 101 }
 102
 103 static void omap3_enable_io_chain(void)
 104 {
 105         int timeout = 0;
 106
 107         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 108                 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 109                                      PM_WKEN);
 110                 /* Do a readback to assure write has been done */
 111                 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 112
 113                 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 114                          OMAP3430_ST_IO_CHAIN_MASK)) {
 115                         timeout++;
 116                         if (timeout > 1000) {
 117                                 printk(KERN_ERR "Wake up daisy chain "
 118                                        "activation failed.\n");
 119                                 return;
 120                         }
 121                         prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 122                                              WKUP_MOD, PM_WKEN);
 123                 }
 124         }
 125 }
 126
 127 static void omap3_disable_io_chain(void)
 128 {
 129         if (omap_rev() >= OMAP3430_REV_ES3_1)
 130                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 131                                        PM_WKEN);
 132 }
 133
 134 static void omap3_core_save_context(void)
 135 {
 136         u32 control_padconf_off;
 137
 138         /* Save the padconf registers */
 139         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 140         control_padconf_off |= START_PADCONF_SAVE;
 141         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 142         /* wait for the save to complete */
 143         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 144                         & PADCONF_SAVE_DONE))
 145                 udelay(1);
 146
 147         /*
 148          * Force write last pad into memory, as this can fail in some
 149          * cases according to errata 1.157, 1.185
 150          */
 151         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 152                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 153
 154         /* Save the Interrupt controller context */
 155         omap_intc_save_context();
 156         /* Save the GPMC context */
 157         omap3_gpmc_save_context();
 158         /* Save the system control module context, padconf already save above*/
 159         omap3_control_save_context();
 160         omap_dma_global_context_save();
 161 }
 162
 163 static void omap3_core_restore_context(void)
 164 {
 165         /* Restore the control module context, padconf restored by h/w */
 166         omap3_control_restore_context();
 167         /* Restore the GPMC context */
 168         omap3_gpmc_restore_context();
 169         /* Restore the interrupt controller context */
 170         omap_intc_restore_context();
 171         omap_dma_global_context_restore();
 172 }
 173
 174 /*
 175  * FIXME: This function should be called before entering off-mode after
 176  * OMAP3 secure services have been accessed. Currently it is only called
 177  * once during boot sequence, but this works as we are not using secure
 178  * services.
 179  */
 180 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 181 {
 182         u32 ret;
 183
 184         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 185                 /*
 186                  * MPU next state must be set to POWER_ON temporarily,
 187                  * otherwise the WFI executed inside the ROM code
 188                  * will hang the system.
 189                  */
 190                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 191                 ret = _omap_save_secure_sram((u32 *)
 192                                 __pa(omap3_secure_ram_storage));
 193                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 194                 /* Following is for error tracking, it should not happen */
 195                 if (ret) {
 196                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 197                                 ret);
 198                         while (1)
 199                                 ;
 200                 }
 201         }
 202 }
 203
 204 /*
 205  * PRCM Interrupt Handler Helper Function
 206  *
 207  * The purpose of this function is to clear any wake-up events latched
 208  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 209  * may occur whilst attempting to clear a PM_WKST_x register and thus
 210  * set another bit in this register. A while loop is used to ensure
 211  * that any peripheral wake-up events occurring while attempting to
 212  * clear the PM_WKST_x are detected and cleared.
 213  */
 214 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 215 {
 216         u32 wkst, fclk, iclk, clken;
 217         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 218         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 219         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 220         u16 grpsel_off = (regs == 3) ?
 221                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 222         int c = 0;
 223
 224         wkst = prm_read_mod_reg(module, wkst_off);
 225         wkst &= prm_read_mod_reg(module, grpsel_off);
 226         if (wkst) {
 227                 iclk = cm_read_mod_reg(module, iclk_off);
 228                 fclk = cm_read_mod_reg(module, fclk_off);
 229                 while (wkst) {
 230                         clken = wkst;
 231                         cm_set_mod_reg_bits(clken, module, iclk_off);
 232                         /*
 233                          * For USBHOST, we don't know whether HOST1 or
 234                          * HOST2 woke us up, so enable both f-clocks
 235                          */
 236                         if (module == OMAP3430ES2_USBHOST_MOD)
 237                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 238                         cm_set_mod_reg_bits(clken, module, fclk_off);
 239                         prm_write_mod_reg(wkst, module, wkst_off);
 240                         wkst = prm_read_mod_reg(module, wkst_off);
 241                         c++;
 242                 }
 243                 cm_write_mod_reg(iclk, module, iclk_off);
 244                 cm_write_mod_reg(fclk, module, fclk_off);
 245         }
 246
 247         return c;
 248 }
 249
 250 static int _prcm_int_handle_wakeup(void)
 251 {
 252         int c;
 253
 254         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 255         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 256         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 257         if (omap_rev() > OMAP3430_REV_ES1_0) {
 258                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 259                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 260         }
 261
 262         return c;
 263 }
 264
 265 /*
 266  * PRCM Interrupt Handler
 267  *
 268  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 269  * interrupts from the PRCM for the MPU. These bits must be cleared in
 270  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 271  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 272  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 273  * register indicates that a wake-up event is pending for the MPU and
 274  * this bit can only be cleared if the all the wake-up events latched
 275  * in the various PM_WKST_x registers have been cleared. The interrupt
 276  * handler is implemented using a do-while loop so that if a wake-up
 277  * event occurred during the processing of the prcm interrupt handler
 278  * (setting a bit in the corresponding PM_WKST_x register and thus
 279  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 280  * this would be handled.
 281  */
 282 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 283 {
 284         u32 irqenable_mpu, irqstatus_mpu;
 285         int c = 0;
 286
 287         irqenable_mpu = prm_read_mod_reg(OCP_MOD,
 288                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 289         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 290                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 291         irqstatus_mpu &= irqenable_mpu;
 292
 293         do {
 294                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 295                                      OMAP3430_IO_ST_MASK)) {
 296                         c = _prcm_int_handle_wakeup();
 297
 298                         /*
 299                          * Is the MPU PRCM interrupt handler racing with the
 300                          * IVA2 PRCM interrupt handler ?
 301                          */
 302                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 303                              "but no wakeup sources are marked\n");
 304                 } else {
 305                         /* XXX we need to expand our PRCM interrupt handler */
 306                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 307                              "no code to handle it (%08x)\n", irqstatus_mpu);
 308                 }
 309
 310                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 311                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 312
 313                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 314                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 315                 irqstatus_mpu &= irqenable_mpu;
 316
 317         } while (irqstatus_mpu);
 318
 319         return IRQ_HANDLED;
 320 }
 321
 322 static void restore_control_register(u32 val)
 323 {
 324         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 325 }
 326
 327 /* Function to restore the table entry that was modified for enabling MMU */
 328 static void restore_table_entry(void)
 329 {
 330         void __iomem *scratchpad_address;
 331         u32 previous_value, control_reg_value;
 332         u32 *address;
 333
 334         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 335
 336         /* Get address of entry that was modified */
 337         address = (u32 *)__raw_readl(scratchpad_address +
 338                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 339         /* Get the previous value which needs to be restored */
 340         previous_value = __raw_readl(scratchpad_address +
 341                                      OMAP343X_TABLE_VALUE_OFFSET);
 342         address = __va(address);
 343         *address = previous_value;
 344         flush_tlb_all();
 345         control_reg_value = __raw_readl(scratchpad_address
 346                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 347         /* This will enable caches and prediction */
 348         restore_control_register(control_reg_value);
 349 }
 350
 351 void omap_sram_idle(void)
 352 {
 353         /* Variable to tell what needs to be saved and restored
 354          * in omap_sram_idle*/
 355         /* save_state = 0 => Nothing to save and restored */
 356         /* save_state = 1 => Only L1 and logic lost */
 357         /* save_state = 2 => Only L2 lost */
 358         /* save_state = 3 => L1, L2 and logic lost */
 359         int save_state = 0;
 360         int mpu_next_state = PWRDM_POWER_ON;
 361         int per_next_state = PWRDM_POWER_ON;
 362         int core_next_state = PWRDM_POWER_ON;
 363         int core_prev_state, per_prev_state;
 364         u32 sdrc_pwr = 0;
 365
 366         if (!_omap_sram_idle)
 367                 return;
 368
 369         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 370         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 371         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 372         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 373
 374         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 375         switch (mpu_next_state) {
 376         case PWRDM_POWER_ON:
 377         case PWRDM_POWER_RET:
 378                 /* No need to save context */
 379                 save_state = 0;
 380                 break;
 381         case PWRDM_POWER_OFF:
 382                 save_state = 3;
 383                 break;
 384         default:
 385                 /* Invalid state */
 386                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 387                 return;
 388         }
 389         pwrdm_pre_transition();
 390
 391         /* NEON control */
 392         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 393                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 394
 395         /* Enable IO-PAD and IO-CHAIN wakeups */
 396         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 397         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 398         if (omap3_has_io_wakeup() &&
 399             (per_next_state < PWRDM_POWER_ON ||
 400              core_next_state < PWRDM_POWER_ON)) {
 401                 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 402                 omap3_enable_io_chain();
 403         }
 404
 405         /* Block console output in case it is on one of the OMAP UARTs */
 406         if (!is_suspending())
 407                 if (per_next_state < PWRDM_POWER_ON ||
 408                     core_next_state < PWRDM_POWER_ON)
 409                         if (try_acquire_console_sem())
 410                                 goto console_still_active;
 411
 412         /* PER */
 413         if (per_next_state < PWRDM_POWER_ON) {
 414                 omap_uart_prepare_idle(2);
 415                 omap_uart_prepare_idle(3);
 416                 omap2_gpio_prepare_for_idle(per_next_state);
 417                 if (per_next_state == PWRDM_POWER_OFF)
 418                                 omap3_per_save_context();
 419         }
 420
 421         /* CORE */
 422         if (core_next_state < PWRDM_POWER_ON) {
 423                 omap_uart_prepare_idle(0);
 424                 omap_uart_prepare_idle(1);
 425                 if (core_next_state == PWRDM_POWER_OFF) {
 426                         omap3_core_save_context();
 427                         omap3_prcm_save_context();
 428                 }
 429         }
 430
 431         omap3_intc_prepare_idle();
 432
 433         /*
 434         * On EMU/HS devices ROM code restores a SRDC value
 435         * from scratchpad which has automatic self refresh on timeout
 436         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 437         * Hence store/restore the SDRC_POWER register here.
 438         */
 439         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 440             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 441             core_next_state == PWRDM_POWER_OFF)
 442                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 443
 444         /*
 445          * omap3_arm_context is the location where ARM registers
 446          * get saved. The restore path then reads from this
 447          * location and restores them back.
 448          */
 449         _omap_sram_idle(omap3_arm_context, save_state);
 450         cpu_init();
 451
 452         /* Restore normal SDRC POWER settings */
 453         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 454             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 455             core_next_state == PWRDM_POWER_OFF)
 456                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 457
 458         /* Restore table entry modified during MMU restoration */
 459         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 460                 restore_table_entry();
 461
 462         /* CORE */
 463         if (core_next_state < PWRDM_POWER_ON) {
 464                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 465                 if (core_prev_state == PWRDM_POWER_OFF) {
 466                         omap3_core_restore_context();
 467                         omap3_prcm_restore_context();
 468                         omap3_sram_restore_context();
 469                         omap2_sms_restore_context();
 470                 }
 471                 omap_uart_resume_idle(0);
 472                 omap_uart_resume_idle(1);
 473                 if (core_next_state == PWRDM_POWER_OFF)
 474                         prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 475                                                OMAP3430_GR_MOD,
 476                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 477         }
 478         omap3_intc_resume_idle();
 479
 480         /* PER */
 481         if (per_next_state < PWRDM_POWER_ON) {
 482                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 483                 omap2_gpio_resume_after_idle();
 484                 if (per_prev_state == PWRDM_POWER_OFF)
 485                         omap3_per_restore_context();
 486                 omap_uart_resume_idle(2);
 487                 omap_uart_resume_idle(3);
 488         }
 489
 490         if (!is_suspending())
 491                 release_console_sem();
 492
 493 console_still_active:
 494         /* Disable IO-PAD and IO-CHAIN wakeup */
 495         if (omap3_has_io_wakeup() &&
 496             (per_next_state < PWRDM_POWER_ON ||
 497              core_next_state < PWRDM_POWER_ON)) {
 498                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 499                 omap3_disable_io_chain();
 500         }
 501
 502         pwrdm_post_transition();
 503
 504         omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 505 }
 506
 507 int omap3_can_sleep(void)
 508 {
 509         if (!sleep_while_idle)
 510                 return 0;
 511         if (!omap_uart_can_sleep())
 512                 return 0;
 513         return 1;
 514 }
 515
 516 static void omap3_pm_idle(void)
 517 {
 518         local_irq_disable();
 519         local_fiq_disable();
 520
 521         if (!omap3_can_sleep())
 522                 goto out;
 523
 524         if (omap_irq_pending() || need_resched())
 525                 goto out;
 526
 527         omap_sram_idle();
 528
 529 out:
 530         local_fiq_enable();
 531         local_irq_enable();
 532 }
 533
 534 #ifdef CONFIG_SUSPEND
 535 static int omap3_pm_suspend(void)
 536 {
 537         struct power_state *pwrst;
 538         int state, ret = 0;
 539
 540         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 541                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 542                                          wakeup_timer_milliseconds);
 543
 544         /* Read current next_pwrsts */
 545         list_for_each_entry(pwrst, &pwrst_list, node)
 546                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 547         /* Set ones wanted by suspend */
 548         list_for_each_entry(pwrst, &pwrst_list, node) {
 549                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 550                         goto restore;
 551                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 552                         goto restore;
 553         }
 554
 555         omap_uart_prepare_suspend();
 556         omap3_intc_suspend();
 557
 558         omap_sram_idle();
 559
 560 restore:
 561         /* Restore next_pwrsts */
 562         list_for_each_entry(pwrst, &pwrst_list, node) {
 563                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 564                 if (state > pwrst->next_state) {
 565                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 566                                "target state %d\n",
 567                                pwrst->pwrdm->name, pwrst->next_state);
 568                         ret = -1;
 569                 }
 570                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 571         }
 572         if (ret)
 573                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 574         else
 575                 printk(KERN_INFO "Successfully put all powerdomains "
 576                        "to target state\n");
 577
 578         return ret;
 579 }
 580
 581 static int omap3_pm_enter(suspend_state_t unused)
 582 {
 583         int ret = 0;
 584
 585         switch (suspend_state) {
 586         case PM_SUSPEND_STANDBY:
 587         case PM_SUSPEND_MEM:
 588                 ret = omap3_pm_suspend();
 589                 break;
 590         default:
 591                 ret = -EINVAL;
 592         }
 593
 594         return ret;
 595 }
 596
 597 /* Hooks to enable / disable UART interrupts during suspend */
 598 static int omap3_pm_begin(suspend_state_t state)
 599 {
 600         disable_hlt();
 601         suspend_state = state;
 602         omap_uart_enable_irqs(0);
 603         return 0;
 604 }
 605
 606 static void omap3_pm_end(void)
 607 {
 608         suspend_state = PM_SUSPEND_ON;
 609         omap_uart_enable_irqs(1);
 610         enable_hlt();
 611         return;
 612 }
 613
 614 static struct platform_suspend_ops omap_pm_ops = {
 615         .begin          = omap3_pm_begin,
 616         .end            = omap3_pm_end,
 617         .enter          = omap3_pm_enter,
 618         .valid          = suspend_valid_only_mem,
 619 };
 620 #endif /* CONFIG_SUSPEND */
 621
 622
 623 /**
 624  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 625  *                   retention
 626  *
 627  * In cases where IVA2 is activated by bootcode, it may prevent
 628  * full-chip retention or off-mode because it is not idle.  This
 629  * function forces the IVA2 into idle state so it can go
 630  * into retention/off and thus allow full-chip retention/off.
 631  *
 632  **/
 633 static void __init omap3_iva_idle(void)
 634 {
 635         /* ensure IVA2 clock is disabled */
 636         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 637
 638         /* if no clock activity, nothing else to do */
 639         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 640               OMAP3430_CLKACTIVITY_IVA2_MASK))
 641                 return;
 642
 643         /* Reset IVA2 */
 644         prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 645                           OMAP3430_RST2_IVA2_MASK |
 646                           OMAP3430_RST3_IVA2_MASK,
 647                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 648
 649         /* Enable IVA2 clock */
 650         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 651                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 652
 653         /* Set IVA2 boot mode to 'idle' */
 654         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 655                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 656
 657         /* Un-reset IVA2 */
 658         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 659
 660         /* Disable IVA2 clock */
 661         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 662
 663         /* Reset IVA2 */
 664         prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 665                           OMAP3430_RST2_IVA2_MASK |
 666                           OMAP3430_RST3_IVA2_MASK,
 667                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 668 }
 669
 670 static void __init omap3_d2d_idle(void)
 671 {
 672         u16 mask, padconf;
 673
 674         /* In a stand alone OMAP3430 where there is not a stacked
 675          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 676          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 677          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 678         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 679         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 680         padconf |= mask;
 681         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 682
 683         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 684         padconf |= mask;
 685         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 686
 687         /* reset modem */
 688         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 689                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 690                           CORE_MOD, OMAP2_RM_RSTCTRL);
 691         prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 692 }
 693
 694 static void __init prcm_setup_regs(void)
 695 {
 696         u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
 697                                         OMAP3630_AUTO_UART4_MASK : 0;
 698         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 699                                         OMAP3630_EN_UART4_MASK : 0;
 700         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 701                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 702
 703
 704         /* XXX Reset all wkdeps. This should be done when initializing
 705          * powerdomains */
 706         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 707         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 708         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 709         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 710         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 711         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 712         if (omap_rev() > OMAP3430_REV_ES1_0) {
 713                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 714                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 715         } else
 716                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 717
 718         /*
 719          * Enable interface clock autoidle for all modules.
 720          * Note that in the long run this should be done by clockfw
 721          */
 722         cm_write_mod_reg(
 723                 OMAP3430_AUTO_MODEM_MASK |
 724                 OMAP3430ES2_AUTO_MMC3_MASK |
 725                 OMAP3430ES2_AUTO_ICR_MASK |
 726                 OMAP3430_AUTO_AES2_MASK |
 727                 OMAP3430_AUTO_SHA12_MASK |
 728                 OMAP3430_AUTO_DES2_MASK |
 729                 OMAP3430_AUTO_MMC2_MASK |
 730                 OMAP3430_AUTO_MMC1_MASK |
 731                 OMAP3430_AUTO_MSPRO_MASK |
 732                 OMAP3430_AUTO_HDQ_MASK |
 733                 OMAP3430_AUTO_MCSPI4_MASK |
 734                 OMAP3430_AUTO_MCSPI3_MASK |
 735                 OMAP3430_AUTO_MCSPI2_MASK |
 736                 OMAP3430_AUTO_MCSPI1_MASK |
 737                 OMAP3430_AUTO_I2C3_MASK |
 738                 OMAP3430_AUTO_I2C2_MASK |
 739                 OMAP3430_AUTO_I2C1_MASK |
 740                 OMAP3430_AUTO_UART2_MASK |
 741                 OMAP3430_AUTO_UART1_MASK |
 742                 OMAP3430_AUTO_GPT11_MASK |
 743                 OMAP3430_AUTO_GPT10_MASK |
 744                 OMAP3430_AUTO_MCBSP5_MASK |
 745                 OMAP3430_AUTO_MCBSP1_MASK |
 746                 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
 747                 OMAP3430_AUTO_MAILBOXES_MASK |
 748                 OMAP3430_AUTO_OMAPCTRL_MASK |
 749                 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
 750                 OMAP3430_AUTO_HSOTGUSB_MASK |
 751                 OMAP3430_AUTO_SAD2D_MASK |
 752                 OMAP3430_AUTO_SSI_MASK,
 753                 CORE_MOD, CM_AUTOIDLE1);
 754
 755         cm_write_mod_reg(
 756                 OMAP3430_AUTO_PKA_MASK |
 757                 OMAP3430_AUTO_AES1_MASK |
 758                 OMAP3430_AUTO_RNG_MASK |
 759                 OMAP3430_AUTO_SHA11_MASK |
 760                 OMAP3430_AUTO_DES1_MASK,
 761                 CORE_MOD, CM_AUTOIDLE2);
 762
 763         if (omap_rev() > OMAP3430_REV_ES1_0) {
 764                 cm_write_mod_reg(
 765                         OMAP3430_AUTO_MAD2D_MASK |
 766                         OMAP3430ES2_AUTO_USBTLL_MASK,
 767                         CORE_MOD, CM_AUTOIDLE3);
 768         }
 769
 770         cm_write_mod_reg(
 771                 OMAP3430_AUTO_WDT2_MASK |
 772                 OMAP3430_AUTO_WDT1_MASK |
 773                 OMAP3430_AUTO_GPIO1_MASK |
 774                 OMAP3430_AUTO_32KSYNC_MASK |
 775                 OMAP3430_AUTO_GPT12_MASK |
 776                 OMAP3430_AUTO_GPT1_MASK,
 777                 WKUP_MOD, CM_AUTOIDLE);
 778
 779         cm_write_mod_reg(
 780                 OMAP3430_AUTO_DSS_MASK,
 781                 OMAP3430_DSS_MOD,
 782                 CM_AUTOIDLE);
 783
 784         cm_write_mod_reg(
 785                 OMAP3430_AUTO_CAM_MASK,
 786                 OMAP3430_CAM_MOD,
 787                 CM_AUTOIDLE);
 788
 789         cm_write_mod_reg(
 790                 omap3630_auto_uart4_mask |
 791                 OMAP3430_AUTO_GPIO6_MASK |
 792                 OMAP3430_AUTO_GPIO5_MASK |
 793                 OMAP3430_AUTO_GPIO4_MASK |
 794                 OMAP3430_AUTO_GPIO3_MASK |
 795                 OMAP3430_AUTO_GPIO2_MASK |
 796                 OMAP3430_AUTO_WDT3_MASK |
 797                 OMAP3430_AUTO_UART3_MASK |
 798                 OMAP3430_AUTO_GPT9_MASK |
 799                 OMAP3430_AUTO_GPT8_MASK |
 800                 OMAP3430_AUTO_GPT7_MASK |
 801                 OMAP3430_AUTO_GPT6_MASK |
 802                 OMAP3430_AUTO_GPT5_MASK |
 803                 OMAP3430_AUTO_GPT4_MASK |
 804                 OMAP3430_AUTO_GPT3_MASK |
 805                 OMAP3430_AUTO_GPT2_MASK |
 806                 OMAP3430_AUTO_MCBSP4_MASK |
 807                 OMAP3430_AUTO_MCBSP3_MASK |
 808                 OMAP3430_AUTO_MCBSP2_MASK,
 809                 OMAP3430_PER_MOD,
 810                 CM_AUTOIDLE);
 811
 812         if (omap_rev() > OMAP3430_REV_ES1_0) {
 813                 cm_write_mod_reg(
 814                         OMAP3430ES2_AUTO_USBHOST_MASK,
 815                         OMAP3430ES2_USBHOST_MOD,
 816                         CM_AUTOIDLE);
 817         }
 818
 819         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 820
 821         /*
 822          * Set all plls to autoidle. This is needed until autoidle is
 823          * enabled by clockfw
 824          */
 825         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 826                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 827         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 828                          MPU_MOD,
 829                          CM_AUTOIDLE2);
 830         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 831                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 832                          PLL_MOD,
 833                          CM_AUTOIDLE);
 834         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 835                          PLL_MOD,
 836                          CM_AUTOIDLE2);
 837
 838         /*
 839          * Enable control of expternal oscillator through
 840          * sys_clkreq. In the long run clock framework should
 841          * take care of this.
 842          */
 843         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 844                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 845                              OMAP3430_GR_MOD,
 846                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 847
 848         /* setup wakup source */
 849         prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 850                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 851                           WKUP_MOD, PM_WKEN);
 852         /* No need to write EN_IO, that is always enabled */
 853         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 854                           OMAP3430_GRPSEL_GPT1_MASK |
 855                           OMAP3430_GRPSEL_GPT12_MASK,
 856                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 857         /* For some reason IO doesn't generate wakeup event even if
 858          * it is selected to mpu wakeup goup */
 859         prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 860                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 861
 862         /* Enable PM_WKEN to support DSS LPR */
 863         prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 864                                 OMAP3430_DSS_MOD, PM_WKEN);
 865
 866         /* Enable wakeups in PER */
 867         prm_write_mod_reg(omap3630_en_uart4_mask |
 868                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 869                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 870                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 871                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 872                           OMAP3430_EN_MCBSP4_MASK,
 873                           OMAP3430_PER_MOD, PM_WKEN);
 874         /* and allow them to wake up MPU */
 875         prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 876                           OMAP3430_GRPSEL_GPIO2_MASK |
 877                           OMAP3430_GRPSEL_GPIO3_MASK |
 878                           OMAP3430_GRPSEL_GPIO4_MASK |
 879                           OMAP3430_GRPSEL_GPIO5_MASK |
 880                           OMAP3430_GRPSEL_GPIO6_MASK |
 881                           OMAP3430_GRPSEL_UART3_MASK |
 882                           OMAP3430_GRPSEL_MCBSP2_MASK |
 883                           OMAP3430_GRPSEL_MCBSP3_MASK |
 884                           OMAP3430_GRPSEL_MCBSP4_MASK,
 885                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 886
 887         /* Don't attach IVA interrupts */
 888         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 889         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 890         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 891         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 892
 893         /* Clear any pending 'reset' flags */
 894         prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 895         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 896         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 897         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 898         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 899         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 900         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 901
 902         /* Clear any pending PRCM interrupts */
 903         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 904
 905         omap3_iva_idle();
 906         omap3_d2d_idle();
 907 }
 908
 909 void omap3_pm_off_mode_enable(int enable)
 910 {
 911         struct power_state *pwrst;
 912         u32 state;
 913
 914         if (enable)
 915                 state = PWRDM_POWER_OFF;
 916         else
 917                 state = PWRDM_POWER_RET;
 918
 919 #ifdef CONFIG_CPU_IDLE
 920         /*
 921          * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
 922          * enable OFF mode in a stable form for previous revisions, restrict
 923          * instead to RET
 924          */
 925         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 926                 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
 927         else
 928                 omap3_cpuidle_update_states(state, state);
 929 #endif
 930
 931         list_for_each_entry(pwrst, &pwrst_list, node) {
 932                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 933                                 pwrst->pwrdm == core_pwrdm &&
 934                                 state == PWRDM_POWER_OFF) {
 935                         pwrst->next_state = PWRDM_POWER_RET;
 936                         WARN_ONCE(1,
 937                                 "%s: Core OFF disabled due to errata i583\n",
 938                                 __func__);
 939                 } else {
 940                         pwrst->next_state = state;
 941                 }
 942                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 943         }
 944 }
 945
 946 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 947 {
 948         struct power_state *pwrst;
 949
 950         list_for_each_entry(pwrst, &pwrst_list, node) {
 951                 if (pwrst->pwrdm == pwrdm)
 952                         return pwrst->next_state;
 953         }
 954         return -EINVAL;
 955 }
 956
 957 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 958 {
 959         struct power_state *pwrst;
 960
 961         list_for_each_entry(pwrst, &pwrst_list, node) {
 962                 if (pwrst->pwrdm == pwrdm) {
 963                         pwrst->next_state = state;
 964                         return 0;
 965                 }
 966         }
 967         return -EINVAL;
 968 }
 969
 970 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 971 {
 972         struct power_state *pwrst;
 973
 974         if (!pwrdm->pwrsts)
 975                 return 0;
 976
 977         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 978         if (!pwrst)
 979                 return -ENOMEM;
 980         pwrst->pwrdm = pwrdm;
 981         pwrst->next_state = PWRDM_POWER_RET;
 982         list_add(&pwrst->node, &pwrst_list);
 983
 984         if (pwrdm_has_hdwr_sar(pwrdm))
 985                 pwrdm_enable_hdwr_sar(pwrdm);
 986
 987         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 988 }
 989
 990 /*
 991  * Enable hw supervised mode for all clockdomains if it's
 992  * supported. Initiate sleep transition for other clockdomains, if
 993  * they are not used
 994  */
 995 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 996 {
 997         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 998                 omap2_clkdm_allow_idle(clkdm);
 999         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
1000                  atomic_read(&clkdm->usecount) == 0)
1001                 omap2_clkdm_sleep(clkdm);
1002         return 0;
1003 }
1004
1005 void omap_push_sram_idle(void)
1006 {
1007         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
1008                                         omap34xx_cpu_suspend_sz);
1009         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1010                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1011                                 save_secure_ram_context_sz);
1012 }
1013
1014 static void __init pm_errata_configure(void)
1015 {
1016         if (cpu_is_omap3630()) {
1017                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
1018                 /* Enable the l2 cache toggling in sleep logic */
1019                 enable_omap3630_toggle_l2_on_restore();
1020                 if (omap_rev() < OMAP3630_REV_ES1_2)
1021                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
1022         }
1023 }
1024
1025 static int __init omap3_pm_init(void)
1026 {
1027         struct power_state *pwrst, *tmp;
1028         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
1029         int ret;
1030
1031         if (!cpu_is_omap34xx())
1032                 return -ENODEV;
1033
1034         pm_errata_configure();
1035
1036         printk(KERN_ERR "Power Management for TI OMAP3.\n");
1037
1038         /* XXX prcm_setup_regs needs to be before enabling hw
1039          * supervised mode for powerdomains */
1040         prcm_setup_regs();
1041
1042         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1043                           (irq_handler_t)prcm_interrupt_handler,
1044                           IRQF_DISABLED, "prcm", NULL);
1045         if (ret) {
1046                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1047                        INT_34XX_PRCM_MPU_IRQ);
1048                 goto err1;
1049         }
1050
1051         ret = pwrdm_for_each(pwrdms_setup, NULL);
1052         if (ret) {
1053                 printk(KERN_ERR "Failed to setup powerdomains\n");
1054                 goto err2;
1055         }
1056
1057         (void) clkdm_for_each(clkdms_setup, NULL);
1058
1059         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1060         if (mpu_pwrdm == NULL) {
1061                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1062                 goto err2;
1063         }
1064
1065         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1066         per_pwrdm = pwrdm_lookup("per_pwrdm");
1067         core_pwrdm = pwrdm_lookup("core_pwrdm");
1068         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1069
1070         neon_clkdm = clkdm_lookup("neon_clkdm");
1071         mpu_clkdm = clkdm_lookup("mpu_clkdm");
1072         per_clkdm = clkdm_lookup("per_clkdm");
1073         core_clkdm = clkdm_lookup("core_clkdm");
1074
1075         omap_push_sram_idle();
1076 #ifdef CONFIG_SUSPEND
1077         suspend_set_ops(&omap_pm_ops);
1078 #endif /* CONFIG_SUSPEND */
1079
1080         pm_idle = omap3_pm_idle;
1081         omap3_idle_init();
1082
1083         /*
1084          * RTA is disabled during initialization as per erratum i608
1085          * it is safer to disable RTA by the bootloader, but we would like
1086          * to be doubly sure here and prevent any mishaps.
1087          */
1088         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
1089                 omap3630_ctrl_disable_rta();
1090
1091         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1092         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1093                 omap3_secure_ram_storage =
1094                         kmalloc(0x803F, GFP_KERNEL);
1095                 if (!omap3_secure_ram_storage)
1096                         printk(KERN_ERR "Memory allocation failed when"
1097                                         "allocating for secure sram context\n");
1098
1099                 local_irq_disable();
1100                 local_fiq_disable();
1101
1102                 omap_dma_global_context_save();
1103                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1104                 omap_dma_global_context_restore();
1105
1106                 local_irq_enable();
1107                 local_fiq_enable();
1108         }
1109
1110         omap3_save_scratchpad_contents();
1111 err1:
1112         return ret;
1113 err2:
1114         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1115         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1116                 list_del(&pwrst->node);
1117                 kfree(pwrst);
1118         }
1119         return ret;
1120 }
1121
1122 late_initcall(omap3_pm_init);