arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32
  33 #include <plat/sram.h>
  34 #include "clockdomain.h"
  35 #include "powerdomain.h"
  36 #include <plat/serial.h>
  37 #include <plat/sdrc.h>
  38 #include <plat/prcm.h>
  39 #include <plat/gpmc.h>
  40 #include <plat/dma.h>
  41
  42 #include <asm/tlbflush.h>
  43
  44 #include "cm2xxx_3xxx.h"
  45 #include "cm-regbits-34xx.h"
  46 #include "prm-regbits-34xx.h"
  47
  48 #include "prm2xxx_3xxx.h"
  49 #include "pm.h"
  50 #include "sdrc.h"
  51 #include "control.h"
  52
  53 #ifdef CONFIG_SUSPEND
  54 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  55 static inline bool is_suspending(void)
  56 {
  57         return (suspend_state != PM_SUSPEND_ON);
  58 }
  59 #else
  60 static inline bool is_suspending(void)
  61 {
  62         return false;
  63 }
  64 #endif
  65
  66 /* Scratchpad offsets */
  67 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
  68 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
  69 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
  70
  71 /* pm34xx errata defined in pm.h */
  72 u16 pm34xx_errata;
  73
  74 struct power_state {
  75         struct powerdomain *pwrdm;
  76         u32 next_state;
  77 #ifdef CONFIG_SUSPEND
  78         u32 saved_state;
  79 #endif
  80         struct list_head node;
  81 };
  82
  83 static LIST_HEAD(pwrst_list);
  84
  85 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  86
  87 static int (*_omap_save_secure_sram)(u32 *addr);
  88
  89 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  90 static struct powerdomain *core_pwrdm, *per_pwrdm;
  91 static struct powerdomain *cam_pwrdm;
  92
  93 static inline void omap3_per_save_context(void)
  94 {
  95         omap_gpio_save_context();
  96 }
  97
  98 static inline void omap3_per_restore_context(void)
  99 {
 100         omap_gpio_restore_context();
 101 }
 102
 103 static void omap3_enable_io_chain(void)
 104 {
 105         int timeout = 0;
 106
 107         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 108                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 109                                      PM_WKEN);
 110                 /* Do a readback to assure write has been done */
 111                 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 112
 113                 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 114                          OMAP3430_ST_IO_CHAIN_MASK)) {
 115                         timeout++;
 116                         if (timeout > 1000) {
 117                                 printk(KERN_ERR "Wake up daisy chain "
 118                                        "activation failed.\n");
 119                                 return;
 120                         }
 121                         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 122                                              WKUP_MOD, PM_WKEN);
 123                 }
 124         }
 125 }
 126
 127 static void omap3_disable_io_chain(void)
 128 {
 129         if (omap_rev() >= OMAP3430_REV_ES3_1)
 130                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 131                                        PM_WKEN);
 132 }
 133
 134 static void omap3_core_save_context(void)
 135 {
 136         omap3_ctrl_save_padconf();
 137
 138         /*
 139          * Force write last pad into memory, as this can fail in some
 140          * cases according to errata 1.157, 1.185
 141          */
 142         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 143                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 144
 145         /* Save the Interrupt controller context */
 146         omap_intc_save_context();
 147         /* Save the GPMC context */
 148         omap3_gpmc_save_context();
 149         /* Save the system control module context, padconf already save above*/
 150         omap3_control_save_context();
 151         omap_dma_global_context_save();
 152 }
 153
 154 static void omap3_core_restore_context(void)
 155 {
 156         /* Restore the control module context, padconf restored by h/w */
 157         omap3_control_restore_context();
 158         /* Restore the GPMC context */
 159         omap3_gpmc_restore_context();
 160         /* Restore the interrupt controller context */
 161         omap_intc_restore_context();
 162         omap_dma_global_context_restore();
 163 }
 164
 165 /*
 166  * FIXME: This function should be called before entering off-mode after
 167  * OMAP3 secure services have been accessed. Currently it is only called
 168  * once during boot sequence, but this works as we are not using secure
 169  * services.
 170  */
 171 static void omap3_save_secure_ram_context(void)
 172 {
 173         u32 ret;
 174         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 175
 176         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 177                 /*
 178                  * MPU next state must be set to POWER_ON temporarily,
 179                  * otherwise the WFI executed inside the ROM code
 180                  * will hang the system.
 181                  */
 182                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 183                 ret = _omap_save_secure_sram((u32 *)
 184                                 __pa(omap3_secure_ram_storage));
 185                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 186                 /* Following is for error tracking, it should not happen */
 187                 if (ret) {
 188                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 189                                 ret);
 190                         while (1)
 191                                 ;
 192                 }
 193         }
 194 }
 195
 196 /*
 197  * PRCM Interrupt Handler Helper Function
 198  *
 199  * The purpose of this function is to clear any wake-up events latched
 200  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 201  * may occur whilst attempting to clear a PM_WKST_x register and thus
 202  * set another bit in this register. A while loop is used to ensure
 203  * that any peripheral wake-up events occurring while attempting to
 204  * clear the PM_WKST_x are detected and cleared.
 205  */
 206 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 207 {
 208         u32 wkst, fclk, iclk, clken;
 209         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 210         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 211         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 212         u16 grpsel_off = (regs == 3) ?
 213                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 214         int c = 0;
 215
 216         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 217         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 218         if (wkst) {
 219                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 220                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 221                 while (wkst) {
 222                         clken = wkst;
 223                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 224                         /*
 225                          * For USBHOST, we don't know whether HOST1 or
 226                          * HOST2 woke us up, so enable both f-clocks
 227                          */
 228                         if (module == OMAP3430ES2_USBHOST_MOD)
 229                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 230                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 231                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 232                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 233                         c++;
 234                 }
 235                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 236                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 237         }
 238
 239         return c;
 240 }
 241
 242 static int _prcm_int_handle_wakeup(void)
 243 {
 244         int c;
 245
 246         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 247         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 248         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 249         if (omap_rev() > OMAP3430_REV_ES1_0) {
 250                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 251                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 252         }
 253
 254         return c;
 255 }
 256
 257 /*
 258  * PRCM Interrupt Handler
 259  *
 260  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 261  * interrupts from the PRCM for the MPU. These bits must be cleared in
 262  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 263  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 264  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 265  * register indicates that a wake-up event is pending for the MPU and
 266  * this bit can only be cleared if the all the wake-up events latched
 267  * in the various PM_WKST_x registers have been cleared. The interrupt
 268  * handler is implemented using a do-while loop so that if a wake-up
 269  * event occurred during the processing of the prcm interrupt handler
 270  * (setting a bit in the corresponding PM_WKST_x register and thus
 271  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 272  * this would be handled.
 273  */
 274 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 275 {
 276         u32 irqenable_mpu, irqstatus_mpu;
 277         int c = 0;
 278
 279         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 280                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 281         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 282                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 283         irqstatus_mpu &= irqenable_mpu;
 284
 285         do {
 286                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 287                                      OMAP3430_IO_ST_MASK)) {
 288                         c = _prcm_int_handle_wakeup();
 289
 290                         /*
 291                          * Is the MPU PRCM interrupt handler racing with the
 292                          * IVA2 PRCM interrupt handler ?
 293                          */
 294                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 295                              "but no wakeup sources are marked\n");
 296                 } else {
 297                         /* XXX we need to expand our PRCM interrupt handler */
 298                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 299                              "no code to handle it (%08x)\n", irqstatus_mpu);
 300                 }
 301
 302                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 303                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 304
 305                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 306                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 307                 irqstatus_mpu &= irqenable_mpu;
 308
 309         } while (irqstatus_mpu);
 310
 311         return IRQ_HANDLED;
 312 }
 313
 314 /* Function to restore the table entry that was modified for enabling MMU */
 315 static void restore_table_entry(void)
 316 {
 317         void __iomem *scratchpad_address;
 318         u32 previous_value, control_reg_value;
 319         u32 *address;
 320
 321         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 322
 323         /* Get address of entry that was modified */
 324         address = (u32 *)__raw_readl(scratchpad_address +
 325                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 326         /* Get the previous value which needs to be restored */
 327         previous_value = __raw_readl(scratchpad_address +
 328                                      OMAP343X_TABLE_VALUE_OFFSET);
 329         address = __va(address);
 330         *address = previous_value;
 331         flush_tlb_all();
 332         control_reg_value = __raw_readl(scratchpad_address
 333                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 334         /* This will enable caches and prediction */
 335         set_cr(control_reg_value);
 336 }
 337
 338 void omap_sram_idle(void)
 339 {
 340         /* Variable to tell what needs to be saved and restored
 341          * in omap_sram_idle*/
 342         /* save_state = 0 => Nothing to save and restored */
 343         /* save_state = 1 => Only L1 and logic lost */
 344         /* save_state = 2 => Only L2 lost */
 345         /* save_state = 3 => L1, L2 and logic lost */
 346         int save_state = 0;
 347         int mpu_next_state = PWRDM_POWER_ON;
 348         int per_next_state = PWRDM_POWER_ON;
 349         int core_next_state = PWRDM_POWER_ON;
 350         int per_going_off;
 351         int core_prev_state, per_prev_state;
 352         u32 sdrc_pwr = 0;
 353
 354         if (!_omap_sram_idle)
 355                 return;
 356
 357         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 358         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 359         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 360         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 361
 362         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 363         switch (mpu_next_state) {
 364         case PWRDM_POWER_ON:
 365         case PWRDM_POWER_RET:
 366                 /* No need to save context */
 367                 save_state = 0;
 368                 break;
 369         case PWRDM_POWER_OFF:
 370                 save_state = 3;
 371                 break;
 372         default:
 373                 /* Invalid state */
 374                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 375                 return;
 376         }
 377         pwrdm_pre_transition();
 378
 379         /* NEON control */
 380         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 381                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 382
 383         /* Enable IO-PAD and IO-CHAIN wakeups */
 384         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 385         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 386         if (omap3_has_io_wakeup() &&
 387             (per_next_state < PWRDM_POWER_ON ||
 388              core_next_state < PWRDM_POWER_ON)) {
 389                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 390                 omap3_enable_io_chain();
 391         }
 392
 393         /* Block console output in case it is on one of the OMAP UARTs */
 394         if (!is_suspending())
 395                 if (per_next_state < PWRDM_POWER_ON ||
 396                     core_next_state < PWRDM_POWER_ON)
 397                         if (!console_trylock())
 398                                 goto console_still_active;
 399
 400         /* PER */
 401         if (per_next_state < PWRDM_POWER_ON) {
 402                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 403                 omap_uart_prepare_idle(2);
 404                 omap_uart_prepare_idle(3);
 405                 omap2_gpio_prepare_for_idle(per_going_off);
 406                 if (per_next_state == PWRDM_POWER_OFF)
 407                                 omap3_per_save_context();
 408         }
 409
 410         /* CORE */
 411         if (core_next_state < PWRDM_POWER_ON) {
 412                 omap_uart_prepare_idle(0);
 413                 omap_uart_prepare_idle(1);
 414                 if (core_next_state == PWRDM_POWER_OFF) {
 415                         omap3_core_save_context();
 416                         omap3_cm_save_context();
 417                 }
 418         }
 419
 420         omap3_intc_prepare_idle();
 421
 422         /*
 423         * On EMU/HS devices ROM code restores a SRDC value
 424         * from scratchpad which has automatic self refresh on timeout
 425         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 426         * Hence store/restore the SDRC_POWER register here.
 427         */
 428         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 429             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 430             core_next_state == PWRDM_POWER_OFF)
 431                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 432
 433         /*
 434          * omap3_arm_context is the location where ARM registers
 435          * get saved. The restore path then reads from this
 436          * location and restores them back.
 437          */
 438         _omap_sram_idle(omap3_arm_context, save_state);
 439         cpu_init();
 440
 441         /* Restore normal SDRC POWER settings */
 442         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 443             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 444             core_next_state == PWRDM_POWER_OFF)
 445                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 446
 447         /* Restore table entry modified during MMU restoration */
 448         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 449                 restore_table_entry();
 450
 451         /* CORE */
 452         if (core_next_state < PWRDM_POWER_ON) {
 453                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 454                 if (core_prev_state == PWRDM_POWER_OFF) {
 455                         omap3_core_restore_context();
 456                         omap3_cm_restore_context();
 457                         omap3_sram_restore_context();
 458                         omap2_sms_restore_context();
 459                 }
 460                 omap_uart_resume_idle(0);
 461                 omap_uart_resume_idle(1);
 462                 if (core_next_state == PWRDM_POWER_OFF)
 463                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 464                                                OMAP3430_GR_MOD,
 465                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 466         }
 467         omap3_intc_resume_idle();
 468
 469         /* PER */
 470         if (per_next_state < PWRDM_POWER_ON) {
 471                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 472                 omap2_gpio_resume_after_idle();
 473                 if (per_prev_state == PWRDM_POWER_OFF)
 474                         omap3_per_restore_context();
 475                 omap_uart_resume_idle(2);
 476                 omap_uart_resume_idle(3);
 477         }
 478
 479         if (!is_suspending())
 480                 console_unlock();
 481
 482 console_still_active:
 483         /* Disable IO-PAD and IO-CHAIN wakeup */
 484         if (omap3_has_io_wakeup() &&
 485             (per_next_state < PWRDM_POWER_ON ||
 486              core_next_state < PWRDM_POWER_ON)) {
 487                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 488                                              PM_WKEN);
 489                 omap3_disable_io_chain();
 490         }
 491
 492         pwrdm_post_transition();
 493
 494         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 495 }
 496
 497 int omap3_can_sleep(void)
 498 {
 499         if (!sleep_while_idle)
 500                 return 0;
 501         if (!omap_uart_can_sleep())
 502                 return 0;
 503         return 1;
 504 }
 505
 506 static void omap3_pm_idle(void)
 507 {
 508         local_irq_disable();
 509         local_fiq_disable();
 510
 511         if (!omap3_can_sleep())
 512                 goto out;
 513
 514         if (omap_irq_pending() || need_resched())
 515                 goto out;
 516
 517         omap_sram_idle();
 518
 519 out:
 520         local_fiq_enable();
 521         local_irq_enable();
 522 }
 523
 524 #ifdef CONFIG_SUSPEND
 525 static int omap3_pm_suspend(void)
 526 {
 527         struct power_state *pwrst;
 528         int state, ret = 0;
 529
 530         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 531                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 532                                          wakeup_timer_milliseconds);
 533
 534         /* Read current next_pwrsts */
 535         list_for_each_entry(pwrst, &pwrst_list, node)
 536                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 537         /* Set ones wanted by suspend */
 538         list_for_each_entry(pwrst, &pwrst_list, node) {
 539                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 540                         goto restore;
 541                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 542                         goto restore;
 543         }
 544
 545         omap_uart_prepare_suspend();
 546         omap3_intc_suspend();
 547
 548         omap_sram_idle();
 549
 550 restore:
 551         /* Restore next_pwrsts */
 552         list_for_each_entry(pwrst, &pwrst_list, node) {
 553                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 554                 if (state > pwrst->next_state) {
 555                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 556                                "target state %d\n",
 557                                pwrst->pwrdm->name, pwrst->next_state);
 558                         ret = -1;
 559                 }
 560                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 561         }
 562         if (ret)
 563                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 564         else
 565                 printk(KERN_INFO "Successfully put all powerdomains "
 566                        "to target state\n");
 567
 568         return ret;
 569 }
 570
 571 static int omap3_pm_enter(suspend_state_t unused)
 572 {
 573         int ret = 0;
 574
 575         switch (suspend_state) {
 576         case PM_SUSPEND_STANDBY:
 577         case PM_SUSPEND_MEM:
 578                 ret = omap3_pm_suspend();
 579                 break;
 580         default:
 581                 ret = -EINVAL;
 582         }
 583
 584         return ret;
 585 }
 586
 587 /* Hooks to enable / disable UART interrupts during suspend */
 588 static int omap3_pm_begin(suspend_state_t state)
 589 {
 590         disable_hlt();
 591         suspend_state = state;
 592         omap_uart_enable_irqs(0);
 593         return 0;
 594 }
 595
 596 static void omap3_pm_end(void)
 597 {
 598         suspend_state = PM_SUSPEND_ON;
 599         omap_uart_enable_irqs(1);
 600         enable_hlt();
 601         return;
 602 }
 603
 604 static const struct platform_suspend_ops omap_pm_ops = {
 605         .begin          = omap3_pm_begin,
 606         .end            = omap3_pm_end,
 607         .enter          = omap3_pm_enter,
 608         .valid          = suspend_valid_only_mem,
 609 };
 610 #endif /* CONFIG_SUSPEND */
 611
 612
 613 /**
 614  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 615  *                   retention
 616  *
 617  * In cases where IVA2 is activated by bootcode, it may prevent
 618  * full-chip retention or off-mode because it is not idle.  This
 619  * function forces the IVA2 into idle state so it can go
 620  * into retention/off and thus allow full-chip retention/off.
 621  *
 622  **/
 623 static void __init omap3_iva_idle(void)
 624 {
 625         /* ensure IVA2 clock is disabled */
 626         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 627
 628         /* if no clock activity, nothing else to do */
 629         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 630               OMAP3430_CLKACTIVITY_IVA2_MASK))
 631                 return;
 632
 633         /* Reset IVA2 */
 634         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 635                           OMAP3430_RST2_IVA2_MASK |
 636                           OMAP3430_RST3_IVA2_MASK,
 637                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 638
 639         /* Enable IVA2 clock */
 640         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 641                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 642
 643         /* Set IVA2 boot mode to 'idle' */
 644         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 645                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 646
 647         /* Un-reset IVA2 */
 648         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 649
 650         /* Disable IVA2 clock */
 651         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 652
 653         /* Reset IVA2 */
 654         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 655                           OMAP3430_RST2_IVA2_MASK |
 656                           OMAP3430_RST3_IVA2_MASK,
 657                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 658 }
 659
 660 static void __init omap3_d2d_idle(void)
 661 {
 662         u16 mask, padconf;
 663
 664         /* In a stand alone OMAP3430 where there is not a stacked
 665          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 666          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 667          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 668         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 669         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 670         padconf |= mask;
 671         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 672
 673         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 674         padconf |= mask;
 675         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 676
 677         /* reset modem */
 678         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 679                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 680                           CORE_MOD, OMAP2_RM_RSTCTRL);
 681         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 682 }
 683
 684 static void __init prcm_setup_regs(void)
 685 {
 686         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 687                                         OMAP3630_EN_UART4_MASK : 0;
 688         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 689                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 690
 691         /* XXX This should be handled by hwmod code or SCM init code */
 692         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 693
 694         /*
 695          * Enable control of expternal oscillator through
 696          * sys_clkreq. In the long run clock framework should
 697          * take care of this.
 698          */
 699         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 700                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 701                              OMAP3430_GR_MOD,
 702                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 703
 704         /* setup wakup source */
 705         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 706                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 707                           WKUP_MOD, PM_WKEN);
 708         /* No need to write EN_IO, that is always enabled */
 709         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 710                           OMAP3430_GRPSEL_GPT1_MASK |
 711                           OMAP3430_GRPSEL_GPT12_MASK,
 712                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 713         /* For some reason IO doesn't generate wakeup event even if
 714          * it is selected to mpu wakeup goup */
 715         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 716                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 717
 718         /* Enable PM_WKEN to support DSS LPR */
 719         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 720                                 OMAP3430_DSS_MOD, PM_WKEN);
 721
 722         /* Enable wakeups in PER */
 723         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 724                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 725                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 726                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 727                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 728                           OMAP3430_EN_MCBSP4_MASK,
 729                           OMAP3430_PER_MOD, PM_WKEN);
 730         /* and allow them to wake up MPU */
 731         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 732                           OMAP3430_GRPSEL_GPIO2_MASK |
 733                           OMAP3430_GRPSEL_GPIO3_MASK |
 734                           OMAP3430_GRPSEL_GPIO4_MASK |
 735                           OMAP3430_GRPSEL_GPIO5_MASK |
 736                           OMAP3430_GRPSEL_GPIO6_MASK |
 737                           OMAP3430_GRPSEL_UART3_MASK |
 738                           OMAP3430_GRPSEL_MCBSP2_MASK |
 739                           OMAP3430_GRPSEL_MCBSP3_MASK |
 740                           OMAP3430_GRPSEL_MCBSP4_MASK,
 741                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 742
 743         /* Don't attach IVA interrupts */
 744         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 745         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 746         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 747         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 748
 749         /* Clear any pending 'reset' flags */
 750         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 751         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 752         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 753         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 754         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 755         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 756         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 757
 758         /* Clear any pending PRCM interrupts */
 759         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 760
 761         omap3_iva_idle();
 762         omap3_d2d_idle();
 763 }
 764
 765 void omap3_pm_off_mode_enable(int enable)
 766 {
 767         struct power_state *pwrst;
 768         u32 state;
 769
 770         if (enable)
 771                 state = PWRDM_POWER_OFF;
 772         else
 773                 state = PWRDM_POWER_RET;
 774
 775 #ifdef CONFIG_CPU_IDLE
 776         /*
 777          * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
 778          * enable OFF mode in a stable form for previous revisions, restrict
 779          * instead to RET
 780          */
 781         if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 782                 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
 783         else
 784                 omap3_cpuidle_update_states(state, state);
 785 #endif
 786
 787         list_for_each_entry(pwrst, &pwrst_list, node) {
 788                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 789                                 pwrst->pwrdm == core_pwrdm &&
 790                                 state == PWRDM_POWER_OFF) {
 791                         pwrst->next_state = PWRDM_POWER_RET;
 792                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 793                                 __func__);
 794                 } else {
 795                         pwrst->next_state = state;
 796                 }
 797                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 798         }
 799 }
 800
 801 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 802 {
 803         struct power_state *pwrst;
 804
 805         list_for_each_entry(pwrst, &pwrst_list, node) {
 806                 if (pwrst->pwrdm == pwrdm)
 807                         return pwrst->next_state;
 808         }
 809         return -EINVAL;
 810 }
 811
 812 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 813 {
 814         struct power_state *pwrst;
 815
 816         list_for_each_entry(pwrst, &pwrst_list, node) {
 817                 if (pwrst->pwrdm == pwrdm) {
 818                         pwrst->next_state = state;
 819                         return 0;
 820                 }
 821         }
 822         return -EINVAL;
 823 }
 824
 825 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 826 {
 827         struct power_state *pwrst;
 828
 829         if (!pwrdm->pwrsts)
 830                 return 0;
 831
 832         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 833         if (!pwrst)
 834                 return -ENOMEM;
 835         pwrst->pwrdm = pwrdm;
 836         pwrst->next_state = PWRDM_POWER_RET;
 837         list_add(&pwrst->node, &pwrst_list);
 838
 839         if (pwrdm_has_hdwr_sar(pwrdm))
 840                 pwrdm_enable_hdwr_sar(pwrdm);
 841
 842         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 843 }
 844
 845 /*
 846  * Enable hw supervised mode for all clockdomains if it's
 847  * supported. Initiate sleep transition for other clockdomains, if
 848  * they are not used
 849  */
 850 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 851 {
 852         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 853                 clkdm_allow_idle(clkdm);
 854         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 855                  atomic_read(&clkdm->usecount) == 0)
 856                 clkdm_sleep(clkdm);
 857         return 0;
 858 }
 859
 860 void omap_push_sram_idle(void)
 861 {
 862         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 863                                         omap34xx_cpu_suspend_sz);
 864         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 865                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 866                                 save_secure_ram_context_sz);
 867 }
 868
 869 static void __init pm_errata_configure(void)
 870 {
 871         if (cpu_is_omap3630()) {
 872                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 873                 /* Enable the l2 cache toggling in sleep logic */
 874                 enable_omap3630_toggle_l2_on_restore();
 875                 if (omap_rev() < OMAP3630_REV_ES1_2)
 876                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 877         }
 878 }
 879
 880 static int __init omap3_pm_init(void)
 881 {
 882         struct power_state *pwrst, *tmp;
 883         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 884         int ret;
 885
 886         if (!cpu_is_omap34xx())
 887                 return -ENODEV;
 888
 889         pm_errata_configure();
 890
 891         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 892
 893         /* XXX prcm_setup_regs needs to be before enabling hw
 894          * supervised mode for powerdomains */
 895         prcm_setup_regs();
 896
 897         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 898                           (irq_handler_t)prcm_interrupt_handler,
 899                           IRQF_DISABLED, "prcm", NULL);
 900         if (ret) {
 901                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 902                        INT_34XX_PRCM_MPU_IRQ);
 903                 goto err1;
 904         }
 905
 906         ret = pwrdm_for_each(pwrdms_setup, NULL);
 907         if (ret) {
 908                 printk(KERN_ERR "Failed to setup powerdomains\n");
 909                 goto err2;
 910         }
 911
 912         (void) clkdm_for_each(clkdms_setup, NULL);
 913
 914         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 915         if (mpu_pwrdm == NULL) {
 916                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 917                 goto err2;
 918         }
 919
 920         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 921         per_pwrdm = pwrdm_lookup("per_pwrdm");
 922         core_pwrdm = pwrdm_lookup("core_pwrdm");
 923         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 924
 925         neon_clkdm = clkdm_lookup("neon_clkdm");
 926         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 927         per_clkdm = clkdm_lookup("per_clkdm");
 928         core_clkdm = clkdm_lookup("core_clkdm");
 929
 930         omap_push_sram_idle();
 931 #ifdef CONFIG_SUSPEND
 932         suspend_set_ops(&omap_pm_ops);
 933 #endif /* CONFIG_SUSPEND */
 934
 935         pm_idle = omap3_pm_idle;
 936         omap3_idle_init();
 937
 938         /*
 939          * RTA is disabled during initialization as per erratum i608
 940          * it is safer to disable RTA by the bootloader, but we would like
 941          * to be doubly sure here and prevent any mishaps.
 942          */
 943         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 944                 omap3630_ctrl_disable_rta();
 945
 946         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 947         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 948                 omap3_secure_ram_storage =
 949                         kmalloc(0x803F, GFP_KERNEL);
 950                 if (!omap3_secure_ram_storage)
 951                         printk(KERN_ERR "Memory allocation failed when"
 952                                         "allocating for secure sram context\n");
 953
 954                 local_irq_disable();
 955                 local_fiq_disable();
 956
 957                 omap_dma_global_context_save();
 958                 omap3_save_secure_ram_context();
 959                 omap_dma_global_context_restore();
 960
 961                 local_irq_enable();
 962                 local_fiq_enable();
 963         }
 964
 965         omap3_save_scratchpad_contents();
 966 err1:
 967         return ret;
 968 err2:
 969         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 970         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 971                 list_del(&pwrst->node);
 972                 kfree(pwrst);
 973         }
 974         return ret;
 975 }
 976
 977 late_initcall(omap3_pm_init);