2 * OMAP3 Power Management Routines
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/suspend.h>
23 #include <linux/interrupt.h>
24 #include <linux/module.h>
25 #include <linux/list.h>
26 #include <linux/err.h>
27 #include <linux/gpio.h>
28 #include <linux/clk.h>
29 #include <linux/delay.h>
30 #include <linux/slab.h>
31 #include <linux/console.h>
33 #include <plat/sram.h>
34 #include "clockdomain.h"
35 #include "powerdomain.h"
36 #include <plat/serial.h>
37 #include <plat/sdrc.h>
38 #include <plat/prcm.h>
39 #include <plat/gpmc.h>
42 #include <asm/tlbflush.h>
44 #include "cm2xxx_3xxx.h"
45 #include "cm-regbits-34xx.h"
46 #include "prm-regbits-34xx.h"
48 #include "prm2xxx_3xxx.h"
54 static suspend_state_t suspend_state = PM_SUSPEND_ON;
55 static inline bool is_suspending(void)
57 return (suspend_state != PM_SUSPEND_ON);
60 static inline bool is_suspending(void)
66 /* Scratchpad offsets */
67 #define OMAP343X_TABLE_ADDRESS_OFFSET 0xc4
68 #define OMAP343X_TABLE_VALUE_OFFSET 0xc0
69 #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
71 /* pm34xx errata defined in pm.h */
75 struct powerdomain *pwrdm;
80 struct list_head node;
83 static LIST_HEAD(pwrst_list);
85 static void (*_omap_sram_idle)(u32 *addr, int save_state);
87 static int (*_omap_save_secure_sram)(u32 *addr);
89 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
90 static struct powerdomain *core_pwrdm, *per_pwrdm;
91 static struct powerdomain *cam_pwrdm;
93 static inline void omap3_per_save_context(void)
95 omap_gpio_save_context();
98 static inline void omap3_per_restore_context(void)
100 omap_gpio_restore_context();
103 static void omap3_enable_io_chain(void)
107 if (omap_rev() >= OMAP3430_REV_ES3_1) {
108 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
110 /* Do a readback to assure write has been done */
111 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
113 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
114 OMAP3430_ST_IO_CHAIN_MASK)) {
116 if (timeout > 1000) {
117 printk(KERN_ERR "Wake up daisy chain "
118 "activation failed.\n");
121 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
127 static void omap3_disable_io_chain(void)
129 if (omap_rev() >= OMAP3430_REV_ES3_1)
130 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
134 static void omap3_core_save_context(void)
136 omap3_ctrl_save_padconf();
139 * Force write last pad into memory, as this can fail in some
140 * cases according to errata 1.157, 1.185
142 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
143 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
145 /* Save the Interrupt controller context */
146 omap_intc_save_context();
147 /* Save the GPMC context */
148 omap3_gpmc_save_context();
149 /* Save the system control module context, padconf already save above*/
150 omap3_control_save_context();
151 omap_dma_global_context_save();
154 static void omap3_core_restore_context(void)
156 /* Restore the control module context, padconf restored by h/w */
157 omap3_control_restore_context();
158 /* Restore the GPMC context */
159 omap3_gpmc_restore_context();
160 /* Restore the interrupt controller context */
161 omap_intc_restore_context();
162 omap_dma_global_context_restore();
166 * FIXME: This function should be called before entering off-mode after
167 * OMAP3 secure services have been accessed. Currently it is only called
168 * once during boot sequence, but this works as we are not using secure
171 static void omap3_save_secure_ram_context(void)
174 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
176 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
178 * MPU next state must be set to POWER_ON temporarily,
179 * otherwise the WFI executed inside the ROM code
180 * will hang the system.
182 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
183 ret = _omap_save_secure_sram((u32 *)
184 __pa(omap3_secure_ram_storage));
185 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
186 /* Following is for error tracking, it should not happen */
188 printk(KERN_ERR "save_secure_sram() returns %08x\n",
197 * PRCM Interrupt Handler Helper Function
199 * The purpose of this function is to clear any wake-up events latched
200 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
201 * may occur whilst attempting to clear a PM_WKST_x register and thus
202 * set another bit in this register. A while loop is used to ensure
203 * that any peripheral wake-up events occurring while attempting to
204 * clear the PM_WKST_x are detected and cleared.
206 static int prcm_clear_mod_irqs(s16 module, u8 regs)
208 u32 wkst, fclk, iclk, clken;
209 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
210 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
211 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
212 u16 grpsel_off = (regs == 3) ?
213 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
216 wkst = omap2_prm_read_mod_reg(module, wkst_off);
217 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
219 iclk = omap2_cm_read_mod_reg(module, iclk_off);
220 fclk = omap2_cm_read_mod_reg(module, fclk_off);
223 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
225 * For USBHOST, we don't know whether HOST1 or
226 * HOST2 woke us up, so enable both f-clocks
228 if (module == OMAP3430ES2_USBHOST_MOD)
229 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
230 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
231 omap2_prm_write_mod_reg(wkst, module, wkst_off);
232 wkst = omap2_prm_read_mod_reg(module, wkst_off);
235 omap2_cm_write_mod_reg(iclk, module, iclk_off);
236 omap2_cm_write_mod_reg(fclk, module, fclk_off);
242 static int _prcm_int_handle_wakeup(void)
246 c = prcm_clear_mod_irqs(WKUP_MOD, 1);
247 c += prcm_clear_mod_irqs(CORE_MOD, 1);
248 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
249 if (omap_rev() > OMAP3430_REV_ES1_0) {
250 c += prcm_clear_mod_irqs(CORE_MOD, 3);
251 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
258 * PRCM Interrupt Handler
260 * The PRM_IRQSTATUS_MPU register indicates if there are any pending
261 * interrupts from the PRCM for the MPU. These bits must be cleared in
262 * order to clear the PRCM interrupt. The PRCM interrupt handler is
263 * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
264 * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
265 * register indicates that a wake-up event is pending for the MPU and
266 * this bit can only be cleared if the all the wake-up events latched
267 * in the various PM_WKST_x registers have been cleared. The interrupt
268 * handler is implemented using a do-while loop so that if a wake-up
269 * event occurred during the processing of the prcm interrupt handler
270 * (setting a bit in the corresponding PM_WKST_x register and thus
271 * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
272 * this would be handled.
274 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
276 u32 irqenable_mpu, irqstatus_mpu;
279 irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
280 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
281 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
282 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
283 irqstatus_mpu &= irqenable_mpu;
286 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
287 OMAP3430_IO_ST_MASK)) {
288 c = _prcm_int_handle_wakeup();
291 * Is the MPU PRCM interrupt handler racing with the
292 * IVA2 PRCM interrupt handler ?
294 WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
295 "but no wakeup sources are marked\n");
297 /* XXX we need to expand our PRCM interrupt handler */
298 WARN(1, "prcm: WARNING: PRCM interrupt received, but "
299 "no code to handle it (%08x)\n", irqstatus_mpu);
302 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
303 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
305 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
306 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
307 irqstatus_mpu &= irqenable_mpu;
309 } while (irqstatus_mpu);
314 static void restore_control_register(u32 val)
316 __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
319 /* Function to restore the table entry that was modified for enabling MMU */
320 static void restore_table_entry(void)
322 void __iomem *scratchpad_address;
323 u32 previous_value, control_reg_value;
326 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
328 /* Get address of entry that was modified */
329 address = (u32 *)__raw_readl(scratchpad_address +
330 OMAP343X_TABLE_ADDRESS_OFFSET);
331 /* Get the previous value which needs to be restored */
332 previous_value = __raw_readl(scratchpad_address +
333 OMAP343X_TABLE_VALUE_OFFSET);
334 address = __va(address);
335 *address = previous_value;
337 control_reg_value = __raw_readl(scratchpad_address
338 + OMAP343X_CONTROL_REG_VALUE_OFFSET);
339 /* This will enable caches and prediction */
340 restore_control_register(control_reg_value);
343 void omap_sram_idle(void)
345 /* Variable to tell what needs to be saved and restored
346 * in omap_sram_idle*/
347 /* save_state = 0 => Nothing to save and restored */
348 /* save_state = 1 => Only L1 and logic lost */
349 /* save_state = 2 => Only L2 lost */
350 /* save_state = 3 => L1, L2 and logic lost */
352 int mpu_next_state = PWRDM_POWER_ON;
353 int per_next_state = PWRDM_POWER_ON;
354 int core_next_state = PWRDM_POWER_ON;
356 int core_prev_state, per_prev_state;
359 if (!_omap_sram_idle)
362 pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
363 pwrdm_clear_all_prev_pwrst(neon_pwrdm);
364 pwrdm_clear_all_prev_pwrst(core_pwrdm);
365 pwrdm_clear_all_prev_pwrst(per_pwrdm);
367 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
368 switch (mpu_next_state) {
370 case PWRDM_POWER_RET:
371 /* No need to save context */
374 case PWRDM_POWER_OFF:
379 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
382 pwrdm_pre_transition();
385 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
386 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
388 /* Enable IO-PAD and IO-CHAIN wakeups */
389 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
390 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
391 if (omap3_has_io_wakeup() &&
392 (per_next_state < PWRDM_POWER_ON ||
393 core_next_state < PWRDM_POWER_ON)) {
394 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
395 omap3_enable_io_chain();
398 /* Block console output in case it is on one of the OMAP UARTs */
399 if (!is_suspending())
400 if (per_next_state < PWRDM_POWER_ON ||
401 core_next_state < PWRDM_POWER_ON)
402 if (!console_trylock())
403 goto console_still_active;
406 if (per_next_state < PWRDM_POWER_ON) {
407 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
408 omap_uart_prepare_idle(2);
409 omap_uart_prepare_idle(3);
410 omap2_gpio_prepare_for_idle(per_going_off);
411 if (per_next_state == PWRDM_POWER_OFF)
412 omap3_per_save_context();
416 if (core_next_state < PWRDM_POWER_ON) {
417 omap_uart_prepare_idle(0);
418 omap_uart_prepare_idle(1);
419 if (core_next_state == PWRDM_POWER_OFF) {
420 omap3_core_save_context();
421 omap3_cm_save_context();
425 omap3_intc_prepare_idle();
428 * On EMU/HS devices ROM code restores a SRDC value
429 * from scratchpad which has automatic self refresh on timeout
430 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
431 * Hence store/restore the SDRC_POWER register here.
433 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
434 omap_type() != OMAP2_DEVICE_TYPE_GP &&
435 core_next_state == PWRDM_POWER_OFF)
436 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
439 * omap3_arm_context is the location where ARM registers
440 * get saved. The restore path then reads from this
441 * location and restores them back.
443 _omap_sram_idle(omap3_arm_context, save_state);
446 /* Restore normal SDRC POWER settings */
447 if (omap_rev() >= OMAP3430_REV_ES3_0 &&
448 omap_type() != OMAP2_DEVICE_TYPE_GP &&
449 core_next_state == PWRDM_POWER_OFF)
450 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
452 /* Restore table entry modified during MMU restoration */
453 if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
454 restore_table_entry();
457 if (core_next_state < PWRDM_POWER_ON) {
458 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
459 if (core_prev_state == PWRDM_POWER_OFF) {
460 omap3_core_restore_context();
461 omap3_cm_restore_context();
462 omap3_sram_restore_context();
463 omap2_sms_restore_context();
465 omap_uart_resume_idle(0);
466 omap_uart_resume_idle(1);
467 if (core_next_state == PWRDM_POWER_OFF)
468 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
470 OMAP3_PRM_VOLTCTRL_OFFSET);
472 omap3_intc_resume_idle();
475 if (per_next_state < PWRDM_POWER_ON) {
476 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
477 omap2_gpio_resume_after_idle();
478 if (per_prev_state == PWRDM_POWER_OFF)
479 omap3_per_restore_context();
480 omap_uart_resume_idle(2);
481 omap_uart_resume_idle(3);
484 if (!is_suspending())
487 console_still_active:
488 /* Disable IO-PAD and IO-CHAIN wakeup */
489 if (omap3_has_io_wakeup() &&
490 (per_next_state < PWRDM_POWER_ON ||
491 core_next_state < PWRDM_POWER_ON)) {
492 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
494 omap3_disable_io_chain();
497 pwrdm_post_transition();
499 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
502 int omap3_can_sleep(void)
504 if (!sleep_while_idle)
506 if (!omap_uart_can_sleep())
511 static void omap3_pm_idle(void)
516 if (!omap3_can_sleep())
519 if (omap_irq_pending() || need_resched())
529 #ifdef CONFIG_SUSPEND
530 static int omap3_pm_suspend(void)
532 struct power_state *pwrst;
535 if (wakeup_timer_seconds || wakeup_timer_milliseconds)
536 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
537 wakeup_timer_milliseconds);
539 /* Read current next_pwrsts */
540 list_for_each_entry(pwrst, &pwrst_list, node)
541 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
542 /* Set ones wanted by suspend */
543 list_for_each_entry(pwrst, &pwrst_list, node) {
544 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
546 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
550 omap_uart_prepare_suspend();
551 omap3_intc_suspend();
556 /* Restore next_pwrsts */
557 list_for_each_entry(pwrst, &pwrst_list, node) {
558 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
559 if (state > pwrst->next_state) {
560 printk(KERN_INFO "Powerdomain (%s) didn't enter "
562 pwrst->pwrdm->name, pwrst->next_state);
565 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
568 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
570 printk(KERN_INFO "Successfully put all powerdomains "
571 "to target state\n");
576 static int omap3_pm_enter(suspend_state_t unused)
580 switch (suspend_state) {
581 case PM_SUSPEND_STANDBY:
583 ret = omap3_pm_suspend();
592 /* Hooks to enable / disable UART interrupts during suspend */
593 static int omap3_pm_begin(suspend_state_t state)
596 suspend_state = state;
597 omap_uart_enable_irqs(0);
601 static void omap3_pm_end(void)
603 suspend_state = PM_SUSPEND_ON;
604 omap_uart_enable_irqs(1);
609 static const struct platform_suspend_ops omap_pm_ops = {
610 .begin = omap3_pm_begin,
612 .enter = omap3_pm_enter,
613 .valid = suspend_valid_only_mem,
615 #endif /* CONFIG_SUSPEND */
619 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
622 * In cases where IVA2 is activated by bootcode, it may prevent
623 * full-chip retention or off-mode because it is not idle. This
624 * function forces the IVA2 into idle state so it can go
625 * into retention/off and thus allow full-chip retention/off.
628 static void __init omap3_iva_idle(void)
630 /* ensure IVA2 clock is disabled */
631 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
633 /* if no clock activity, nothing else to do */
634 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
635 OMAP3430_CLKACTIVITY_IVA2_MASK))
639 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
640 OMAP3430_RST2_IVA2_MASK |
641 OMAP3430_RST3_IVA2_MASK,
642 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
644 /* Enable IVA2 clock */
645 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
646 OMAP3430_IVA2_MOD, CM_FCLKEN);
648 /* Set IVA2 boot mode to 'idle' */
649 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
650 OMAP343X_CONTROL_IVA2_BOOTMOD);
653 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
655 /* Disable IVA2 clock */
656 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
659 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
660 OMAP3430_RST2_IVA2_MASK |
661 OMAP3430_RST3_IVA2_MASK,
662 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
665 static void __init omap3_d2d_idle(void)
669 /* In a stand alone OMAP3430 where there is not a stacked
670 * modem for the D2D Idle Ack and D2D MStandby must be pulled
671 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
672 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
673 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
674 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
676 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
678 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
680 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
683 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
684 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
685 CORE_MOD, OMAP2_RM_RSTCTRL);
686 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
689 static void __init prcm_setup_regs(void)
691 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
692 OMAP3630_EN_UART4_MASK : 0;
693 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
694 OMAP3630_GRPSEL_UART4_MASK : 0;
696 /* XXX Reset all wkdeps. This should be done when initializing
698 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
699 omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
700 omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
701 omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
702 omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
703 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
704 if (omap_rev() > OMAP3430_REV_ES1_0) {
705 omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
706 omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
708 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
710 /* XXX This should be handled by hwmod code or SCM init code */
711 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
714 * Enable control of expternal oscillator through
715 * sys_clkreq. In the long run clock framework should
718 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
719 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
721 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
723 /* setup wakup source */
724 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
725 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
727 /* No need to write EN_IO, that is always enabled */
728 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
729 OMAP3430_GRPSEL_GPT1_MASK |
730 OMAP3430_GRPSEL_GPT12_MASK,
731 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
732 /* For some reason IO doesn't generate wakeup event even if
733 * it is selected to mpu wakeup goup */
734 omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
735 OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
737 /* Enable PM_WKEN to support DSS LPR */
738 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
739 OMAP3430_DSS_MOD, PM_WKEN);
741 /* Enable wakeups in PER */
742 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
743 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
744 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
745 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
746 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
747 OMAP3430_EN_MCBSP4_MASK,
748 OMAP3430_PER_MOD, PM_WKEN);
749 /* and allow them to wake up MPU */
750 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
751 OMAP3430_GRPSEL_GPIO2_MASK |
752 OMAP3430_GRPSEL_GPIO3_MASK |
753 OMAP3430_GRPSEL_GPIO4_MASK |
754 OMAP3430_GRPSEL_GPIO5_MASK |
755 OMAP3430_GRPSEL_GPIO6_MASK |
756 OMAP3430_GRPSEL_UART3_MASK |
757 OMAP3430_GRPSEL_MCBSP2_MASK |
758 OMAP3430_GRPSEL_MCBSP3_MASK |
759 OMAP3430_GRPSEL_MCBSP4_MASK,
760 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
762 /* Don't attach IVA interrupts */
763 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
764 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
765 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
766 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
768 /* Clear any pending 'reset' flags */
769 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
770 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
771 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
772 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
773 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
774 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
775 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
777 /* Clear any pending PRCM interrupts */
778 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
784 void omap3_pm_off_mode_enable(int enable)
786 struct power_state *pwrst;
790 state = PWRDM_POWER_OFF;
792 state = PWRDM_POWER_RET;
794 #ifdef CONFIG_CPU_IDLE
796 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
797 * enable OFF mode in a stable form for previous revisions, restrict
800 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
801 omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
803 omap3_cpuidle_update_states(state, state);
806 list_for_each_entry(pwrst, &pwrst_list, node) {
807 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
808 pwrst->pwrdm == core_pwrdm &&
809 state == PWRDM_POWER_OFF) {
810 pwrst->next_state = PWRDM_POWER_RET;
812 "%s: Core OFF disabled due to errata i583\n",
815 pwrst->next_state = state;
817 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
821 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
823 struct power_state *pwrst;
825 list_for_each_entry(pwrst, &pwrst_list, node) {
826 if (pwrst->pwrdm == pwrdm)
827 return pwrst->next_state;
832 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
834 struct power_state *pwrst;
836 list_for_each_entry(pwrst, &pwrst_list, node) {
837 if (pwrst->pwrdm == pwrdm) {
838 pwrst->next_state = state;
845 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
847 struct power_state *pwrst;
852 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
855 pwrst->pwrdm = pwrdm;
856 pwrst->next_state = PWRDM_POWER_RET;
857 list_add(&pwrst->node, &pwrst_list);
859 if (pwrdm_has_hdwr_sar(pwrdm))
860 pwrdm_enable_hdwr_sar(pwrdm);
862 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
866 * Enable hw supervised mode for all clockdomains if it's
867 * supported. Initiate sleep transition for other clockdomains, if
870 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
872 if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
873 clkdm_allow_idle(clkdm);
874 else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
875 atomic_read(&clkdm->usecount) == 0)
880 void omap_push_sram_idle(void)
882 _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
883 omap34xx_cpu_suspend_sz);
884 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
885 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
886 save_secure_ram_context_sz);
889 static void __init pm_errata_configure(void)
891 if (cpu_is_omap3630()) {
892 pm34xx_errata |= PM_RTA_ERRATUM_i608;
893 /* Enable the l2 cache toggling in sleep logic */
894 enable_omap3630_toggle_l2_on_restore();
895 if (omap_rev() < OMAP3630_REV_ES1_2)
896 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
900 static int __init omap3_pm_init(void)
902 struct power_state *pwrst, *tmp;
903 struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
906 if (!cpu_is_omap34xx())
909 pm_errata_configure();
911 printk(KERN_ERR "Power Management for TI OMAP3.\n");
913 /* XXX prcm_setup_regs needs to be before enabling hw
914 * supervised mode for powerdomains */
917 ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
918 (irq_handler_t)prcm_interrupt_handler,
919 IRQF_DISABLED, "prcm", NULL);
921 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
922 INT_34XX_PRCM_MPU_IRQ);
926 ret = pwrdm_for_each(pwrdms_setup, NULL);
928 printk(KERN_ERR "Failed to setup powerdomains\n");
932 (void) clkdm_for_each(clkdms_setup, NULL);
934 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
935 if (mpu_pwrdm == NULL) {
936 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
940 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
941 per_pwrdm = pwrdm_lookup("per_pwrdm");
942 core_pwrdm = pwrdm_lookup("core_pwrdm");
943 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
945 neon_clkdm = clkdm_lookup("neon_clkdm");
946 mpu_clkdm = clkdm_lookup("mpu_clkdm");
947 per_clkdm = clkdm_lookup("per_clkdm");
948 core_clkdm = clkdm_lookup("core_clkdm");
950 omap_push_sram_idle();
951 #ifdef CONFIG_SUSPEND
952 suspend_set_ops(&omap_pm_ops);
953 #endif /* CONFIG_SUSPEND */
955 pm_idle = omap3_pm_idle;
959 * RTA is disabled during initialization as per erratum i608
960 * it is safer to disable RTA by the bootloader, but we would like
961 * to be doubly sure here and prevent any mishaps.
963 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
964 omap3630_ctrl_disable_rta();
966 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
967 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
968 omap3_secure_ram_storage =
969 kmalloc(0x803F, GFP_KERNEL);
970 if (!omap3_secure_ram_storage)
971 printk(KERN_ERR "Memory allocation failed when"
972 "allocating for secure sram context\n");
977 omap_dma_global_context_save();
978 omap3_save_secure_ram_context();
979 omap_dma_global_context_restore();
985 omap3_save_scratchpad_contents();
989 free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
990 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
991 list_del(&pwrst->node);
997 late_initcall(omap3_pm_init);