arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32
  33 #include <plat/sram.h>
  34 #include <plat/clockdomain.h>
  35 #include <plat/powerdomain.h>
  36 #include <plat/serial.h>
  37 #include <plat/sdrc.h>
  38 #include <plat/prcm.h>
  39 #include <plat/gpmc.h>
  40 #include <plat/dma.h>
  41
  42 #include <asm/tlbflush.h>
  43
  44 #include "cm.h"
  45 #include "cm-regbits-34xx.h"
  46 #include "prm-regbits-34xx.h"
  47
  48 #include "prm.h"
  49 #include "pm.h"
  50 #include "sdrc.h"
  51 #include "control.h"
  52
  53 #ifdef CONFIG_SUSPEND
  54 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  55 static inline bool is_suspending(void)
  56 {
  57         return (suspend_state != PM_SUSPEND_ON);
  58 }
  59 #else
  60 static inline bool is_suspending(void)
  61 {
  62         return false;
  63 }
  64 #endif
  65
  66 /* Scratchpad offsets */
  67 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
  68 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
  69 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
  70
  71 struct power_state {
  72         struct powerdomain *pwrdm;
  73         u32 next_state;
  74 #ifdef CONFIG_SUSPEND
  75         u32 saved_state;
  76 #endif
  77         struct list_head node;
  78 };
  79
  80 static LIST_HEAD(pwrst_list);
  81
  82 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  83
  84 static int (*_omap_save_secure_sram)(u32 *addr);
  85
  86 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  87 static struct powerdomain *core_pwrdm, *per_pwrdm;
  88 static struct powerdomain *cam_pwrdm;
  89
  90 static inline void omap3_per_save_context(void)
  91 {
  92         omap_gpio_save_context();
  93 }
  94
  95 static inline void omap3_per_restore_context(void)
  96 {
  97         omap_gpio_restore_context();
  98 }
  99
 100 static void omap3_enable_io_chain(void)
 101 {
 102         int timeout = 0;
 103
 104         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 105                 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 106                                      PM_WKEN);
 107                 /* Do a readback to assure write has been done */
 108                 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 109
 110                 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 111                          OMAP3430_ST_IO_CHAIN_MASK)) {
 112                         timeout++;
 113                         if (timeout > 1000) {
 114                                 printk(KERN_ERR "Wake up daisy chain "
 115                                        "activation failed.\n");
 116                                 return;
 117                         }
 118                         prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 119                                              WKUP_MOD, PM_WKEN);
 120                 }
 121         }
 122 }
 123
 124 static void omap3_disable_io_chain(void)
 125 {
 126         if (omap_rev() >= OMAP3430_REV_ES3_1)
 127                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 128                                        PM_WKEN);
 129 }
 130
 131 static void omap3_core_save_context(void)
 132 {
 133         u32 control_padconf_off;
 134
 135         /* Save the padconf registers */
 136         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 137         control_padconf_off |= START_PADCONF_SAVE;
 138         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 139         /* wait for the save to complete */
 140         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 141                         & PADCONF_SAVE_DONE))
 142                 udelay(1);
 143
 144         /*
 145          * Force write last pad into memory, as this can fail in some
 146          * cases according to erratas 1.157, 1.185
 147          */
 148         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 149                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 150
 151         /* Save the Interrupt controller context */
 152         omap_intc_save_context();
 153         /* Save the GPMC context */
 154         omap3_gpmc_save_context();
 155         /* Save the system control module context, padconf already save above*/
 156         omap3_control_save_context();
 157         omap_dma_global_context_save();
 158 }
 159
 160 static void omap3_core_restore_context(void)
 161 {
 162         /* Restore the control module context, padconf restored by h/w */
 163         omap3_control_restore_context();
 164         /* Restore the GPMC context */
 165         omap3_gpmc_restore_context();
 166         /* Restore the interrupt controller context */
 167         omap_intc_restore_context();
 168         omap_dma_global_context_restore();
 169 }
 170
 171 /*
 172  * FIXME: This function should be called before entering off-mode after
 173  * OMAP3 secure services have been accessed. Currently it is only called
 174  * once during boot sequence, but this works as we are not using secure
 175  * services.
 176  */
 177 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 178 {
 179         u32 ret;
 180
 181         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 182                 /*
 183                  * MPU next state must be set to POWER_ON temporarily,
 184                  * otherwise the WFI executed inside the ROM code
 185                  * will hang the system.
 186                  */
 187                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 188                 ret = _omap_save_secure_sram((u32 *)
 189                                 __pa(omap3_secure_ram_storage));
 190                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 191                 /* Following is for error tracking, it should not happen */
 192                 if (ret) {
 193                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 194                                 ret);
 195                         while (1)
 196                                 ;
 197                 }
 198         }
 199 }
 200
 201 /*
 202  * PRCM Interrupt Handler Helper Function
 203  *
 204  * The purpose of this function is to clear any wake-up events latched
 205  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 206  * may occur whilst attempting to clear a PM_WKST_x register and thus
 207  * set another bit in this register. A while loop is used to ensure
 208  * that any peripheral wake-up events occurring while attempting to
 209  * clear the PM_WKST_x are detected and cleared.
 210  */
 211 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 212 {
 213         u32 wkst, fclk, iclk, clken;
 214         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 215         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 216         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 217         u16 grpsel_off = (regs == 3) ?
 218                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 219         int c = 0;
 220
 221         wkst = prm_read_mod_reg(module, wkst_off);
 222         wkst &= prm_read_mod_reg(module, grpsel_off);
 223         if (wkst) {
 224                 iclk = cm_read_mod_reg(module, iclk_off);
 225                 fclk = cm_read_mod_reg(module, fclk_off);
 226                 while (wkst) {
 227                         clken = wkst;
 228                         cm_set_mod_reg_bits(clken, module, iclk_off);
 229                         /*
 230                          * For USBHOST, we don't know whether HOST1 or
 231                          * HOST2 woke us up, so enable both f-clocks
 232                          */
 233                         if (module == OMAP3430ES2_USBHOST_MOD)
 234                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 235                         cm_set_mod_reg_bits(clken, module, fclk_off);
 236                         prm_write_mod_reg(wkst, module, wkst_off);
 237                         wkst = prm_read_mod_reg(module, wkst_off);
 238                         c++;
 239                 }
 240                 cm_write_mod_reg(iclk, module, iclk_off);
 241                 cm_write_mod_reg(fclk, module, fclk_off);
 242         }
 243
 244         return c;
 245 }
 246
 247 static int _prcm_int_handle_wakeup(void)
 248 {
 249         int c;
 250
 251         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 252         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 253         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 254         if (omap_rev() > OMAP3430_REV_ES1_0) {
 255                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 256                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 257         }
 258
 259         return c;
 260 }
 261
 262 /*
 263  * PRCM Interrupt Handler
 264  *
 265  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 266  * interrupts from the PRCM for the MPU. These bits must be cleared in
 267  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 268  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 269  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 270  * register indicates that a wake-up event is pending for the MPU and
 271  * this bit can only be cleared if the all the wake-up events latched
 272  * in the various PM_WKST_x registers have been cleared. The interrupt
 273  * handler is implemented using a do-while loop so that if a wake-up
 274  * event occurred during the processing of the prcm interrupt handler
 275  * (setting a bit in the corresponding PM_WKST_x register and thus
 276  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 277  * this would be handled.
 278  */
 279 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 280 {
 281         u32 irqenable_mpu, irqstatus_mpu;
 282         int c = 0;
 283
 284         irqenable_mpu = prm_read_mod_reg(OCP_MOD,
 285                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 286         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 287                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 288         irqstatus_mpu &= irqenable_mpu;
 289
 290         do {
 291                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 292                                      OMAP3430_IO_ST_MASK)) {
 293                         c = _prcm_int_handle_wakeup();
 294
 295                         /*
 296                          * Is the MPU PRCM interrupt handler racing with the
 297                          * IVA2 PRCM interrupt handler ?
 298                          */
 299                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 300                              "but no wakeup sources are marked\n");
 301                 } else {
 302                         /* XXX we need to expand our PRCM interrupt handler */
 303                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 304                              "no code to handle it (%08x)\n", irqstatus_mpu);
 305                 }
 306
 307                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 308                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 309
 310                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 311                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 312                 irqstatus_mpu &= irqenable_mpu;
 313
 314         } while (irqstatus_mpu);
 315
 316         return IRQ_HANDLED;
 317 }
 318
 319 static void restore_control_register(u32 val)
 320 {
 321         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 322 }
 323
 324 /* Function to restore the table entry that was modified for enabling MMU */
 325 static void restore_table_entry(void)
 326 {
 327         void __iomem *scratchpad_address;
 328         u32 previous_value, control_reg_value;
 329         u32 *address;
 330
 331         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 332
 333         /* Get address of entry that was modified */
 334         address = (u32 *)__raw_readl(scratchpad_address +
 335                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 336         /* Get the previous value which needs to be restored */
 337         previous_value = __raw_readl(scratchpad_address +
 338                                      OMAP343X_TABLE_VALUE_OFFSET);
 339         address = __va(address);
 340         *address = previous_value;
 341         flush_tlb_all();
 342         control_reg_value = __raw_readl(scratchpad_address
 343                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 344         /* This will enable caches and prediction */
 345         restore_control_register(control_reg_value);
 346 }
 347
 348 void omap_sram_idle(void)
 349 {
 350         /* Variable to tell what needs to be saved and restored
 351          * in omap_sram_idle*/
 352         /* save_state = 0 => Nothing to save and restored */
 353         /* save_state = 1 => Only L1 and logic lost */
 354         /* save_state = 2 => Only L2 lost */
 355         /* save_state = 3 => L1, L2 and logic lost */
 356         int save_state = 0;
 357         int mpu_next_state = PWRDM_POWER_ON;
 358         int per_next_state = PWRDM_POWER_ON;
 359         int core_next_state = PWRDM_POWER_ON;
 360         int core_prev_state, per_prev_state;
 361         u32 sdrc_pwr = 0;
 362
 363         if (!_omap_sram_idle)
 364                 return;
 365
 366         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 367         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 368         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 369         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 370
 371         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 372         switch (mpu_next_state) {
 373         case PWRDM_POWER_ON:
 374         case PWRDM_POWER_RET:
 375                 /* No need to save context */
 376                 save_state = 0;
 377                 break;
 378         case PWRDM_POWER_OFF:
 379                 save_state = 3;
 380                 break;
 381         default:
 382                 /* Invalid state */
 383                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 384                 return;
 385         }
 386         pwrdm_pre_transition();
 387
 388         /* NEON control */
 389         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 390                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 391
 392         /* Enable IO-PAD and IO-CHAIN wakeups */
 393         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 394         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 395         if (omap3_has_io_wakeup() &&
 396             (per_next_state < PWRDM_POWER_ON ||
 397              core_next_state < PWRDM_POWER_ON)) {
 398                 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 399                 omap3_enable_io_chain();
 400         }
 401
 402         /* Block console output in case it is on one of the OMAP UARTs */
 403         if (!is_suspending())
 404                 if (per_next_state < PWRDM_POWER_ON ||
 405                     core_next_state < PWRDM_POWER_ON)
 406                         if (try_acquire_console_sem())
 407                                 goto console_still_active;
 408
 409         /* PER */
 410         if (per_next_state < PWRDM_POWER_ON) {
 411                 omap_uart_prepare_idle(2);
 412                 omap_uart_prepare_idle(3);
 413                 omap2_gpio_prepare_for_idle(per_next_state);
 414                 if (per_next_state == PWRDM_POWER_OFF)
 415                                 omap3_per_save_context();
 416         }
 417
 418         /* CORE */
 419         if (core_next_state < PWRDM_POWER_ON) {
 420                 omap_uart_prepare_idle(0);
 421                 omap_uart_prepare_idle(1);
 422                 if (core_next_state == PWRDM_POWER_OFF) {
 423                         omap3_core_save_context();
 424                         omap3_prcm_save_context();
 425                 }
 426         }
 427
 428         omap3_intc_prepare_idle();
 429
 430         /*
 431         * On EMU/HS devices ROM code restores a SRDC value
 432         * from scratchpad which has automatic self refresh on timeout
 433         * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
 434         * Hence store/restore the SDRC_POWER register here.
 435         */
 436         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 437             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 438             core_next_state == PWRDM_POWER_OFF)
 439                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 440
 441         /*
 442          * omap3_arm_context is the location where ARM registers
 443          * get saved. The restore path then reads from this
 444          * location and restores them back.
 445          */
 446         _omap_sram_idle(omap3_arm_context, save_state);
 447         cpu_init();
 448
 449         /* Restore normal SDRC POWER settings */
 450         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 451             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 452             core_next_state == PWRDM_POWER_OFF)
 453                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 454
 455         /* Restore table entry modified during MMU restoration */
 456         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 457                 restore_table_entry();
 458
 459         /* CORE */
 460         if (core_next_state < PWRDM_POWER_ON) {
 461                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 462                 if (core_prev_state == PWRDM_POWER_OFF) {
 463                         omap3_core_restore_context();
 464                         omap3_prcm_restore_context();
 465                         omap3_sram_restore_context();
 466                         omap2_sms_restore_context();
 467                 }
 468                 omap_uart_resume_idle(0);
 469                 omap_uart_resume_idle(1);
 470                 if (core_next_state == PWRDM_POWER_OFF)
 471                         prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 472                                                OMAP3430_GR_MOD,
 473                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 474         }
 475         omap3_intc_resume_idle();
 476
 477         /* PER */
 478         if (per_next_state < PWRDM_POWER_ON) {
 479                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 480                 omap2_gpio_resume_after_idle();
 481                 if (per_prev_state == PWRDM_POWER_OFF)
 482                         omap3_per_restore_context();
 483                 omap_uart_resume_idle(2);
 484                 omap_uart_resume_idle(3);
 485         }
 486
 487         if (!is_suspending())
 488                 release_console_sem();
 489
 490 console_still_active:
 491         /* Disable IO-PAD and IO-CHAIN wakeup */
 492         if (omap3_has_io_wakeup() &&
 493             (per_next_state < PWRDM_POWER_ON ||
 494              core_next_state < PWRDM_POWER_ON)) {
 495                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 496                 omap3_disable_io_chain();
 497         }
 498
 499         pwrdm_post_transition();
 500
 501         omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 502 }
 503
 504 int omap3_can_sleep(void)
 505 {
 506         if (!sleep_while_idle)
 507                 return 0;
 508         if (!omap_uart_can_sleep())
 509                 return 0;
 510         return 1;
 511 }
 512
 513 static void omap3_pm_idle(void)
 514 {
 515         local_irq_disable();
 516         local_fiq_disable();
 517
 518         if (!omap3_can_sleep())
 519                 goto out;
 520
 521         if (omap_irq_pending() || need_resched())
 522                 goto out;
 523
 524         omap_sram_idle();
 525
 526 out:
 527         local_fiq_enable();
 528         local_irq_enable();
 529 }
 530
 531 #ifdef CONFIG_SUSPEND
 532 static int omap3_pm_prepare(void)
 533 {
 534         disable_hlt();
 535         return 0;
 536 }
 537
 538 static int omap3_pm_suspend(void)
 539 {
 540         struct power_state *pwrst;
 541         int state, ret = 0;
 542
 543         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 544                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 545                                          wakeup_timer_milliseconds);
 546
 547         /* Read current next_pwrsts */
 548         list_for_each_entry(pwrst, &pwrst_list, node)
 549                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 550         /* Set ones wanted by suspend */
 551         list_for_each_entry(pwrst, &pwrst_list, node) {
 552                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 553                         goto restore;
 554                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 555                         goto restore;
 556         }
 557
 558         omap_uart_prepare_suspend();
 559         omap3_intc_suspend();
 560
 561         omap_sram_idle();
 562
 563 restore:
 564         /* Restore next_pwrsts */
 565         list_for_each_entry(pwrst, &pwrst_list, node) {
 566                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 567                 if (state > pwrst->next_state) {
 568                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 569                                "target state %d\n",
 570                                pwrst->pwrdm->name, pwrst->next_state);
 571                         ret = -1;
 572                 }
 573                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 574         }
 575         if (ret)
 576                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 577         else
 578                 printk(KERN_INFO "Successfully put all powerdomains "
 579                        "to target state\n");
 580
 581         return ret;
 582 }
 583
 584 static int omap3_pm_enter(suspend_state_t unused)
 585 {
 586         int ret = 0;
 587
 588         switch (suspend_state) {
 589         case PM_SUSPEND_STANDBY:
 590         case PM_SUSPEND_MEM:
 591                 ret = omap3_pm_suspend();
 592                 break;
 593         default:
 594                 ret = -EINVAL;
 595         }
 596
 597         return ret;
 598 }
 599
 600 static void omap3_pm_finish(void)
 601 {
 602         enable_hlt();
 603 }
 604
 605 /* Hooks to enable / disable UART interrupts during suspend */
 606 static int omap3_pm_begin(suspend_state_t state)
 607 {
 608         suspend_state = state;
 609         omap_uart_enable_irqs(0);
 610         return 0;
 611 }
 612
 613 static void omap3_pm_end(void)
 614 {
 615         suspend_state = PM_SUSPEND_ON;
 616         omap_uart_enable_irqs(1);
 617         return;
 618 }
 619
 620 static struct platform_suspend_ops omap_pm_ops = {
 621         .begin          = omap3_pm_begin,
 622         .end            = omap3_pm_end,
 623         .prepare        = omap3_pm_prepare,
 624         .enter          = omap3_pm_enter,
 625         .finish         = omap3_pm_finish,
 626         .valid          = suspend_valid_only_mem,
 627 };
 628 #endif /* CONFIG_SUSPEND */
 629
 630
 631 /**
 632  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 633  *                   retention
 634  *
 635  * In cases where IVA2 is activated by bootcode, it may prevent
 636  * full-chip retention or off-mode because it is not idle.  This
 637  * function forces the IVA2 into idle state so it can go
 638  * into retention/off and thus allow full-chip retention/off.
 639  *
 640  **/
 641 static void __init omap3_iva_idle(void)
 642 {
 643         /* ensure IVA2 clock is disabled */
 644         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 645
 646         /* if no clock activity, nothing else to do */
 647         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 648               OMAP3430_CLKACTIVITY_IVA2_MASK))
 649                 return;
 650
 651         /* Reset IVA2 */
 652         prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 653                           OMAP3430_RST2_IVA2_MASK |
 654                           OMAP3430_RST3_IVA2_MASK,
 655                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 656
 657         /* Enable IVA2 clock */
 658         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 659                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 660
 661         /* Set IVA2 boot mode to 'idle' */
 662         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 663                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 664
 665         /* Un-reset IVA2 */
 666         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 667
 668         /* Disable IVA2 clock */
 669         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 670
 671         /* Reset IVA2 */
 672         prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 673                           OMAP3430_RST2_IVA2_MASK |
 674                           OMAP3430_RST3_IVA2_MASK,
 675                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 676 }
 677
 678 static void __init omap3_d2d_idle(void)
 679 {
 680         u16 mask, padconf;
 681
 682         /* In a stand alone OMAP3430 where there is not a stacked
 683          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 684          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 685          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 686         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 687         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 688         padconf |= mask;
 689         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 690
 691         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 692         padconf |= mask;
 693         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 694
 695         /* reset modem */
 696         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 697                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 698                           CORE_MOD, OMAP2_RM_RSTCTRL);
 699         prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 700 }
 701
 702 static void __init prcm_setup_regs(void)
 703 {
 704         u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
 705                                         OMAP3630_AUTO_UART4_MASK : 0;
 706         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 707                                         OMAP3630_EN_UART4_MASK : 0;
 708         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 709                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 710
 711
 712         /* XXX Reset all wkdeps. This should be done when initializing
 713          * powerdomains */
 714         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 715         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 716         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 717         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 718         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 719         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 720         if (omap_rev() > OMAP3430_REV_ES1_0) {
 721                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 722                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 723         } else
 724                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 725
 726         /*
 727          * Enable interface clock autoidle for all modules.
 728          * Note that in the long run this should be done by clockfw
 729          */
 730         cm_write_mod_reg(
 731                 OMAP3430_AUTO_MODEM_MASK |
 732                 OMAP3430ES2_AUTO_MMC3_MASK |
 733                 OMAP3430ES2_AUTO_ICR_MASK |
 734                 OMAP3430_AUTO_AES2_MASK |
 735                 OMAP3430_AUTO_SHA12_MASK |
 736                 OMAP3430_AUTO_DES2_MASK |
 737                 OMAP3430_AUTO_MMC2_MASK |
 738                 OMAP3430_AUTO_MMC1_MASK |
 739                 OMAP3430_AUTO_MSPRO_MASK |
 740                 OMAP3430_AUTO_HDQ_MASK |
 741                 OMAP3430_AUTO_MCSPI4_MASK |
 742                 OMAP3430_AUTO_MCSPI3_MASK |
 743                 OMAP3430_AUTO_MCSPI2_MASK |
 744                 OMAP3430_AUTO_MCSPI1_MASK |
 745                 OMAP3430_AUTO_I2C3_MASK |
 746                 OMAP3430_AUTO_I2C2_MASK |
 747                 OMAP3430_AUTO_I2C1_MASK |
 748                 OMAP3430_AUTO_UART2_MASK |
 749                 OMAP3430_AUTO_UART1_MASK |
 750                 OMAP3430_AUTO_GPT11_MASK |
 751                 OMAP3430_AUTO_GPT10_MASK |
 752                 OMAP3430_AUTO_MCBSP5_MASK |
 753                 OMAP3430_AUTO_MCBSP1_MASK |
 754                 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
 755                 OMAP3430_AUTO_MAILBOXES_MASK |
 756                 OMAP3430_AUTO_OMAPCTRL_MASK |
 757                 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
 758                 OMAP3430_AUTO_HSOTGUSB_MASK |
 759                 OMAP3430_AUTO_SAD2D_MASK |
 760                 OMAP3430_AUTO_SSI_MASK,
 761                 CORE_MOD, CM_AUTOIDLE1);
 762
 763         cm_write_mod_reg(
 764                 OMAP3430_AUTO_PKA_MASK |
 765                 OMAP3430_AUTO_AES1_MASK |
 766                 OMAP3430_AUTO_RNG_MASK |
 767                 OMAP3430_AUTO_SHA11_MASK |
 768                 OMAP3430_AUTO_DES1_MASK,
 769                 CORE_MOD, CM_AUTOIDLE2);
 770
 771         if (omap_rev() > OMAP3430_REV_ES1_0) {
 772                 cm_write_mod_reg(
 773                         OMAP3430_AUTO_MAD2D_MASK |
 774                         OMAP3430ES2_AUTO_USBTLL_MASK,
 775                         CORE_MOD, CM_AUTOIDLE3);
 776         }
 777
 778         cm_write_mod_reg(
 779                 OMAP3430_AUTO_WDT2_MASK |
 780                 OMAP3430_AUTO_WDT1_MASK |
 781                 OMAP3430_AUTO_GPIO1_MASK |
 782                 OMAP3430_AUTO_32KSYNC_MASK |
 783                 OMAP3430_AUTO_GPT12_MASK |
 784                 OMAP3430_AUTO_GPT1_MASK,
 785                 WKUP_MOD, CM_AUTOIDLE);
 786
 787         cm_write_mod_reg(
 788                 OMAP3430_AUTO_DSS_MASK,
 789                 OMAP3430_DSS_MOD,
 790                 CM_AUTOIDLE);
 791
 792         cm_write_mod_reg(
 793                 OMAP3430_AUTO_CAM_MASK,
 794                 OMAP3430_CAM_MOD,
 795                 CM_AUTOIDLE);
 796
 797         cm_write_mod_reg(
 798                 omap3630_auto_uart4_mask |
 799                 OMAP3430_AUTO_GPIO6_MASK |
 800                 OMAP3430_AUTO_GPIO5_MASK |
 801                 OMAP3430_AUTO_GPIO4_MASK |
 802                 OMAP3430_AUTO_GPIO3_MASK |
 803                 OMAP3430_AUTO_GPIO2_MASK |
 804                 OMAP3430_AUTO_WDT3_MASK |
 805                 OMAP3430_AUTO_UART3_MASK |
 806                 OMAP3430_AUTO_GPT9_MASK |
 807                 OMAP3430_AUTO_GPT8_MASK |
 808                 OMAP3430_AUTO_GPT7_MASK |
 809                 OMAP3430_AUTO_GPT6_MASK |
 810                 OMAP3430_AUTO_GPT5_MASK |
 811                 OMAP3430_AUTO_GPT4_MASK |
 812                 OMAP3430_AUTO_GPT3_MASK |
 813                 OMAP3430_AUTO_GPT2_MASK |
 814                 OMAP3430_AUTO_MCBSP4_MASK |
 815                 OMAP3430_AUTO_MCBSP3_MASK |
 816                 OMAP3430_AUTO_MCBSP2_MASK,
 817                 OMAP3430_PER_MOD,
 818                 CM_AUTOIDLE);
 819
 820         if (omap_rev() > OMAP3430_REV_ES1_0) {
 821                 cm_write_mod_reg(
 822                         OMAP3430ES2_AUTO_USBHOST_MASK,
 823                         OMAP3430ES2_USBHOST_MOD,
 824                         CM_AUTOIDLE);
 825         }
 826
 827         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 828
 829         /*
 830          * Set all plls to autoidle. This is needed until autoidle is
 831          * enabled by clockfw
 832          */
 833         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 834                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 835         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 836                          MPU_MOD,
 837                          CM_AUTOIDLE2);
 838         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 839                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 840                          PLL_MOD,
 841                          CM_AUTOIDLE);
 842         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 843                          PLL_MOD,
 844                          CM_AUTOIDLE2);
 845
 846         /*
 847          * Enable control of expternal oscillator through
 848          * sys_clkreq. In the long run clock framework should
 849          * take care of this.
 850          */
 851         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 852                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 853                              OMAP3430_GR_MOD,
 854                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 855
 856         /* setup wakup source */
 857         prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 858                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 859                           WKUP_MOD, PM_WKEN);
 860         /* No need to write EN_IO, that is always enabled */
 861         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 862                           OMAP3430_GRPSEL_GPT1_MASK |
 863                           OMAP3430_GRPSEL_GPT12_MASK,
 864                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 865         /* For some reason IO doesn't generate wakeup event even if
 866          * it is selected to mpu wakeup goup */
 867         prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 868                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 869
 870         /* Enable PM_WKEN to support DSS LPR */
 871         prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 872                                 OMAP3430_DSS_MOD, PM_WKEN);
 873
 874         /* Enable wakeups in PER */
 875         prm_write_mod_reg(omap3630_en_uart4_mask |
 876                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 877                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 878                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 879                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 880                           OMAP3430_EN_MCBSP4_MASK,
 881                           OMAP3430_PER_MOD, PM_WKEN);
 882         /* and allow them to wake up MPU */
 883         prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 884                           OMAP3430_GRPSEL_GPIO2_MASK |
 885                           OMAP3430_GRPSEL_GPIO3_MASK |
 886                           OMAP3430_GRPSEL_GPIO4_MASK |
 887                           OMAP3430_GRPSEL_GPIO5_MASK |
 888                           OMAP3430_GRPSEL_GPIO6_MASK |
 889                           OMAP3430_GRPSEL_UART3_MASK |
 890                           OMAP3430_GRPSEL_MCBSP2_MASK |
 891                           OMAP3430_GRPSEL_MCBSP3_MASK |
 892                           OMAP3430_GRPSEL_MCBSP4_MASK,
 893                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 894
 895         /* Don't attach IVA interrupts */
 896         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 897         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 898         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 899         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 900
 901         /* Clear any pending 'reset' flags */
 902         prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 903         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 904         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 905         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 906         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 907         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 908         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 909
 910         /* Clear any pending PRCM interrupts */
 911         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 912
 913         omap3_iva_idle();
 914         omap3_d2d_idle();
 915 }
 916
 917 void omap3_pm_off_mode_enable(int enable)
 918 {
 919         struct power_state *pwrst;
 920         u32 state;
 921
 922         if (enable)
 923                 state = PWRDM_POWER_OFF;
 924         else
 925                 state = PWRDM_POWER_RET;
 926
 927 #ifdef CONFIG_CPU_IDLE
 928         omap3_cpuidle_update_states();
 929 #endif
 930
 931         list_for_each_entry(pwrst, &pwrst_list, node) {
 932                 pwrst->next_state = state;
 933                 omap_set_pwrdm_state(pwrst->pwrdm, state);
 934         }
 935 }
 936
 937 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 938 {
 939         struct power_state *pwrst;
 940
 941         list_for_each_entry(pwrst, &pwrst_list, node) {
 942                 if (pwrst->pwrdm == pwrdm)
 943                         return pwrst->next_state;
 944         }
 945         return -EINVAL;
 946 }
 947
 948 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 949 {
 950         struct power_state *pwrst;
 951
 952         list_for_each_entry(pwrst, &pwrst_list, node) {
 953                 if (pwrst->pwrdm == pwrdm) {
 954                         pwrst->next_state = state;
 955                         return 0;
 956                 }
 957         }
 958         return -EINVAL;
 959 }
 960
 961 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 962 {
 963         struct power_state *pwrst;
 964
 965         if (!pwrdm->pwrsts)
 966                 return 0;
 967
 968         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 969         if (!pwrst)
 970                 return -ENOMEM;
 971         pwrst->pwrdm = pwrdm;
 972         pwrst->next_state = PWRDM_POWER_RET;
 973         list_add(&pwrst->node, &pwrst_list);
 974
 975         if (pwrdm_has_hdwr_sar(pwrdm))
 976                 pwrdm_enable_hdwr_sar(pwrdm);
 977
 978         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 979 }
 980
 981 /*
 982  * Enable hw supervised mode for all clockdomains if it's
 983  * supported. Initiate sleep transition for other clockdomains, if
 984  * they are not used
 985  */
 986 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 987 {
 988         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 989                 omap2_clkdm_allow_idle(clkdm);
 990         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 991                  atomic_read(&clkdm->usecount) == 0)
 992                 omap2_clkdm_sleep(clkdm);
 993         return 0;
 994 }
 995
 996 void omap_push_sram_idle(void)
 997 {
 998         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 999                                         omap34xx_cpu_suspend_sz);
1000         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
1001                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
1002                                 save_secure_ram_context_sz);
1003 }
1004
1005 static int __init omap3_pm_init(void)
1006 {
1007         struct power_state *pwrst, *tmp;
1008         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
1009         int ret;
1010
1011         if (!cpu_is_omap34xx())
1012                 return -ENODEV;
1013
1014         printk(KERN_ERR "Power Management for TI OMAP3.\n");
1015
1016         /* XXX prcm_setup_regs needs to be before enabling hw
1017          * supervised mode for powerdomains */
1018         prcm_setup_regs();
1019
1020         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1021                           (irq_handler_t)prcm_interrupt_handler,
1022                           IRQF_DISABLED, "prcm", NULL);
1023         if (ret) {
1024                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1025                        INT_34XX_PRCM_MPU_IRQ);
1026                 goto err1;
1027         }
1028
1029         ret = pwrdm_for_each(pwrdms_setup, NULL);
1030         if (ret) {
1031                 printk(KERN_ERR "Failed to setup powerdomains\n");
1032                 goto err2;
1033         }
1034
1035         (void) clkdm_for_each(clkdms_setup, NULL);
1036
1037         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1038         if (mpu_pwrdm == NULL) {
1039                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1040                 goto err2;
1041         }
1042
1043         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1044         per_pwrdm = pwrdm_lookup("per_pwrdm");
1045         core_pwrdm = pwrdm_lookup("core_pwrdm");
1046         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1047
1048         neon_clkdm = clkdm_lookup("neon_clkdm");
1049         mpu_clkdm = clkdm_lookup("mpu_clkdm");
1050         per_clkdm = clkdm_lookup("per_clkdm");
1051         core_clkdm = clkdm_lookup("core_clkdm");
1052
1053         omap_push_sram_idle();
1054 #ifdef CONFIG_SUSPEND
1055         suspend_set_ops(&omap_pm_ops);
1056 #endif /* CONFIG_SUSPEND */
1057
1058         pm_idle = omap3_pm_idle;
1059         omap3_idle_init();
1060
1061         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1062         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1063                 omap3_secure_ram_storage =
1064                         kmalloc(0x803F, GFP_KERNEL);
1065                 if (!omap3_secure_ram_storage)
1066                         printk(KERN_ERR "Memory allocation failed when"
1067                                         "allocating for secure sram context\n");
1068
1069                 local_irq_disable();
1070                 local_fiq_disable();
1071
1072                 omap_dma_global_context_save();
1073                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1074                 omap_dma_global_context_restore();
1075
1076                 local_irq_enable();
1077                 local_fiq_enable();
1078         }
1079
1080         omap3_save_scratchpad_contents();
1081 err1:
1082         return ret;
1083 err2:
1084         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1085         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1086                 list_del(&pwrst->node);
1087                 kfree(pwrst);
1088         }
1089         return ret;
1090 }
1091
1092 late_initcall(omap3_pm_init);