arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2005 Texas Instruments, Inc.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * Based on pm.c for omap1
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17
  18 #include <linux/pm.h>
  19 #include <linux/suspend.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/module.h>
  22 #include <linux/list.h>
  23 #include <linux/err.h>
  24 #include <linux/gpio.h>
  25
  26 #include <plat/sram.h>
  27 #include <plat/clockdomain.h>
  28 #include <plat/powerdomain.h>
  29 #include <plat/control.h>
  30 #include <plat/serial.h>
  31 #include <plat/sdrc.h>
  32
  33 #include <asm/tlbflush.h>
  34
  35 #include "cm.h"
  36 #include "cm-regbits-34xx.h"
  37 #include "prm-regbits-34xx.h"
  38
  39 #include "prm.h"
  40 #include "pm.h"
  41
  42 struct power_state {
  43         struct powerdomain *pwrdm;
  44         u32 next_state;
  45 #ifdef CONFIG_SUSPEND
  46         u32 saved_state;
  47 #endif
  48         struct list_head node;
  49 };
  50
  51 static LIST_HEAD(pwrst_list);
  52
  53 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  54
  55 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  56 static struct powerdomain *core_pwrdm, *per_pwrdm;
  57
  58 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
  59
  60 /*
  61  * PRCM Interrupt Handler Helper Function
  62  *
  63  * The purpose of this function is to clear any wake-up events latched
  64  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
  65  * may occur whilst attempting to clear a PM_WKST_x register and thus
  66  * set another bit in this register. A while loop is used to ensure
  67  * that any peripheral wake-up events occurring while attempting to
  68  * clear the PM_WKST_x are detected and cleared.
  69  */
  70 static int prcm_clear_mod_irqs(s16 module, u8 regs)
  71 {
  72         u32 wkst, fclk, iclk, clken;
  73         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
  74         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
  75         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
  76         u16 grpsel_off = (regs == 3) ?
  77                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
  78         int c = 0;
  79
  80         wkst = prm_read_mod_reg(module, wkst_off);
  81         wkst &= prm_read_mod_reg(module, grpsel_off);
  82         if (wkst) {
  83                 iclk = cm_read_mod_reg(module, iclk_off);
  84                 fclk = cm_read_mod_reg(module, fclk_off);
  85                 while (wkst) {
  86                         clken = wkst;
  87                         cm_set_mod_reg_bits(clken, module, iclk_off);
  88                         /*
  89                          * For USBHOST, we don't know whether HOST1 or
  90                          * HOST2 woke us up, so enable both f-clocks
  91                          */
  92                         if (module == OMAP3430ES2_USBHOST_MOD)
  93                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
  94                         cm_set_mod_reg_bits(clken, module, fclk_off);
  95                         prm_write_mod_reg(wkst, module, wkst_off);
  96                         wkst = prm_read_mod_reg(module, wkst_off);
  97                         c++;
  98                 }
  99                 cm_write_mod_reg(iclk, module, iclk_off);
 100                 cm_write_mod_reg(fclk, module, fclk_off);
 101         }
 102
 103         return c;
 104 }
 105
 106 static int _prcm_int_handle_wakeup(void)
 107 {
 108         int c;
 109
 110         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 111         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 112         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 113         if (omap_rev() > OMAP3430_REV_ES1_0) {
 114                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 115                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 116         }
 117
 118         return c;
 119 }
 120
 121 /*
 122  * PRCM Interrupt Handler
 123  *
 124  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 125  * interrupts from the PRCM for the MPU. These bits must be cleared in
 126  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 127  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 128  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 129  * register indicates that a wake-up event is pending for the MPU and
 130  * this bit can only be cleared if the all the wake-up events latched
 131  * in the various PM_WKST_x registers have been cleared. The interrupt
 132  * handler is implemented using a do-while loop so that if a wake-up
 133  * event occurred during the processing of the prcm interrupt handler
 134  * (setting a bit in the corresponding PM_WKST_x register and thus
 135  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 136  * this would be handled.
 137  */
 138 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 139 {
 140         u32 irqstatus_mpu;
 141         int c = 0;
 142
 143         do {
 144                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 145                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 146
 147                 if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) {
 148                         c = _prcm_int_handle_wakeup();
 149
 150                         /*
 151                          * Is the MPU PRCM interrupt handler racing with the
 152                          * IVA2 PRCM interrupt handler ?
 153                          */
 154                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 155                              "but no wakeup sources are marked\n");
 156                 } else {
 157                         /* XXX we need to expand our PRCM interrupt handler */
 158                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 159                              "no code to handle it (%08x)\n", irqstatus_mpu);
 160                 }
 161
 162                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 163                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 164
 165         } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET));
 166
 167         return IRQ_HANDLED;
 168 }
 169
 170 static void restore_control_register(u32 val)
 171 {
 172         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 173 }
 174
 175 /* Function to restore the table entry that was modified for enabling MMU */
 176 static void restore_table_entry(void)
 177 {
 178         u32 *scratchpad_address;
 179         u32 previous_value, control_reg_value;
 180         u32 *address;
 181
 182         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 183
 184         /* Get address of entry that was modified */
 185         address = (u32 *)__raw_readl(scratchpad_address +
 186                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 187         /* Get the previous value which needs to be restored */
 188         previous_value = __raw_readl(scratchpad_address +
 189                                      OMAP343X_TABLE_VALUE_OFFSET);
 190         address = __va(address);
 191         *address = previous_value;
 192         flush_tlb_all();
 193         control_reg_value = __raw_readl(scratchpad_address
 194                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 195         /* This will enable caches and prediction */
 196         restore_control_register(control_reg_value);
 197 }
 198
 199 static void omap_sram_idle(void)
 200 {
 201         /* Variable to tell what needs to be saved and restored
 202          * in omap_sram_idle*/
 203         /* save_state = 0 => Nothing to save and restored */
 204         /* save_state = 1 => Only L1 and logic lost */
 205         /* save_state = 2 => Only L2 lost */
 206         /* save_state = 3 => L1, L2 and logic lost */
 207         int save_state = 0;
 208         int mpu_next_state = PWRDM_POWER_ON;
 209         int per_next_state = PWRDM_POWER_ON;
 210         int core_next_state = PWRDM_POWER_ON;
 211
 212         if (!_omap_sram_idle)
 213                 return;
 214
 215         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 216         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 217         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 218         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 219
 220         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 221         switch (mpu_next_state) {
 222         case PWRDM_POWER_ON:
 223         case PWRDM_POWER_RET:
 224                 /* No need to save context */
 225                 save_state = 0;
 226                 break;
 227         case PWRDM_POWER_OFF:
 228                 save_state = 3;
 229                 break;
 230         default:
 231                 /* Invalid state */
 232                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 233                 return;
 234         }
 235         pwrdm_pre_transition();
 236
 237         /* NEON control */
 238         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 239                 set_pwrdm_state(neon_pwrdm, mpu_next_state);
 240
 241         /* CORE & PER */
 242         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 243         if (core_next_state < PWRDM_POWER_ON) {
 244                 omap2_gpio_prepare_for_retention();
 245                 omap_uart_prepare_idle(0);
 246                 omap_uart_prepare_idle(1);
 247                 /* PER changes only with core */
 248                 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 249                 if (per_next_state < PWRDM_POWER_ON)
 250                         omap_uart_prepare_idle(2);
 251                 /* Enable IO-PAD wakeup */
 252                 prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 253         }
 254
 255         /*
 256          * omap3_arm_context is the location where ARM registers
 257          * get saved. The restore path then reads from this
 258          * location and restores them back.
 259          */
 260         _omap_sram_idle(omap3_arm_context, save_state);
 261         cpu_init();
 262
 263         /* Restore table entry modified during MMU restoration */
 264         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 265                 restore_table_entry();
 266
 267         if (core_next_state < PWRDM_POWER_ON) {
 268                 if (per_next_state < PWRDM_POWER_ON)
 269                         omap_uart_resume_idle(2);
 270                 omap_uart_resume_idle(1);
 271                 omap_uart_resume_idle(0);
 272
 273                 /* Disable IO-PAD wakeup */
 274                 prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN);
 275                 omap2_gpio_resume_after_retention();
 276         }
 277
 278         pwrdm_post_transition();
 279
 280 }
 281
 282 /*
 283  * Check if functional clocks are enabled before entering
 284  * sleep. This function could be behind CONFIG_PM_DEBUG
 285  * when all drivers are configuring their sysconfig registers
 286  * properly and using their clocks properly.
 287  */
 288 static int omap3_fclks_active(void)
 289 {
 290         u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
 291                 fck_cam = 0, fck_per = 0, fck_usbhost = 0;
 292
 293         fck_core1 = cm_read_mod_reg(CORE_MOD,
 294                                     CM_FCLKEN1);
 295         if (omap_rev() > OMAP3430_REV_ES1_0) {
 296                 fck_core3 = cm_read_mod_reg(CORE_MOD,
 297                                             OMAP3430ES2_CM_FCLKEN3);
 298                 fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
 299                                           CM_FCLKEN);
 300                 fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
 301                                               CM_FCLKEN);
 302         } else
 303                 fck_sgx = cm_read_mod_reg(GFX_MOD,
 304                                           OMAP3430ES2_CM_FCLKEN3);
 305         fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
 306                                   CM_FCLKEN);
 307         fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
 308                                   CM_FCLKEN);
 309         fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
 310                                   CM_FCLKEN);
 311
 312         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
 313         fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
 314         fck_per &= ~OMAP3430_EN_UART3;
 315
 316         if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
 317             fck_cam | fck_per | fck_usbhost)
 318                 return 1;
 319         return 0;
 320 }
 321
 322 static int omap3_can_sleep(void)
 323 {
 324         if (!omap_uart_can_sleep())
 325                 return 0;
 326         if (omap3_fclks_active())
 327                 return 0;
 328         return 1;
 329 }
 330
 331 /* This sets pwrdm state (other than mpu & core. Currently only ON &
 332  * RET are supported. Function is assuming that clkdm doesn't have
 333  * hw_sup mode enabled. */
 334 static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
 335 {
 336         u32 cur_state;
 337         int sleep_switch = 0;
 338         int ret = 0;
 339
 340         if (pwrdm == NULL || IS_ERR(pwrdm))
 341                 return -EINVAL;
 342
 343         while (!(pwrdm->pwrsts & (1 << state))) {
 344                 if (state == PWRDM_POWER_OFF)
 345                         return ret;
 346                 state--;
 347         }
 348
 349         cur_state = pwrdm_read_next_pwrst(pwrdm);
 350         if (cur_state == state)
 351                 return ret;
 352
 353         if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
 354                 omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
 355                 sleep_switch = 1;
 356                 pwrdm_wait_transition(pwrdm);
 357         }
 358
 359         ret = pwrdm_set_next_pwrst(pwrdm, state);
 360         if (ret) {
 361                 printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
 362                        pwrdm->name);
 363                 goto err;
 364         }
 365
 366         if (sleep_switch) {
 367                 omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
 368                 pwrdm_wait_transition(pwrdm);
 369                 pwrdm_state_switch(pwrdm);
 370         }
 371
 372 err:
 373         return ret;
 374 }
 375
 376 static void omap3_pm_idle(void)
 377 {
 378         local_irq_disable();
 379         local_fiq_disable();
 380
 381         if (!omap3_can_sleep())
 382                 goto out;
 383
 384         if (omap_irq_pending())
 385                 goto out;
 386
 387         omap_sram_idle();
 388
 389 out:
 390         local_fiq_enable();
 391         local_irq_enable();
 392 }
 393
 394 #ifdef CONFIG_SUSPEND
 395 static suspend_state_t suspend_state;
 396
 397 static int omap3_pm_prepare(void)
 398 {
 399         disable_hlt();
 400         return 0;
 401 }
 402
 403 static int omap3_pm_suspend(void)
 404 {
 405         struct power_state *pwrst;
 406         int state, ret = 0;
 407
 408         /* Read current next_pwrsts */
 409         list_for_each_entry(pwrst, &pwrst_list, node)
 410                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 411         /* Set ones wanted by suspend */
 412         list_for_each_entry(pwrst, &pwrst_list, node) {
 413                 if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 414                         goto restore;
 415                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 416                         goto restore;
 417         }
 418
 419         omap_uart_prepare_suspend();
 420         omap_sram_idle();
 421
 422 restore:
 423         /* Restore next_pwrsts */
 424         list_for_each_entry(pwrst, &pwrst_list, node) {
 425                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 426                 if (state > pwrst->next_state) {
 427                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 428                                "target state %d\n",
 429                                pwrst->pwrdm->name, pwrst->next_state);
 430                         ret = -1;
 431                 }
 432                 set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 433         }
 434         if (ret)
 435                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 436         else
 437                 printk(KERN_INFO "Successfully put all powerdomains "
 438                        "to target state\n");
 439
 440         return ret;
 441 }
 442
 443 static int omap3_pm_enter(suspend_state_t unused)
 444 {
 445         int ret = 0;
 446
 447         switch (suspend_state) {
 448         case PM_SUSPEND_STANDBY:
 449         case PM_SUSPEND_MEM:
 450                 ret = omap3_pm_suspend();
 451                 break;
 452         default:
 453                 ret = -EINVAL;
 454         }
 455
 456         return ret;
 457 }
 458
 459 static void omap3_pm_finish(void)
 460 {
 461         enable_hlt();
 462 }
 463
 464 /* Hooks to enable / disable UART interrupts during suspend */
 465 static int omap3_pm_begin(suspend_state_t state)
 466 {
 467         suspend_state = state;
 468         omap_uart_enable_irqs(0);
 469         return 0;
 470 }
 471
 472 static void omap3_pm_end(void)
 473 {
 474         suspend_state = PM_SUSPEND_ON;
 475         omap_uart_enable_irqs(1);
 476         return;
 477 }
 478
 479 static struct platform_suspend_ops omap_pm_ops = {
 480         .begin          = omap3_pm_begin,
 481         .end            = omap3_pm_end,
 482         .prepare        = omap3_pm_prepare,
 483         .enter          = omap3_pm_enter,
 484         .finish         = omap3_pm_finish,
 485         .valid          = suspend_valid_only_mem,
 486 };
 487 #endif /* CONFIG_SUSPEND */
 488
 489
 490 /**
 491  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 492  *                   retention
 493  *
 494  * In cases where IVA2 is activated by bootcode, it may prevent
 495  * full-chip retention or off-mode because it is not idle.  This
 496  * function forces the IVA2 into idle state so it can go
 497  * into retention/off and thus allow full-chip retention/off.
 498  *
 499  **/
 500 static void __init omap3_iva_idle(void)
 501 {
 502         /* ensure IVA2 clock is disabled */
 503         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 504
 505         /* if no clock activity, nothing else to do */
 506         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 507               OMAP3430_CLKACTIVITY_IVA2_MASK))
 508                 return;
 509
 510         /* Reset IVA2 */
 511         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 512                           OMAP3430_RST2_IVA2 |
 513                           OMAP3430_RST3_IVA2,
 514                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 515
 516         /* Enable IVA2 clock */
 517         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
 518                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 519
 520         /* Set IVA2 boot mode to 'idle' */
 521         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 522                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 523
 524         /* Un-reset IVA2 */
 525         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
 526
 527         /* Disable IVA2 clock */
 528         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 529
 530         /* Reset IVA2 */
 531         prm_write_mod_reg(OMAP3430_RST1_IVA2 |
 532                           OMAP3430_RST2_IVA2 |
 533                           OMAP3430_RST3_IVA2,
 534                           OMAP3430_IVA2_MOD, RM_RSTCTRL);
 535 }
 536
 537 static void __init omap3_d2d_idle(void)
 538 {
 539         u16 mask, padconf;
 540
 541         /* In a stand alone OMAP3430 where there is not a stacked
 542          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 543          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 544          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 545         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 546         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 547         padconf |= mask;
 548         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 549
 550         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 551         padconf |= mask;
 552         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 553
 554         /* reset modem */
 555         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
 556                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
 557                           CORE_MOD, RM_RSTCTRL);
 558         prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
 559 }
 560
 561 static void __init prcm_setup_regs(void)
 562 {
 563         /* XXX Reset all wkdeps. This should be done when initializing
 564          * powerdomains */
 565         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 566         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 567         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 568         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 569         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 570         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 571         if (omap_rev() > OMAP3430_REV_ES1_0) {
 572                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 573                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 574         } else
 575                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 576
 577         /*
 578          * Enable interface clock autoidle for all modules.
 579          * Note that in the long run this should be done by clockfw
 580          */
 581         cm_write_mod_reg(
 582                 OMAP3430_AUTO_MODEM |
 583                 OMAP3430ES2_AUTO_MMC3 |
 584                 OMAP3430ES2_AUTO_ICR |
 585                 OMAP3430_AUTO_AES2 |
 586                 OMAP3430_AUTO_SHA12 |
 587                 OMAP3430_AUTO_DES2 |
 588                 OMAP3430_AUTO_MMC2 |
 589                 OMAP3430_AUTO_MMC1 |
 590                 OMAP3430_AUTO_MSPRO |
 591                 OMAP3430_AUTO_HDQ |
 592                 OMAP3430_AUTO_MCSPI4 |
 593                 OMAP3430_AUTO_MCSPI3 |
 594                 OMAP3430_AUTO_MCSPI2 |
 595                 OMAP3430_AUTO_MCSPI1 |
 596                 OMAP3430_AUTO_I2C3 |
 597                 OMAP3430_AUTO_I2C2 |
 598                 OMAP3430_AUTO_I2C1 |
 599                 OMAP3430_AUTO_UART2 |
 600                 OMAP3430_AUTO_UART1 |
 601                 OMAP3430_AUTO_GPT11 |
 602                 OMAP3430_AUTO_GPT10 |
 603                 OMAP3430_AUTO_MCBSP5 |
 604                 OMAP3430_AUTO_MCBSP1 |
 605                 OMAP3430ES1_AUTO_FAC | /* This is es1 only */
 606                 OMAP3430_AUTO_MAILBOXES |
 607                 OMAP3430_AUTO_OMAPCTRL |
 608                 OMAP3430ES1_AUTO_FSHOSTUSB |
 609                 OMAP3430_AUTO_HSOTGUSB |
 610                 OMAP3430_AUTO_SAD2D |
 611                 OMAP3430_AUTO_SSI,
 612                 CORE_MOD, CM_AUTOIDLE1);
 613
 614         cm_write_mod_reg(
 615                 OMAP3430_AUTO_PKA |
 616                 OMAP3430_AUTO_AES1 |
 617                 OMAP3430_AUTO_RNG |
 618                 OMAP3430_AUTO_SHA11 |
 619                 OMAP3430_AUTO_DES1,
 620                 CORE_MOD, CM_AUTOIDLE2);
 621
 622         if (omap_rev() > OMAP3430_REV_ES1_0) {
 623                 cm_write_mod_reg(
 624                         OMAP3430_AUTO_MAD2D |
 625                         OMAP3430ES2_AUTO_USBTLL,
 626                         CORE_MOD, CM_AUTOIDLE3);
 627         }
 628
 629         cm_write_mod_reg(
 630                 OMAP3430_AUTO_WDT2 |
 631                 OMAP3430_AUTO_WDT1 |
 632                 OMAP3430_AUTO_GPIO1 |
 633                 OMAP3430_AUTO_32KSYNC |
 634                 OMAP3430_AUTO_GPT12 |
 635                 OMAP3430_AUTO_GPT1 ,
 636                 WKUP_MOD, CM_AUTOIDLE);
 637
 638         cm_write_mod_reg(
 639                 OMAP3430_AUTO_DSS,
 640                 OMAP3430_DSS_MOD,
 641                 CM_AUTOIDLE);
 642
 643         cm_write_mod_reg(
 644                 OMAP3430_AUTO_CAM,
 645                 OMAP3430_CAM_MOD,
 646                 CM_AUTOIDLE);
 647
 648         cm_write_mod_reg(
 649                 OMAP3430_AUTO_GPIO6 |
 650                 OMAP3430_AUTO_GPIO5 |
 651                 OMAP3430_AUTO_GPIO4 |
 652                 OMAP3430_AUTO_GPIO3 |
 653                 OMAP3430_AUTO_GPIO2 |
 654                 OMAP3430_AUTO_WDT3 |
 655                 OMAP3430_AUTO_UART3 |
 656                 OMAP3430_AUTO_GPT9 |
 657                 OMAP3430_AUTO_GPT8 |
 658                 OMAP3430_AUTO_GPT7 |
 659                 OMAP3430_AUTO_GPT6 |
 660                 OMAP3430_AUTO_GPT5 |
 661                 OMAP3430_AUTO_GPT4 |
 662                 OMAP3430_AUTO_GPT3 |
 663                 OMAP3430_AUTO_GPT2 |
 664                 OMAP3430_AUTO_MCBSP4 |
 665                 OMAP3430_AUTO_MCBSP3 |
 666                 OMAP3430_AUTO_MCBSP2,
 667                 OMAP3430_PER_MOD,
 668                 CM_AUTOIDLE);
 669
 670         if (omap_rev() > OMAP3430_REV_ES1_0) {
 671                 cm_write_mod_reg(
 672                         OMAP3430ES2_AUTO_USBHOST,
 673                         OMAP3430ES2_USBHOST_MOD,
 674                         CM_AUTOIDLE);
 675         }
 676
 677         /*
 678          * Set all plls to autoidle. This is needed until autoidle is
 679          * enabled by clockfw
 680          */
 681         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 682                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 683         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 684                          MPU_MOD,
 685                          CM_AUTOIDLE2);
 686         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 687                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 688                          PLL_MOD,
 689                          CM_AUTOIDLE);
 690         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 691                          PLL_MOD,
 692                          CM_AUTOIDLE2);
 693
 694         /*
 695          * Enable control of expternal oscillator through
 696          * sys_clkreq. In the long run clock framework should
 697          * take care of this.
 698          */
 699         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 700                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 701                              OMAP3430_GR_MOD,
 702                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 703
 704         /* setup wakup source */
 705         prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
 706                           OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
 707                           WKUP_MOD, PM_WKEN);
 708         /* No need to write EN_IO, that is always enabled */
 709         prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
 710                           OMAP3430_EN_GPT12,
 711                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 712         /* For some reason IO doesn't generate wakeup event even if
 713          * it is selected to mpu wakeup goup */
 714         prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
 715                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 716
 717         /* Enable wakeups in PER */
 718         prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 |
 719                           OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 |
 720                           OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3,
 721                           OMAP3430_PER_MOD, PM_WKEN);
 722         /* and allow them to wake up MPU */
 723         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 |
 724                           OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 |
 725                           OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3,
 726                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 727
 728         /* Don't attach IVA interrupts */
 729         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 730         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 731         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 732         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 733
 734         /* Clear any pending 'reset' flags */
 735         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 736         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 737         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 738         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 739         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 740         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 741         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 742
 743         /* Clear any pending PRCM interrupts */
 744         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 745
 746         /* Don't attach IVA interrupts */
 747         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 748         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 749         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 750         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 751
 752         /* Clear any pending 'reset' flags */
 753         prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
 754         prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
 755         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
 756         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
 757         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
 758         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
 759         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
 760
 761         /* Clear any pending PRCM interrupts */
 762         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 763
 764         omap3_iva_idle();
 765         omap3_d2d_idle();
 766 }
 767
 768 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 769 {
 770         struct power_state *pwrst;
 771
 772         list_for_each_entry(pwrst, &pwrst_list, node) {
 773                 if (pwrst->pwrdm == pwrdm)
 774                         return pwrst->next_state;
 775         }
 776         return -EINVAL;
 777 }
 778
 779 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 780 {
 781         struct power_state *pwrst;
 782
 783         list_for_each_entry(pwrst, &pwrst_list, node) {
 784                 if (pwrst->pwrdm == pwrdm) {
 785                         pwrst->next_state = state;
 786                         return 0;
 787                 }
 788         }
 789         return -EINVAL;
 790 }
 791
 792 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 793 {
 794         struct power_state *pwrst;
 795
 796         if (!pwrdm->pwrsts)
 797                 return 0;
 798
 799         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 800         if (!pwrst)
 801                 return -ENOMEM;
 802         pwrst->pwrdm = pwrdm;
 803         pwrst->next_state = PWRDM_POWER_RET;
 804         list_add(&pwrst->node, &pwrst_list);
 805
 806         if (pwrdm_has_hdwr_sar(pwrdm))
 807                 pwrdm_enable_hdwr_sar(pwrdm);
 808
 809         return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 810 }
 811
 812 /*
 813  * Enable hw supervised mode for all clockdomains if it's
 814  * supported. Initiate sleep transition for other clockdomains, if
 815  * they are not used
 816  */
 817 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 818 {
 819         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 820                 omap2_clkdm_allow_idle(clkdm);
 821         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 822                  atomic_read(&clkdm->usecount) == 0)
 823                 omap2_clkdm_sleep(clkdm);
 824         return 0;
 825 }
 826
 827 void omap_push_sram_idle(void)
 828 {
 829         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 830                                         omap34xx_cpu_suspend_sz);
 831 }
 832
 833 static int __init omap3_pm_init(void)
 834 {
 835         struct power_state *pwrst, *tmp;
 836         int ret;
 837
 838         if (!cpu_is_omap34xx())
 839                 return -ENODEV;
 840
 841         printk(KERN_ERR "Power Management for TI OMAP3.\n");
 842
 843         /* XXX prcm_setup_regs needs to be before enabling hw
 844          * supervised mode for powerdomains */
 845         prcm_setup_regs();
 846
 847         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 848                           (irq_handler_t)prcm_interrupt_handler,
 849                           IRQF_DISABLED, "prcm", NULL);
 850         if (ret) {
 851                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 852                        INT_34XX_PRCM_MPU_IRQ);
 853                 goto err1;
 854         }
 855
 856         ret = pwrdm_for_each(pwrdms_setup, NULL);
 857         if (ret) {
 858                 printk(KERN_ERR "Failed to setup powerdomains\n");
 859                 goto err2;
 860         }
 861
 862         (void) clkdm_for_each(clkdms_setup, NULL);
 863
 864         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 865         if (mpu_pwrdm == NULL) {
 866                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 867                 goto err2;
 868         }
 869
 870         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 871         per_pwrdm = pwrdm_lookup("per_pwrdm");
 872         core_pwrdm = pwrdm_lookup("core_pwrdm");
 873
 874         omap_push_sram_idle();
 875 #ifdef CONFIG_SUSPEND
 876         suspend_set_ops(&omap_pm_ops);
 877 #endif /* CONFIG_SUSPEND */
 878
 879         pm_idle = omap3_pm_idle;
 880
 881         pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm);
 882         /*
 883          * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for
 884          * IO-pad wakeup.  Otherwise it will unnecessarily waste power
 885          * waking up PER with every CORE wakeup - see
 886          * http://marc.info/?l=linux-omap&m=121852150710062&w=2
 887         */
 888         pwrdm_add_wkdep(per_pwrdm, core_pwrdm);
 889
 890 err1:
 891         return ret;
 892 err2:
 893         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 894         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 895                 list_del(&pwrst->node);
 896                 kfree(pwrst);
 897         }
 898         return ret;
 899 }
 900
 901 late_initcall(omap3_pm_init);