arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32
  33 #include <plat/sram.h>
  34 #include <plat/clockdomain.h>
  35 #include <plat/powerdomain.h>
  36 #include <plat/serial.h>
  37 #include <plat/sdrc.h>
  38 #include <plat/prcm.h>
  39 #include <plat/gpmc.h>
  40 #include <plat/dma.h>
  41
  42 #include <asm/tlbflush.h>
  43
  44 #include "cm.h"
  45 #include "cm-regbits-34xx.h"
  46 #include "prm-regbits-34xx.h"
  47
  48 #include "prm.h"
  49 #include "pm.h"
  50 #include "sdrc.h"
  51 #include "control.h"
  52
  53 /* Scratchpad offsets */
  54 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
  55 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
  56 #define OMAP343X_CONTROL_REG_VALUE_OFFSET  0xc8
  57
  58 struct power_state {
  59         struct powerdomain *pwrdm;
  60         u32 next_state;
  61 #ifdef CONFIG_SUSPEND
  62         u32 saved_state;
  63 #endif
  64         struct list_head node;
  65 };
  66
  67 static LIST_HEAD(pwrst_list);
  68
  69 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  70
  71 static int (*_omap_save_secure_sram)(u32 *addr);
  72
  73 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  74 static struct powerdomain *core_pwrdm, *per_pwrdm;
  75 static struct powerdomain *cam_pwrdm;
  76
  77 static inline void omap3_per_save_context(void)
  78 {
  79         omap_gpio_save_context();
  80 }
  81
  82 static inline void omap3_per_restore_context(void)
  83 {
  84         omap_gpio_restore_context();
  85 }
  86
  87 static void omap3_enable_io_chain(void)
  88 {
  89         int timeout = 0;
  90
  91         if (omap_rev() >= OMAP3430_REV_ES3_1) {
  92                 prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
  93                                      PM_WKEN);
  94                 /* Do a readback to assure write has been done */
  95                 prm_read_mod_reg(WKUP_MOD, PM_WKEN);
  96
  97                 while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
  98                          OMAP3430_ST_IO_CHAIN_MASK)) {
  99                         timeout++;
 100                         if (timeout > 1000) {
 101                                 printk(KERN_ERR "Wake up daisy chain "
 102                                        "activation failed.\n");
 103                                 return;
 104                         }
 105                         prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 106                                              WKUP_MOD, PM_WKEN);
 107                 }
 108         }
 109 }
 110
 111 static void omap3_disable_io_chain(void)
 112 {
 113         if (omap_rev() >= OMAP3430_REV_ES3_1)
 114                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 115                                        PM_WKEN);
 116 }
 117
 118 static void omap3_core_save_context(void)
 119 {
 120         u32 control_padconf_off;
 121
 122         /* Save the padconf registers */
 123         control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF);
 124         control_padconf_off |= START_PADCONF_SAVE;
 125         omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF);
 126         /* wait for the save to complete */
 127         while (!(omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS)
 128                         & PADCONF_SAVE_DONE))
 129                 udelay(1);
 130
 131         /*
 132          * Force write last pad into memory, as this can fail in some
 133          * cases according to erratas 1.157, 1.185
 134          */
 135         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 136                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 137
 138         /* Save the Interrupt controller context */
 139         omap_intc_save_context();
 140         /* Save the GPMC context */
 141         omap3_gpmc_save_context();
 142         /* Save the system control module context, padconf already save above*/
 143         omap3_control_save_context();
 144         omap_dma_global_context_save();
 145 }
 146
 147 static void omap3_core_restore_context(void)
 148 {
 149         /* Restore the control module context, padconf restored by h/w */
 150         omap3_control_restore_context();
 151         /* Restore the GPMC context */
 152         omap3_gpmc_restore_context();
 153         /* Restore the interrupt controller context */
 154         omap_intc_restore_context();
 155         omap_dma_global_context_restore();
 156 }
 157
 158 /*
 159  * FIXME: This function should be called before entering off-mode after
 160  * OMAP3 secure services have been accessed. Currently it is only called
 161  * once during boot sequence, but this works as we are not using secure
 162  * services.
 163  */
 164 static void omap3_save_secure_ram_context(u32 target_mpu_state)
 165 {
 166         u32 ret;
 167
 168         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 169                 /*
 170                  * MPU next state must be set to POWER_ON temporarily,
 171                  * otherwise the WFI executed inside the ROM code
 172                  * will hang the system.
 173                  */
 174                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 175                 ret = _omap_save_secure_sram((u32 *)
 176                                 __pa(omap3_secure_ram_storage));
 177                 pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state);
 178                 /* Following is for error tracking, it should not happen */
 179                 if (ret) {
 180                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 181                                 ret);
 182                         while (1)
 183                                 ;
 184                 }
 185         }
 186 }
 187
 188 /*
 189  * PRCM Interrupt Handler Helper Function
 190  *
 191  * The purpose of this function is to clear any wake-up events latched
 192  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 193  * may occur whilst attempting to clear a PM_WKST_x register and thus
 194  * set another bit in this register. A while loop is used to ensure
 195  * that any peripheral wake-up events occurring while attempting to
 196  * clear the PM_WKST_x are detected and cleared.
 197  */
 198 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 199 {
 200         u32 wkst, fclk, iclk, clken;
 201         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 202         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 203         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 204         u16 grpsel_off = (regs == 3) ?
 205                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 206         int c = 0;
 207
 208         wkst = prm_read_mod_reg(module, wkst_off);
 209         wkst &= prm_read_mod_reg(module, grpsel_off);
 210         if (wkst) {
 211                 iclk = cm_read_mod_reg(module, iclk_off);
 212                 fclk = cm_read_mod_reg(module, fclk_off);
 213                 while (wkst) {
 214                         clken = wkst;
 215                         cm_set_mod_reg_bits(clken, module, iclk_off);
 216                         /*
 217                          * For USBHOST, we don't know whether HOST1 or
 218                          * HOST2 woke us up, so enable both f-clocks
 219                          */
 220                         if (module == OMAP3430ES2_USBHOST_MOD)
 221                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 222                         cm_set_mod_reg_bits(clken, module, fclk_off);
 223                         prm_write_mod_reg(wkst, module, wkst_off);
 224                         wkst = prm_read_mod_reg(module, wkst_off);
 225                         c++;
 226                 }
 227                 cm_write_mod_reg(iclk, module, iclk_off);
 228                 cm_write_mod_reg(fclk, module, fclk_off);
 229         }
 230
 231         return c;
 232 }
 233
 234 static int _prcm_int_handle_wakeup(void)
 235 {
 236         int c;
 237
 238         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 239         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 240         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 241         if (omap_rev() > OMAP3430_REV_ES1_0) {
 242                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 243                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 244         }
 245
 246         return c;
 247 }
 248
 249 /*
 250  * PRCM Interrupt Handler
 251  *
 252  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 253  * interrupts from the PRCM for the MPU. These bits must be cleared in
 254  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 255  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 256  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 257  * register indicates that a wake-up event is pending for the MPU and
 258  * this bit can only be cleared if the all the wake-up events latched
 259  * in the various PM_WKST_x registers have been cleared. The interrupt
 260  * handler is implemented using a do-while loop so that if a wake-up
 261  * event occurred during the processing of the prcm interrupt handler
 262  * (setting a bit in the corresponding PM_WKST_x register and thus
 263  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 264  * this would be handled.
 265  */
 266 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 267 {
 268         u32 irqenable_mpu, irqstatus_mpu;
 269         int c = 0;
 270
 271         irqenable_mpu = prm_read_mod_reg(OCP_MOD,
 272                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 273         irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 274                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 275         irqstatus_mpu &= irqenable_mpu;
 276
 277         do {
 278                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 279                                      OMAP3430_IO_ST_MASK)) {
 280                         c = _prcm_int_handle_wakeup();
 281
 282                         /*
 283                          * Is the MPU PRCM interrupt handler racing with the
 284                          * IVA2 PRCM interrupt handler ?
 285                          */
 286                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 287                              "but no wakeup sources are marked\n");
 288                 } else {
 289                         /* XXX we need to expand our PRCM interrupt handler */
 290                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 291                              "no code to handle it (%08x)\n", irqstatus_mpu);
 292                 }
 293
 294                 prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 295                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 296
 297                 irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
 298                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 299                 irqstatus_mpu &= irqenable_mpu;
 300
 301         } while (irqstatus_mpu);
 302
 303         return IRQ_HANDLED;
 304 }
 305
 306 static void restore_control_register(u32 val)
 307 {
 308         __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val));
 309 }
 310
 311 /* Function to restore the table entry that was modified for enabling MMU */
 312 static void restore_table_entry(void)
 313 {
 314         void __iomem *scratchpad_address;
 315         u32 previous_value, control_reg_value;
 316         u32 *address;
 317
 318         scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD);
 319
 320         /* Get address of entry that was modified */
 321         address = (u32 *)__raw_readl(scratchpad_address +
 322                                      OMAP343X_TABLE_ADDRESS_OFFSET);
 323         /* Get the previous value which needs to be restored */
 324         previous_value = __raw_readl(scratchpad_address +
 325                                      OMAP343X_TABLE_VALUE_OFFSET);
 326         address = __va(address);
 327         *address = previous_value;
 328         flush_tlb_all();
 329         control_reg_value = __raw_readl(scratchpad_address
 330                                         + OMAP343X_CONTROL_REG_VALUE_OFFSET);
 331         /* This will enable caches and prediction */
 332         restore_control_register(control_reg_value);
 333 }
 334
 335 void omap_sram_idle(void)
 336 {
 337         /* Variable to tell what needs to be saved and restored
 338          * in omap_sram_idle*/
 339         /* save_state = 0 => Nothing to save and restored */
 340         /* save_state = 1 => Only L1 and logic lost */
 341         /* save_state = 2 => Only L2 lost */
 342         /* save_state = 3 => L1, L2 and logic lost */
 343         int save_state = 0;
 344         int mpu_next_state = PWRDM_POWER_ON;
 345         int per_next_state = PWRDM_POWER_ON;
 346         int core_next_state = PWRDM_POWER_ON;
 347         int core_prev_state, per_prev_state;
 348         u32 sdrc_pwr = 0;
 349
 350         if (!_omap_sram_idle)
 351                 return;
 352
 353         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 354         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 355         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 356         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 357
 358         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 359         switch (mpu_next_state) {
 360         case PWRDM_POWER_ON:
 361         case PWRDM_POWER_RET:
 362                 /* No need to save context */
 363                 save_state = 0;
 364                 break;
 365         case PWRDM_POWER_OFF:
 366                 save_state = 3;
 367                 break;
 368         default:
 369                 /* Invalid state */
 370                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 371                 return;
 372         }
 373         pwrdm_pre_transition();
 374
 375         /* NEON control */
 376         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 377                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 378
 379         /* Enable IO-PAD and IO-CHAIN wakeups */
 380         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 381         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 382         if (omap3_has_io_wakeup() &&
 383             (per_next_state < PWRDM_POWER_ON ||
 384              core_next_state < PWRDM_POWER_ON)) {
 385                 prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 386                 omap3_enable_io_chain();
 387         }
 388
 389         /* Block console output in case it is on one of the OMAP UARTs */
 390         if (per_next_state < PWRDM_POWER_ON ||
 391             core_next_state < PWRDM_POWER_ON)
 392                 if (try_acquire_console_sem())
 393                         goto console_still_active;
 394
 395         /* PER */
 396         if (per_next_state < PWRDM_POWER_ON) {
 397                 omap_uart_prepare_idle(2);
 398                 omap_uart_prepare_idle(3);
 399                 omap2_gpio_prepare_for_idle(per_next_state);
 400                 if (per_next_state == PWRDM_POWER_OFF)
 401                                 omap3_per_save_context();
 402         }
 403
 404         /* CORE */
 405         if (core_next_state < PWRDM_POWER_ON) {
 406                 omap_uart_prepare_idle(0);
 407                 omap_uart_prepare_idle(1);
 408                 if (core_next_state == PWRDM_POWER_OFF) {
 409                         omap3_core_save_context();
 410                         omap3_prcm_save_context();
 411                 }
 412         }
 413
 414         omap3_intc_prepare_idle();
 415
 416         /*
 417         * On EMU/HS devices ROM code restores a SRDC value
 418         * from scratchpad which has automatic self refresh on timeout
 419         * of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
 420         * Hence store/restore the SDRC_POWER register here.
 421         */
 422         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 423             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 424             core_next_state == PWRDM_POWER_OFF)
 425                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 426
 427         /*
 428          * omap3_arm_context is the location where ARM registers
 429          * get saved. The restore path then reads from this
 430          * location and restores them back.
 431          */
 432         _omap_sram_idle(omap3_arm_context, save_state);
 433         cpu_init();
 434
 435         /* Restore normal SDRC POWER settings */
 436         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 437             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 438             core_next_state == PWRDM_POWER_OFF)
 439                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 440
 441         /* Restore table entry modified during MMU restoration */
 442         if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF)
 443                 restore_table_entry();
 444
 445         /* CORE */
 446         if (core_next_state < PWRDM_POWER_ON) {
 447                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 448                 if (core_prev_state == PWRDM_POWER_OFF) {
 449                         omap3_core_restore_context();
 450                         omap3_prcm_restore_context();
 451                         omap3_sram_restore_context();
 452                         omap2_sms_restore_context();
 453                 }
 454                 omap_uart_resume_idle(0);
 455                 omap_uart_resume_idle(1);
 456                 if (core_next_state == PWRDM_POWER_OFF)
 457                         prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 458                                                OMAP3430_GR_MOD,
 459                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 460         }
 461         omap3_intc_resume_idle();
 462
 463         /* PER */
 464         if (per_next_state < PWRDM_POWER_ON) {
 465                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 466                 omap2_gpio_resume_after_idle();
 467                 if (per_prev_state == PWRDM_POWER_OFF)
 468                         omap3_per_restore_context();
 469                 omap_uart_resume_idle(2);
 470                 omap_uart_resume_idle(3);
 471         }
 472
 473         release_console_sem();
 474
 475 console_still_active:
 476         /* Disable IO-PAD and IO-CHAIN wakeup */
 477         if (omap3_has_io_wakeup() &&
 478             (per_next_state < PWRDM_POWER_ON ||
 479              core_next_state < PWRDM_POWER_ON)) {
 480                 prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 481                 omap3_disable_io_chain();
 482         }
 483
 484         pwrdm_post_transition();
 485
 486         omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 487 }
 488
 489 int omap3_can_sleep(void)
 490 {
 491         if (!sleep_while_idle)
 492                 return 0;
 493         if (!omap_uart_can_sleep())
 494                 return 0;
 495         return 1;
 496 }
 497
 498 static void omap3_pm_idle(void)
 499 {
 500         local_irq_disable();
 501         local_fiq_disable();
 502
 503         if (!omap3_can_sleep())
 504                 goto out;
 505
 506         if (omap_irq_pending() || need_resched())
 507                 goto out;
 508
 509         omap_sram_idle();
 510
 511 out:
 512         local_fiq_enable();
 513         local_irq_enable();
 514 }
 515
 516 #ifdef CONFIG_SUSPEND
 517 static suspend_state_t suspend_state;
 518
 519 static int omap3_pm_prepare(void)
 520 {
 521         disable_hlt();
 522         return 0;
 523 }
 524
 525 static int omap3_pm_suspend(void)
 526 {
 527         struct power_state *pwrst;
 528         int state, ret = 0;
 529
 530         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 531                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 532                                          wakeup_timer_milliseconds);
 533
 534         /* Read current next_pwrsts */
 535         list_for_each_entry(pwrst, &pwrst_list, node)
 536                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 537         /* Set ones wanted by suspend */
 538         list_for_each_entry(pwrst, &pwrst_list, node) {
 539                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 540                         goto restore;
 541                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 542                         goto restore;
 543         }
 544
 545         omap_uart_prepare_suspend();
 546         omap3_intc_suspend();
 547
 548         omap_sram_idle();
 549
 550 restore:
 551         /* Restore next_pwrsts */
 552         list_for_each_entry(pwrst, &pwrst_list, node) {
 553                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 554                 if (state > pwrst->next_state) {
 555                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 556                                "target state %d\n",
 557                                pwrst->pwrdm->name, pwrst->next_state);
 558                         ret = -1;
 559                 }
 560                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 561         }
 562         if (ret)
 563                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 564         else
 565                 printk(KERN_INFO "Successfully put all powerdomains "
 566                        "to target state\n");
 567
 568         return ret;
 569 }
 570
 571 static int omap3_pm_enter(suspend_state_t unused)
 572 {
 573         int ret = 0;
 574
 575         switch (suspend_state) {
 576         case PM_SUSPEND_STANDBY:
 577         case PM_SUSPEND_MEM:
 578                 ret = omap3_pm_suspend();
 579                 break;
 580         default:
 581                 ret = -EINVAL;
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void omap3_pm_finish(void)
 588 {
 589         enable_hlt();
 590 }
 591
 592 /* Hooks to enable / disable UART interrupts during suspend */
 593 static int omap3_pm_begin(suspend_state_t state)
 594 {
 595         suspend_state = state;
 596         omap_uart_enable_irqs(0);
 597         return 0;
 598 }
 599
 600 static void omap3_pm_end(void)
 601 {
 602         suspend_state = PM_SUSPEND_ON;
 603         omap_uart_enable_irqs(1);
 604         return;
 605 }
 606
 607 static struct platform_suspend_ops omap_pm_ops = {
 608         .begin          = omap3_pm_begin,
 609         .end            = omap3_pm_end,
 610         .prepare        = omap3_pm_prepare,
 611         .enter          = omap3_pm_enter,
 612         .finish         = omap3_pm_finish,
 613         .valid          = suspend_valid_only_mem,
 614 };
 615 #endif /* CONFIG_SUSPEND */
 616
 617
 618 /**
 619  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 620  *                   retention
 621  *
 622  * In cases where IVA2 is activated by bootcode, it may prevent
 623  * full-chip retention or off-mode because it is not idle.  This
 624  * function forces the IVA2 into idle state so it can go
 625  * into retention/off and thus allow full-chip retention/off.
 626  *
 627  **/
 628 static void __init omap3_iva_idle(void)
 629 {
 630         /* ensure IVA2 clock is disabled */
 631         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 632
 633         /* if no clock activity, nothing else to do */
 634         if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 635               OMAP3430_CLKACTIVITY_IVA2_MASK))
 636                 return;
 637
 638         /* Reset IVA2 */
 639         prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 640                           OMAP3430_RST2_IVA2_MASK |
 641                           OMAP3430_RST3_IVA2_MASK,
 642                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 643
 644         /* Enable IVA2 clock */
 645         cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 646                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 647
 648         /* Set IVA2 boot mode to 'idle' */
 649         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 650                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 651
 652         /* Un-reset IVA2 */
 653         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 654
 655         /* Disable IVA2 clock */
 656         cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 657
 658         /* Reset IVA2 */
 659         prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 660                           OMAP3430_RST2_IVA2_MASK |
 661                           OMAP3430_RST3_IVA2_MASK,
 662                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 663 }
 664
 665 static void __init omap3_d2d_idle(void)
 666 {
 667         u16 mask, padconf;
 668
 669         /* In a stand alone OMAP3430 where there is not a stacked
 670          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 671          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 672          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 673         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 674         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 675         padconf |= mask;
 676         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 677
 678         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 679         padconf |= mask;
 680         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 681
 682         /* reset modem */
 683         prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 684                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 685                           CORE_MOD, OMAP2_RM_RSTCTRL);
 686         prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 687 }
 688
 689 static void __init prcm_setup_regs(void)
 690 {
 691         u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
 692                                         OMAP3630_AUTO_UART4_MASK : 0;
 693         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 694                                         OMAP3630_EN_UART4_MASK : 0;
 695         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 696                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 697
 698
 699         /* XXX Reset all wkdeps. This should be done when initializing
 700          * powerdomains */
 701         prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
 702         prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
 703         prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
 704         prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
 705         prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
 706         prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
 707         if (omap_rev() > OMAP3430_REV_ES1_0) {
 708                 prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
 709                 prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
 710         } else
 711                 prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 712
 713         /*
 714          * Enable interface clock autoidle for all modules.
 715          * Note that in the long run this should be done by clockfw
 716          */
 717         cm_write_mod_reg(
 718                 OMAP3430_AUTO_MODEM_MASK |
 719                 OMAP3430ES2_AUTO_MMC3_MASK |
 720                 OMAP3430ES2_AUTO_ICR_MASK |
 721                 OMAP3430_AUTO_AES2_MASK |
 722                 OMAP3430_AUTO_SHA12_MASK |
 723                 OMAP3430_AUTO_DES2_MASK |
 724                 OMAP3430_AUTO_MMC2_MASK |
 725                 OMAP3430_AUTO_MMC1_MASK |
 726                 OMAP3430_AUTO_MSPRO_MASK |
 727                 OMAP3430_AUTO_HDQ_MASK |
 728                 OMAP3430_AUTO_MCSPI4_MASK |
 729                 OMAP3430_AUTO_MCSPI3_MASK |
 730                 OMAP3430_AUTO_MCSPI2_MASK |
 731                 OMAP3430_AUTO_MCSPI1_MASK |
 732                 OMAP3430_AUTO_I2C3_MASK |
 733                 OMAP3430_AUTO_I2C2_MASK |
 734                 OMAP3430_AUTO_I2C1_MASK |
 735                 OMAP3430_AUTO_UART2_MASK |
 736                 OMAP3430_AUTO_UART1_MASK |
 737                 OMAP3430_AUTO_GPT11_MASK |
 738                 OMAP3430_AUTO_GPT10_MASK |
 739                 OMAP3430_AUTO_MCBSP5_MASK |
 740                 OMAP3430_AUTO_MCBSP1_MASK |
 741                 OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
 742                 OMAP3430_AUTO_MAILBOXES_MASK |
 743                 OMAP3430_AUTO_OMAPCTRL_MASK |
 744                 OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
 745                 OMAP3430_AUTO_HSOTGUSB_MASK |
 746                 OMAP3430_AUTO_SAD2D_MASK |
 747                 OMAP3430_AUTO_SSI_MASK,
 748                 CORE_MOD, CM_AUTOIDLE1);
 749
 750         cm_write_mod_reg(
 751                 OMAP3430_AUTO_PKA_MASK |
 752                 OMAP3430_AUTO_AES1_MASK |
 753                 OMAP3430_AUTO_RNG_MASK |
 754                 OMAP3430_AUTO_SHA11_MASK |
 755                 OMAP3430_AUTO_DES1_MASK,
 756                 CORE_MOD, CM_AUTOIDLE2);
 757
 758         if (omap_rev() > OMAP3430_REV_ES1_0) {
 759                 cm_write_mod_reg(
 760                         OMAP3430_AUTO_MAD2D_MASK |
 761                         OMAP3430ES2_AUTO_USBTLL_MASK,
 762                         CORE_MOD, CM_AUTOIDLE3);
 763         }
 764
 765         cm_write_mod_reg(
 766                 OMAP3430_AUTO_WDT2_MASK |
 767                 OMAP3430_AUTO_WDT1_MASK |
 768                 OMAP3430_AUTO_GPIO1_MASK |
 769                 OMAP3430_AUTO_32KSYNC_MASK |
 770                 OMAP3430_AUTO_GPT12_MASK |
 771                 OMAP3430_AUTO_GPT1_MASK,
 772                 WKUP_MOD, CM_AUTOIDLE);
 773
 774         cm_write_mod_reg(
 775                 OMAP3430_AUTO_DSS_MASK,
 776                 OMAP3430_DSS_MOD,
 777                 CM_AUTOIDLE);
 778
 779         cm_write_mod_reg(
 780                 OMAP3430_AUTO_CAM_MASK,
 781                 OMAP3430_CAM_MOD,
 782                 CM_AUTOIDLE);
 783
 784         cm_write_mod_reg(
 785                 omap3630_auto_uart4_mask |
 786                 OMAP3430_AUTO_GPIO6_MASK |
 787                 OMAP3430_AUTO_GPIO5_MASK |
 788                 OMAP3430_AUTO_GPIO4_MASK |
 789                 OMAP3430_AUTO_GPIO3_MASK |
 790                 OMAP3430_AUTO_GPIO2_MASK |
 791                 OMAP3430_AUTO_WDT3_MASK |
 792                 OMAP3430_AUTO_UART3_MASK |
 793                 OMAP3430_AUTO_GPT9_MASK |
 794                 OMAP3430_AUTO_GPT8_MASK |
 795                 OMAP3430_AUTO_GPT7_MASK |
 796                 OMAP3430_AUTO_GPT6_MASK |
 797                 OMAP3430_AUTO_GPT5_MASK |
 798                 OMAP3430_AUTO_GPT4_MASK |
 799                 OMAP3430_AUTO_GPT3_MASK |
 800                 OMAP3430_AUTO_GPT2_MASK |
 801                 OMAP3430_AUTO_MCBSP4_MASK |
 802                 OMAP3430_AUTO_MCBSP3_MASK |
 803                 OMAP3430_AUTO_MCBSP2_MASK,
 804                 OMAP3430_PER_MOD,
 805                 CM_AUTOIDLE);
 806
 807         if (omap_rev() > OMAP3430_REV_ES1_0) {
 808                 cm_write_mod_reg(
 809                         OMAP3430ES2_AUTO_USBHOST_MASK,
 810                         OMAP3430ES2_USBHOST_MOD,
 811                         CM_AUTOIDLE);
 812         }
 813
 814         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 815
 816         /*
 817          * Set all plls to autoidle. This is needed until autoidle is
 818          * enabled by clockfw
 819          */
 820         cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
 821                          OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
 822         cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
 823                          MPU_MOD,
 824                          CM_AUTOIDLE2);
 825         cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
 826                          (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
 827                          PLL_MOD,
 828                          CM_AUTOIDLE);
 829         cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
 830                          PLL_MOD,
 831                          CM_AUTOIDLE2);
 832
 833         /*
 834          * Enable control of expternal oscillator through
 835          * sys_clkreq. In the long run clock framework should
 836          * take care of this.
 837          */
 838         prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 839                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 840                              OMAP3430_GR_MOD,
 841                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 842
 843         /* setup wakup source */
 844         prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 845                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 846                           WKUP_MOD, PM_WKEN);
 847         /* No need to write EN_IO, that is always enabled */
 848         prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 849                           OMAP3430_GRPSEL_GPT1_MASK |
 850                           OMAP3430_GRPSEL_GPT12_MASK,
 851                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 852         /* For some reason IO doesn't generate wakeup event even if
 853          * it is selected to mpu wakeup goup */
 854         prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 855                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 856
 857         /* Enable PM_WKEN to support DSS LPR */
 858         prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 859                                 OMAP3430_DSS_MOD, PM_WKEN);
 860
 861         /* Enable wakeups in PER */
 862         prm_write_mod_reg(omap3630_en_uart4_mask |
 863                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 864                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 865                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 866                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 867                           OMAP3430_EN_MCBSP4_MASK,
 868                           OMAP3430_PER_MOD, PM_WKEN);
 869         /* and allow them to wake up MPU */
 870         prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 871                           OMAP3430_GRPSEL_GPIO2_MASK |
 872                           OMAP3430_GRPSEL_GPIO3_MASK |
 873                           OMAP3430_GRPSEL_GPIO4_MASK |
 874                           OMAP3430_GRPSEL_GPIO5_MASK |
 875                           OMAP3430_GRPSEL_GPIO6_MASK |
 876                           OMAP3430_GRPSEL_UART3_MASK |
 877                           OMAP3430_GRPSEL_MCBSP2_MASK |
 878                           OMAP3430_GRPSEL_MCBSP3_MASK |
 879                           OMAP3430_GRPSEL_MCBSP4_MASK,
 880                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 881
 882         /* Don't attach IVA interrupts */
 883         prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 884         prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 885         prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 886         prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 887
 888         /* Clear any pending 'reset' flags */
 889         prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 890         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 891         prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 892         prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 893         prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 894         prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 895         prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 896
 897         /* Clear any pending PRCM interrupts */
 898         prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 899
 900         omap3_iva_idle();
 901         omap3_d2d_idle();
 902 }
 903
 904 void omap3_pm_off_mode_enable(int enable)
 905 {
 906         struct power_state *pwrst;
 907         u32 state;
 908
 909         if (enable)
 910                 state = PWRDM_POWER_OFF;
 911         else
 912                 state = PWRDM_POWER_RET;
 913
 914 #ifdef CONFIG_CPU_IDLE
 915         omap3_cpuidle_update_states();
 916 #endif
 917
 918         list_for_each_entry(pwrst, &pwrst_list, node) {
 919                 pwrst->next_state = state;
 920                 omap_set_pwrdm_state(pwrst->pwrdm, state);
 921         }
 922 }
 923
 924 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 925 {
 926         struct power_state *pwrst;
 927
 928         list_for_each_entry(pwrst, &pwrst_list, node) {
 929                 if (pwrst->pwrdm == pwrdm)
 930                         return pwrst->next_state;
 931         }
 932         return -EINVAL;
 933 }
 934
 935 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 936 {
 937         struct power_state *pwrst;
 938
 939         list_for_each_entry(pwrst, &pwrst_list, node) {
 940                 if (pwrst->pwrdm == pwrdm) {
 941                         pwrst->next_state = state;
 942                         return 0;
 943                 }
 944         }
 945         return -EINVAL;
 946 }
 947
 948 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 949 {
 950         struct power_state *pwrst;
 951
 952         if (!pwrdm->pwrsts)
 953                 return 0;
 954
 955         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 956         if (!pwrst)
 957                 return -ENOMEM;
 958         pwrst->pwrdm = pwrdm;
 959         pwrst->next_state = PWRDM_POWER_RET;
 960         list_add(&pwrst->node, &pwrst_list);
 961
 962         if (pwrdm_has_hdwr_sar(pwrdm))
 963                 pwrdm_enable_hdwr_sar(pwrdm);
 964
 965         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 966 }
 967
 968 /*
 969  * Enable hw supervised mode for all clockdomains if it's
 970  * supported. Initiate sleep transition for other clockdomains, if
 971  * they are not used
 972  */
 973 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 974 {
 975         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 976                 omap2_clkdm_allow_idle(clkdm);
 977         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 978                  atomic_read(&clkdm->usecount) == 0)
 979                 omap2_clkdm_sleep(clkdm);
 980         return 0;
 981 }
 982
 983 void omap_push_sram_idle(void)
 984 {
 985         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 986                                         omap34xx_cpu_suspend_sz);
 987         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 988                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 989                                 save_secure_ram_context_sz);
 990 }
 991
 992 static int __init omap3_pm_init(void)
 993 {
 994         struct power_state *pwrst, *tmp;
 995         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 996         int ret;
 997
 998         if (!cpu_is_omap34xx())
 999                 return -ENODEV;
1000
1001         printk(KERN_ERR "Power Management for TI OMAP3.\n");
1002
1003         /* XXX prcm_setup_regs needs to be before enabling hw
1004          * supervised mode for powerdomains */
1005         prcm_setup_regs();
1006
1007         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
1008                           (irq_handler_t)prcm_interrupt_handler,
1009                           IRQF_DISABLED, "prcm", NULL);
1010         if (ret) {
1011                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
1012                        INT_34XX_PRCM_MPU_IRQ);
1013                 goto err1;
1014         }
1015
1016         ret = pwrdm_for_each(pwrdms_setup, NULL);
1017         if (ret) {
1018                 printk(KERN_ERR "Failed to setup powerdomains\n");
1019                 goto err2;
1020         }
1021
1022         (void) clkdm_for_each(clkdms_setup, NULL);
1023
1024         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
1025         if (mpu_pwrdm == NULL) {
1026                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
1027                 goto err2;
1028         }
1029
1030         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
1031         per_pwrdm = pwrdm_lookup("per_pwrdm");
1032         core_pwrdm = pwrdm_lookup("core_pwrdm");
1033         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
1034
1035         neon_clkdm = clkdm_lookup("neon_clkdm");
1036         mpu_clkdm = clkdm_lookup("mpu_clkdm");
1037         per_clkdm = clkdm_lookup("per_clkdm");
1038         core_clkdm = clkdm_lookup("core_clkdm");
1039
1040         omap_push_sram_idle();
1041 #ifdef CONFIG_SUSPEND
1042         suspend_set_ops(&omap_pm_ops);
1043 #endif /* CONFIG_SUSPEND */
1044
1045         pm_idle = omap3_pm_idle;
1046         omap3_idle_init();
1047
1048         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
1049         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
1050                 omap3_secure_ram_storage =
1051                         kmalloc(0x803F, GFP_KERNEL);
1052                 if (!omap3_secure_ram_storage)
1053                         printk(KERN_ERR "Memory allocation failed when"
1054                                         "allocating for secure sram context\n");
1055
1056                 local_irq_disable();
1057                 local_fiq_disable();
1058
1059                 omap_dma_global_context_save();
1060                 omap3_save_secure_ram_context(PWRDM_POWER_ON);
1061                 omap_dma_global_context_restore();
1062
1063                 local_irq_enable();
1064                 local_fiq_enable();
1065         }
1066
1067         omap3_save_scratchpad_contents();
1068 err1:
1069         return ret;
1070 err2:
1071         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
1072         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
1073                 list_del(&pwrst->node);
1074                 kfree(pwrst);
1075         }
1076         return ret;
1077 }
1078
1079 late_initcall(omap3_pm_init);