arch/arm/mach-omap2/pm24xx.c

   1 /*
   2  * OMAP2 Power Management Routines
   3  *
   4  * Copyright (C) 2005 Texas Instruments, Inc.
   5  * Copyright (C) 2006-2008 Nokia Corporation
   6  *
   7  * Written by:
   8  * Richard Woodruff <r-woodruff2@ti.com>
   9  * Tony Lindgren
  10  * Juha Yrjola
  11  * Amit Kucheria <amit.kucheria@nokia.com>
  12  * Igor Stoppa <igor.stoppa@nokia.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/suspend.h>
  22 #include <linux/sched.h>
  23 #include <linux/proc_fs.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/sysfs.h>
  26 #include <linux/module.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/irq.h>
  31 #include <linux/time.h>
  32 #include <linux/gpio.h>
  33
  34 #include <asm/mach/time.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <mach/irqs.h>
  39 #include <plat/clock.h>
  40 #include <plat/sram.h>
  41 #include <plat/control.h>
  42 #include <plat/dma.h>
  43 #include <plat/board.h>
  44
  45 #include "prm.h"
  46 #include "prm-regbits-24xx.h"
  47 #include "cm.h"
  48 #include "cm-regbits-24xx.h"
  49 #include "sdrc.h"
  50 #include "pm.h"
  51
  52 #include <plat/powerdomain.h>
  53 #include <plat/clockdomain.h>
  54
  55 static void (*omap2_sram_idle)(void);
  56 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
  57                                   void __iomem *sdrc_power);
  58
  59 static struct powerdomain *mpu_pwrdm, *core_pwrdm;
  60 static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;
  61
  62 static struct clk *osc_ck, *emul_ck;
  63
  64 static int omap2_fclks_active(void)
  65 {
  66         u32 f1, f2;
  67
  68         f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
  69         f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
  70
  71         /* Ignore UART clocks.  These are handled by UART core (serial.c) */
  72         f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
  73         f2 &= ~OMAP24XX_EN_UART3_MASK;
  74
  75         if (f1 | f2)
  76                 return 1;
  77         return 0;
  78 }
  79
  80 static void omap2_enter_full_retention(void)
  81 {
  82         u32 l;
  83         struct timespec ts_preidle, ts_postidle, ts_idle;
  84
  85         /* There is 1 reference hold for all children of the oscillator
  86          * clock, the following will remove it. If no one else uses the
  87          * oscillator itself it will be disabled if/when we enter retention
  88          * mode.
  89          */
  90         clk_disable(osc_ck);
  91
  92         /* Clear old wake-up events */
  93         /* REVISIT: These write to reserved bits? */
  94         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
  95         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
  96         prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
  97
  98         /*
  99          * Set MPU powerdomain's next power state to RETENTION;
 100          * preserve logic state during retention
 101          */
 102         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 103         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 104
 105         /* Workaround to kill USB */
 106         l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
 107         omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
 108
 109         omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
 110
 111         if (omap2_pm_debug) {
 112                 omap2_pm_dump(0, 0, 0);
 113                 getnstimeofday(&ts_preidle);
 114         }
 115
 116         /* One last check for pending IRQs to avoid extra latency due
 117          * to sleeping unnecessarily. */
 118         if (omap_irq_pending())
 119                 goto no_sleep;
 120
 121         omap_uart_prepare_idle(0);
 122         omap_uart_prepare_idle(1);
 123         omap_uart_prepare_idle(2);
 124
 125         /* Jump to SRAM suspend code */
 126         omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
 127                            OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
 128                            OMAP_SDRC_REGADDR(SDRC_POWER));
 129
 130         omap_uart_resume_idle(2);
 131         omap_uart_resume_idle(1);
 132         omap_uart_resume_idle(0);
 133
 134 no_sleep:
 135         if (omap2_pm_debug) {
 136                 unsigned long long tmp;
 137
 138                 getnstimeofday(&ts_postidle);
 139                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 140                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 141                 omap2_pm_dump(0, 1, tmp);
 142         }
 143         omap2_gpio_resume_after_idle();
 144
 145         clk_enable(osc_ck);
 146
 147         /* clear CORE wake-up events */
 148         prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 149         prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 150
 151         /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
 152         prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);
 153
 154         /* MPU domain wake events */
 155         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 156         if (l & 0x01)
 157                 prm_write_mod_reg(0x01, OCP_MOD,
 158                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 159         if (l & 0x20)
 160                 prm_write_mod_reg(0x20, OCP_MOD,
 161                                   OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 162
 163         /* Mask future PRCM-to-MPU interrupts */
 164         prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
 165 }
 166
 167 static int omap2_i2c_active(void)
 168 {
 169         u32 l;
 170
 171         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 172         return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
 173 }
 174
 175 static int sti_console_enabled;
 176
 177 static int omap2_allow_mpu_retention(void)
 178 {
 179         u32 l;
 180
 181         /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
 182         l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
 183         if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
 184                  OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
 185                  OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
 186                 return 0;
 187         /* Check for UART3. */
 188         l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
 189         if (l & OMAP24XX_EN_UART3_MASK)
 190                 return 0;
 191         if (sti_console_enabled)
 192                 return 0;
 193
 194         return 1;
 195 }
 196
 197 static void omap2_enter_mpu_retention(void)
 198 {
 199         int only_idle = 0;
 200         struct timespec ts_preidle, ts_postidle, ts_idle;
 201
 202         /* Putting MPU into the WFI state while a transfer is active
 203          * seems to cause the I2C block to timeout. Why? Good question. */
 204         if (omap2_i2c_active())
 205                 return;
 206
 207         /* The peripherals seem not to be able to wake up the MPU when
 208          * it is in retention mode. */
 209         if (omap2_allow_mpu_retention()) {
 210                 /* REVISIT: These write to reserved bits? */
 211                 prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
 212                 prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
 213                 prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
 214
 215                 /* Try to enter MPU retention */
 216                 prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
 217                                   OMAP_LOGICRETSTATE_MASK,
 218                                   MPU_MOD, OMAP2_PM_PWSTCTRL);
 219         } else {
 220                 /* Block MPU retention */
 221
 222                 prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
 223                                                  OMAP2_PM_PWSTCTRL);
 224                 only_idle = 1;
 225         }
 226
 227         if (omap2_pm_debug) {
 228                 omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
 229                 getnstimeofday(&ts_preidle);
 230         }
 231
 232         omap2_sram_idle();
 233
 234         if (omap2_pm_debug) {
 235                 unsigned long long tmp;
 236
 237                 getnstimeofday(&ts_postidle);
 238                 ts_idle = timespec_sub(ts_postidle, ts_preidle);
 239                 tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
 240                 omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
 241         }
 242 }
 243
 244 static int omap2_can_sleep(void)
 245 {
 246         if (omap2_fclks_active())
 247                 return 0;
 248         if (osc_ck->usecount > 1)
 249                 return 0;
 250         if (omap_dma_running())
 251                 return 0;
 252
 253         return 1;
 254 }
 255
 256 static void omap2_pm_idle(void)
 257 {
 258         local_irq_disable();
 259         local_fiq_disable();
 260
 261         if (!omap2_can_sleep()) {
 262                 if (omap_irq_pending())
 263                         goto out;
 264                 omap2_enter_mpu_retention();
 265                 goto out;
 266         }
 267
 268         if (omap_irq_pending())
 269                 goto out;
 270
 271         omap2_enter_full_retention();
 272
 273 out:
 274         local_fiq_enable();
 275         local_irq_enable();
 276 }
 277
 278 static int omap2_pm_prepare(void)
 279 {
 280         /* We cannot sleep in idle until we have resumed */
 281         disable_hlt();
 282         return 0;
 283 }
 284
 285 static int omap2_pm_suspend(void)
 286 {
 287         u32 wken_wkup, mir1;
 288
 289         wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 290         wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
 291         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 292
 293         /* Mask GPT1 */
 294         mir1 = omap_readl(0x480fe0a4);
 295         omap_writel(1 << 5, 0x480fe0ac);
 296
 297         omap_uart_prepare_suspend();
 298         omap2_enter_full_retention();
 299
 300         omap_writel(mir1, 0x480fe0a4);
 301         prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
 302
 303         return 0;
 304 }
 305
 306 static int omap2_pm_enter(suspend_state_t state)
 307 {
 308         int ret = 0;
 309
 310         switch (state) {
 311         case PM_SUSPEND_STANDBY:
 312         case PM_SUSPEND_MEM:
 313                 ret = omap2_pm_suspend();
 314                 break;
 315         default:
 316                 ret = -EINVAL;
 317         }
 318
 319         return ret;
 320 }
 321
 322 static void omap2_pm_finish(void)
 323 {
 324         enable_hlt();
 325 }
 326
 327 static struct platform_suspend_ops omap_pm_ops = {
 328         .prepare        = omap2_pm_prepare,
 329         .enter          = omap2_pm_enter,
 330         .finish         = omap2_pm_finish,
 331         .valid          = suspend_valid_only_mem,
 332 };
 333
 334 /* XXX This function should be shareable between OMAP2xxx and OMAP3 */
 335 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 336 {
 337         clkdm_clear_all_wkdeps(clkdm);
 338         clkdm_clear_all_sleepdeps(clkdm);
 339
 340         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 341                 omap2_clkdm_allow_idle(clkdm);
 342         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 343                  atomic_read(&clkdm->usecount) == 0)
 344                 omap2_clkdm_sleep(clkdm);
 345         return 0;
 346 }
 347
 348 static void __init prcm_setup_regs(void)
 349 {
 350         int i, num_mem_banks;
 351         struct powerdomain *pwrdm;
 352
 353         /* Enable autoidle */
 354         prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
 355                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 356
 357         /*
 358          * Set CORE powerdomain memory banks to retain their contents
 359          * during RETENTION
 360          */
 361         num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
 362         for (i = 0; i < num_mem_banks; i++)
 363                 pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
 364
 365         /* Set CORE powerdomain's next power state to RETENTION */
 366         pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
 367
 368         /*
 369          * Set MPU powerdomain's next power state to RETENTION;
 370          * preserve logic state during retention
 371          */
 372         pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
 373         pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
 374
 375         /* Force-power down DSP, GFX powerdomains */
 376
 377         pwrdm = clkdm_get_pwrdm(dsp_clkdm);
 378         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 379         omap2_clkdm_sleep(dsp_clkdm);
 380
 381         pwrdm = clkdm_get_pwrdm(gfx_clkdm);
 382         pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
 383         omap2_clkdm_sleep(gfx_clkdm);
 384
 385         /*
 386          * Clear clockdomain wakeup dependencies and enable
 387          * hardware-supervised idle for all clkdms
 388          */
 389         clkdm_for_each(clkdms_setup, NULL);
 390         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 391
 392         /* Enable clock autoidle for all domains */
 393         cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
 394                          OMAP24XX_AUTO_MAILBOXES_MASK |
 395                          OMAP24XX_AUTO_WDT4_MASK |
 396                          OMAP2420_AUTO_WDT3_MASK |
 397                          OMAP24XX_AUTO_MSPRO_MASK |
 398                          OMAP2420_AUTO_MMC_MASK |
 399                          OMAP24XX_AUTO_FAC_MASK |
 400                          OMAP2420_AUTO_EAC_MASK |
 401                          OMAP24XX_AUTO_HDQ_MASK |
 402                          OMAP24XX_AUTO_UART2_MASK |
 403                          OMAP24XX_AUTO_UART1_MASK |
 404                          OMAP24XX_AUTO_I2C2_MASK |
 405                          OMAP24XX_AUTO_I2C1_MASK |
 406                          OMAP24XX_AUTO_MCSPI2_MASK |
 407                          OMAP24XX_AUTO_MCSPI1_MASK |
 408                          OMAP24XX_AUTO_MCBSP2_MASK |
 409                          OMAP24XX_AUTO_MCBSP1_MASK |
 410                          OMAP24XX_AUTO_GPT12_MASK |
 411                          OMAP24XX_AUTO_GPT11_MASK |
 412                          OMAP24XX_AUTO_GPT10_MASK |
 413                          OMAP24XX_AUTO_GPT9_MASK |
 414                          OMAP24XX_AUTO_GPT8_MASK |
 415                          OMAP24XX_AUTO_GPT7_MASK |
 416                          OMAP24XX_AUTO_GPT6_MASK |
 417                          OMAP24XX_AUTO_GPT5_MASK |
 418                          OMAP24XX_AUTO_GPT4_MASK |
 419                          OMAP24XX_AUTO_GPT3_MASK |
 420                          OMAP24XX_AUTO_GPT2_MASK |
 421                          OMAP2420_AUTO_VLYNQ_MASK |
 422                          OMAP24XX_AUTO_DSS_MASK,
 423                          CORE_MOD, CM_AUTOIDLE1);
 424         cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
 425                          OMAP24XX_AUTO_SSI_MASK |
 426                          OMAP24XX_AUTO_USB_MASK,
 427                          CORE_MOD, CM_AUTOIDLE2);
 428         cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
 429                          OMAP24XX_AUTO_GPMC_MASK |
 430                          OMAP24XX_AUTO_SDMA_MASK,
 431                          CORE_MOD, CM_AUTOIDLE3);
 432         cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
 433                          OMAP24XX_AUTO_AES_MASK |
 434                          OMAP24XX_AUTO_RNG_MASK |
 435                          OMAP24XX_AUTO_SHA_MASK |
 436                          OMAP24XX_AUTO_DES_MASK,
 437                          CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
 438
 439         cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
 440                          CM_AUTOIDLE);
 441
 442         /* Put DPLL and both APLLs into autoidle mode */
 443         cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
 444                          (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
 445                          (0x03 << OMAP24XX_AUTO_54M_SHIFT),
 446                          PLL_MOD, CM_AUTOIDLE);
 447
 448         cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
 449                          OMAP24XX_AUTO_WDT1_MASK |
 450                          OMAP24XX_AUTO_MPU_WDT_MASK |
 451                          OMAP24XX_AUTO_GPIOS_MASK |
 452                          OMAP24XX_AUTO_32KSYNC_MASK |
 453                          OMAP24XX_AUTO_GPT1_MASK,
 454                          WKUP_MOD, CM_AUTOIDLE);
 455
 456         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
 457          * stabilisation */
 458         prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 459                           OMAP2_PRCM_CLKSSETUP_OFFSET);
 460
 461         /* Configure automatic voltage transition */
 462         prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
 463                           OMAP2_PRCM_VOLTSETUP_OFFSET);
 464         prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
 465                           (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
 466                           OMAP24XX_MEMRETCTRL_MASK |
 467                           (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
 468                           (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
 469                           OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
 470
 471         /* Enable wake-up events */
 472         prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
 473                           WKUP_MOD, PM_WKEN);
 474 }
 475
 476 static int __init omap2_pm_init(void)
 477 {
 478         u32 l;
 479
 480         if (!cpu_is_omap24xx())
 481                 return -ENODEV;
 482
 483         printk(KERN_INFO "Power Management for OMAP2 initializing\n");
 484         l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
 485         printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
 486
 487         /* Look up important powerdomains */
 488
 489         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 490         if (!mpu_pwrdm)
 491                 pr_err("PM: mpu_pwrdm not found\n");
 492
 493         core_pwrdm = pwrdm_lookup("core_pwrdm");
 494         if (!core_pwrdm)
 495                 pr_err("PM: core_pwrdm not found\n");
 496
 497         /* Look up important clockdomains */
 498
 499         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 500         if (!mpu_clkdm)
 501                 pr_err("PM: mpu_clkdm not found\n");
 502
 503         wkup_clkdm = clkdm_lookup("wkup_clkdm");
 504         if (!wkup_clkdm)
 505                 pr_err("PM: wkup_clkdm not found\n");
 506
 507         dsp_clkdm = clkdm_lookup("dsp_clkdm");
 508         if (!dsp_clkdm)
 509                 pr_err("PM: dsp_clkdm not found\n");
 510
 511         gfx_clkdm = clkdm_lookup("gfx_clkdm");
 512         if (!gfx_clkdm)
 513                 pr_err("PM: gfx_clkdm not found\n");
 514
 515
 516         osc_ck = clk_get(NULL, "osc_ck");
 517         if (IS_ERR(osc_ck)) {
 518                 printk(KERN_ERR "could not get osc_ck\n");
 519                 return -ENODEV;
 520         }
 521
 522         if (cpu_is_omap242x()) {
 523                 emul_ck = clk_get(NULL, "emul_ck");
 524                 if (IS_ERR(emul_ck)) {
 525                         printk(KERN_ERR "could not get emul_ck\n");
 526                         clk_put(osc_ck);
 527                         return -ENODEV;
 528                 }
 529         }
 530
 531         prcm_setup_regs();
 532
 533         /* Hack to prevent MPU retention when STI console is enabled. */
 534         {
 535                 const struct omap_sti_console_config *sti;
 536
 537                 sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
 538                                       struct omap_sti_console_config);
 539                 if (sti != NULL && sti->enable)
 540                         sti_console_enabled = 1;
 541         }
 542
 543         /*
 544          * We copy the assembler sleep/wakeup routines to SRAM.
 545          * These routines need to be in SRAM as that's the only
 546          * memory the MPU can see when it wakes up.
 547          */
 548         if (cpu_is_omap24xx()) {
 549                 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
 550                                                  omap24xx_idle_loop_suspend_sz);
 551
 552                 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
 553                                                     omap24xx_cpu_suspend_sz);
 554         }
 555
 556         suspend_set_ops(&omap_pm_ops);
 557         pm_idle = omap2_pm_idle;
 558
 559         return 0;
 560 }
 561
 562 late_initcall(omap2_pm_init);