arch/arm/mach-omap2/omap_phy_internal.c

   1 /*
   2   * This file configures the internal USB PHY in OMAP4430. Used
   3   * with TWL6030 transceiver and MUSB on OMAP4430.
   4   *
   5   * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
   6   * This program is free software; you can redistribute it and/or modify
   7   * it under the terms of the GNU General Public License as published by
   8   * the Free Software Foundation; either version 2 of the License, or
   9   * (at your option) any later version.
  10   *
  11   * Author: Hema HK <hemahk@ti.com>
  12   *
  13   * This program is distributed in the hope that it will be useful,
  14   * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   * GNU General Public License for more details.
  17   *
  18   * You should have received a copy of the GNU General Public License
  19   * along with this program; if not, write to the Free Software
  20   * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21   *
  22   */
  23
  24 #include <linux/types.h>
  25 #include <linux/delay.h>
  26 #include <linux/clk.h>
  27 #include <linux/io.h>
  28 #include <linux/err.h>
  29 #include <linux/usb.h>
  30
  31 #include <plat/usb.h>
  32
  33 /* OMAP control module register for UTMI PHY */
  34 #define CONTROL_DEV_CONF                0x300
  35 #define PHY_PD                          0x1
  36
  37 #define USBOTGHS_CONTROL                0x33c
  38 #define AVALID                          BIT(0)
  39 #define BVALID                          BIT(1)
  40 #define VBUSVALID                       BIT(2)
  41 #define SESSEND                         BIT(3)
  42 #define IDDIG                           BIT(4)
  43
  44 static struct clk *phyclk, *clk48m, *clk32k;
  45 static void __iomem *ctrl_base;
  46 static int usbotghs_control;
  47
  48 int omap4430_phy_init(struct device *dev)
  49 {
  50         ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K);
  51         if (!ctrl_base) {
  52                 dev_err(dev, "control module ioremap failed\n");
  53                 return -ENOMEM;
  54         }
  55         /* Power down the phy */
  56         __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
  57         phyclk = clk_get(dev, "ocp2scp_usb_phy_ick");
  58
  59         if (IS_ERR(phyclk)) {
  60                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_ick\n");
  61                 iounmap(ctrl_base);
  62                 return PTR_ERR(phyclk);
  63         }
  64
  65         clk48m = clk_get(dev, "ocp2scp_usb_phy_phy_48m");
  66         if (IS_ERR(clk48m)) {
  67                 dev_err(dev, "cannot clk_get ocp2scp_usb_phy_phy_48m\n");
  68                 clk_put(phyclk);
  69                 iounmap(ctrl_base);
  70                 return PTR_ERR(clk48m);
  71         }
  72
  73         clk32k = clk_get(dev, "usb_phy_cm_clk32k");
  74         if (IS_ERR(clk32k)) {
  75                 dev_err(dev, "cannot clk_get usb_phy_cm_clk32k\n");
  76                 clk_put(phyclk);
  77                 clk_put(clk48m);
  78                 iounmap(ctrl_base);
  79                 return PTR_ERR(clk32k);
  80         }
  81         return 0;
  82 }
  83
  84 int omap4430_phy_set_clk(struct device *dev, int on)
  85 {
  86         static int state;
  87
  88         if (on && !state) {
  89                 /* Enable the phy clocks */
  90                 clk_enable(phyclk);
  91                 clk_enable(clk48m);
  92                 clk_enable(clk32k);
  93                 state = 1;
  94         } else if (state) {
  95                 /* Disable the phy clocks */
  96                 clk_disable(phyclk);
  97                 clk_disable(clk48m);
  98                 clk_disable(clk32k);
  99                 state = 0;
 100         }
 101         return 0;
 102 }
 103
 104 int omap4430_phy_power(struct device *dev, int ID, int on)
 105 {
 106         if (on) {
 107                 if (ID)
 108                         /* enable VBUS valid, IDDIG groung */
 109                         __raw_writel(AVALID | VBUSVALID, ctrl_base +
 110                                                         USBOTGHS_CONTROL);
 111                 else
 112                         /*
 113                          * Enable VBUS Valid, AValid and IDDIG
 114                          * high impedence
 115                          */
 116                         __raw_writel(IDDIG | AVALID | VBUSVALID,
 117                                                 ctrl_base + USBOTGHS_CONTROL);
 118         } else {
 119                 /* Enable session END and IDIG to high impedence. */
 120                 __raw_writel(SESSEND | IDDIG, ctrl_base +
 121                                         USBOTGHS_CONTROL);
 122         }
 123         return 0;
 124 }
 125
 126 int omap4430_phy_suspend(struct device *dev, int suspend)
 127 {
 128         if (suspend) {
 129                 /* Disable the clocks */
 130                 omap4430_phy_set_clk(dev, 0);
 131                 /* Power down the phy */
 132                 __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 133
 134                 /* save the context */
 135                 usbotghs_control = __raw_readl(ctrl_base + USBOTGHS_CONTROL);
 136         } else {
 137                 /* Enable the internel phy clcoks */
 138                 omap4430_phy_set_clk(dev, 1);
 139                 /* power on the phy */
 140                 if (__raw_readl(ctrl_base + CONTROL_DEV_CONF) & PHY_PD) {
 141                         __raw_writel(~PHY_PD, ctrl_base + CONTROL_DEV_CONF);
 142                         mdelay(200);
 143                 }
 144
 145                 /* restore the context */
 146                 __raw_writel(usbotghs_control, ctrl_base + USBOTGHS_CONTROL);
 147         }
 148
 149         return 0;
 150 }
 151
 152 int omap4430_phy_exit(struct device *dev)
 153 {
 154         if (ctrl_base)
 155                 iounmap(ctrl_base);
 156         if (phyclk)
 157                 clk_put(phyclk);
 158         if (clk48m)
 159                 clk_put(clk48m);
 160         if (clk32k)
 161                 clk_put(clk32k);
 162
 163         return 0;
 164 }