arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm.h"
  31 #include "prm-regbits-44xx.h"
  32 #include "wd_timer.h"
  33
  34 /* Base offset for all OMAP4 interrupts external to MPUSS */
  35 #define OMAP44XX_IRQ_GIC_START  32
  36
  37 /* Base offset for all OMAP4 dma requests */
  38 #define OMAP44XX_DMA_REQ_START  1
  39
  40 /* Backward references (IPs with Bus Master capability) */
  41 static struct omap_hwmod omap44xx_dma_system_hwmod;
  42 static struct omap_hwmod omap44xx_dmm_hwmod;
  43 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  44 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  45 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  46 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  47 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  48 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  49 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  50 static struct omap_hwmod omap44xx_l4_per_hwmod;
  51 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  52 static struct omap_hwmod omap44xx_mpu_hwmod;
  53 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  54
  55 /*
  56  * Interconnects omap_hwmod structures
  57  * hwmods that compose the global OMAP interconnect
  58  */
  59
  60 /*
  61  * 'dmm' class
  62  * instance(s): dmm
  63  */
  64 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  65         .name = "dmm",
  66 };
  67
  68 /* dmm interface data */
  69 /* l3_main_1 -> dmm */
  70 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  71         .master         = &omap44xx_l3_main_1_hwmod,
  72         .slave          = &omap44xx_dmm_hwmod,
  73         .clk            = "l3_div_ck",
  74         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  75 };
  76
  77 /* mpu -> dmm */
  78 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  79         .master         = &omap44xx_mpu_hwmod,
  80         .slave          = &omap44xx_dmm_hwmod,
  81         .clk            = "l3_div_ck",
  82         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  83 };
  84
  85 /* dmm slave ports */
  86 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
  87         &omap44xx_l3_main_1__dmm,
  88         &omap44xx_mpu__dmm,
  89 };
  90
  91 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  92         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  93 };
  94
  95 static struct omap_hwmod omap44xx_dmm_hwmod = {
  96         .name           = "dmm",
  97         .class          = &omap44xx_dmm_hwmod_class,
  98         .slaves         = omap44xx_dmm_slaves,
  99         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 100         .mpu_irqs       = omap44xx_dmm_irqs,
 101         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 102         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 103 };
 104
 105 /*
 106  * 'emif_fw' class
 107  * instance(s): emif_fw
 108  */
 109 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 110         .name = "emif_fw",
 111 };
 112
 113 /* emif_fw interface data */
 114 /* dmm -> emif_fw */
 115 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 116         .master         = &omap44xx_dmm_hwmod,
 117         .slave          = &omap44xx_emif_fw_hwmod,
 118         .clk            = "l3_div_ck",
 119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 120 };
 121
 122 /* l4_cfg -> emif_fw */
 123 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 124         .master         = &omap44xx_l4_cfg_hwmod,
 125         .slave          = &omap44xx_emif_fw_hwmod,
 126         .clk            = "l4_div_ck",
 127         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 128 };
 129
 130 /* emif_fw slave ports */
 131 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 132         &omap44xx_dmm__emif_fw,
 133         &omap44xx_l4_cfg__emif_fw,
 134 };
 135
 136 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 137         .name           = "emif_fw",
 138         .class          = &omap44xx_emif_fw_hwmod_class,
 139         .slaves         = omap44xx_emif_fw_slaves,
 140         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 141         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 142 };
 143
 144 /*
 145  * 'l3' class
 146  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 147  */
 148 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 149         .name = "l3",
 150 };
 151
 152 /* l3_instr interface data */
 153 /* l3_main_3 -> l3_instr */
 154 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 155         .master         = &omap44xx_l3_main_3_hwmod,
 156         .slave          = &omap44xx_l3_instr_hwmod,
 157         .clk            = "l3_div_ck",
 158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 159 };
 160
 161 /* l3_instr slave ports */
 162 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 163         &omap44xx_l3_main_3__l3_instr,
 164 };
 165
 166 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 167         .name           = "l3_instr",
 168         .class          = &omap44xx_l3_hwmod_class,
 169         .slaves         = omap44xx_l3_instr_slaves,
 170         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 171         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 172 };
 173
 174 /* l3_main_2 -> l3_main_1 */
 175 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 176         .master         = &omap44xx_l3_main_2_hwmod,
 177         .slave          = &omap44xx_l3_main_1_hwmod,
 178         .clk            = "l3_div_ck",
 179         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 180 };
 181
 182 /* l4_cfg -> l3_main_1 */
 183 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 184         .master         = &omap44xx_l4_cfg_hwmod,
 185         .slave          = &omap44xx_l3_main_1_hwmod,
 186         .clk            = "l4_div_ck",
 187         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 188 };
 189
 190 /* mpu -> l3_main_1 */
 191 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 192         .master         = &omap44xx_mpu_hwmod,
 193         .slave          = &omap44xx_l3_main_1_hwmod,
 194         .clk            = "l3_div_ck",
 195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 196 };
 197
 198 /* l3_main_1 slave ports */
 199 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 200         &omap44xx_l3_main_2__l3_main_1,
 201         &omap44xx_l4_cfg__l3_main_1,
 202         &omap44xx_mpu__l3_main_1,
 203 };
 204
 205 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 206         .name           = "l3_main_1",
 207         .class          = &omap44xx_l3_hwmod_class,
 208         .slaves         = omap44xx_l3_main_1_slaves,
 209         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 210         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 211 };
 212
 213 /* l3_main_2 interface data */
 214 /* l3_main_1 -> l3_main_2 */
 215 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 216         .master         = &omap44xx_l3_main_1_hwmod,
 217         .slave          = &omap44xx_l3_main_2_hwmod,
 218         .clk            = "l3_div_ck",
 219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 220 };
 221
 222 /* dma_system -> l3_main_2 */
 223 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 224         .master         = &omap44xx_dma_system_hwmod,
 225         .slave          = &omap44xx_l3_main_2_hwmod,
 226         .clk            = "l3_div_ck",
 227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 228 };
 229
 230 /* l4_cfg -> l3_main_2 */
 231 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 232         .master         = &omap44xx_l4_cfg_hwmod,
 233         .slave          = &omap44xx_l3_main_2_hwmod,
 234         .clk            = "l4_div_ck",
 235         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 236 };
 237
 238 /* l3_main_2 slave ports */
 239 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 240         &omap44xx_dma_system__l3_main_2,
 241         &omap44xx_l3_main_1__l3_main_2,
 242         &omap44xx_l4_cfg__l3_main_2,
 243 };
 244
 245 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 246         .name           = "l3_main_2",
 247         .class          = &omap44xx_l3_hwmod_class,
 248         .slaves         = omap44xx_l3_main_2_slaves,
 249         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 250         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 251 };
 252
 253 /* l3_main_3 interface data */
 254 /* l3_main_1 -> l3_main_3 */
 255 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 256         .master         = &omap44xx_l3_main_1_hwmod,
 257         .slave          = &omap44xx_l3_main_3_hwmod,
 258         .clk            = "l3_div_ck",
 259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 260 };
 261
 262 /* l3_main_2 -> l3_main_3 */
 263 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 264         .master         = &omap44xx_l3_main_2_hwmod,
 265         .slave          = &omap44xx_l3_main_3_hwmod,
 266         .clk            = "l3_div_ck",
 267         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 268 };
 269
 270 /* l4_cfg -> l3_main_3 */
 271 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 272         .master         = &omap44xx_l4_cfg_hwmod,
 273         .slave          = &omap44xx_l3_main_3_hwmod,
 274         .clk            = "l4_div_ck",
 275         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 276 };
 277
 278 /* l3_main_3 slave ports */
 279 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 280         &omap44xx_l3_main_1__l3_main_3,
 281         &omap44xx_l3_main_2__l3_main_3,
 282         &omap44xx_l4_cfg__l3_main_3,
 283 };
 284
 285 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 286         .name           = "l3_main_3",
 287         .class          = &omap44xx_l3_hwmod_class,
 288         .slaves         = omap44xx_l3_main_3_slaves,
 289         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 290         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 291 };
 292
 293 /*
 294  * 'l4' class
 295  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 296  */
 297 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 298         .name = "l4",
 299 };
 300
 301 /* l4_abe interface data */
 302 /* l3_main_1 -> l4_abe */
 303 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 304         .master         = &omap44xx_l3_main_1_hwmod,
 305         .slave          = &omap44xx_l4_abe_hwmod,
 306         .clk            = "l3_div_ck",
 307         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 308 };
 309
 310 /* mpu -> l4_abe */
 311 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 312         .master         = &omap44xx_mpu_hwmod,
 313         .slave          = &omap44xx_l4_abe_hwmod,
 314         .clk            = "ocp_abe_iclk",
 315         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 316 };
 317
 318 /* l4_abe slave ports */
 319 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 320         &omap44xx_l3_main_1__l4_abe,
 321         &omap44xx_mpu__l4_abe,
 322 };
 323
 324 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 325         .name           = "l4_abe",
 326         .class          = &omap44xx_l4_hwmod_class,
 327         .slaves         = omap44xx_l4_abe_slaves,
 328         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 329         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 330 };
 331
 332 /* l4_cfg interface data */
 333 /* l3_main_1 -> l4_cfg */
 334 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 335         .master         = &omap44xx_l3_main_1_hwmod,
 336         .slave          = &omap44xx_l4_cfg_hwmod,
 337         .clk            = "l3_div_ck",
 338         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 339 };
 340
 341 /* l4_cfg slave ports */
 342 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 343         &omap44xx_l3_main_1__l4_cfg,
 344 };
 345
 346 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 347         .name           = "l4_cfg",
 348         .class          = &omap44xx_l4_hwmod_class,
 349         .slaves         = omap44xx_l4_cfg_slaves,
 350         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 351         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 352 };
 353
 354 /* l4_per interface data */
 355 /* l3_main_2 -> l4_per */
 356 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 357         .master         = &omap44xx_l3_main_2_hwmod,
 358         .slave          = &omap44xx_l4_per_hwmod,
 359         .clk            = "l3_div_ck",
 360         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 361 };
 362
 363 /* l4_per slave ports */
 364 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 365         &omap44xx_l3_main_2__l4_per,
 366 };
 367
 368 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 369         .name           = "l4_per",
 370         .class          = &omap44xx_l4_hwmod_class,
 371         .slaves         = omap44xx_l4_per_slaves,
 372         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 373         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 374 };
 375
 376 /* l4_wkup interface data */
 377 /* l4_cfg -> l4_wkup */
 378 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 379         .master         = &omap44xx_l4_cfg_hwmod,
 380         .slave          = &omap44xx_l4_wkup_hwmod,
 381         .clk            = "l4_div_ck",
 382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 383 };
 384
 385 /* l4_wkup slave ports */
 386 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 387         &omap44xx_l4_cfg__l4_wkup,
 388 };
 389
 390 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 391         .name           = "l4_wkup",
 392         .class          = &omap44xx_l4_hwmod_class,
 393         .slaves         = omap44xx_l4_wkup_slaves,
 394         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 395         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 396 };
 397
 398 /*
 399  * 'i2c' class
 400  * multimaster high-speed i2c controller
 401  */
 402
 403 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
 404         .sysc_offs      = 0x0010,
 405         .syss_offs      = 0x0090,
 406         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 407                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
 408                            SYSC_HAS_AUTOIDLE),
 409         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 410         .sysc_fields    = &omap_hwmod_sysc_type1,
 411 };
 412
 413 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
 414         .name = "i2c",
 415         .sysc = &omap44xx_i2c_sysc,
 416 };
 417
 418 /* i2c1 */
 419 static struct omap_hwmod omap44xx_i2c1_hwmod;
 420 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
 421         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
 422 };
 423
 424 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
 425         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
 426         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
 427 };
 428
 429 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
 430         {
 431                 .pa_start       = 0x48070000,
 432                 .pa_end         = 0x480700ff,
 433                 .flags          = ADDR_TYPE_RT
 434         },
 435 };
 436
 437 /* l4_per -> i2c1 */
 438 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
 439         .master         = &omap44xx_l4_per_hwmod,
 440         .slave          = &omap44xx_i2c1_hwmod,
 441         .clk            = "l4_div_ck",
 442         .addr           = omap44xx_i2c1_addrs,
 443         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
 444         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 445 };
 446
 447 /* i2c1 slave ports */
 448 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
 449         &omap44xx_l4_per__i2c1,
 450 };
 451
 452 static struct omap_hwmod omap44xx_i2c1_hwmod = {
 453         .name           = "i2c1",
 454         .class          = &omap44xx_i2c_hwmod_class,
 455         .flags          = HWMOD_INIT_NO_RESET,
 456         .mpu_irqs       = omap44xx_i2c1_irqs,
 457         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
 458         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
 459         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
 460         .main_clk       = "i2c1_fck",
 461         .prcm = {
 462                 .omap4 = {
 463                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
 464                 },
 465         },
 466         .slaves         = omap44xx_i2c1_slaves,
 467         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
 468         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 469 };
 470
 471 /* i2c2 */
 472 static struct omap_hwmod omap44xx_i2c2_hwmod;
 473 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
 474         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
 475 };
 476
 477 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
 478         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
 479         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
 480 };
 481
 482 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
 483         {
 484                 .pa_start       = 0x48072000,
 485                 .pa_end         = 0x480720ff,
 486                 .flags          = ADDR_TYPE_RT
 487         },
 488 };
 489
 490 /* l4_per -> i2c2 */
 491 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
 492         .master         = &omap44xx_l4_per_hwmod,
 493         .slave          = &omap44xx_i2c2_hwmod,
 494         .clk            = "l4_div_ck",
 495         .addr           = omap44xx_i2c2_addrs,
 496         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
 497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 498 };
 499
 500 /* i2c2 slave ports */
 501 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
 502         &omap44xx_l4_per__i2c2,
 503 };
 504
 505 static struct omap_hwmod omap44xx_i2c2_hwmod = {
 506         .name           = "i2c2",
 507         .class          = &omap44xx_i2c_hwmod_class,
 508         .flags          = HWMOD_INIT_NO_RESET,
 509         .mpu_irqs       = omap44xx_i2c2_irqs,
 510         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
 511         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
 512         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
 513         .main_clk       = "i2c2_fck",
 514         .prcm = {
 515                 .omap4 = {
 516                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
 517                 },
 518         },
 519         .slaves         = omap44xx_i2c2_slaves,
 520         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
 521         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 522 };
 523
 524 /* i2c3 */
 525 static struct omap_hwmod omap44xx_i2c3_hwmod;
 526 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
 527         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
 528 };
 529
 530 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
 531         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
 532         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
 533 };
 534
 535 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
 536         {
 537                 .pa_start       = 0x48060000,
 538                 .pa_end         = 0x480600ff,
 539                 .flags          = ADDR_TYPE_RT
 540         },
 541 };
 542
 543 /* l4_per -> i2c3 */
 544 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
 545         .master         = &omap44xx_l4_per_hwmod,
 546         .slave          = &omap44xx_i2c3_hwmod,
 547         .clk            = "l4_div_ck",
 548         .addr           = omap44xx_i2c3_addrs,
 549         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
 550         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 551 };
 552
 553 /* i2c3 slave ports */
 554 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
 555         &omap44xx_l4_per__i2c3,
 556 };
 557
 558 static struct omap_hwmod omap44xx_i2c3_hwmod = {
 559         .name           = "i2c3",
 560         .class          = &omap44xx_i2c_hwmod_class,
 561         .flags          = HWMOD_INIT_NO_RESET,
 562         .mpu_irqs       = omap44xx_i2c3_irqs,
 563         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
 564         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
 565         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
 566         .main_clk       = "i2c3_fck",
 567         .prcm = {
 568                 .omap4 = {
 569                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
 570                 },
 571         },
 572         .slaves         = omap44xx_i2c3_slaves,
 573         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
 574         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 575 };
 576
 577 /* i2c4 */
 578 static struct omap_hwmod omap44xx_i2c4_hwmod;
 579 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
 580         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
 581 };
 582
 583 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
 584         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
 585         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
 586 };
 587
 588 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
 589         {
 590                 .pa_start       = 0x48350000,
 591                 .pa_end         = 0x483500ff,
 592                 .flags          = ADDR_TYPE_RT
 593         },
 594 };
 595
 596 /* l4_per -> i2c4 */
 597 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
 598         .master         = &omap44xx_l4_per_hwmod,
 599         .slave          = &omap44xx_i2c4_hwmod,
 600         .clk            = "l4_div_ck",
 601         .addr           = omap44xx_i2c4_addrs,
 602         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
 603         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 604 };
 605
 606 /* i2c4 slave ports */
 607 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
 608         &omap44xx_l4_per__i2c4,
 609 };
 610
 611 static struct omap_hwmod omap44xx_i2c4_hwmod = {
 612         .name           = "i2c4",
 613         .class          = &omap44xx_i2c_hwmod_class,
 614         .flags          = HWMOD_INIT_NO_RESET,
 615         .mpu_irqs       = omap44xx_i2c4_irqs,
 616         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
 617         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
 618         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
 619         .main_clk       = "i2c4_fck",
 620         .prcm = {
 621                 .omap4 = {
 622                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
 623                 },
 624         },
 625         .slaves         = omap44xx_i2c4_slaves,
 626         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
 627         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 628 };
 629
 630 /*
 631  * 'mpu_bus' class
 632  * instance(s): mpu_private
 633  */
 634 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 635         .name = "mpu_bus",
 636 };
 637
 638 /* mpu_private interface data */
 639 /* mpu -> mpu_private */
 640 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 641         .master         = &omap44xx_mpu_hwmod,
 642         .slave          = &omap44xx_mpu_private_hwmod,
 643         .clk            = "l3_div_ck",
 644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 645 };
 646
 647 /* mpu_private slave ports */
 648 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 649         &omap44xx_mpu__mpu_private,
 650 };
 651
 652 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 653         .name           = "mpu_private",
 654         .class          = &omap44xx_mpu_bus_hwmod_class,
 655         .slaves         = omap44xx_mpu_private_slaves,
 656         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 658 };
 659
 660 /*
 661  * 'mpu' class
 662  * mpu sub-system
 663  */
 664
 665 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 666         .name = "mpu",
 667 };
 668
 669 /* mpu */
 670 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
 671         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
 672         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
 673         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
 674 };
 675
 676 /* mpu master ports */
 677 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
 678         &omap44xx_mpu__l3_main_1,
 679         &omap44xx_mpu__l4_abe,
 680         &omap44xx_mpu__dmm,
 681 };
 682
 683 static struct omap_hwmod omap44xx_mpu_hwmod = {
 684         .name           = "mpu",
 685         .class          = &omap44xx_mpu_hwmod_class,
 686         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 687         .mpu_irqs       = omap44xx_mpu_irqs,
 688         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
 689         .main_clk       = "dpll_mpu_m2_ck",
 690         .prcm = {
 691                 .omap4 = {
 692                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
 693                 },
 694         },
 695         .masters        = omap44xx_mpu_masters,
 696         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
 697         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 698 };
 699
 700 /*
 701  * 'wd_timer' class
 702  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 703  * overflow condition
 704  */
 705
 706 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
 707         .rev_offs       = 0x0000,
 708         .sysc_offs      = 0x0010,
 709         .syss_offs      = 0x0014,
 710         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 711                            SYSC_HAS_SOFTRESET),
 712         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 713         .sysc_fields    = &omap_hwmod_sysc_type1,
 714 };
 715
 716 /*
 717  * 'uart' class
 718  * universal asynchronous receiver/transmitter (uart)
 719  */
 720
 721 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
 722         .rev_offs       = 0x0050,
 723         .sysc_offs      = 0x0054,
 724         .syss_offs      = 0x0058,
 725         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 726                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 727         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 728         .sysc_fields    = &omap_hwmod_sysc_type1,
 729 };
 730
 731 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 732         .name           = "wd_timer",
 733         .sysc           = &omap44xx_wd_timer_sysc,
 734         .pre_shutdown   = &omap2_wd_timer_disable
 735 };
 736
 737 /* wd_timer2 */
 738 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 739 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
 740         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
 741 };
 742
 743 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
 744         {
 745                 .pa_start       = 0x4a314000,
 746                 .pa_end         = 0x4a31407f,
 747                 .flags          = ADDR_TYPE_RT
 748         },
 749 };
 750
 751 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 752         .name = "uart",
 753         .sysc = &omap44xx_uart_sysc,
 754 };
 755
 756 /* uart1 */
 757 static struct omap_hwmod omap44xx_uart1_hwmod;
 758 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
 759         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
 760 };
 761
 762 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
 763         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
 764         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
 765 };
 766
 767 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
 768         {
 769                 .pa_start       = 0x4806a000,
 770                 .pa_end         = 0x4806a0ff,
 771                 .flags          = ADDR_TYPE_RT
 772         },
 773 };
 774
 775 /* l4_per -> uart1 */
 776 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
 777         .master         = &omap44xx_l4_per_hwmod,
 778         .slave          = &omap44xx_uart1_hwmod,
 779         .clk            = "l4_div_ck",
 780         .addr           = omap44xx_uart1_addrs,
 781         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
 782         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 783 };
 784
 785 /* uart1 slave ports */
 786 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
 787         &omap44xx_l4_per__uart1,
 788 };
 789
 790 static struct omap_hwmod omap44xx_uart1_hwmod = {
 791         .name           = "uart1",
 792         .class          = &omap44xx_uart_hwmod_class,
 793         .mpu_irqs       = omap44xx_uart1_irqs,
 794         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
 795         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
 796         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
 797         .main_clk       = "uart1_fck",
 798         .prcm = {
 799                 .omap4 = {
 800                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
 801                 },
 802         },
 803         .slaves         = omap44xx_uart1_slaves,
 804         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
 805         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 806 };
 807
 808 /* uart2 */
 809 static struct omap_hwmod omap44xx_uart2_hwmod;
 810 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
 811         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
 812 };
 813
 814 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
 815         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
 816         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
 817 };
 818
 819 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
 820         {
 821                 .pa_start       = 0x4806c000,
 822                 .pa_end         = 0x4806c0ff,
 823                 .flags          = ADDR_TYPE_RT
 824         },
 825 };
 826
 827 /* l4_wkup -> wd_timer2 */
 828 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
 829         .master         = &omap44xx_l4_wkup_hwmod,
 830         .slave          = &omap44xx_wd_timer2_hwmod,
 831         .clk            = "l4_wkup_clk_mux_ck",
 832         .addr           = omap44xx_wd_timer2_addrs,
 833         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
 834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 835 };
 836
 837 /* wd_timer2 slave ports */
 838 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
 839         &omap44xx_l4_wkup__wd_timer2,
 840 };
 841
 842 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 843         .name           = "wd_timer2",
 844         .class          = &omap44xx_wd_timer_hwmod_class,
 845         .mpu_irqs       = omap44xx_wd_timer2_irqs,
 846         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
 847         .main_clk       = "wd_timer2_fck",
 848         .prcm = {
 849                 .omap4 = {
 850                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
 851                 },
 852         },
 853         .slaves         = omap44xx_wd_timer2_slaves,
 854         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
 855         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 856 };
 857
 858 /* wd_timer3 */
 859 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 860 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
 861         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
 862 };
 863
 864 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
 865         {
 866                 .pa_start       = 0x40130000,
 867                 .pa_end         = 0x4013007f,
 868                 .flags          = ADDR_TYPE_RT
 869         },
 870 };
 871
 872 /* l4_per -> uart2 */
 873 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
 874         .master         = &omap44xx_l4_per_hwmod,
 875         .slave          = &omap44xx_uart2_hwmod,
 876         .clk            = "l4_div_ck",
 877         .addr           = omap44xx_uart2_addrs,
 878         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
 879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 880 };
 881
 882 /* uart2 slave ports */
 883 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
 884         &omap44xx_l4_per__uart2,
 885 };
 886
 887 static struct omap_hwmod omap44xx_uart2_hwmod = {
 888         .name           = "uart2",
 889         .class          = &omap44xx_uart_hwmod_class,
 890         .mpu_irqs       = omap44xx_uart2_irqs,
 891         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
 892         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
 893         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
 894         .main_clk       = "uart2_fck",
 895         .prcm = {
 896                 .omap4 = {
 897                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
 898                 },
 899         },
 900         .slaves         = omap44xx_uart2_slaves,
 901         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
 902         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 903 };
 904
 905 /* uart3 */
 906 static struct omap_hwmod omap44xx_uart3_hwmod;
 907 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
 908         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
 909 };
 910
 911 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
 912         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
 913         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
 914 };
 915
 916 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
 917         {
 918                 .pa_start       = 0x48020000,
 919                 .pa_end         = 0x480200ff,
 920                 .flags          = ADDR_TYPE_RT
 921         },
 922 };
 923
 924 /* l4_abe -> wd_timer3 */
 925 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
 926         .master         = &omap44xx_l4_abe_hwmod,
 927         .slave          = &omap44xx_wd_timer3_hwmod,
 928         .clk            = "ocp_abe_iclk",
 929         .addr           = omap44xx_wd_timer3_addrs,
 930         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
 931         .user           = OCP_USER_MPU,
 932 };
 933
 934 /* l4_abe -> wd_timer3 (dma) */
 935 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
 936         {
 937                 .pa_start       = 0x49030000,
 938                 .pa_end         = 0x4903007f,
 939                 .flags          = ADDR_TYPE_RT
 940         },
 941 };
 942
 943 /* l4_per -> uart3 */
 944 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
 945         .master         = &omap44xx_l4_per_hwmod,
 946         .slave          = &omap44xx_uart3_hwmod,
 947         .clk            = "l4_div_ck",
 948         .addr           = omap44xx_uart3_addrs,
 949         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
 950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 951 };
 952
 953 /* uart3 slave ports */
 954 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
 955         &omap44xx_l4_per__uart3,
 956 };
 957
 958 static struct omap_hwmod omap44xx_uart3_hwmod = {
 959         .name           = "uart3",
 960         .class          = &omap44xx_uart_hwmod_class,
 961         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 962         .mpu_irqs       = omap44xx_uart3_irqs,
 963         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
 964         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
 965         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
 966         .main_clk       = "uart3_fck",
 967         .prcm = {
 968                 .omap4 = {
 969                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
 970                 },
 971         },
 972         .slaves         = omap44xx_uart3_slaves,
 973         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
 974         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 975 };
 976
 977 /* uart4 */
 978 static struct omap_hwmod omap44xx_uart4_hwmod;
 979 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
 980         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
 981 };
 982
 983 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
 984         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
 985         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
 986 };
 987
 988 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
 989         {
 990                 .pa_start       = 0x4806e000,
 991                 .pa_end         = 0x4806e0ff,
 992                 .flags          = ADDR_TYPE_RT
 993         },
 994 };
 995
 996 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
 997         .master         = &omap44xx_l4_abe_hwmod,
 998         .slave          = &omap44xx_wd_timer3_hwmod,
 999         .clk            = "ocp_abe_iclk",
1000         .addr           = omap44xx_wd_timer3_dma_addrs,
1001         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1002         .user           = OCP_USER_SDMA,
1003 };
1004
1005 /* wd_timer3 slave ports */
1006 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1007         &omap44xx_l4_abe__wd_timer3,
1008         &omap44xx_l4_abe__wd_timer3_dma,
1009 };
1010
1011 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1012         .name           = "wd_timer3",
1013         .class          = &omap44xx_wd_timer_hwmod_class,
1014         .mpu_irqs       = omap44xx_wd_timer3_irqs,
1015         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1016         .main_clk       = "wd_timer3_fck",
1017         .prcm = {
1018                 .omap4 = {
1019                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1020                 },
1021         },
1022         .slaves         = omap44xx_wd_timer3_slaves,
1023         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1024         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1025 };
1026
1027 /* l4_per -> uart4 */
1028 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1029         .master         = &omap44xx_l4_per_hwmod,
1030         .slave          = &omap44xx_uart4_hwmod,
1031         .clk            = "l4_div_ck",
1032         .addr           = omap44xx_uart4_addrs,
1033         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
1034         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1035 };
1036
1037 /* uart4 slave ports */
1038 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1039         &omap44xx_l4_per__uart4,
1040 };
1041
1042 static struct omap_hwmod omap44xx_uart4_hwmod = {
1043         .name           = "uart4",
1044         .class          = &omap44xx_uart_hwmod_class,
1045         .mpu_irqs       = omap44xx_uart4_irqs,
1046         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
1047         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
1048         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1049         .main_clk       = "uart4_fck",
1050         .prcm = {
1051                 .omap4 = {
1052                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1053                 },
1054         },
1055         .slaves         = omap44xx_uart4_slaves,
1056         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
1057         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1058 };
1059
1060 /*
1061  * 'gpio' class
1062  * general purpose io module
1063  */
1064
1065 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1066         .rev_offs       = 0x0000,
1067         .sysc_offs      = 0x0010,
1068         .syss_offs      = 0x0114,
1069         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1070                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1071         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1072         .sysc_fields    = &omap_hwmod_sysc_type1,
1073 };
1074
1075 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1076         .name = "gpio",
1077         .sysc = &omap44xx_gpio_sysc,
1078         .rev = 2,
1079 };
1080
1081 /* gpio dev_attr */
1082 static struct omap_gpio_dev_attr gpio_dev_attr = {
1083         .bank_width = 32,
1084         .dbck_flag = true,
1085 };
1086
1087 /* gpio1 */
1088 static struct omap_hwmod omap44xx_gpio1_hwmod;
1089 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1090         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1091 };
1092
1093 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1094         {
1095                 .pa_start       = 0x4a310000,
1096                 .pa_end         = 0x4a3101ff,
1097                 .flags          = ADDR_TYPE_RT
1098         },
1099 };
1100
1101 /* l4_wkup -> gpio1 */
1102 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1103         .master         = &omap44xx_l4_wkup_hwmod,
1104         .slave          = &omap44xx_gpio1_hwmod,
1105         .addr           = omap44xx_gpio1_addrs,
1106         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1107         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1108 };
1109
1110 /* gpio1 slave ports */
1111 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1112         &omap44xx_l4_wkup__gpio1,
1113 };
1114
1115 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1116         { .role = "dbclk", .clk = "sys_32k_ck" },
1117 };
1118
1119 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1120         .name           = "gpio1",
1121         .class          = &omap44xx_gpio_hwmod_class,
1122         .mpu_irqs       = omap44xx_gpio1_irqs,
1123         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1124         .main_clk       = "gpio1_ick",
1125         .prcm = {
1126                 .omap4 = {
1127                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1128                 },
1129         },
1130         .opt_clks       = gpio1_opt_clks,
1131         .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1132         .dev_attr       = &gpio_dev_attr,
1133         .slaves         = omap44xx_gpio1_slaves,
1134         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1135         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1136 };
1137
1138 /* gpio2 */
1139 static struct omap_hwmod omap44xx_gpio2_hwmod;
1140 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1141         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1142 };
1143
1144 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1145         {
1146                 .pa_start       = 0x48055000,
1147                 .pa_end         = 0x480551ff,
1148                 .flags          = ADDR_TYPE_RT
1149         },
1150 };
1151
1152 /* l4_per -> gpio2 */
1153 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1154         .master         = &omap44xx_l4_per_hwmod,
1155         .slave          = &omap44xx_gpio2_hwmod,
1156         .addr           = omap44xx_gpio2_addrs,
1157         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1159 };
1160
1161 /* gpio2 slave ports */
1162 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1163         &omap44xx_l4_per__gpio2,
1164 };
1165
1166 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1167         { .role = "dbclk", .clk = "sys_32k_ck" },
1168 };
1169
1170 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1171         .name           = "gpio2",
1172         .class          = &omap44xx_gpio_hwmod_class,
1173         .mpu_irqs       = omap44xx_gpio2_irqs,
1174         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1175         .main_clk       = "gpio2_ick",
1176         .prcm = {
1177                 .omap4 = {
1178                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1179                 },
1180         },
1181         .opt_clks       = gpio2_opt_clks,
1182         .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1183         .dev_attr       = &gpio_dev_attr,
1184         .slaves         = omap44xx_gpio2_slaves,
1185         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1186         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1187 };
1188
1189 /* gpio3 */
1190 static struct omap_hwmod omap44xx_gpio3_hwmod;
1191 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1192         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1193 };
1194
1195 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1196         {
1197                 .pa_start       = 0x48057000,
1198                 .pa_end         = 0x480571ff,
1199                 .flags          = ADDR_TYPE_RT
1200         },
1201 };
1202
1203 /* l4_per -> gpio3 */
1204 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1205         .master         = &omap44xx_l4_per_hwmod,
1206         .slave          = &omap44xx_gpio3_hwmod,
1207         .addr           = omap44xx_gpio3_addrs,
1208         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1209         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1210 };
1211
1212 /* gpio3 slave ports */
1213 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1214         &omap44xx_l4_per__gpio3,
1215 };
1216
1217 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1218         { .role = "dbclk", .clk = "sys_32k_ck" },
1219 };
1220
1221 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1222         .name           = "gpio3",
1223         .class          = &omap44xx_gpio_hwmod_class,
1224         .mpu_irqs       = omap44xx_gpio3_irqs,
1225         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1226         .main_clk       = "gpio3_ick",
1227         .prcm = {
1228                 .omap4 = {
1229                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1230                 },
1231         },
1232         .opt_clks       = gpio3_opt_clks,
1233         .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1234         .dev_attr       = &gpio_dev_attr,
1235         .slaves         = omap44xx_gpio3_slaves,
1236         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1237         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1238 };
1239
1240 /* gpio4 */
1241 static struct omap_hwmod omap44xx_gpio4_hwmod;
1242 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1243         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1244 };
1245
1246 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1247         {
1248                 .pa_start       = 0x48059000,
1249                 .pa_end         = 0x480591ff,
1250                 .flags          = ADDR_TYPE_RT
1251         },
1252 };
1253
1254 /* l4_per -> gpio4 */
1255 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1256         .master         = &omap44xx_l4_per_hwmod,
1257         .slave          = &omap44xx_gpio4_hwmod,
1258         .addr           = omap44xx_gpio4_addrs,
1259         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1260         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1261 };
1262
1263 /* gpio4 slave ports */
1264 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1265         &omap44xx_l4_per__gpio4,
1266 };
1267
1268 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1269         { .role = "dbclk", .clk = "sys_32k_ck" },
1270 };
1271
1272 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1273         .name           = "gpio4",
1274         .class          = &omap44xx_gpio_hwmod_class,
1275         .mpu_irqs       = omap44xx_gpio4_irqs,
1276         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1277         .main_clk       = "gpio4_ick",
1278         .prcm = {
1279                 .omap4 = {
1280                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1281                 },
1282         },
1283         .opt_clks       = gpio4_opt_clks,
1284         .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1285         .dev_attr       = &gpio_dev_attr,
1286         .slaves         = omap44xx_gpio4_slaves,
1287         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1288         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1289 };
1290
1291 /* gpio5 */
1292 static struct omap_hwmod omap44xx_gpio5_hwmod;
1293 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1294         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1295 };
1296
1297 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1298         {
1299                 .pa_start       = 0x4805b000,
1300                 .pa_end         = 0x4805b1ff,
1301                 .flags          = ADDR_TYPE_RT
1302         },
1303 };
1304
1305 /* l4_per -> gpio5 */
1306 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1307         .master         = &omap44xx_l4_per_hwmod,
1308         .slave          = &omap44xx_gpio5_hwmod,
1309         .addr           = omap44xx_gpio5_addrs,
1310         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1312 };
1313
1314 /* gpio5 slave ports */
1315 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1316         &omap44xx_l4_per__gpio5,
1317 };
1318
1319 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1320         { .role = "dbclk", .clk = "sys_32k_ck" },
1321 };
1322
1323 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1324         .name           = "gpio5",
1325         .class          = &omap44xx_gpio_hwmod_class,
1326         .mpu_irqs       = omap44xx_gpio5_irqs,
1327         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1328         .main_clk       = "gpio5_ick",
1329         .prcm = {
1330                 .omap4 = {
1331                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1332                 },
1333         },
1334         .opt_clks       = gpio5_opt_clks,
1335         .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1336         .dev_attr       = &gpio_dev_attr,
1337         .slaves         = omap44xx_gpio5_slaves,
1338         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1340 };
1341
1342 /* gpio6 */
1343 static struct omap_hwmod omap44xx_gpio6_hwmod;
1344 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1345         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1346 };
1347
1348 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1349         {
1350                 .pa_start       = 0x4805d000,
1351                 .pa_end         = 0x4805d1ff,
1352                 .flags          = ADDR_TYPE_RT
1353         },
1354 };
1355
1356 /* l4_per -> gpio6 */
1357 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1358         .master         = &omap44xx_l4_per_hwmod,
1359         .slave          = &omap44xx_gpio6_hwmod,
1360         .addr           = omap44xx_gpio6_addrs,
1361         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1362         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1363 };
1364
1365 /* gpio6 slave ports */
1366 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1367         &omap44xx_l4_per__gpio6,
1368 };
1369
1370 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1371         { .role = "dbclk", .clk = "sys_32k_ck" },
1372 };
1373
1374 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1375         .name           = "gpio6",
1376         .class          = &omap44xx_gpio_hwmod_class,
1377         .mpu_irqs       = omap44xx_gpio6_irqs,
1378         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1379         .main_clk       = "gpio6_ick",
1380         .prcm = {
1381                 .omap4 = {
1382                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1383                 },
1384         },
1385         .opt_clks       = gpio6_opt_clks,
1386         .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1387         .dev_attr       = &gpio_dev_attr,
1388         .slaves         = omap44xx_gpio6_slaves,
1389         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1390         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1391 };
1392
1393 /*
1394  * 'dma' class
1395  * dma controller for data exchange between memory to memory (i.e. internal or
1396  * external memory) and gp peripherals to memory or memory to gp peripherals
1397  */
1398
1399 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1400         .rev_offs       = 0x0000,
1401         .sysc_offs      = 0x002c,
1402         .syss_offs      = 0x0028,
1403         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1404                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1405                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1406                            SYSS_HAS_RESET_STATUS),
1407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1409         .sysc_fields    = &omap_hwmod_sysc_type1,
1410 };
1411
1412 /* dma attributes */
1413 static struct omap_dma_dev_attr dma_dev_attr = {
1414         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1415                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1416         .lch_count = 32,
1417 };
1418
1419 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1420         .name   = "dma",
1421         .sysc   = &omap44xx_dma_sysc,
1422 };
1423
1424 /* dma_system */
1425 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1426         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1427         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1428         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1429         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1430 };
1431
1432 /* dma_system master ports */
1433 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1434         &omap44xx_dma_system__l3_main_2,
1435 };
1436
1437 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1438         {
1439                 .pa_start       = 0x4a056000,
1440                 .pa_end         = 0x4a0560ff,
1441                 .flags          = ADDR_TYPE_RT
1442         },
1443 };
1444
1445 /* l4_cfg -> dma_system */
1446 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1447         .master         = &omap44xx_l4_cfg_hwmod,
1448         .slave          = &omap44xx_dma_system_hwmod,
1449         .clk            = "l4_div_ck",
1450         .addr           = omap44xx_dma_system_addrs,
1451         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
1452         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1453 };
1454
1455 /* dma_system slave ports */
1456 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1457         &omap44xx_l4_cfg__dma_system,
1458 };
1459
1460 static struct omap_hwmod omap44xx_dma_system_hwmod = {
1461         .name           = "dma_system",
1462         .class          = &omap44xx_dma_hwmod_class,
1463         .mpu_irqs       = omap44xx_dma_system_irqs,
1464         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
1465         .main_clk       = "l3_div_ck",
1466         .prcm = {
1467                 .omap4 = {
1468                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1469                 },
1470         },
1471         .slaves         = omap44xx_dma_system_slaves,
1472         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1473         .masters        = omap44xx_dma_system_masters,
1474         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1475         .dev_attr       = &dma_dev_attr,
1476         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1477 };
1478
1479 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1480         /* dmm class */
1481         &omap44xx_dmm_hwmod,
1482         /* emif_fw class */
1483         &omap44xx_emif_fw_hwmod,
1484         /* l3 class */
1485         &omap44xx_l3_instr_hwmod,
1486         &omap44xx_l3_main_1_hwmod,
1487         &omap44xx_l3_main_2_hwmod,
1488         &omap44xx_l3_main_3_hwmod,
1489         /* l4 class */
1490         &omap44xx_l4_abe_hwmod,
1491         &omap44xx_l4_cfg_hwmod,
1492         &omap44xx_l4_per_hwmod,
1493         &omap44xx_l4_wkup_hwmod,
1494
1495         /* dma class */
1496         &omap44xx_dma_system_hwmod,
1497
1498         /* i2c class */
1499         &omap44xx_i2c1_hwmod,
1500         &omap44xx_i2c2_hwmod,
1501         &omap44xx_i2c3_hwmod,
1502         &omap44xx_i2c4_hwmod,
1503         /* mpu_bus class */
1504         &omap44xx_mpu_private_hwmod,
1505
1506         /* gpio class */
1507         &omap44xx_gpio1_hwmod,
1508         &omap44xx_gpio2_hwmod,
1509         &omap44xx_gpio3_hwmod,
1510         &omap44xx_gpio4_hwmod,
1511         &omap44xx_gpio5_hwmod,
1512         &omap44xx_gpio6_hwmod,
1513
1514         /* mpu class */
1515         &omap44xx_mpu_hwmod,
1516         /* wd_timer class */
1517         &omap44xx_wd_timer2_hwmod,
1518         &omap44xx_wd_timer3_hwmod,
1519
1520         /* uart class */
1521         &omap44xx_uart1_hwmod,
1522         &omap44xx_uart2_hwmod,
1523         &omap44xx_uart3_hwmod,
1524         &omap44xx_uart4_hwmod,
1525         NULL,
1526 };
1527
1528 int __init omap44xx_hwmod_init(void)
1529 {
1530         return omap_hwmod_init(omap44xx_hwmods);
1531 }
1532