arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26
  27 #include "omap_hwmod_common_data.h"
  28
  29 #include "cm.h"
  30 #include "prm-regbits-44xx.h"
  31
  32 /* Base offset for all OMAP4 interrupts external to MPUSS */
  33 #define OMAP44XX_IRQ_GIC_START  32
  34
  35 /* Base offset for all OMAP4 dma requests */
  36 #define OMAP44XX_DMA_REQ_START  1
  37
  38 /* Backward references (IPs with Bus Master capability) */
  39 static struct omap_hwmod omap44xx_dmm_hwmod;
  40 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  41 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  42 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  43 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  44 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  45 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  46 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  47 static struct omap_hwmod omap44xx_l4_per_hwmod;
  48 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  49 static struct omap_hwmod omap44xx_mpu_hwmod;
  50 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  51
  52 /*
  53  * Interconnects omap_hwmod structures
  54  * hwmods that compose the global OMAP interconnect
  55  */
  56
  57 /*
  58  * 'dmm' class
  59  * instance(s): dmm
  60  */
  61 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  62         .name = "dmm",
  63 };
  64
  65 /* dmm interface data */
  66 /* l3_main_1 -> dmm */
  67 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  68         .master         = &omap44xx_l3_main_1_hwmod,
  69         .slave          = &omap44xx_dmm_hwmod,
  70         .clk            = "l3_div_ck",
  71         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  72 };
  73
  74 /* mpu -> dmm */
  75 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  76         .master         = &omap44xx_mpu_hwmod,
  77         .slave          = &omap44xx_dmm_hwmod,
  78         .clk            = "l3_div_ck",
  79         .user           = OCP_USER_MPU | OCP_USER_SDMA,
  80 };
  81
  82 /* dmm slave ports */
  83 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
  84         &omap44xx_l3_main_1__dmm,
  85         &omap44xx_mpu__dmm,
  86 };
  87
  88 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  89         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  90 };
  91
  92 static struct omap_hwmod omap44xx_dmm_hwmod = {
  93         .name           = "dmm",
  94         .class          = &omap44xx_dmm_hwmod_class,
  95         .slaves         = omap44xx_dmm_slaves,
  96         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
  97         .mpu_irqs       = omap44xx_dmm_irqs,
  98         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
  99         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 100 };
 101
 102 /*
 103  * 'emif_fw' class
 104  * instance(s): emif_fw
 105  */
 106 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 107         .name = "emif_fw",
 108 };
 109
 110 /* emif_fw interface data */
 111 /* dmm -> emif_fw */
 112 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 113         .master         = &omap44xx_dmm_hwmod,
 114         .slave          = &omap44xx_emif_fw_hwmod,
 115         .clk            = "l3_div_ck",
 116         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 117 };
 118
 119 /* l4_cfg -> emif_fw */
 120 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 121         .master         = &omap44xx_l4_cfg_hwmod,
 122         .slave          = &omap44xx_emif_fw_hwmod,
 123         .clk            = "l4_div_ck",
 124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 125 };
 126
 127 /* emif_fw slave ports */
 128 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 129         &omap44xx_dmm__emif_fw,
 130         &omap44xx_l4_cfg__emif_fw,
 131 };
 132
 133 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 134         .name           = "emif_fw",
 135         .class          = &omap44xx_emif_fw_hwmod_class,
 136         .slaves         = omap44xx_emif_fw_slaves,
 137         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 138         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 139 };
 140
 141 /*
 142  * 'l3' class
 143  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 144  */
 145 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 146         .name = "l3",
 147 };
 148
 149 /* l3_instr interface data */
 150 /* l3_main_3 -> l3_instr */
 151 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 152         .master         = &omap44xx_l3_main_3_hwmod,
 153         .slave          = &omap44xx_l3_instr_hwmod,
 154         .clk            = "l3_div_ck",
 155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 /* l3_instr slave ports */
 159 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 160         &omap44xx_l3_main_3__l3_instr,
 161 };
 162
 163 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 164         .name           = "l3_instr",
 165         .class          = &omap44xx_l3_hwmod_class,
 166         .slaves         = omap44xx_l3_instr_slaves,
 167         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 168         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 169 };
 170
 171 /* l3_main_2 -> l3_main_1 */
 172 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 173         .master         = &omap44xx_l3_main_2_hwmod,
 174         .slave          = &omap44xx_l3_main_1_hwmod,
 175         .clk            = "l3_div_ck",
 176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 177 };
 178
 179 /* l4_cfg -> l3_main_1 */
 180 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 181         .master         = &omap44xx_l4_cfg_hwmod,
 182         .slave          = &omap44xx_l3_main_1_hwmod,
 183         .clk            = "l4_div_ck",
 184         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 185 };
 186
 187 /* mpu -> l3_main_1 */
 188 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 189         .master         = &omap44xx_mpu_hwmod,
 190         .slave          = &omap44xx_l3_main_1_hwmod,
 191         .clk            = "l3_div_ck",
 192         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 193 };
 194
 195 /* l3_main_1 slave ports */
 196 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 197         &omap44xx_l3_main_2__l3_main_1,
 198         &omap44xx_l4_cfg__l3_main_1,
 199         &omap44xx_mpu__l3_main_1,
 200 };
 201
 202 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 203         .name           = "l3_main_1",
 204         .class          = &omap44xx_l3_hwmod_class,
 205         .slaves         = omap44xx_l3_main_1_slaves,
 206         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 207         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 208 };
 209
 210 /* l3_main_2 interface data */
 211 /* l3_main_1 -> l3_main_2 */
 212 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 213         .master         = &omap44xx_l3_main_1_hwmod,
 214         .slave          = &omap44xx_l3_main_2_hwmod,
 215         .clk            = "l3_div_ck",
 216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 217 };
 218
 219 /* l4_cfg -> l3_main_2 */
 220 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 221         .master         = &omap44xx_l4_cfg_hwmod,
 222         .slave          = &omap44xx_l3_main_2_hwmod,
 223         .clk            = "l4_div_ck",
 224         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 225 };
 226
 227 /* l3_main_2 slave ports */
 228 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 229         &omap44xx_l3_main_1__l3_main_2,
 230         &omap44xx_l4_cfg__l3_main_2,
 231 };
 232
 233 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 234         .name           = "l3_main_2",
 235         .class          = &omap44xx_l3_hwmod_class,
 236         .slaves         = omap44xx_l3_main_2_slaves,
 237         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 238         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 239 };
 240
 241 /* l3_main_3 interface data */
 242 /* l3_main_1 -> l3_main_3 */
 243 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 244         .master         = &omap44xx_l3_main_1_hwmod,
 245         .slave          = &omap44xx_l3_main_3_hwmod,
 246         .clk            = "l3_div_ck",
 247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 248 };
 249
 250 /* l3_main_2 -> l3_main_3 */
 251 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 252         .master         = &omap44xx_l3_main_2_hwmod,
 253         .slave          = &omap44xx_l3_main_3_hwmod,
 254         .clk            = "l3_div_ck",
 255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 256 };
 257
 258 /* l4_cfg -> l3_main_3 */
 259 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 260         .master         = &omap44xx_l4_cfg_hwmod,
 261         .slave          = &omap44xx_l3_main_3_hwmod,
 262         .clk            = "l4_div_ck",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* l3_main_3 slave ports */
 267 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 268         &omap44xx_l3_main_1__l3_main_3,
 269         &omap44xx_l3_main_2__l3_main_3,
 270         &omap44xx_l4_cfg__l3_main_3,
 271 };
 272
 273 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 274         .name           = "l3_main_3",
 275         .class          = &omap44xx_l3_hwmod_class,
 276         .slaves         = omap44xx_l3_main_3_slaves,
 277         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 278         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 279 };
 280
 281 /*
 282  * 'l4' class
 283  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 284  */
 285 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 286         .name = "l4",
 287 };
 288
 289 /* l4_abe interface data */
 290 /* l3_main_1 -> l4_abe */
 291 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 292         .master         = &omap44xx_l3_main_1_hwmod,
 293         .slave          = &omap44xx_l4_abe_hwmod,
 294         .clk            = "l3_div_ck",
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 /* mpu -> l4_abe */
 299 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 300         .master         = &omap44xx_mpu_hwmod,
 301         .slave          = &omap44xx_l4_abe_hwmod,
 302         .clk            = "ocp_abe_iclk",
 303         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 304 };
 305
 306 /* l4_abe slave ports */
 307 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 308         &omap44xx_l3_main_1__l4_abe,
 309         &omap44xx_mpu__l4_abe,
 310 };
 311
 312 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 313         .name           = "l4_abe",
 314         .class          = &omap44xx_l4_hwmod_class,
 315         .slaves         = omap44xx_l4_abe_slaves,
 316         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 317         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 318 };
 319
 320 /* l4_cfg interface data */
 321 /* l3_main_1 -> l4_cfg */
 322 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 323         .master         = &omap44xx_l3_main_1_hwmod,
 324         .slave          = &omap44xx_l4_cfg_hwmod,
 325         .clk            = "l3_div_ck",
 326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 327 };
 328
 329 /* l4_cfg slave ports */
 330 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 331         &omap44xx_l3_main_1__l4_cfg,
 332 };
 333
 334 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 335         .name           = "l4_cfg",
 336         .class          = &omap44xx_l4_hwmod_class,
 337         .slaves         = omap44xx_l4_cfg_slaves,
 338         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 339         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 340 };
 341
 342 /* l4_per interface data */
 343 /* l3_main_2 -> l4_per */
 344 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 345         .master         = &omap44xx_l3_main_2_hwmod,
 346         .slave          = &omap44xx_l4_per_hwmod,
 347         .clk            = "l3_div_ck",
 348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 349 };
 350
 351 /* l4_per slave ports */
 352 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 353         &omap44xx_l3_main_2__l4_per,
 354 };
 355
 356 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 357         .name           = "l4_per",
 358         .class          = &omap44xx_l4_hwmod_class,
 359         .slaves         = omap44xx_l4_per_slaves,
 360         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 361         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 362 };
 363
 364 /* l4_wkup interface data */
 365 /* l4_cfg -> l4_wkup */
 366 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 367         .master         = &omap44xx_l4_cfg_hwmod,
 368         .slave          = &omap44xx_l4_wkup_hwmod,
 369         .clk            = "l4_div_ck",
 370         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 371 };
 372
 373 /* l4_wkup slave ports */
 374 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 375         &omap44xx_l4_cfg__l4_wkup,
 376 };
 377
 378 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 379         .name           = "l4_wkup",
 380         .class          = &omap44xx_l4_hwmod_class,
 381         .slaves         = omap44xx_l4_wkup_slaves,
 382         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 383         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 384 };
 385
 386 /*
 387  * 'i2c' class
 388  * multimaster high-speed i2c controller
 389  */
 390
 391 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
 392         .sysc_offs      = 0x0010,
 393         .syss_offs      = 0x0090,
 394         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 395                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET |
 396                            SYSC_HAS_AUTOIDLE),
 397         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 398         .sysc_fields    = &omap_hwmod_sysc_type1,
 399 };
 400
 401 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
 402         .name = "i2c",
 403         .sysc = &omap44xx_i2c_sysc,
 404 };
 405
 406 /* i2c1 */
 407 static struct omap_hwmod omap44xx_i2c1_hwmod;
 408 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
 409         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
 410 };
 411
 412 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
 413         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
 414         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
 415 };
 416
 417 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
 418         {
 419                 .pa_start       = 0x48070000,
 420                 .pa_end         = 0x480700ff,
 421                 .flags          = ADDR_TYPE_RT
 422         },
 423 };
 424
 425 /* l4_per -> i2c1 */
 426 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
 427         .master         = &omap44xx_l4_per_hwmod,
 428         .slave          = &omap44xx_i2c1_hwmod,
 429         .clk            = "l4_div_ck",
 430         .addr           = omap44xx_i2c1_addrs,
 431         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
 432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 433 };
 434
 435 /* i2c1 slave ports */
 436 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
 437         &omap44xx_l4_per__i2c1,
 438 };
 439
 440 static struct omap_hwmod omap44xx_i2c1_hwmod = {
 441         .name           = "i2c1",
 442         .class          = &omap44xx_i2c_hwmod_class,
 443         .flags          = HWMOD_INIT_NO_RESET,
 444         .mpu_irqs       = omap44xx_i2c1_irqs,
 445         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
 446         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
 447         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
 448         .main_clk       = "i2c1_fck",
 449         .prcm = {
 450                 .omap4 = {
 451                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
 452                 },
 453         },
 454         .slaves         = omap44xx_i2c1_slaves,
 455         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
 456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 457 };
 458
 459 /* i2c2 */
 460 static struct omap_hwmod omap44xx_i2c2_hwmod;
 461 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
 462         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
 463 };
 464
 465 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
 466         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
 467         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
 468 };
 469
 470 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
 471         {
 472                 .pa_start       = 0x48072000,
 473                 .pa_end         = 0x480720ff,
 474                 .flags          = ADDR_TYPE_RT
 475         },
 476 };
 477
 478 /* l4_per -> i2c2 */
 479 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
 480         .master         = &omap44xx_l4_per_hwmod,
 481         .slave          = &omap44xx_i2c2_hwmod,
 482         .clk            = "l4_div_ck",
 483         .addr           = omap44xx_i2c2_addrs,
 484         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
 485         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 486 };
 487
 488 /* i2c2 slave ports */
 489 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
 490         &omap44xx_l4_per__i2c2,
 491 };
 492
 493 static struct omap_hwmod omap44xx_i2c2_hwmod = {
 494         .name           = "i2c2",
 495         .class          = &omap44xx_i2c_hwmod_class,
 496         .flags          = HWMOD_INIT_NO_RESET,
 497         .mpu_irqs       = omap44xx_i2c2_irqs,
 498         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
 499         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
 500         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
 501         .main_clk       = "i2c2_fck",
 502         .prcm = {
 503                 .omap4 = {
 504                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
 505                 },
 506         },
 507         .slaves         = omap44xx_i2c2_slaves,
 508         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
 509         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 510 };
 511
 512 /* i2c3 */
 513 static struct omap_hwmod omap44xx_i2c3_hwmod;
 514 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
 515         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
 516 };
 517
 518 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
 519         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
 520         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
 521 };
 522
 523 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
 524         {
 525                 .pa_start       = 0x48060000,
 526                 .pa_end         = 0x480600ff,
 527                 .flags          = ADDR_TYPE_RT
 528         },
 529 };
 530
 531 /* l4_per -> i2c3 */
 532 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
 533         .master         = &omap44xx_l4_per_hwmod,
 534         .slave          = &omap44xx_i2c3_hwmod,
 535         .clk            = "l4_div_ck",
 536         .addr           = omap44xx_i2c3_addrs,
 537         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
 538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 539 };
 540
 541 /* i2c3 slave ports */
 542 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
 543         &omap44xx_l4_per__i2c3,
 544 };
 545
 546 static struct omap_hwmod omap44xx_i2c3_hwmod = {
 547         .name           = "i2c3",
 548         .class          = &omap44xx_i2c_hwmod_class,
 549         .flags          = HWMOD_INIT_NO_RESET,
 550         .mpu_irqs       = omap44xx_i2c3_irqs,
 551         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
 552         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
 553         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
 554         .main_clk       = "i2c3_fck",
 555         .prcm = {
 556                 .omap4 = {
 557                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
 558                 },
 559         },
 560         .slaves         = omap44xx_i2c3_slaves,
 561         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
 562         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 563 };
 564
 565 /* i2c4 */
 566 static struct omap_hwmod omap44xx_i2c4_hwmod;
 567 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
 568         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
 569 };
 570
 571 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
 572         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
 573         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
 574 };
 575
 576 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
 577         {
 578                 .pa_start       = 0x48350000,
 579                 .pa_end         = 0x483500ff,
 580                 .flags          = ADDR_TYPE_RT
 581         },
 582 };
 583
 584 /* l4_per -> i2c4 */
 585 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
 586         .master         = &omap44xx_l4_per_hwmod,
 587         .slave          = &omap44xx_i2c4_hwmod,
 588         .clk            = "l4_div_ck",
 589         .addr           = omap44xx_i2c4_addrs,
 590         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
 591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 592 };
 593
 594 /* i2c4 slave ports */
 595 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
 596         &omap44xx_l4_per__i2c4,
 597 };
 598
 599 static struct omap_hwmod omap44xx_i2c4_hwmod = {
 600         .name           = "i2c4",
 601         .class          = &omap44xx_i2c_hwmod_class,
 602         .flags          = HWMOD_INIT_NO_RESET,
 603         .mpu_irqs       = omap44xx_i2c4_irqs,
 604         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
 605         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
 606         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
 607         .main_clk       = "i2c4_fck",
 608         .prcm = {
 609                 .omap4 = {
 610                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
 611                 },
 612         },
 613         .slaves         = omap44xx_i2c4_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
 615         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 616 };
 617
 618 /*
 619  * 'mpu_bus' class
 620  * instance(s): mpu_private
 621  */
 622 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 623         .name = "mpu_bus",
 624 };
 625
 626 /* mpu_private interface data */
 627 /* mpu -> mpu_private */
 628 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 629         .master         = &omap44xx_mpu_hwmod,
 630         .slave          = &omap44xx_mpu_private_hwmod,
 631         .clk            = "l3_div_ck",
 632         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 633 };
 634
 635 /* mpu_private slave ports */
 636 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 637         &omap44xx_mpu__mpu_private,
 638 };
 639
 640 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 641         .name           = "mpu_private",
 642         .class          = &omap44xx_mpu_bus_hwmod_class,
 643         .slaves         = omap44xx_mpu_private_slaves,
 644         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 645         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 646 };
 647
 648 /*
 649  * 'mpu' class
 650  * mpu sub-system
 651  */
 652
 653 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 654         .name = "mpu",
 655 };
 656
 657 /* mpu */
 658 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
 659         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
 660         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
 661         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
 662 };
 663
 664 /* mpu master ports */
 665 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
 666         &omap44xx_mpu__l3_main_1,
 667         &omap44xx_mpu__l4_abe,
 668         &omap44xx_mpu__dmm,
 669 };
 670
 671 static struct omap_hwmod omap44xx_mpu_hwmod = {
 672         .name           = "mpu",
 673         .class          = &omap44xx_mpu_hwmod_class,
 674         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 675         .mpu_irqs       = omap44xx_mpu_irqs,
 676         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
 677         .main_clk       = "dpll_mpu_m2_ck",
 678         .prcm = {
 679                 .omap4 = {
 680                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
 681                 },
 682         },
 683         .masters        = omap44xx_mpu_masters,
 684         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
 685         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 686 };
 687
 688 /*
 689  * 'wd_timer' class
 690  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 691  * overflow condition
 692  */
 693
 694 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
 695         .rev_offs       = 0x0000,
 696         .sysc_offs      = 0x0010,
 697         .syss_offs      = 0x0014,
 698         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 699                            SYSC_HAS_SOFTRESET),
 700         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 701         .sysc_fields    = &omap_hwmod_sysc_type1,
 702 };
 703
 704 /*
 705  * 'uart' class
 706  * universal asynchronous receiver/transmitter (uart)
 707  */
 708
 709 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
 710         .rev_offs       = 0x0050,
 711         .sysc_offs      = 0x0054,
 712         .syss_offs      = 0x0058,
 713         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 714                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 715         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 716         .sysc_fields    = &omap_hwmod_sysc_type1,
 717 };
 718
 719 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
 720         .name = "wd_timer",
 721         .sysc = &omap44xx_wd_timer_sysc,
 722 };
 723
 724 /* wd_timer2 */
 725 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
 726 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
 727         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
 728 };
 729
 730 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
 731         {
 732                 .pa_start       = 0x4a314000,
 733                 .pa_end         = 0x4a31407f,
 734                 .flags          = ADDR_TYPE_RT
 735         },
 736 };
 737
 738 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
 739         .name = "uart",
 740         .sysc = &omap44xx_uart_sysc,
 741 };
 742
 743 /* uart1 */
 744 static struct omap_hwmod omap44xx_uart1_hwmod;
 745 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
 746         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
 747 };
 748
 749 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
 750         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
 751         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
 752 };
 753
 754 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
 755         {
 756                 .pa_start       = 0x4806a000,
 757                 .pa_end         = 0x4806a0ff,
 758                 .flags          = ADDR_TYPE_RT
 759         },
 760 };
 761
 762 /* l4_per -> uart1 */
 763 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
 764         .master         = &omap44xx_l4_per_hwmod,
 765         .slave          = &omap44xx_uart1_hwmod,
 766         .clk            = "l4_div_ck",
 767         .addr           = omap44xx_uart1_addrs,
 768         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
 769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 770 };
 771
 772 /* uart1 slave ports */
 773 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
 774         &omap44xx_l4_per__uart1,
 775 };
 776
 777 static struct omap_hwmod omap44xx_uart1_hwmod = {
 778         .name           = "uart1",
 779         .class          = &omap44xx_uart_hwmod_class,
 780         .mpu_irqs       = omap44xx_uart1_irqs,
 781         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
 782         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
 783         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
 784         .main_clk       = "uart1_fck",
 785         .prcm = {
 786                 .omap4 = {
 787                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
 788                 },
 789         },
 790         .slaves         = omap44xx_uart1_slaves,
 791         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
 792         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 793 };
 794
 795 /* uart2 */
 796 static struct omap_hwmod omap44xx_uart2_hwmod;
 797 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
 798         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
 799 };
 800
 801 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
 802         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
 803         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
 804 };
 805
 806 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
 807         {
 808                 .pa_start       = 0x4806c000,
 809                 .pa_end         = 0x4806c0ff,
 810                 .flags          = ADDR_TYPE_RT
 811         },
 812 };
 813
 814 /* l4_wkup -> wd_timer2 */
 815 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
 816         .master         = &omap44xx_l4_wkup_hwmod,
 817         .slave          = &omap44xx_wd_timer2_hwmod,
 818         .clk            = "l4_wkup_clk_mux_ck",
 819         .addr           = omap44xx_wd_timer2_addrs,
 820         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 /* wd_timer2 slave ports */
 825 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
 826         &omap44xx_l4_wkup__wd_timer2,
 827 };
 828
 829 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
 830         .name           = "wd_timer2",
 831         .class          = &omap44xx_wd_timer_hwmod_class,
 832         .mpu_irqs       = omap44xx_wd_timer2_irqs,
 833         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
 834         .main_clk       = "wd_timer2_fck",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
 838                 },
 839         },
 840         .slaves         = omap44xx_wd_timer2_slaves,
 841         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
 842         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 843 };
 844
 845 /* wd_timer3 */
 846 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
 847 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
 848         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
 849 };
 850
 851 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
 852         {
 853                 .pa_start       = 0x40130000,
 854                 .pa_end         = 0x4013007f,
 855                 .flags          = ADDR_TYPE_RT
 856         },
 857 };
 858
 859 /* l4_per -> uart2 */
 860 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
 861         .master         = &omap44xx_l4_per_hwmod,
 862         .slave          = &omap44xx_uart2_hwmod,
 863         .clk            = "l4_div_ck",
 864         .addr           = omap44xx_uart2_addrs,
 865         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
 866         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 867 };
 868
 869 /* uart2 slave ports */
 870 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
 871         &omap44xx_l4_per__uart2,
 872 };
 873
 874 static struct omap_hwmod omap44xx_uart2_hwmod = {
 875         .name           = "uart2",
 876         .class          = &omap44xx_uart_hwmod_class,
 877         .mpu_irqs       = omap44xx_uart2_irqs,
 878         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
 879         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
 880         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
 881         .main_clk       = "uart2_fck",
 882         .prcm = {
 883                 .omap4 = {
 884                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
 885                 },
 886         },
 887         .slaves         = omap44xx_uart2_slaves,
 888         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
 889         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 890 };
 891
 892 /* uart3 */
 893 static struct omap_hwmod omap44xx_uart3_hwmod;
 894 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
 895         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
 896 };
 897
 898 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
 899         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
 900         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
 901 };
 902
 903 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
 904         {
 905                 .pa_start       = 0x48020000,
 906                 .pa_end         = 0x480200ff,
 907                 .flags          = ADDR_TYPE_RT
 908         },
 909 };
 910
 911 /* l4_abe -> wd_timer3 */
 912 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
 913         .master         = &omap44xx_l4_abe_hwmod,
 914         .slave          = &omap44xx_wd_timer3_hwmod,
 915         .clk            = "ocp_abe_iclk",
 916         .addr           = omap44xx_wd_timer3_addrs,
 917         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
 918         .user           = OCP_USER_MPU,
 919 };
 920
 921 /* l4_abe -> wd_timer3 (dma) */
 922 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
 923         {
 924                 .pa_start       = 0x49030000,
 925                 .pa_end         = 0x4903007f,
 926                 .flags          = ADDR_TYPE_RT
 927         },
 928 };
 929
 930 /* l4_per -> uart3 */
 931 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
 932         .master         = &omap44xx_l4_per_hwmod,
 933         .slave          = &omap44xx_uart3_hwmod,
 934         .clk            = "l4_div_ck",
 935         .addr           = omap44xx_uart3_addrs,
 936         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
 937         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 938 };
 939
 940 /* uart3 slave ports */
 941 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
 942         &omap44xx_l4_per__uart3,
 943 };
 944
 945 static struct omap_hwmod omap44xx_uart3_hwmod = {
 946         .name           = "uart3",
 947         .class          = &omap44xx_uart_hwmod_class,
 948         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 949         .mpu_irqs       = omap44xx_uart3_irqs,
 950         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
 951         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
 952         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
 953         .main_clk       = "uart3_fck",
 954         .prcm = {
 955                 .omap4 = {
 956                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
 957                 },
 958         },
 959         .slaves         = omap44xx_uart3_slaves,
 960         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
 961         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 962 };
 963
 964 /* uart4 */
 965 static struct omap_hwmod omap44xx_uart4_hwmod;
 966 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
 967         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
 968 };
 969
 970 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
 971         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
 972         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
 973 };
 974
 975 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
 976         {
 977                 .pa_start       = 0x4806e000,
 978                 .pa_end         = 0x4806e0ff,
 979                 .flags          = ADDR_TYPE_RT
 980         },
 981 };
 982
 983 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
 984         .master         = &omap44xx_l4_abe_hwmod,
 985         .slave          = &omap44xx_wd_timer3_hwmod,
 986         .clk            = "ocp_abe_iclk",
 987         .addr           = omap44xx_wd_timer3_dma_addrs,
 988         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
 989         .user           = OCP_USER_SDMA,
 990 };
 991
 992 /* wd_timer3 slave ports */
 993 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
 994         &omap44xx_l4_abe__wd_timer3,
 995         &omap44xx_l4_abe__wd_timer3_dma,
 996 };
 997
 998 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 999         .name           = "wd_timer3",
1000         .class          = &omap44xx_wd_timer_hwmod_class,
1001         .mpu_irqs       = omap44xx_wd_timer3_irqs,
1002         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1003         .main_clk       = "wd_timer3_fck",
1004         .prcm = {
1005                 .omap4 = {
1006                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1007                 },
1008         },
1009         .slaves         = omap44xx_wd_timer3_slaves,
1010         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1011         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1012 };
1013
1014 /* l4_per -> uart4 */
1015 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1016         .master         = &omap44xx_l4_per_hwmod,
1017         .slave          = &omap44xx_uart4_hwmod,
1018         .clk            = "l4_div_ck",
1019         .addr           = omap44xx_uart4_addrs,
1020         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
1021         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1022 };
1023
1024 /* uart4 slave ports */
1025 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1026         &omap44xx_l4_per__uart4,
1027 };
1028
1029 static struct omap_hwmod omap44xx_uart4_hwmod = {
1030         .name           = "uart4",
1031         .class          = &omap44xx_uart_hwmod_class,
1032         .mpu_irqs       = omap44xx_uart4_irqs,
1033         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
1034         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
1035         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1036         .main_clk       = "uart4_fck",
1037         .prcm = {
1038                 .omap4 = {
1039                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1040                 },
1041         },
1042         .slaves         = omap44xx_uart4_slaves,
1043         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
1044         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1045 };
1046
1047 /*
1048  * 'gpio' class
1049  * general purpose io module
1050  */
1051
1052 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1053         .rev_offs       = 0x0000,
1054         .sysc_offs      = 0x0010,
1055         .syss_offs      = 0x0114,
1056         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1057                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1058         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1059         .sysc_fields    = &omap_hwmod_sysc_type1,
1060 };
1061
1062 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1063         .name = "gpio",
1064         .sysc = &omap44xx_gpio_sysc,
1065         .rev = 2,
1066 };
1067
1068 /* gpio dev_attr */
1069 static struct omap_gpio_dev_attr gpio_dev_attr = {
1070         .bank_width = 32,
1071         .dbck_flag = true,
1072 };
1073
1074 /* gpio1 */
1075 static struct omap_hwmod omap44xx_gpio1_hwmod;
1076 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1077         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1078 };
1079
1080 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1081         {
1082                 .pa_start       = 0x4a310000,
1083                 .pa_end         = 0x4a3101ff,
1084                 .flags          = ADDR_TYPE_RT
1085         },
1086 };
1087
1088 /* l4_wkup -> gpio1 */
1089 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1090         .master         = &omap44xx_l4_wkup_hwmod,
1091         .slave          = &omap44xx_gpio1_hwmod,
1092         .addr           = omap44xx_gpio1_addrs,
1093         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
1094         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1095 };
1096
1097 /* gpio1 slave ports */
1098 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1099         &omap44xx_l4_wkup__gpio1,
1100 };
1101
1102 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1103         { .role = "dbclk", .clk = "sys_32k_ck" },
1104 };
1105
1106 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1107         .name           = "gpio1",
1108         .class          = &omap44xx_gpio_hwmod_class,
1109         .mpu_irqs       = omap44xx_gpio1_irqs,
1110         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
1111         .main_clk       = "gpio1_ick",
1112         .prcm = {
1113                 .omap4 = {
1114                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1115                 },
1116         },
1117         .opt_clks       = gpio1_opt_clks,
1118         .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1119         .dev_attr       = &gpio_dev_attr,
1120         .slaves         = omap44xx_gpio1_slaves,
1121         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1122         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1123 };
1124
1125 /* gpio2 */
1126 static struct omap_hwmod omap44xx_gpio2_hwmod;
1127 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1128         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1129 };
1130
1131 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1132         {
1133                 .pa_start       = 0x48055000,
1134                 .pa_end         = 0x480551ff,
1135                 .flags          = ADDR_TYPE_RT
1136         },
1137 };
1138
1139 /* l4_per -> gpio2 */
1140 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1141         .master         = &omap44xx_l4_per_hwmod,
1142         .slave          = &omap44xx_gpio2_hwmod,
1143         .addr           = omap44xx_gpio2_addrs,
1144         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
1145         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1146 };
1147
1148 /* gpio2 slave ports */
1149 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1150         &omap44xx_l4_per__gpio2,
1151 };
1152
1153 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1154         { .role = "dbclk", .clk = "sys_32k_ck" },
1155 };
1156
1157 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1158         .name           = "gpio2",
1159         .class          = &omap44xx_gpio_hwmod_class,
1160         .mpu_irqs       = omap44xx_gpio2_irqs,
1161         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
1162         .main_clk       = "gpio2_ick",
1163         .prcm = {
1164                 .omap4 = {
1165                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1166                 },
1167         },
1168         .opt_clks       = gpio2_opt_clks,
1169         .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1170         .dev_attr       = &gpio_dev_attr,
1171         .slaves         = omap44xx_gpio2_slaves,
1172         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1173         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1174 };
1175
1176 /* gpio3 */
1177 static struct omap_hwmod omap44xx_gpio3_hwmod;
1178 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1179         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1180 };
1181
1182 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1183         {
1184                 .pa_start       = 0x48057000,
1185                 .pa_end         = 0x480571ff,
1186                 .flags          = ADDR_TYPE_RT
1187         },
1188 };
1189
1190 /* l4_per -> gpio3 */
1191 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1192         .master         = &omap44xx_l4_per_hwmod,
1193         .slave          = &omap44xx_gpio3_hwmod,
1194         .addr           = omap44xx_gpio3_addrs,
1195         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
1196         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1197 };
1198
1199 /* gpio3 slave ports */
1200 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1201         &omap44xx_l4_per__gpio3,
1202 };
1203
1204 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1205         { .role = "dbclk", .clk = "sys_32k_ck" },
1206 };
1207
1208 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1209         .name           = "gpio3",
1210         .class          = &omap44xx_gpio_hwmod_class,
1211         .mpu_irqs       = omap44xx_gpio3_irqs,
1212         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
1213         .main_clk       = "gpio3_ick",
1214         .prcm = {
1215                 .omap4 = {
1216                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1217                 },
1218         },
1219         .opt_clks       = gpio3_opt_clks,
1220         .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1221         .dev_attr       = &gpio_dev_attr,
1222         .slaves         = omap44xx_gpio3_slaves,
1223         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1224         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1225 };
1226
1227 /* gpio4 */
1228 static struct omap_hwmod omap44xx_gpio4_hwmod;
1229 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1230         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1231 };
1232
1233 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1234         {
1235                 .pa_start       = 0x48059000,
1236                 .pa_end         = 0x480591ff,
1237                 .flags          = ADDR_TYPE_RT
1238         },
1239 };
1240
1241 /* l4_per -> gpio4 */
1242 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1243         .master         = &omap44xx_l4_per_hwmod,
1244         .slave          = &omap44xx_gpio4_hwmod,
1245         .addr           = omap44xx_gpio4_addrs,
1246         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
1247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1248 };
1249
1250 /* gpio4 slave ports */
1251 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1252         &omap44xx_l4_per__gpio4,
1253 };
1254
1255 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1256         { .role = "dbclk", .clk = "sys_32k_ck" },
1257 };
1258
1259 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1260         .name           = "gpio4",
1261         .class          = &omap44xx_gpio_hwmod_class,
1262         .mpu_irqs       = omap44xx_gpio4_irqs,
1263         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
1264         .main_clk       = "gpio4_ick",
1265         .prcm = {
1266                 .omap4 = {
1267                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1268                 },
1269         },
1270         .opt_clks       = gpio4_opt_clks,
1271         .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1272         .dev_attr       = &gpio_dev_attr,
1273         .slaves         = omap44xx_gpio4_slaves,
1274         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1275         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1276 };
1277
1278 /* gpio5 */
1279 static struct omap_hwmod omap44xx_gpio5_hwmod;
1280 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1281         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1282 };
1283
1284 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1285         {
1286                 .pa_start       = 0x4805b000,
1287                 .pa_end         = 0x4805b1ff,
1288                 .flags          = ADDR_TYPE_RT
1289         },
1290 };
1291
1292 /* l4_per -> gpio5 */
1293 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1294         .master         = &omap44xx_l4_per_hwmod,
1295         .slave          = &omap44xx_gpio5_hwmod,
1296         .addr           = omap44xx_gpio5_addrs,
1297         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
1298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1299 };
1300
1301 /* gpio5 slave ports */
1302 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1303         &omap44xx_l4_per__gpio5,
1304 };
1305
1306 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1307         { .role = "dbclk", .clk = "sys_32k_ck" },
1308 };
1309
1310 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1311         .name           = "gpio5",
1312         .class          = &omap44xx_gpio_hwmod_class,
1313         .mpu_irqs       = omap44xx_gpio5_irqs,
1314         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
1315         .main_clk       = "gpio5_ick",
1316         .prcm = {
1317                 .omap4 = {
1318                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1319                 },
1320         },
1321         .opt_clks       = gpio5_opt_clks,
1322         .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1323         .dev_attr       = &gpio_dev_attr,
1324         .slaves         = omap44xx_gpio5_slaves,
1325         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1326         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1327 };
1328
1329 /* gpio6 */
1330 static struct omap_hwmod omap44xx_gpio6_hwmod;
1331 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1332         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1333 };
1334
1335 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1336         {
1337                 .pa_start       = 0x4805d000,
1338                 .pa_end         = 0x4805d1ff,
1339                 .flags          = ADDR_TYPE_RT
1340         },
1341 };
1342
1343 /* l4_per -> gpio6 */
1344 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1345         .master         = &omap44xx_l4_per_hwmod,
1346         .slave          = &omap44xx_gpio6_hwmod,
1347         .addr           = omap44xx_gpio6_addrs,
1348         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
1349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1350 };
1351
1352 /* gpio6 slave ports */
1353 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1354         &omap44xx_l4_per__gpio6,
1355 };
1356
1357 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1358         { .role = "dbclk", .clk = "sys_32k_ck" },
1359 };
1360
1361 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1362         .name           = "gpio6",
1363         .class          = &omap44xx_gpio_hwmod_class,
1364         .mpu_irqs       = omap44xx_gpio6_irqs,
1365         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
1366         .main_clk       = "gpio6_ick",
1367         .prcm = {
1368                 .omap4 = {
1369                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1370                 },
1371         },
1372         .opt_clks       = gpio6_opt_clks,
1373         .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1374         .dev_attr       = &gpio_dev_attr,
1375         .slaves         = omap44xx_gpio6_slaves,
1376         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1377         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1378 };
1379 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
1380         /* dmm class */
1381         &omap44xx_dmm_hwmod,
1382         /* emif_fw class */
1383         &omap44xx_emif_fw_hwmod,
1384         /* l3 class */
1385         &omap44xx_l3_instr_hwmod,
1386         &omap44xx_l3_main_1_hwmod,
1387         &omap44xx_l3_main_2_hwmod,
1388         &omap44xx_l3_main_3_hwmod,
1389         /* l4 class */
1390         &omap44xx_l4_abe_hwmod,
1391         &omap44xx_l4_cfg_hwmod,
1392         &omap44xx_l4_per_hwmod,
1393         &omap44xx_l4_wkup_hwmod,
1394         /* i2c class */
1395         &omap44xx_i2c1_hwmod,
1396         &omap44xx_i2c2_hwmod,
1397         &omap44xx_i2c3_hwmod,
1398         &omap44xx_i2c4_hwmod,
1399         /* mpu_bus class */
1400         &omap44xx_mpu_private_hwmod,
1401
1402         /* gpio class */
1403         &omap44xx_gpio1_hwmod,
1404         &omap44xx_gpio2_hwmod,
1405         &omap44xx_gpio3_hwmod,
1406         &omap44xx_gpio4_hwmod,
1407         &omap44xx_gpio5_hwmod,
1408         &omap44xx_gpio6_hwmod,
1409
1410         /* mpu class */
1411         &omap44xx_mpu_hwmod,
1412         /* wd_timer class */
1413         &omap44xx_wd_timer2_hwmod,
1414         &omap44xx_wd_timer3_hwmod,
1415
1416         /* uart class */
1417         &omap44xx_uart1_hwmod,
1418         &omap44xx_uart2_hwmod,
1419         &omap44xx_uart3_hwmod,
1420         &omap44xx_uart4_hwmod,
1421         NULL,
1422 };
1423
1424 int __init omap44xx_hwmod_init(void)
1425 {
1426         return omap_hwmod_init(omap44xx_hwmods);
1427 }
1428