2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
25 #include <plat/gpio.h>
28 #include "omap_hwmod_common_data.h"
33 #include "prm-regbits-44xx.h"
36 /* Base offset for all OMAP4 interrupts external to MPUSS */
37 #define OMAP44XX_IRQ_GIC_START 32
39 /* Base offset for all OMAP4 dma requests */
40 #define OMAP44XX_DMA_REQ_START 1
42 /* Backward references (IPs with Bus Master capability) */
43 static struct omap_hwmod omap44xx_dma_system_hwmod;
44 static struct omap_hwmod omap44xx_dmm_hwmod;
45 static struct omap_hwmod omap44xx_dsp_hwmod;
46 static struct omap_hwmod omap44xx_emif_fw_hwmod;
47 static struct omap_hwmod omap44xx_iva_hwmod;
48 static struct omap_hwmod omap44xx_l3_instr_hwmod;
49 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
50 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
51 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
52 static struct omap_hwmod omap44xx_l4_abe_hwmod;
53 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
54 static struct omap_hwmod omap44xx_l4_per_hwmod;
55 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
56 static struct omap_hwmod omap44xx_mpu_hwmod;
57 static struct omap_hwmod omap44xx_mpu_private_hwmod;
60 * Interconnects omap_hwmod structures
61 * hwmods that compose the global OMAP interconnect
68 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
72 /* dmm interface data */
73 /* l3_main_1 -> dmm */
74 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
75 .master = &omap44xx_l3_main_1_hwmod,
76 .slave = &omap44xx_dmm_hwmod,
78 .user = OCP_USER_SDMA,
81 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
83 .pa_start = 0x4e000000,
90 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
91 .master = &omap44xx_mpu_hwmod,
92 .slave = &omap44xx_dmm_hwmod,
94 .addr = omap44xx_dmm_addrs,
95 .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
100 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
101 &omap44xx_l3_main_1__dmm,
105 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
106 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
109 static struct omap_hwmod omap44xx_dmm_hwmod = {
111 .class = &omap44xx_dmm_hwmod_class,
112 .slaves = omap44xx_dmm_slaves,
113 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
114 .mpu_irqs = omap44xx_dmm_irqs,
115 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
116 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
121 * instance(s): emif_fw
123 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
127 /* emif_fw interface data */
129 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
130 .master = &omap44xx_dmm_hwmod,
131 .slave = &omap44xx_emif_fw_hwmod,
133 .user = OCP_USER_MPU | OCP_USER_SDMA,
136 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
138 .pa_start = 0x4a20c000,
139 .pa_end = 0x4a20c0ff,
140 .flags = ADDR_TYPE_RT
144 /* l4_cfg -> emif_fw */
145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
146 .master = &omap44xx_l4_cfg_hwmod,
147 .slave = &omap44xx_emif_fw_hwmod,
149 .addr = omap44xx_emif_fw_addrs,
150 .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
151 .user = OCP_USER_MPU,
154 /* emif_fw slave ports */
155 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
156 &omap44xx_dmm__emif_fw,
157 &omap44xx_l4_cfg__emif_fw,
160 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
162 .class = &omap44xx_emif_fw_hwmod_class,
163 .slaves = omap44xx_emif_fw_slaves,
164 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
165 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
170 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
172 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
176 /* l3_instr interface data */
177 /* iva -> l3_instr */
178 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
179 .master = &omap44xx_iva_hwmod,
180 .slave = &omap44xx_l3_instr_hwmod,
182 .user = OCP_USER_MPU | OCP_USER_SDMA,
185 /* l3_main_3 -> l3_instr */
186 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
187 .master = &omap44xx_l3_main_3_hwmod,
188 .slave = &omap44xx_l3_instr_hwmod,
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
193 /* l3_instr slave ports */
194 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
195 &omap44xx_iva__l3_instr,
196 &omap44xx_l3_main_3__l3_instr,
199 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
201 .class = &omap44xx_l3_hwmod_class,
202 .slaves = omap44xx_l3_instr_slaves,
203 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
204 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
207 /* l3_main_1 interface data */
208 /* dsp -> l3_main_1 */
209 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
210 .master = &omap44xx_dsp_hwmod,
211 .slave = &omap44xx_l3_main_1_hwmod,
213 .user = OCP_USER_MPU | OCP_USER_SDMA,
216 /* l3_main_2 -> l3_main_1 */
217 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
218 .master = &omap44xx_l3_main_2_hwmod,
219 .slave = &omap44xx_l3_main_1_hwmod,
221 .user = OCP_USER_MPU | OCP_USER_SDMA,
224 /* l4_cfg -> l3_main_1 */
225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
226 .master = &omap44xx_l4_cfg_hwmod,
227 .slave = &omap44xx_l3_main_1_hwmod,
229 .user = OCP_USER_MPU | OCP_USER_SDMA,
232 /* mpu -> l3_main_1 */
233 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
234 .master = &omap44xx_mpu_hwmod,
235 .slave = &omap44xx_l3_main_1_hwmod,
237 .user = OCP_USER_MPU | OCP_USER_SDMA,
240 /* l3_main_1 slave ports */
241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
242 &omap44xx_dsp__l3_main_1,
243 &omap44xx_l3_main_2__l3_main_1,
244 &omap44xx_l4_cfg__l3_main_1,
245 &omap44xx_mpu__l3_main_1,
248 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
250 .class = &omap44xx_l3_hwmod_class,
251 .slaves = omap44xx_l3_main_1_slaves,
252 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
253 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
256 /* l3_main_2 interface data */
257 /* dma_system -> l3_main_2 */
258 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
259 .master = &omap44xx_dma_system_hwmod,
260 .slave = &omap44xx_l3_main_2_hwmod,
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 /* iva -> l3_main_2 */
266 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
267 .master = &omap44xx_iva_hwmod,
268 .slave = &omap44xx_l3_main_2_hwmod,
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
273 /* l3_main_1 -> l3_main_2 */
274 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
275 .master = &omap44xx_l3_main_1_hwmod,
276 .slave = &omap44xx_l3_main_2_hwmod,
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
281 /* l4_cfg -> l3_main_2 */
282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
283 .master = &omap44xx_l4_cfg_hwmod,
284 .slave = &omap44xx_l3_main_2_hwmod,
286 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 /* l3_main_2 slave ports */
290 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
291 &omap44xx_dma_system__l3_main_2,
292 &omap44xx_iva__l3_main_2,
293 &omap44xx_l3_main_1__l3_main_2,
294 &omap44xx_l4_cfg__l3_main_2,
297 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
299 .class = &omap44xx_l3_hwmod_class,
300 .slaves = omap44xx_l3_main_2_slaves,
301 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
302 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
305 /* l3_main_3 interface data */
306 /* l3_main_1 -> l3_main_3 */
307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
308 .master = &omap44xx_l3_main_1_hwmod,
309 .slave = &omap44xx_l3_main_3_hwmod,
311 .user = OCP_USER_MPU | OCP_USER_SDMA,
314 /* l3_main_2 -> l3_main_3 */
315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
316 .master = &omap44xx_l3_main_2_hwmod,
317 .slave = &omap44xx_l3_main_3_hwmod,
319 .user = OCP_USER_MPU | OCP_USER_SDMA,
322 /* l4_cfg -> l3_main_3 */
323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
324 .master = &omap44xx_l4_cfg_hwmod,
325 .slave = &omap44xx_l3_main_3_hwmod,
327 .user = OCP_USER_MPU | OCP_USER_SDMA,
330 /* l3_main_3 slave ports */
331 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
332 &omap44xx_l3_main_1__l3_main_3,
333 &omap44xx_l3_main_2__l3_main_3,
334 &omap44xx_l4_cfg__l3_main_3,
337 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
339 .class = &omap44xx_l3_hwmod_class,
340 .slaves = omap44xx_l3_main_3_slaves,
341 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
342 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
347 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
349 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
353 /* l4_abe interface data */
355 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
356 .master = &omap44xx_dsp_hwmod,
357 .slave = &omap44xx_l4_abe_hwmod,
358 .clk = "ocp_abe_iclk",
359 .user = OCP_USER_MPU | OCP_USER_SDMA,
362 /* l3_main_1 -> l4_abe */
363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
364 .master = &omap44xx_l3_main_1_hwmod,
365 .slave = &omap44xx_l4_abe_hwmod,
367 .user = OCP_USER_MPU | OCP_USER_SDMA,
371 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
372 .master = &omap44xx_mpu_hwmod,
373 .slave = &omap44xx_l4_abe_hwmod,
374 .clk = "ocp_abe_iclk",
375 .user = OCP_USER_MPU | OCP_USER_SDMA,
378 /* l4_abe slave ports */
379 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
380 &omap44xx_dsp__l4_abe,
381 &omap44xx_l3_main_1__l4_abe,
382 &omap44xx_mpu__l4_abe,
385 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
387 .class = &omap44xx_l4_hwmod_class,
388 .slaves = omap44xx_l4_abe_slaves,
389 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
390 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
393 /* l4_cfg interface data */
394 /* l3_main_1 -> l4_cfg */
395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
396 .master = &omap44xx_l3_main_1_hwmod,
397 .slave = &omap44xx_l4_cfg_hwmod,
399 .user = OCP_USER_MPU | OCP_USER_SDMA,
402 /* l4_cfg slave ports */
403 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
404 &omap44xx_l3_main_1__l4_cfg,
407 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
409 .class = &omap44xx_l4_hwmod_class,
410 .slaves = omap44xx_l4_cfg_slaves,
411 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
412 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
415 /* l4_per interface data */
416 /* l3_main_2 -> l4_per */
417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
418 .master = &omap44xx_l3_main_2_hwmod,
419 .slave = &omap44xx_l4_per_hwmod,
421 .user = OCP_USER_MPU | OCP_USER_SDMA,
424 /* l4_per slave ports */
425 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
426 &omap44xx_l3_main_2__l4_per,
429 static struct omap_hwmod omap44xx_l4_per_hwmod = {
431 .class = &omap44xx_l4_hwmod_class,
432 .slaves = omap44xx_l4_per_slaves,
433 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
437 /* l4_wkup interface data */
438 /* l4_cfg -> l4_wkup */
439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
440 .master = &omap44xx_l4_cfg_hwmod,
441 .slave = &omap44xx_l4_wkup_hwmod,
443 .user = OCP_USER_MPU | OCP_USER_SDMA,
446 /* l4_wkup slave ports */
447 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
448 &omap44xx_l4_cfg__l4_wkup,
451 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
453 .class = &omap44xx_l4_hwmod_class,
454 .slaves = omap44xx_l4_wkup_slaves,
455 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
456 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
461 * instance(s): mpu_private
463 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
467 /* mpu_private interface data */
468 /* mpu -> mpu_private */
469 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
470 .master = &omap44xx_mpu_hwmod,
471 .slave = &omap44xx_mpu_private_hwmod,
473 .user = OCP_USER_MPU | OCP_USER_SDMA,
476 /* mpu_private slave ports */
477 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
478 &omap44xx_mpu__mpu_private,
481 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
482 .name = "mpu_private",
483 .class = &omap44xx_mpu_bus_hwmod_class,
484 .slaves = omap44xx_mpu_private_slaves,
485 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
486 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
490 * Modules omap_hwmod structures
492 * The following IPs are excluded for the moment because:
493 * - They do not need an explicit SW control using omap_hwmod API.
494 * - They still need to be validated with the driver
495 * properly adapted to omap_hwmod / omap_device
505 * ctrl_module_pad_core
506 * ctrl_module_pad_wkup
580 * dma controller for data exchange between memory to memory (i.e. internal or
581 * external memory) and gp peripherals to memory or memory to gp peripherals
584 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
588 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
589 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
590 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
591 SYSS_HAS_RESET_STATUS),
592 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
593 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
594 .sysc_fields = &omap_hwmod_sysc_type1,
597 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
599 .sysc = &omap44xx_dma_sysc,
603 static struct omap_dma_dev_attr dma_dev_attr = {
604 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
605 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
610 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
611 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
612 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
613 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
614 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
617 /* dma_system master ports */
618 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
619 &omap44xx_dma_system__l3_main_2,
622 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
624 .pa_start = 0x4a056000,
625 .pa_end = 0x4a0560ff,
626 .flags = ADDR_TYPE_RT
630 /* l4_cfg -> dma_system */
631 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
632 .master = &omap44xx_l4_cfg_hwmod,
633 .slave = &omap44xx_dma_system_hwmod,
635 .addr = omap44xx_dma_system_addrs,
636 .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
637 .user = OCP_USER_MPU | OCP_USER_SDMA,
640 /* dma_system slave ports */
641 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
642 &omap44xx_l4_cfg__dma_system,
645 static struct omap_hwmod omap44xx_dma_system_hwmod = {
646 .name = "dma_system",
647 .class = &omap44xx_dma_hwmod_class,
648 .mpu_irqs = omap44xx_dma_system_irqs,
649 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
650 .main_clk = "l3_div_ck",
653 .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
656 .dev_attr = &dma_dev_attr,
657 .slaves = omap44xx_dma_system_slaves,
658 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
659 .masters = omap44xx_dma_system_masters,
660 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
661 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
669 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
674 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
675 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
678 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
679 { .name = "mmu_cache", .rst_shift = 1 },
682 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
683 { .name = "dsp", .rst_shift = 0 },
687 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
688 .master = &omap44xx_dsp_hwmod,
689 .slave = &omap44xx_iva_hwmod,
690 .clk = "dpll_iva_m5x2_ck",
693 /* dsp master ports */
694 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
695 &omap44xx_dsp__l3_main_1,
696 &omap44xx_dsp__l4_abe,
701 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
702 .master = &omap44xx_l4_cfg_hwmod,
703 .slave = &omap44xx_dsp_hwmod,
705 .user = OCP_USER_MPU | OCP_USER_SDMA,
708 /* dsp slave ports */
709 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
710 &omap44xx_l4_cfg__dsp,
713 /* Pseudo hwmod for reset control purpose only */
714 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
716 .class = &omap44xx_dsp_hwmod_class,
717 .flags = HWMOD_INIT_NO_RESET,
718 .rst_lines = omap44xx_dsp_c0_resets,
719 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
722 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
725 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
728 static struct omap_hwmod omap44xx_dsp_hwmod = {
730 .class = &omap44xx_dsp_hwmod_class,
731 .mpu_irqs = omap44xx_dsp_irqs,
732 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
733 .rst_lines = omap44xx_dsp_resets,
734 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
735 .main_clk = "dsp_fck",
738 .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
739 .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
742 .slaves = omap44xx_dsp_slaves,
743 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
744 .masters = omap44xx_dsp_masters,
745 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
746 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
751 * general purpose io module
754 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
758 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
759 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
760 SYSS_HAS_RESET_STATUS),
761 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
763 .sysc_fields = &omap_hwmod_sysc_type1,
766 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
768 .sysc = &omap44xx_gpio_sysc,
773 static struct omap_gpio_dev_attr gpio_dev_attr = {
779 static struct omap_hwmod omap44xx_gpio1_hwmod;
780 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
781 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
784 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
786 .pa_start = 0x4a310000,
787 .pa_end = 0x4a3101ff,
788 .flags = ADDR_TYPE_RT
792 /* l4_wkup -> gpio1 */
793 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
794 .master = &omap44xx_l4_wkup_hwmod,
795 .slave = &omap44xx_gpio1_hwmod,
796 .clk = "l4_wkup_clk_mux_ck",
797 .addr = omap44xx_gpio1_addrs,
798 .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
799 .user = OCP_USER_MPU | OCP_USER_SDMA,
802 /* gpio1 slave ports */
803 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
804 &omap44xx_l4_wkup__gpio1,
807 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
808 { .role = "dbclk", .clk = "gpio1_dbclk" },
811 static struct omap_hwmod omap44xx_gpio1_hwmod = {
813 .class = &omap44xx_gpio_hwmod_class,
814 .mpu_irqs = omap44xx_gpio1_irqs,
815 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
816 .main_clk = "gpio1_ick",
819 .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
822 .opt_clks = gpio1_opt_clks,
823 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
824 .dev_attr = &gpio_dev_attr,
825 .slaves = omap44xx_gpio1_slaves,
826 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
827 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
831 static struct omap_hwmod omap44xx_gpio2_hwmod;
832 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
833 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
836 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
838 .pa_start = 0x48055000,
839 .pa_end = 0x480551ff,
840 .flags = ADDR_TYPE_RT
844 /* l4_per -> gpio2 */
845 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
846 .master = &omap44xx_l4_per_hwmod,
847 .slave = &omap44xx_gpio2_hwmod,
849 .addr = omap44xx_gpio2_addrs,
850 .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
851 .user = OCP_USER_MPU | OCP_USER_SDMA,
854 /* gpio2 slave ports */
855 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
856 &omap44xx_l4_per__gpio2,
859 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
860 { .role = "dbclk", .clk = "gpio2_dbclk" },
863 static struct omap_hwmod omap44xx_gpio2_hwmod = {
865 .class = &omap44xx_gpio_hwmod_class,
866 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
867 .mpu_irqs = omap44xx_gpio2_irqs,
868 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
869 .main_clk = "gpio2_ick",
872 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
875 .opt_clks = gpio2_opt_clks,
876 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
877 .dev_attr = &gpio_dev_attr,
878 .slaves = omap44xx_gpio2_slaves,
879 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
880 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
884 static struct omap_hwmod omap44xx_gpio3_hwmod;
885 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
886 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
889 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
891 .pa_start = 0x48057000,
892 .pa_end = 0x480571ff,
893 .flags = ADDR_TYPE_RT
897 /* l4_per -> gpio3 */
898 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
899 .master = &omap44xx_l4_per_hwmod,
900 .slave = &omap44xx_gpio3_hwmod,
902 .addr = omap44xx_gpio3_addrs,
903 .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
904 .user = OCP_USER_MPU | OCP_USER_SDMA,
907 /* gpio3 slave ports */
908 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
909 &omap44xx_l4_per__gpio3,
912 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
913 { .role = "dbclk", .clk = "gpio3_dbclk" },
916 static struct omap_hwmod omap44xx_gpio3_hwmod = {
918 .class = &omap44xx_gpio_hwmod_class,
919 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
920 .mpu_irqs = omap44xx_gpio3_irqs,
921 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
922 .main_clk = "gpio3_ick",
925 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
928 .opt_clks = gpio3_opt_clks,
929 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
930 .dev_attr = &gpio_dev_attr,
931 .slaves = omap44xx_gpio3_slaves,
932 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
933 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
937 static struct omap_hwmod omap44xx_gpio4_hwmod;
938 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
939 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
942 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
944 .pa_start = 0x48059000,
945 .pa_end = 0x480591ff,
946 .flags = ADDR_TYPE_RT
950 /* l4_per -> gpio4 */
951 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
952 .master = &omap44xx_l4_per_hwmod,
953 .slave = &omap44xx_gpio4_hwmod,
955 .addr = omap44xx_gpio4_addrs,
956 .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
957 .user = OCP_USER_MPU | OCP_USER_SDMA,
960 /* gpio4 slave ports */
961 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
962 &omap44xx_l4_per__gpio4,
965 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
966 { .role = "dbclk", .clk = "gpio4_dbclk" },
969 static struct omap_hwmod omap44xx_gpio4_hwmod = {
971 .class = &omap44xx_gpio_hwmod_class,
972 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
973 .mpu_irqs = omap44xx_gpio4_irqs,
974 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
975 .main_clk = "gpio4_ick",
978 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
981 .opt_clks = gpio4_opt_clks,
982 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
983 .dev_attr = &gpio_dev_attr,
984 .slaves = omap44xx_gpio4_slaves,
985 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
986 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
990 static struct omap_hwmod omap44xx_gpio5_hwmod;
991 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
992 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
995 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
997 .pa_start = 0x4805b000,
998 .pa_end = 0x4805b1ff,
999 .flags = ADDR_TYPE_RT
1003 /* l4_per -> gpio5 */
1004 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1005 .master = &omap44xx_l4_per_hwmod,
1006 .slave = &omap44xx_gpio5_hwmod,
1008 .addr = omap44xx_gpio5_addrs,
1009 .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
1010 .user = OCP_USER_MPU | OCP_USER_SDMA,
1013 /* gpio5 slave ports */
1014 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1015 &omap44xx_l4_per__gpio5,
1018 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1019 { .role = "dbclk", .clk = "gpio5_dbclk" },
1022 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1024 .class = &omap44xx_gpio_hwmod_class,
1025 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1026 .mpu_irqs = omap44xx_gpio5_irqs,
1027 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
1028 .main_clk = "gpio5_ick",
1031 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1034 .opt_clks = gpio5_opt_clks,
1035 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1036 .dev_attr = &gpio_dev_attr,
1037 .slaves = omap44xx_gpio5_slaves,
1038 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
1039 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1043 static struct omap_hwmod omap44xx_gpio6_hwmod;
1044 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1045 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1048 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1050 .pa_start = 0x4805d000,
1051 .pa_end = 0x4805d1ff,
1052 .flags = ADDR_TYPE_RT
1056 /* l4_per -> gpio6 */
1057 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1058 .master = &omap44xx_l4_per_hwmod,
1059 .slave = &omap44xx_gpio6_hwmod,
1061 .addr = omap44xx_gpio6_addrs,
1062 .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
1063 .user = OCP_USER_MPU | OCP_USER_SDMA,
1066 /* gpio6 slave ports */
1067 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
1068 &omap44xx_l4_per__gpio6,
1071 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1072 { .role = "dbclk", .clk = "gpio6_dbclk" },
1075 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1077 .class = &omap44xx_gpio_hwmod_class,
1078 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1079 .mpu_irqs = omap44xx_gpio6_irqs,
1080 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
1081 .main_clk = "gpio6_ick",
1084 .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1087 .opt_clks = gpio6_opt_clks,
1088 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1089 .dev_attr = &gpio_dev_attr,
1090 .slaves = omap44xx_gpio6_slaves,
1091 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
1092 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1097 * multimaster high-speed i2c controller
1100 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1101 .sysc_offs = 0x0010,
1102 .syss_offs = 0x0090,
1103 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1104 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1105 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1106 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1108 .sysc_fields = &omap_hwmod_sysc_type1,
1111 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1113 .sysc = &omap44xx_i2c_sysc,
1117 static struct omap_hwmod omap44xx_i2c1_hwmod;
1118 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1119 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1122 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1123 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1124 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1127 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1129 .pa_start = 0x48070000,
1130 .pa_end = 0x480700ff,
1131 .flags = ADDR_TYPE_RT
1135 /* l4_per -> i2c1 */
1136 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1137 .master = &omap44xx_l4_per_hwmod,
1138 .slave = &omap44xx_i2c1_hwmod,
1140 .addr = omap44xx_i2c1_addrs,
1141 .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
1142 .user = OCP_USER_MPU | OCP_USER_SDMA,
1145 /* i2c1 slave ports */
1146 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1147 &omap44xx_l4_per__i2c1,
1150 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1152 .class = &omap44xx_i2c_hwmod_class,
1153 .flags = HWMOD_INIT_NO_RESET,
1154 .mpu_irqs = omap44xx_i2c1_irqs,
1155 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
1156 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
1157 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1158 .main_clk = "i2c1_fck",
1161 .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1164 .slaves = omap44xx_i2c1_slaves,
1165 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
1166 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1170 static struct omap_hwmod omap44xx_i2c2_hwmod;
1171 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1172 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1175 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1176 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1177 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1180 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1182 .pa_start = 0x48072000,
1183 .pa_end = 0x480720ff,
1184 .flags = ADDR_TYPE_RT
1188 /* l4_per -> i2c2 */
1189 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1190 .master = &omap44xx_l4_per_hwmod,
1191 .slave = &omap44xx_i2c2_hwmod,
1193 .addr = omap44xx_i2c2_addrs,
1194 .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
1195 .user = OCP_USER_MPU | OCP_USER_SDMA,
1198 /* i2c2 slave ports */
1199 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1200 &omap44xx_l4_per__i2c2,
1203 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1205 .class = &omap44xx_i2c_hwmod_class,
1206 .flags = HWMOD_INIT_NO_RESET,
1207 .mpu_irqs = omap44xx_i2c2_irqs,
1208 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
1209 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
1210 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1211 .main_clk = "i2c2_fck",
1214 .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1217 .slaves = omap44xx_i2c2_slaves,
1218 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
1219 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1223 static struct omap_hwmod omap44xx_i2c3_hwmod;
1224 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1225 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1228 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1229 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1230 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1233 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1235 .pa_start = 0x48060000,
1236 .pa_end = 0x480600ff,
1237 .flags = ADDR_TYPE_RT
1241 /* l4_per -> i2c3 */
1242 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1243 .master = &omap44xx_l4_per_hwmod,
1244 .slave = &omap44xx_i2c3_hwmod,
1246 .addr = omap44xx_i2c3_addrs,
1247 .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
1248 .user = OCP_USER_MPU | OCP_USER_SDMA,
1251 /* i2c3 slave ports */
1252 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1253 &omap44xx_l4_per__i2c3,
1256 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1258 .class = &omap44xx_i2c_hwmod_class,
1259 .flags = HWMOD_INIT_NO_RESET,
1260 .mpu_irqs = omap44xx_i2c3_irqs,
1261 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
1262 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
1263 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1264 .main_clk = "i2c3_fck",
1267 .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1270 .slaves = omap44xx_i2c3_slaves,
1271 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
1272 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1276 static struct omap_hwmod omap44xx_i2c4_hwmod;
1277 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1278 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1281 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1282 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1283 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1286 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1288 .pa_start = 0x48350000,
1289 .pa_end = 0x483500ff,
1290 .flags = ADDR_TYPE_RT
1294 /* l4_per -> i2c4 */
1295 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1296 .master = &omap44xx_l4_per_hwmod,
1297 .slave = &omap44xx_i2c4_hwmod,
1299 .addr = omap44xx_i2c4_addrs,
1300 .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
1301 .user = OCP_USER_MPU | OCP_USER_SDMA,
1304 /* i2c4 slave ports */
1305 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1306 &omap44xx_l4_per__i2c4,
1309 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1311 .class = &omap44xx_i2c_hwmod_class,
1312 .flags = HWMOD_INIT_NO_RESET,
1313 .mpu_irqs = omap44xx_i2c4_irqs,
1314 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
1315 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
1316 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1317 .main_clk = "i2c4_fck",
1320 .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1323 .slaves = omap44xx_i2c4_slaves,
1324 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
1325 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1330 * multi-standard video encoder/decoder hardware accelerator
1333 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1338 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1339 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1340 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1341 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1344 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1345 { .name = "logic", .rst_shift = 2 },
1348 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1349 { .name = "seq0", .rst_shift = 0 },
1352 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1353 { .name = "seq1", .rst_shift = 1 },
1356 /* iva master ports */
1357 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1358 &omap44xx_iva__l3_main_2,
1359 &omap44xx_iva__l3_instr,
1362 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1364 .pa_start = 0x5a000000,
1365 .pa_end = 0x5a07ffff,
1366 .flags = ADDR_TYPE_RT
1370 /* l3_main_2 -> iva */
1371 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1372 .master = &omap44xx_l3_main_2_hwmod,
1373 .slave = &omap44xx_iva_hwmod,
1375 .addr = omap44xx_iva_addrs,
1376 .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
1377 .user = OCP_USER_MPU,
1380 /* iva slave ports */
1381 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1383 &omap44xx_l3_main_2__iva,
1386 /* Pseudo hwmod for reset control purpose only */
1387 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1389 .class = &omap44xx_iva_hwmod_class,
1390 .flags = HWMOD_INIT_NO_RESET,
1391 .rst_lines = omap44xx_iva_seq0_resets,
1392 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1395 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1398 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1401 /* Pseudo hwmod for reset control purpose only */
1402 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1404 .class = &omap44xx_iva_hwmod_class,
1405 .flags = HWMOD_INIT_NO_RESET,
1406 .rst_lines = omap44xx_iva_seq1_resets,
1407 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1410 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1413 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1416 static struct omap_hwmod omap44xx_iva_hwmod = {
1418 .class = &omap44xx_iva_hwmod_class,
1419 .mpu_irqs = omap44xx_iva_irqs,
1420 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
1421 .rst_lines = omap44xx_iva_resets,
1422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1423 .main_clk = "iva_fck",
1426 .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1427 .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1430 .slaves = omap44xx_iva_slaves,
1431 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
1432 .masters = omap44xx_iva_masters,
1433 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
1434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1442 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1447 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1448 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1449 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1450 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
1453 /* mpu master ports */
1454 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1455 &omap44xx_mpu__l3_main_1,
1456 &omap44xx_mpu__l4_abe,
1460 static struct omap_hwmod omap44xx_mpu_hwmod = {
1462 .class = &omap44xx_mpu_hwmod_class,
1463 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1464 .mpu_irqs = omap44xx_mpu_irqs,
1465 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
1466 .main_clk = "dpll_mpu_m2_ck",
1469 .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
1472 .masters = omap44xx_mpu_masters,
1473 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
1474 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1478 * 'smartreflex' class
1479 * smartreflex module (monitor silicon performance and outputs a measure of
1480 * performance error)
1483 /* The IP is not compliant to type1 / type2 scheme */
1484 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1489 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1490 .sysc_offs = 0x0038,
1491 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1492 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1494 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1497 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1498 .name = "smartreflex",
1499 .sysc = &omap44xx_smartreflex_sysc,
1503 /* smartreflex_core */
1504 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
1505 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
1506 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
1509 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
1511 .pa_start = 0x4a0dd000,
1512 .pa_end = 0x4a0dd03f,
1513 .flags = ADDR_TYPE_RT
1517 /* l4_cfg -> smartreflex_core */
1518 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
1519 .master = &omap44xx_l4_cfg_hwmod,
1520 .slave = &omap44xx_smartreflex_core_hwmod,
1522 .addr = omap44xx_smartreflex_core_addrs,
1523 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
1524 .user = OCP_USER_MPU | OCP_USER_SDMA,
1527 /* smartreflex_core slave ports */
1528 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
1529 &omap44xx_l4_cfg__smartreflex_core,
1532 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1533 .name = "smartreflex_core",
1534 .class = &omap44xx_smartreflex_hwmod_class,
1535 .mpu_irqs = omap44xx_smartreflex_core_irqs,
1536 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
1537 .main_clk = "smartreflex_core_fck",
1541 .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1544 .slaves = omap44xx_smartreflex_core_slaves,
1545 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
1546 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1549 /* smartreflex_iva */
1550 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
1551 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
1552 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
1555 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
1557 .pa_start = 0x4a0db000,
1558 .pa_end = 0x4a0db03f,
1559 .flags = ADDR_TYPE_RT
1563 /* l4_cfg -> smartreflex_iva */
1564 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
1565 .master = &omap44xx_l4_cfg_hwmod,
1566 .slave = &omap44xx_smartreflex_iva_hwmod,
1568 .addr = omap44xx_smartreflex_iva_addrs,
1569 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
1570 .user = OCP_USER_MPU | OCP_USER_SDMA,
1573 /* smartreflex_iva slave ports */
1574 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
1575 &omap44xx_l4_cfg__smartreflex_iva,
1578 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1579 .name = "smartreflex_iva",
1580 .class = &omap44xx_smartreflex_hwmod_class,
1581 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
1582 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
1583 .main_clk = "smartreflex_iva_fck",
1587 .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1590 .slaves = omap44xx_smartreflex_iva_slaves,
1591 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
1592 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1595 /* smartreflex_mpu */
1596 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
1597 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
1598 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
1601 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
1603 .pa_start = 0x4a0d9000,
1604 .pa_end = 0x4a0d903f,
1605 .flags = ADDR_TYPE_RT
1609 /* l4_cfg -> smartreflex_mpu */
1610 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
1611 .master = &omap44xx_l4_cfg_hwmod,
1612 .slave = &omap44xx_smartreflex_mpu_hwmod,
1614 .addr = omap44xx_smartreflex_mpu_addrs,
1615 .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
1616 .user = OCP_USER_MPU | OCP_USER_SDMA,
1619 /* smartreflex_mpu slave ports */
1620 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
1621 &omap44xx_l4_cfg__smartreflex_mpu,
1624 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1625 .name = "smartreflex_mpu",
1626 .class = &omap44xx_smartreflex_hwmod_class,
1627 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
1628 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
1629 .main_clk = "smartreflex_mpu_fck",
1633 .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
1636 .slaves = omap44xx_smartreflex_mpu_slaves,
1637 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
1638 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1643 * universal asynchronous receiver/transmitter (uart)
1646 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
1648 .sysc_offs = 0x0054,
1649 .syss_offs = 0x0058,
1650 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1651 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1652 SYSS_HAS_RESET_STATUS),
1653 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1655 .sysc_fields = &omap_hwmod_sysc_type1,
1658 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
1660 .sysc = &omap44xx_uart_sysc,
1664 static struct omap_hwmod omap44xx_uart1_hwmod;
1665 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
1666 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
1669 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
1670 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
1671 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
1674 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
1676 .pa_start = 0x4806a000,
1677 .pa_end = 0x4806a0ff,
1678 .flags = ADDR_TYPE_RT
1682 /* l4_per -> uart1 */
1683 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
1684 .master = &omap44xx_l4_per_hwmod,
1685 .slave = &omap44xx_uart1_hwmod,
1687 .addr = omap44xx_uart1_addrs,
1688 .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
1689 .user = OCP_USER_MPU | OCP_USER_SDMA,
1692 /* uart1 slave ports */
1693 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
1694 &omap44xx_l4_per__uart1,
1697 static struct omap_hwmod omap44xx_uart1_hwmod = {
1699 .class = &omap44xx_uart_hwmod_class,
1700 .mpu_irqs = omap44xx_uart1_irqs,
1701 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
1702 .sdma_reqs = omap44xx_uart1_sdma_reqs,
1703 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
1704 .main_clk = "uart1_fck",
1707 .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
1710 .slaves = omap44xx_uart1_slaves,
1711 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
1712 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1716 static struct omap_hwmod omap44xx_uart2_hwmod;
1717 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
1718 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
1721 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
1722 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
1723 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
1726 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
1728 .pa_start = 0x4806c000,
1729 .pa_end = 0x4806c0ff,
1730 .flags = ADDR_TYPE_RT
1734 /* l4_per -> uart2 */
1735 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
1736 .master = &omap44xx_l4_per_hwmod,
1737 .slave = &omap44xx_uart2_hwmod,
1739 .addr = omap44xx_uart2_addrs,
1740 .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
1741 .user = OCP_USER_MPU | OCP_USER_SDMA,
1744 /* uart2 slave ports */
1745 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
1746 &omap44xx_l4_per__uart2,
1749 static struct omap_hwmod omap44xx_uart2_hwmod = {
1751 .class = &omap44xx_uart_hwmod_class,
1752 .mpu_irqs = omap44xx_uart2_irqs,
1753 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
1754 .sdma_reqs = omap44xx_uart2_sdma_reqs,
1755 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
1756 .main_clk = "uart2_fck",
1759 .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
1762 .slaves = omap44xx_uart2_slaves,
1763 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
1764 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1768 static struct omap_hwmod omap44xx_uart3_hwmod;
1769 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
1770 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
1773 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
1774 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
1775 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
1778 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
1780 .pa_start = 0x48020000,
1781 .pa_end = 0x480200ff,
1782 .flags = ADDR_TYPE_RT
1786 /* l4_per -> uart3 */
1787 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
1788 .master = &omap44xx_l4_per_hwmod,
1789 .slave = &omap44xx_uart3_hwmod,
1791 .addr = omap44xx_uart3_addrs,
1792 .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
1793 .user = OCP_USER_MPU | OCP_USER_SDMA,
1796 /* uart3 slave ports */
1797 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
1798 &omap44xx_l4_per__uart3,
1801 static struct omap_hwmod omap44xx_uart3_hwmod = {
1803 .class = &omap44xx_uart_hwmod_class,
1804 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1805 .mpu_irqs = omap44xx_uart3_irqs,
1806 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
1807 .sdma_reqs = omap44xx_uart3_sdma_reqs,
1808 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
1809 .main_clk = "uart3_fck",
1812 .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
1815 .slaves = omap44xx_uart3_slaves,
1816 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
1817 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1821 static struct omap_hwmod omap44xx_uart4_hwmod;
1822 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
1823 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
1826 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
1827 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
1828 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
1831 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
1833 .pa_start = 0x4806e000,
1834 .pa_end = 0x4806e0ff,
1835 .flags = ADDR_TYPE_RT
1839 /* l4_per -> uart4 */
1840 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1841 .master = &omap44xx_l4_per_hwmod,
1842 .slave = &omap44xx_uart4_hwmod,
1844 .addr = omap44xx_uart4_addrs,
1845 .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
1846 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849 /* uart4 slave ports */
1850 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1851 &omap44xx_l4_per__uart4,
1854 static struct omap_hwmod omap44xx_uart4_hwmod = {
1856 .class = &omap44xx_uart_hwmod_class,
1857 .mpu_irqs = omap44xx_uart4_irqs,
1858 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
1859 .sdma_reqs = omap44xx_uart4_sdma_reqs,
1860 .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1861 .main_clk = "uart4_fck",
1864 .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1867 .slaves = omap44xx_uart4_slaves,
1868 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
1869 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1874 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1875 * overflow condition
1878 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1880 .sysc_offs = 0x0010,
1881 .syss_offs = 0x0014,
1882 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1883 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1884 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1886 .sysc_fields = &omap_hwmod_sysc_type1,
1889 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1891 .sysc = &omap44xx_wd_timer_sysc,
1892 .pre_shutdown = &omap2_wd_timer_disable,
1896 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1897 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1898 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1901 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1903 .pa_start = 0x4a314000,
1904 .pa_end = 0x4a31407f,
1905 .flags = ADDR_TYPE_RT
1909 /* l4_wkup -> wd_timer2 */
1910 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1911 .master = &omap44xx_l4_wkup_hwmod,
1912 .slave = &omap44xx_wd_timer2_hwmod,
1913 .clk = "l4_wkup_clk_mux_ck",
1914 .addr = omap44xx_wd_timer2_addrs,
1915 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1916 .user = OCP_USER_MPU | OCP_USER_SDMA,
1919 /* wd_timer2 slave ports */
1920 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1921 &omap44xx_l4_wkup__wd_timer2,
1924 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1925 .name = "wd_timer2",
1926 .class = &omap44xx_wd_timer_hwmod_class,
1927 .mpu_irqs = omap44xx_wd_timer2_irqs,
1928 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1929 .main_clk = "wd_timer2_fck",
1932 .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1935 .slaves = omap44xx_wd_timer2_slaves,
1936 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1937 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1941 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1942 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1943 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1946 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1948 .pa_start = 0x40130000,
1949 .pa_end = 0x4013007f,
1950 .flags = ADDR_TYPE_RT
1954 /* l4_abe -> wd_timer3 */
1955 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1956 .master = &omap44xx_l4_abe_hwmod,
1957 .slave = &omap44xx_wd_timer3_hwmod,
1958 .clk = "ocp_abe_iclk",
1959 .addr = omap44xx_wd_timer3_addrs,
1960 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1961 .user = OCP_USER_MPU,
1964 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1966 .pa_start = 0x49030000,
1967 .pa_end = 0x4903007f,
1968 .flags = ADDR_TYPE_RT
1972 /* l4_abe -> wd_timer3 (dma) */
1973 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1974 .master = &omap44xx_l4_abe_hwmod,
1975 .slave = &omap44xx_wd_timer3_hwmod,
1976 .clk = "ocp_abe_iclk",
1977 .addr = omap44xx_wd_timer3_dma_addrs,
1978 .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1979 .user = OCP_USER_SDMA,
1982 /* wd_timer3 slave ports */
1983 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1984 &omap44xx_l4_abe__wd_timer3,
1985 &omap44xx_l4_abe__wd_timer3_dma,
1988 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1989 .name = "wd_timer3",
1990 .class = &omap44xx_wd_timer_hwmod_class,
1991 .mpu_irqs = omap44xx_wd_timer3_irqs,
1992 .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1993 .main_clk = "wd_timer3_fck",
1996 .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1999 .slaves = omap44xx_wd_timer3_slaves,
2000 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
2001 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2004 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2007 &omap44xx_dmm_hwmod,
2010 &omap44xx_emif_fw_hwmod,
2013 &omap44xx_l3_instr_hwmod,
2014 &omap44xx_l3_main_1_hwmod,
2015 &omap44xx_l3_main_2_hwmod,
2016 &omap44xx_l3_main_3_hwmod,
2019 &omap44xx_l4_abe_hwmod,
2020 &omap44xx_l4_cfg_hwmod,
2021 &omap44xx_l4_per_hwmod,
2022 &omap44xx_l4_wkup_hwmod,
2025 &omap44xx_mpu_private_hwmod,
2028 &omap44xx_dma_system_hwmod,
2031 &omap44xx_dsp_hwmod,
2032 &omap44xx_dsp_c0_hwmod,
2035 &omap44xx_gpio1_hwmod,
2036 &omap44xx_gpio2_hwmod,
2037 &omap44xx_gpio3_hwmod,
2038 &omap44xx_gpio4_hwmod,
2039 &omap44xx_gpio5_hwmod,
2040 &omap44xx_gpio6_hwmod,
2043 &omap44xx_i2c1_hwmod,
2044 &omap44xx_i2c2_hwmod,
2045 &omap44xx_i2c3_hwmod,
2046 &omap44xx_i2c4_hwmod,
2049 &omap44xx_iva_hwmod,
2050 &omap44xx_iva_seq0_hwmod,
2051 &omap44xx_iva_seq1_hwmod,
2054 &omap44xx_mpu_hwmod,
2056 /* smartreflex class */
2057 &omap44xx_smartreflex_core_hwmod,
2058 &omap44xx_smartreflex_iva_hwmod,
2059 &omap44xx_smartreflex_mpu_hwmod,
2062 &omap44xx_uart1_hwmod,
2063 &omap44xx_uart2_hwmod,
2064 &omap44xx_uart3_hwmod,
2065 &omap44xx_uart4_hwmod,
2067 /* wd_timer class */
2068 &omap44xx_wd_timer2_hwmod,
2069 &omap44xx_wd_timer3_hwmod,
2074 int __init omap44xx_hwmod_init(void)
2076 return omap_hwmod_init(omap44xx_hwmods);