arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2010 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27
  28 #include "omap_hwmod_common_data.h"
  29
  30 #include "cm1_44xx.h"
  31 #include "cm2_44xx.h"
  32 #include "prm44xx.h"
  33 #include "prm-regbits-44xx.h"
  34 #include "wd_timer.h"
  35
  36 /* Base offset for all OMAP4 interrupts external to MPUSS */
  37 #define OMAP44XX_IRQ_GIC_START  32
  38
  39 /* Base offset for all OMAP4 dma requests */
  40 #define OMAP44XX_DMA_REQ_START  1
  41
  42 /* Backward references (IPs with Bus Master capability) */
  43 static struct omap_hwmod omap44xx_dma_system_hwmod;
  44 static struct omap_hwmod omap44xx_dmm_hwmod;
  45 static struct omap_hwmod omap44xx_dsp_hwmod;
  46 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  47 static struct omap_hwmod omap44xx_iva_hwmod;
  48 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  49 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  50 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  51 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  52 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  53 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  54 static struct omap_hwmod omap44xx_l4_per_hwmod;
  55 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  56 static struct omap_hwmod omap44xx_mpu_hwmod;
  57 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  58
  59 /*
  60  * Interconnects omap_hwmod structures
  61  * hwmods that compose the global OMAP interconnect
  62  */
  63
  64 /*
  65  * 'dmm' class
  66  * instance(s): dmm
  67  */
  68 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  69         .name = "dmm",
  70 };
  71
  72 /* dmm interface data */
  73 /* l3_main_1 -> dmm */
  74 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  75         .master         = &omap44xx_l3_main_1_hwmod,
  76         .slave          = &omap44xx_dmm_hwmod,
  77         .clk            = "l3_div_ck",
  78         .user           = OCP_USER_SDMA,
  79 };
  80
  81 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  82         {
  83                 .pa_start       = 0x4e000000,
  84                 .pa_end         = 0x4e0007ff,
  85                 .flags          = ADDR_TYPE_RT
  86         },
  87 };
  88
  89 /* mpu -> dmm */
  90 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
  91         .master         = &omap44xx_mpu_hwmod,
  92         .slave          = &omap44xx_dmm_hwmod,
  93         .clk            = "l3_div_ck",
  94         .addr           = omap44xx_dmm_addrs,
  95         .addr_cnt       = ARRAY_SIZE(omap44xx_dmm_addrs),
  96         .user           = OCP_USER_MPU,
  97 };
  98
  99 /* dmm slave ports */
 100 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 101         &omap44xx_l3_main_1__dmm,
 102         &omap44xx_mpu__dmm,
 103 };
 104
 105 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
 106         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
 107 };
 108
 109 static struct omap_hwmod omap44xx_dmm_hwmod = {
 110         .name           = "dmm",
 111         .class          = &omap44xx_dmm_hwmod_class,
 112         .slaves         = omap44xx_dmm_slaves,
 113         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 114         .mpu_irqs       = omap44xx_dmm_irqs,
 115         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dmm_irqs),
 116         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 117 };
 118
 119 /*
 120  * 'emif_fw' class
 121  * instance(s): emif_fw
 122  */
 123 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 124         .name = "emif_fw",
 125 };
 126
 127 /* emif_fw interface data */
 128 /* dmm -> emif_fw */
 129 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 130         .master         = &omap44xx_dmm_hwmod,
 131         .slave          = &omap44xx_emif_fw_hwmod,
 132         .clk            = "l3_div_ck",
 133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 134 };
 135
 136 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 137         {
 138                 .pa_start       = 0x4a20c000,
 139                 .pa_end         = 0x4a20c0ff,
 140                 .flags          = ADDR_TYPE_RT
 141         },
 142 };
 143
 144 /* l4_cfg -> emif_fw */
 145 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 146         .master         = &omap44xx_l4_cfg_hwmod,
 147         .slave          = &omap44xx_emif_fw_hwmod,
 148         .clk            = "l4_div_ck",
 149         .addr           = omap44xx_emif_fw_addrs,
 150         .addr_cnt       = ARRAY_SIZE(omap44xx_emif_fw_addrs),
 151         .user           = OCP_USER_MPU,
 152 };
 153
 154 /* emif_fw slave ports */
 155 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 156         &omap44xx_dmm__emif_fw,
 157         &omap44xx_l4_cfg__emif_fw,
 158 };
 159
 160 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 161         .name           = "emif_fw",
 162         .class          = &omap44xx_emif_fw_hwmod_class,
 163         .slaves         = omap44xx_emif_fw_slaves,
 164         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 165         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 166 };
 167
 168 /*
 169  * 'l3' class
 170  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 171  */
 172 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 173         .name = "l3",
 174 };
 175
 176 /* l3_instr interface data */
 177 /* iva -> l3_instr */
 178 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 179         .master         = &omap44xx_iva_hwmod,
 180         .slave          = &omap44xx_l3_instr_hwmod,
 181         .clk            = "l3_div_ck",
 182         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 183 };
 184
 185 /* l3_main_3 -> l3_instr */
 186 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 187         .master         = &omap44xx_l3_main_3_hwmod,
 188         .slave          = &omap44xx_l3_instr_hwmod,
 189         .clk            = "l3_div_ck",
 190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 191 };
 192
 193 /* l3_instr slave ports */
 194 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 195         &omap44xx_iva__l3_instr,
 196         &omap44xx_l3_main_3__l3_instr,
 197 };
 198
 199 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 200         .name           = "l3_instr",
 201         .class          = &omap44xx_l3_hwmod_class,
 202         .slaves         = omap44xx_l3_instr_slaves,
 203         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 204         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 205 };
 206
 207 /* l3_main_1 interface data */
 208 /* dsp -> l3_main_1 */
 209 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 210         .master         = &omap44xx_dsp_hwmod,
 211         .slave          = &omap44xx_l3_main_1_hwmod,
 212         .clk            = "l3_div_ck",
 213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 214 };
 215
 216 /* l3_main_2 -> l3_main_1 */
 217 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 218         .master         = &omap44xx_l3_main_2_hwmod,
 219         .slave          = &omap44xx_l3_main_1_hwmod,
 220         .clk            = "l3_div_ck",
 221         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 222 };
 223
 224 /* l4_cfg -> l3_main_1 */
 225 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 226         .master         = &omap44xx_l4_cfg_hwmod,
 227         .slave          = &omap44xx_l3_main_1_hwmod,
 228         .clk            = "l4_div_ck",
 229         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 230 };
 231
 232 /* mpu -> l3_main_1 */
 233 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 234         .master         = &omap44xx_mpu_hwmod,
 235         .slave          = &omap44xx_l3_main_1_hwmod,
 236         .clk            = "l3_div_ck",
 237         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 238 };
 239
 240 /* l3_main_1 slave ports */
 241 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 242         &omap44xx_dsp__l3_main_1,
 243         &omap44xx_l3_main_2__l3_main_1,
 244         &omap44xx_l4_cfg__l3_main_1,
 245         &omap44xx_mpu__l3_main_1,
 246 };
 247
 248 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 249         .name           = "l3_main_1",
 250         .class          = &omap44xx_l3_hwmod_class,
 251         .slaves         = omap44xx_l3_main_1_slaves,
 252         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 253         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 254 };
 255
 256 /* l3_main_2 interface data */
 257 /* iva -> l3_main_2 */
 258 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 259         .master         = &omap44xx_iva_hwmod,
 260         .slave          = &omap44xx_l3_main_2_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* l3_main_1 -> l3_main_2 */
 266 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 267         .master         = &omap44xx_l3_main_1_hwmod,
 268         .slave          = &omap44xx_l3_main_2_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* dma_system -> l3_main_2 */
 274 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 275         .master         = &omap44xx_dma_system_hwmod,
 276         .slave          = &omap44xx_l3_main_2_hwmod,
 277         .clk            = "l3_div_ck",
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* l4_cfg -> l3_main_2 */
 282 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 283         .master         = &omap44xx_l4_cfg_hwmod,
 284         .slave          = &omap44xx_l3_main_2_hwmod,
 285         .clk            = "l4_div_ck",
 286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 287 };
 288
 289 /* l3_main_2 slave ports */
 290 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 291         &omap44xx_dma_system__l3_main_2,
 292         &omap44xx_iva__l3_main_2,
 293         &omap44xx_l3_main_1__l3_main_2,
 294         &omap44xx_l4_cfg__l3_main_2,
 295 };
 296
 297 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 298         .name           = "l3_main_2",
 299         .class          = &omap44xx_l3_hwmod_class,
 300         .slaves         = omap44xx_l3_main_2_slaves,
 301         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 302         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 303 };
 304
 305 /* l3_main_3 interface data */
 306 /* l3_main_1 -> l3_main_3 */
 307 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 308         .master         = &omap44xx_l3_main_1_hwmod,
 309         .slave          = &omap44xx_l3_main_3_hwmod,
 310         .clk            = "l3_div_ck",
 311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 312 };
 313
 314 /* l3_main_2 -> l3_main_3 */
 315 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 316         .master         = &omap44xx_l3_main_2_hwmod,
 317         .slave          = &omap44xx_l3_main_3_hwmod,
 318         .clk            = "l3_div_ck",
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* l4_cfg -> l3_main_3 */
 323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 324         .master         = &omap44xx_l4_cfg_hwmod,
 325         .slave          = &omap44xx_l3_main_3_hwmod,
 326         .clk            = "l4_div_ck",
 327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 328 };
 329
 330 /* l3_main_3 slave ports */
 331 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 332         &omap44xx_l3_main_1__l3_main_3,
 333         &omap44xx_l3_main_2__l3_main_3,
 334         &omap44xx_l4_cfg__l3_main_3,
 335 };
 336
 337 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 338         .name           = "l3_main_3",
 339         .class          = &omap44xx_l3_hwmod_class,
 340         .slaves         = omap44xx_l3_main_3_slaves,
 341         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 342         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 343 };
 344
 345 /*
 346  * 'l4' class
 347  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 348  */
 349 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 350         .name = "l4",
 351 };
 352
 353 /* l4_abe interface data */
 354 /* dsp -> l4_abe */
 355 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 356         .master         = &omap44xx_dsp_hwmod,
 357         .slave          = &omap44xx_l4_abe_hwmod,
 358         .clk            = "ocp_abe_iclk",
 359         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 360 };
 361
 362 /* l3_main_1 -> l4_abe */
 363 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 364         .master         = &omap44xx_l3_main_1_hwmod,
 365         .slave          = &omap44xx_l4_abe_hwmod,
 366         .clk            = "l3_div_ck",
 367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 368 };
 369
 370 /* mpu -> l4_abe */
 371 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 372         .master         = &omap44xx_mpu_hwmod,
 373         .slave          = &omap44xx_l4_abe_hwmod,
 374         .clk            = "ocp_abe_iclk",
 375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 376 };
 377
 378 /* l4_abe slave ports */
 379 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 380         &omap44xx_dsp__l4_abe,
 381         &omap44xx_l3_main_1__l4_abe,
 382         &omap44xx_mpu__l4_abe,
 383 };
 384
 385 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 386         .name           = "l4_abe",
 387         .class          = &omap44xx_l4_hwmod_class,
 388         .slaves         = omap44xx_l4_abe_slaves,
 389         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 390         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 391 };
 392
 393 /* l4_cfg interface data */
 394 /* l3_main_1 -> l4_cfg */
 395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 396         .master         = &omap44xx_l3_main_1_hwmod,
 397         .slave          = &omap44xx_l4_cfg_hwmod,
 398         .clk            = "l3_div_ck",
 399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 400 };
 401
 402 /* l4_cfg slave ports */
 403 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 404         &omap44xx_l3_main_1__l4_cfg,
 405 };
 406
 407 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 408         .name           = "l4_cfg",
 409         .class          = &omap44xx_l4_hwmod_class,
 410         .slaves         = omap44xx_l4_cfg_slaves,
 411         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 412         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 413 };
 414
 415 /* l4_per interface data */
 416 /* l3_main_2 -> l4_per */
 417 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 418         .master         = &omap44xx_l3_main_2_hwmod,
 419         .slave          = &omap44xx_l4_per_hwmod,
 420         .clk            = "l3_div_ck",
 421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 422 };
 423
 424 /* l4_per slave ports */
 425 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 426         &omap44xx_l3_main_2__l4_per,
 427 };
 428
 429 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 430         .name           = "l4_per",
 431         .class          = &omap44xx_l4_hwmod_class,
 432         .slaves         = omap44xx_l4_per_slaves,
 433         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 434         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 435 };
 436
 437 /* l4_wkup interface data */
 438 /* l4_cfg -> l4_wkup */
 439 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 440         .master         = &omap44xx_l4_cfg_hwmod,
 441         .slave          = &omap44xx_l4_wkup_hwmod,
 442         .clk            = "l4_div_ck",
 443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 444 };
 445
 446 /* l4_wkup slave ports */
 447 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 448         &omap44xx_l4_cfg__l4_wkup,
 449 };
 450
 451 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 452         .name           = "l4_wkup",
 453         .class          = &omap44xx_l4_hwmod_class,
 454         .slaves         = omap44xx_l4_wkup_slaves,
 455         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 456         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 457 };
 458
 459 /*
 460  * 'mpu_bus' class
 461  * instance(s): mpu_private
 462  */
 463 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 464         .name = "mpu_bus",
 465 };
 466
 467 /* mpu_private interface data */
 468 /* mpu -> mpu_private */
 469 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 470         .master         = &omap44xx_mpu_hwmod,
 471         .slave          = &omap44xx_mpu_private_hwmod,
 472         .clk            = "l3_div_ck",
 473         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 474 };
 475
 476 /* mpu_private slave ports */
 477 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 478         &omap44xx_mpu__mpu_private,
 479 };
 480
 481 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 482         .name           = "mpu_private",
 483         .class          = &omap44xx_mpu_bus_hwmod_class,
 484         .slaves         = omap44xx_mpu_private_slaves,
 485         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 486         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 487 };
 488
 489 /*
 490  * Modules omap_hwmod structures
 491  *
 492  * The following IPs are excluded for the moment because:
 493  * - They do not need an explicit SW control using omap_hwmod API.
 494  * - They still need to be validated with the driver
 495  *   properly adapted to omap_hwmod / omap_device
 496  *
 497  *  aess
 498  *  bandgap
 499  *  c2c
 500  *  c2c_target_fw
 501  *  cm_core
 502  *  cm_core_aon
 503  *  counter_32k
 504  *  ctrl_module_core
 505  *  ctrl_module_pad_core
 506  *  ctrl_module_pad_wkup
 507  *  ctrl_module_wkup
 508  *  debugss
 509  *  dma_system
 510  *  dmic
 511  *  dss
 512  *  dss_dispc
 513  *  dss_dsi1
 514  *  dss_dsi2
 515  *  dss_hdmi
 516  *  dss_rfbi
 517  *  dss_venc
 518  *  efuse_ctrl_cust
 519  *  efuse_ctrl_std
 520  *  elm
 521  *  emif1
 522  *  emif2
 523  *  fdif
 524  *  gpmc
 525  *  gpu
 526  *  hdq1w
 527  *  hsi
 528  *  ipu
 529  *  iss
 530  *  kbd
 531  *  mailbox
 532  *  mcasp
 533  *  mcbsp1
 534  *  mcbsp2
 535  *  mcbsp3
 536  *  mcbsp4
 537  *  mcpdm
 538  *  mcspi1
 539  *  mcspi2
 540  *  mcspi3
 541  *  mcspi4
 542  *  mmc1
 543  *  mmc2
 544  *  mmc3
 545  *  mmc4
 546  *  mmc5
 547  *  mpu_c0
 548  *  mpu_c1
 549  *  ocmc_ram
 550  *  ocp2scp_usb_phy
 551  *  ocp_wp_noc
 552  *  prcm
 553  *  prcm_mpu
 554  *  prm
 555  *  scrm
 556  *  sl2if
 557  *  slimbus1
 558  *  slimbus2
 559  *  smartreflex_core
 560  *  smartreflex_iva
 561  *  smartreflex_mpu
 562  *  spinlock
 563  *  timer1
 564  *  timer10
 565  *  timer11
 566  *  timer2
 567  *  timer3
 568  *  timer4
 569  *  timer5
 570  *  timer6
 571  *  timer7
 572  *  timer8
 573  *  timer9
 574  *  usb_host_fs
 575  *  usb_host_hs
 576  *  usb_otg_hs
 577  *  usb_phy_cm
 578  *  usb_tll_hs
 579  *  usim
 580  */
 581
 582 /*
 583  * 'dsp' class
 584  * dsp sub-system
 585  */
 586
 587 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 588         .name = "dsp",
 589 };
 590
 591 /* dsp */
 592 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 593         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 594 };
 595
 596 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 597         { .name = "mmu_cache", .rst_shift = 1 },
 598 };
 599
 600 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
 601         { .name = "dsp", .rst_shift = 0 },
 602 };
 603
 604 /* dsp -> iva */
 605 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 606         .master         = &omap44xx_dsp_hwmod,
 607         .slave          = &omap44xx_iva_hwmod,
 608         .clk            = "dpll_iva_m5x2_ck",
 609 };
 610
 611 /* dsp master ports */
 612 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
 613         &omap44xx_dsp__l3_main_1,
 614         &omap44xx_dsp__l4_abe,
 615         &omap44xx_dsp__iva,
 616 };
 617
 618 /* l4_cfg -> dsp */
 619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
 620         .master         = &omap44xx_l4_cfg_hwmod,
 621         .slave          = &omap44xx_dsp_hwmod,
 622         .clk            = "l4_div_ck",
 623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 624 };
 625
 626 /* dsp slave ports */
 627 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
 628         &omap44xx_l4_cfg__dsp,
 629 };
 630
 631 /* Pseudo hwmod for reset control purpose only */
 632 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
 633         .name           = "dsp_c0",
 634         .class          = &omap44xx_dsp_hwmod_class,
 635         .flags          = HWMOD_INIT_NO_RESET,
 636         .rst_lines      = omap44xx_dsp_c0_resets,
 637         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
 638         .prcm = {
 639                 .omap4 = {
 640                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 641                 },
 642         },
 643         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 644 };
 645
 646 static struct omap_hwmod omap44xx_dsp_hwmod = {
 647         .name           = "dsp",
 648         .class          = &omap44xx_dsp_hwmod_class,
 649         .mpu_irqs       = omap44xx_dsp_irqs,
 650         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dsp_irqs),
 651         .rst_lines      = omap44xx_dsp_resets,
 652         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 653         .main_clk       = "dsp_fck",
 654         .prcm = {
 655                 .omap4 = {
 656                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
 657                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
 658                 },
 659         },
 660         .slaves         = omap44xx_dsp_slaves,
 661         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
 662         .masters        = omap44xx_dsp_masters,
 663         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
 664         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 665 };
 666
 667 /*
 668  * 'gpio' class
 669  * general purpose io module
 670  */
 671
 672 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
 673         .rev_offs       = 0x0000,
 674         .sysc_offs      = 0x0010,
 675         .syss_offs      = 0x0114,
 676         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 677                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 678                            SYSS_HAS_RESET_STATUS),
 679         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 680                            SIDLE_SMART_WKUP),
 681         .sysc_fields    = &omap_hwmod_sysc_type1,
 682 };
 683
 684 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
 685         .name = "gpio",
 686         .sysc = &omap44xx_gpio_sysc,
 687         .rev = 2,
 688 };
 689
 690 /* gpio dev_attr */
 691 static struct omap_gpio_dev_attr gpio_dev_attr = {
 692         .bank_width = 32,
 693         .dbck_flag = true,
 694 };
 695
 696 /* gpio1 */
 697 static struct omap_hwmod omap44xx_gpio1_hwmod;
 698 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
 699         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
 700 };
 701
 702 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
 703         {
 704                 .pa_start       = 0x4a310000,
 705                 .pa_end         = 0x4a3101ff,
 706                 .flags          = ADDR_TYPE_RT
 707         },
 708 };
 709
 710 /* l4_wkup -> gpio1 */
 711 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
 712         .master         = &omap44xx_l4_wkup_hwmod,
 713         .slave          = &omap44xx_gpio1_hwmod,
 714         .clk            = "l4_wkup_clk_mux_ck",
 715         .addr           = omap44xx_gpio1_addrs,
 716         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio1_addrs),
 717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 718 };
 719
 720 /* gpio1 slave ports */
 721 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
 722         &omap44xx_l4_wkup__gpio1,
 723 };
 724
 725 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 726         { .role = "dbclk", .clk = "gpio1_dbclk" },
 727 };
 728
 729 static struct omap_hwmod omap44xx_gpio1_hwmod = {
 730         .name           = "gpio1",
 731         .class          = &omap44xx_gpio_hwmod_class,
 732         .mpu_irqs       = omap44xx_gpio1_irqs,
 733         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio1_irqs),
 734         .main_clk       = "gpio1_ick",
 735         .prcm = {
 736                 .omap4 = {
 737                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
 738                 },
 739         },
 740         .opt_clks       = gpio1_opt_clks,
 741         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 742         .dev_attr       = &gpio_dev_attr,
 743         .slaves         = omap44xx_gpio1_slaves,
 744         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
 745         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 746 };
 747
 748 /* gpio2 */
 749 static struct omap_hwmod omap44xx_gpio2_hwmod;
 750 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
 751         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
 752 };
 753
 754 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
 755         {
 756                 .pa_start       = 0x48055000,
 757                 .pa_end         = 0x480551ff,
 758                 .flags          = ADDR_TYPE_RT
 759         },
 760 };
 761
 762 /* l4_per -> gpio2 */
 763 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
 764         .master         = &omap44xx_l4_per_hwmod,
 765         .slave          = &omap44xx_gpio2_hwmod,
 766         .clk            = "l4_div_ck",
 767         .addr           = omap44xx_gpio2_addrs,
 768         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio2_addrs),
 769         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 770 };
 771
 772 /* gpio2 slave ports */
 773 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
 774         &omap44xx_l4_per__gpio2,
 775 };
 776
 777 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 778         { .role = "dbclk", .clk = "gpio2_dbclk" },
 779 };
 780
 781 static struct omap_hwmod omap44xx_gpio2_hwmod = {
 782         .name           = "gpio2",
 783         .class          = &omap44xx_gpio_hwmod_class,
 784         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 785         .mpu_irqs       = omap44xx_gpio2_irqs,
 786         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio2_irqs),
 787         .main_clk       = "gpio2_ick",
 788         .prcm = {
 789                 .omap4 = {
 790                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
 791                 },
 792         },
 793         .opt_clks       = gpio2_opt_clks,
 794         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 795         .dev_attr       = &gpio_dev_attr,
 796         .slaves         = omap44xx_gpio2_slaves,
 797         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
 798         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 799 };
 800
 801 /* gpio3 */
 802 static struct omap_hwmod omap44xx_gpio3_hwmod;
 803 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
 804         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
 805 };
 806
 807 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
 808         {
 809                 .pa_start       = 0x48057000,
 810                 .pa_end         = 0x480571ff,
 811                 .flags          = ADDR_TYPE_RT
 812         },
 813 };
 814
 815 /* l4_per -> gpio3 */
 816 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
 817         .master         = &omap44xx_l4_per_hwmod,
 818         .slave          = &omap44xx_gpio3_hwmod,
 819         .clk            = "l4_div_ck",
 820         .addr           = omap44xx_gpio3_addrs,
 821         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio3_addrs),
 822         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 823 };
 824
 825 /* gpio3 slave ports */
 826 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
 827         &omap44xx_l4_per__gpio3,
 828 };
 829
 830 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 831         { .role = "dbclk", .clk = "gpio3_dbclk" },
 832 };
 833
 834 static struct omap_hwmod omap44xx_gpio3_hwmod = {
 835         .name           = "gpio3",
 836         .class          = &omap44xx_gpio_hwmod_class,
 837         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 838         .mpu_irqs       = omap44xx_gpio3_irqs,
 839         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio3_irqs),
 840         .main_clk       = "gpio3_ick",
 841         .prcm = {
 842                 .omap4 = {
 843                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
 844                 },
 845         },
 846         .opt_clks       = gpio3_opt_clks,
 847         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 848         .dev_attr       = &gpio_dev_attr,
 849         .slaves         = omap44xx_gpio3_slaves,
 850         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
 851         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 852 };
 853
 854 /* gpio4 */
 855 static struct omap_hwmod omap44xx_gpio4_hwmod;
 856 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
 857         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
 858 };
 859
 860 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
 861         {
 862                 .pa_start       = 0x48059000,
 863                 .pa_end         = 0x480591ff,
 864                 .flags          = ADDR_TYPE_RT
 865         },
 866 };
 867
 868 /* l4_per -> gpio4 */
 869 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
 870         .master         = &omap44xx_l4_per_hwmod,
 871         .slave          = &omap44xx_gpio4_hwmod,
 872         .clk            = "l4_div_ck",
 873         .addr           = omap44xx_gpio4_addrs,
 874         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio4_addrs),
 875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 876 };
 877
 878 /* gpio4 slave ports */
 879 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
 880         &omap44xx_l4_per__gpio4,
 881 };
 882
 883 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 884         { .role = "dbclk", .clk = "gpio4_dbclk" },
 885 };
 886
 887 static struct omap_hwmod omap44xx_gpio4_hwmod = {
 888         .name           = "gpio4",
 889         .class          = &omap44xx_gpio_hwmod_class,
 890         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 891         .mpu_irqs       = omap44xx_gpio4_irqs,
 892         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio4_irqs),
 893         .main_clk       = "gpio4_ick",
 894         .prcm = {
 895                 .omap4 = {
 896                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
 897                 },
 898         },
 899         .opt_clks       = gpio4_opt_clks,
 900         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 901         .dev_attr       = &gpio_dev_attr,
 902         .slaves         = omap44xx_gpio4_slaves,
 903         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
 904         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 905 };
 906
 907 /* gpio5 */
 908 static struct omap_hwmod omap44xx_gpio5_hwmod;
 909 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
 910         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
 911 };
 912
 913 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
 914         {
 915                 .pa_start       = 0x4805b000,
 916                 .pa_end         = 0x4805b1ff,
 917                 .flags          = ADDR_TYPE_RT
 918         },
 919 };
 920
 921 /* l4_per -> gpio5 */
 922 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
 923         .master         = &omap44xx_l4_per_hwmod,
 924         .slave          = &omap44xx_gpio5_hwmod,
 925         .clk            = "l4_div_ck",
 926         .addr           = omap44xx_gpio5_addrs,
 927         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio5_addrs),
 928         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 929 };
 930
 931 /* gpio5 slave ports */
 932 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
 933         &omap44xx_l4_per__gpio5,
 934 };
 935
 936 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 937         { .role = "dbclk", .clk = "gpio5_dbclk" },
 938 };
 939
 940 static struct omap_hwmod omap44xx_gpio5_hwmod = {
 941         .name           = "gpio5",
 942         .class          = &omap44xx_gpio_hwmod_class,
 943         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 944         .mpu_irqs       = omap44xx_gpio5_irqs,
 945         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio5_irqs),
 946         .main_clk       = "gpio5_ick",
 947         .prcm = {
 948                 .omap4 = {
 949                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
 950                 },
 951         },
 952         .opt_clks       = gpio5_opt_clks,
 953         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 954         .dev_attr       = &gpio_dev_attr,
 955         .slaves         = omap44xx_gpio5_slaves,
 956         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
 957         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 958 };
 959
 960 /* gpio6 */
 961 static struct omap_hwmod omap44xx_gpio6_hwmod;
 962 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
 963         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
 964 };
 965
 966 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
 967         {
 968                 .pa_start       = 0x4805d000,
 969                 .pa_end         = 0x4805d1ff,
 970                 .flags          = ADDR_TYPE_RT
 971         },
 972 };
 973
 974 /* l4_per -> gpio6 */
 975 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
 976         .master         = &omap44xx_l4_per_hwmod,
 977         .slave          = &omap44xx_gpio6_hwmod,
 978         .clk            = "l4_div_ck",
 979         .addr           = omap44xx_gpio6_addrs,
 980         .addr_cnt       = ARRAY_SIZE(omap44xx_gpio6_addrs),
 981         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 982 };
 983
 984 /* gpio6 slave ports */
 985 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
 986         &omap44xx_l4_per__gpio6,
 987 };
 988
 989 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 990         { .role = "dbclk", .clk = "gpio6_dbclk" },
 991 };
 992
 993 static struct omap_hwmod omap44xx_gpio6_hwmod = {
 994         .name           = "gpio6",
 995         .class          = &omap44xx_gpio_hwmod_class,
 996         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 997         .mpu_irqs       = omap44xx_gpio6_irqs,
 998         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_gpio6_irqs),
 999         .main_clk       = "gpio6_ick",
1000         .prcm = {
1001                 .omap4 = {
1002                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1003                 },
1004         },
1005         .opt_clks       = gpio6_opt_clks,
1006         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1007         .dev_attr       = &gpio_dev_attr,
1008         .slaves         = omap44xx_gpio6_slaves,
1009         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
1010         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1011 };
1012
1013 /*
1014  * 'i2c' class
1015  * multimaster high-speed i2c controller
1016  */
1017
1018 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1019         .sysc_offs      = 0x0010,
1020         .syss_offs      = 0x0090,
1021         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1022                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1023                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1024         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1025                            SIDLE_SMART_WKUP),
1026         .sysc_fields    = &omap_hwmod_sysc_type1,
1027 };
1028
1029 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1030         .name = "i2c",
1031         .sysc = &omap44xx_i2c_sysc,
1032 };
1033
1034 /* i2c1 */
1035 static struct omap_hwmod omap44xx_i2c1_hwmod;
1036 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1037         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1038 };
1039
1040 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1041         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1042         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1043 };
1044
1045 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1046         {
1047                 .pa_start       = 0x48070000,
1048                 .pa_end         = 0x480700ff,
1049                 .flags          = ADDR_TYPE_RT
1050         },
1051 };
1052
1053 /* l4_per -> i2c1 */
1054 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1055         .master         = &omap44xx_l4_per_hwmod,
1056         .slave          = &omap44xx_i2c1_hwmod,
1057         .clk            = "l4_div_ck",
1058         .addr           = omap44xx_i2c1_addrs,
1059         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c1_addrs),
1060         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1061 };
1062
1063 /* i2c1 slave ports */
1064 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
1065         &omap44xx_l4_per__i2c1,
1066 };
1067
1068 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1069         .name           = "i2c1",
1070         .class          = &omap44xx_i2c_hwmod_class,
1071         .flags          = HWMOD_INIT_NO_RESET,
1072         .mpu_irqs       = omap44xx_i2c1_irqs,
1073         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c1_irqs),
1074         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1075         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
1076         .main_clk       = "i2c1_fck",
1077         .prcm = {
1078                 .omap4 = {
1079                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1080                 },
1081         },
1082         .slaves         = omap44xx_i2c1_slaves,
1083         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
1084         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1085 };
1086
1087 /* i2c2 */
1088 static struct omap_hwmod omap44xx_i2c2_hwmod;
1089 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1090         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
1091 };
1092
1093 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
1094         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
1095         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
1096 };
1097
1098 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
1099         {
1100                 .pa_start       = 0x48072000,
1101                 .pa_end         = 0x480720ff,
1102                 .flags          = ADDR_TYPE_RT
1103         },
1104 };
1105
1106 /* l4_per -> i2c2 */
1107 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
1108         .master         = &omap44xx_l4_per_hwmod,
1109         .slave          = &omap44xx_i2c2_hwmod,
1110         .clk            = "l4_div_ck",
1111         .addr           = omap44xx_i2c2_addrs,
1112         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c2_addrs),
1113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1114 };
1115
1116 /* i2c2 slave ports */
1117 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
1118         &omap44xx_l4_per__i2c2,
1119 };
1120
1121 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1122         .name           = "i2c2",
1123         .class          = &omap44xx_i2c_hwmod_class,
1124         .flags          = HWMOD_INIT_NO_RESET,
1125         .mpu_irqs       = omap44xx_i2c2_irqs,
1126         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c2_irqs),
1127         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
1128         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
1129         .main_clk       = "i2c2_fck",
1130         .prcm = {
1131                 .omap4 = {
1132                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1133                 },
1134         },
1135         .slaves         = omap44xx_i2c2_slaves,
1136         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
1137         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1138 };
1139
1140 /* i2c3 */
1141 static struct omap_hwmod omap44xx_i2c3_hwmod;
1142 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
1143         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
1144 };
1145
1146 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
1147         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
1148         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
1149 };
1150
1151 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
1152         {
1153                 .pa_start       = 0x48060000,
1154                 .pa_end         = 0x480600ff,
1155                 .flags          = ADDR_TYPE_RT
1156         },
1157 };
1158
1159 /* l4_per -> i2c3 */
1160 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
1161         .master         = &omap44xx_l4_per_hwmod,
1162         .slave          = &omap44xx_i2c3_hwmod,
1163         .clk            = "l4_div_ck",
1164         .addr           = omap44xx_i2c3_addrs,
1165         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c3_addrs),
1166         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1167 };
1168
1169 /* i2c3 slave ports */
1170 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
1171         &omap44xx_l4_per__i2c3,
1172 };
1173
1174 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1175         .name           = "i2c3",
1176         .class          = &omap44xx_i2c_hwmod_class,
1177         .flags          = HWMOD_INIT_NO_RESET,
1178         .mpu_irqs       = omap44xx_i2c3_irqs,
1179         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c3_irqs),
1180         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
1181         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
1182         .main_clk       = "i2c3_fck",
1183         .prcm = {
1184                 .omap4 = {
1185                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1186                 },
1187         },
1188         .slaves         = omap44xx_i2c3_slaves,
1189         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
1190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1191 };
1192
1193 /* i2c4 */
1194 static struct omap_hwmod omap44xx_i2c4_hwmod;
1195 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
1196         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
1197 };
1198
1199 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
1200         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
1201         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
1202 };
1203
1204 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
1205         {
1206                 .pa_start       = 0x48350000,
1207                 .pa_end         = 0x483500ff,
1208                 .flags          = ADDR_TYPE_RT
1209         },
1210 };
1211
1212 /* l4_per -> i2c4 */
1213 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
1214         .master         = &omap44xx_l4_per_hwmod,
1215         .slave          = &omap44xx_i2c4_hwmod,
1216         .clk            = "l4_div_ck",
1217         .addr           = omap44xx_i2c4_addrs,
1218         .addr_cnt       = ARRAY_SIZE(omap44xx_i2c4_addrs),
1219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1220 };
1221
1222 /* i2c4 slave ports */
1223 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
1224         &omap44xx_l4_per__i2c4,
1225 };
1226
1227 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1228         .name           = "i2c4",
1229         .class          = &omap44xx_i2c_hwmod_class,
1230         .flags          = HWMOD_INIT_NO_RESET,
1231         .mpu_irqs       = omap44xx_i2c4_irqs,
1232         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_i2c4_irqs),
1233         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
1234         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
1235         .main_clk       = "i2c4_fck",
1236         .prcm = {
1237                 .omap4 = {
1238                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1239                 },
1240         },
1241         .slaves         = omap44xx_i2c4_slaves,
1242         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
1243         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1244 };
1245
1246 /*
1247  * 'iva' class
1248  * multi-standard video encoder/decoder hardware accelerator
1249  */
1250
1251 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1252         .name = "iva",
1253 };
1254
1255 /* iva */
1256 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
1257         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
1258         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
1259         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
1260 };
1261
1262 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1263         { .name = "logic", .rst_shift = 2 },
1264 };
1265
1266 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
1267         { .name = "seq0", .rst_shift = 0 },
1268 };
1269
1270 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
1271         { .name = "seq1", .rst_shift = 1 },
1272 };
1273
1274 /* iva master ports */
1275 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
1276         &omap44xx_iva__l3_main_2,
1277         &omap44xx_iva__l3_instr,
1278 };
1279
1280 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
1281         {
1282                 .pa_start       = 0x5a000000,
1283                 .pa_end         = 0x5a07ffff,
1284                 .flags          = ADDR_TYPE_RT
1285         },
1286 };
1287
1288 /* l3_main_2 -> iva */
1289 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
1290         .master         = &omap44xx_l3_main_2_hwmod,
1291         .slave          = &omap44xx_iva_hwmod,
1292         .clk            = "l3_div_ck",
1293         .addr           = omap44xx_iva_addrs,
1294         .addr_cnt       = ARRAY_SIZE(omap44xx_iva_addrs),
1295         .user           = OCP_USER_MPU,
1296 };
1297
1298 /* iva slave ports */
1299 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
1300         &omap44xx_dsp__iva,
1301         &omap44xx_l3_main_2__iva,
1302 };
1303
1304 /* Pseudo hwmod for reset control purpose only */
1305 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
1306         .name           = "iva_seq0",
1307         .class          = &omap44xx_iva_hwmod_class,
1308         .flags          = HWMOD_INIT_NO_RESET,
1309         .rst_lines      = omap44xx_iva_seq0_resets,
1310         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
1311         .prcm = {
1312                 .omap4 = {
1313                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1314                 },
1315         },
1316         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1317 };
1318
1319 /* Pseudo hwmod for reset control purpose only */
1320 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
1321         .name           = "iva_seq1",
1322         .class          = &omap44xx_iva_hwmod_class,
1323         .flags          = HWMOD_INIT_NO_RESET,
1324         .rst_lines      = omap44xx_iva_seq1_resets,
1325         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
1326         .prcm = {
1327                 .omap4 = {
1328                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1329                 },
1330         },
1331         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1332 };
1333
1334 static struct omap_hwmod omap44xx_iva_hwmod = {
1335         .name           = "iva",
1336         .class          = &omap44xx_iva_hwmod_class,
1337         .mpu_irqs       = omap44xx_iva_irqs,
1338         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_iva_irqs),
1339         .rst_lines      = omap44xx_iva_resets,
1340         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
1341         .main_clk       = "iva_fck",
1342         .prcm = {
1343                 .omap4 = {
1344                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1345                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
1346                 },
1347         },
1348         .slaves         = omap44xx_iva_slaves,
1349         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
1350         .masters        = omap44xx_iva_masters,
1351         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
1352         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1353 };
1354
1355 /*
1356  * 'mpu' class
1357  * mpu sub-system
1358  */
1359
1360 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
1361         .name = "mpu",
1362 };
1363
1364 /* mpu */
1365 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
1366         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
1367         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
1368         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
1369 };
1370
1371 /* mpu master ports */
1372 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
1373         &omap44xx_mpu__l3_main_1,
1374         &omap44xx_mpu__l4_abe,
1375         &omap44xx_mpu__dmm,
1376 };
1377
1378 static struct omap_hwmod omap44xx_mpu_hwmod = {
1379         .name           = "mpu",
1380         .class          = &omap44xx_mpu_hwmod_class,
1381         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1382         .mpu_irqs       = omap44xx_mpu_irqs,
1383         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mpu_irqs),
1384         .main_clk       = "dpll_mpu_m2_ck",
1385         .prcm = {
1386                 .omap4 = {
1387                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
1388                 },
1389         },
1390         .masters        = omap44xx_mpu_masters,
1391         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
1392         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1393 };
1394
1395 /*
1396  * 'uart' class
1397  * universal asynchronous receiver/transmitter (uart)
1398  */
1399
1400 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
1401         .rev_offs       = 0x0050,
1402         .sysc_offs      = 0x0054,
1403         .syss_offs      = 0x0058,
1404         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1405                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1406                            SYSS_HAS_RESET_STATUS),
1407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408                            SIDLE_SMART_WKUP),
1409         .sysc_fields    = &omap_hwmod_sysc_type1,
1410 };
1411
1412 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
1413         .name = "uart",
1414         .sysc = &omap44xx_uart_sysc,
1415 };
1416
1417 /* uart1 */
1418 static struct omap_hwmod omap44xx_uart1_hwmod;
1419 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
1420         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
1421 };
1422
1423 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
1424         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
1425         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
1426 };
1427
1428 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
1429         {
1430                 .pa_start       = 0x4806a000,
1431                 .pa_end         = 0x4806a0ff,
1432                 .flags          = ADDR_TYPE_RT
1433         },
1434 };
1435
1436 /* l4_per -> uart1 */
1437 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
1438         .master         = &omap44xx_l4_per_hwmod,
1439         .slave          = &omap44xx_uart1_hwmod,
1440         .clk            = "l4_div_ck",
1441         .addr           = omap44xx_uart1_addrs,
1442         .addr_cnt       = ARRAY_SIZE(omap44xx_uart1_addrs),
1443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1444 };
1445
1446 /* uart1 slave ports */
1447 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
1448         &omap44xx_l4_per__uart1,
1449 };
1450
1451 static struct omap_hwmod omap44xx_uart1_hwmod = {
1452         .name           = "uart1",
1453         .class          = &omap44xx_uart_hwmod_class,
1454         .mpu_irqs       = omap44xx_uart1_irqs,
1455         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart1_irqs),
1456         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
1457         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
1458         .main_clk       = "uart1_fck",
1459         .prcm = {
1460                 .omap4 = {
1461                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
1462                 },
1463         },
1464         .slaves         = omap44xx_uart1_slaves,
1465         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
1466         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1467 };
1468
1469 /* uart2 */
1470 static struct omap_hwmod omap44xx_uart2_hwmod;
1471 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
1472         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
1473 };
1474
1475 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
1476         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
1477         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
1478 };
1479
1480 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
1481         {
1482                 .pa_start       = 0x4806c000,
1483                 .pa_end         = 0x4806c0ff,
1484                 .flags          = ADDR_TYPE_RT
1485         },
1486 };
1487
1488 /* l4_per -> uart2 */
1489 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
1490         .master         = &omap44xx_l4_per_hwmod,
1491         .slave          = &omap44xx_uart2_hwmod,
1492         .clk            = "l4_div_ck",
1493         .addr           = omap44xx_uart2_addrs,
1494         .addr_cnt       = ARRAY_SIZE(omap44xx_uart2_addrs),
1495         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1496 };
1497
1498 /* uart2 slave ports */
1499 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
1500         &omap44xx_l4_per__uart2,
1501 };
1502
1503 static struct omap_hwmod omap44xx_uart2_hwmod = {
1504         .name           = "uart2",
1505         .class          = &omap44xx_uart_hwmod_class,
1506         .mpu_irqs       = omap44xx_uart2_irqs,
1507         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart2_irqs),
1508         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
1509         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
1510         .main_clk       = "uart2_fck",
1511         .prcm = {
1512                 .omap4 = {
1513                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
1514                 },
1515         },
1516         .slaves         = omap44xx_uart2_slaves,
1517         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
1518         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1519 };
1520
1521 /* uart3 */
1522 static struct omap_hwmod omap44xx_uart3_hwmod;
1523 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
1524         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
1525 };
1526
1527 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
1528         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
1529         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
1530 };
1531
1532 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
1533         {
1534                 .pa_start       = 0x48020000,
1535                 .pa_end         = 0x480200ff,
1536                 .flags          = ADDR_TYPE_RT
1537         },
1538 };
1539
1540 /* l4_per -> uart3 */
1541 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
1542         .master         = &omap44xx_l4_per_hwmod,
1543         .slave          = &omap44xx_uart3_hwmod,
1544         .clk            = "l4_div_ck",
1545         .addr           = omap44xx_uart3_addrs,
1546         .addr_cnt       = ARRAY_SIZE(omap44xx_uart3_addrs),
1547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1548 };
1549
1550 /* uart3 slave ports */
1551 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
1552         &omap44xx_l4_per__uart3,
1553 };
1554
1555 static struct omap_hwmod omap44xx_uart3_hwmod = {
1556         .name           = "uart3",
1557         .class          = &omap44xx_uart_hwmod_class,
1558         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1559         .mpu_irqs       = omap44xx_uart3_irqs,
1560         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart3_irqs),
1561         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
1562         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
1563         .main_clk       = "uart3_fck",
1564         .prcm = {
1565                 .omap4 = {
1566                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
1567                 },
1568         },
1569         .slaves         = omap44xx_uart3_slaves,
1570         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
1571         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1572 };
1573
1574 /* uart4 */
1575 static struct omap_hwmod omap44xx_uart4_hwmod;
1576 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
1577         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
1578 };
1579
1580 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
1581         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
1582         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
1583 };
1584
1585 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
1586         {
1587                 .pa_start       = 0x4806e000,
1588                 .pa_end         = 0x4806e0ff,
1589                 .flags          = ADDR_TYPE_RT
1590         },
1591 };
1592
1593 /* l4_per -> uart4 */
1594 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
1595         .master         = &omap44xx_l4_per_hwmod,
1596         .slave          = &omap44xx_uart4_hwmod,
1597         .clk            = "l4_div_ck",
1598         .addr           = omap44xx_uart4_addrs,
1599         .addr_cnt       = ARRAY_SIZE(omap44xx_uart4_addrs),
1600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1601 };
1602
1603 /* uart4 slave ports */
1604 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
1605         &omap44xx_l4_per__uart4,
1606 };
1607
1608 static struct omap_hwmod omap44xx_uart4_hwmod = {
1609         .name           = "uart4",
1610         .class          = &omap44xx_uart_hwmod_class,
1611         .mpu_irqs       = omap44xx_uart4_irqs,
1612         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_uart4_irqs),
1613         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
1614         .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
1615         .main_clk       = "uart4_fck",
1616         .prcm = {
1617                 .omap4 = {
1618                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
1619                 },
1620         },
1621         .slaves         = omap44xx_uart4_slaves,
1622         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
1623         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1624 };
1625
1626 /*
1627  * 'wd_timer' class
1628  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1629  * overflow condition
1630  */
1631
1632 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
1633         .rev_offs       = 0x0000,
1634         .sysc_offs      = 0x0010,
1635         .syss_offs      = 0x0014,
1636         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1637                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1638         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1639                            SIDLE_SMART_WKUP),
1640         .sysc_fields    = &omap_hwmod_sysc_type1,
1641 };
1642
1643 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
1644         .name           = "wd_timer",
1645         .sysc           = &omap44xx_wd_timer_sysc,
1646         .pre_shutdown   = &omap2_wd_timer_disable
1647 };
1648
1649 /* wd_timer2 */
1650 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
1651 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
1652         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
1653 };
1654
1655 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
1656         {
1657                 .pa_start       = 0x4a314000,
1658                 .pa_end         = 0x4a31407f,
1659                 .flags          = ADDR_TYPE_RT
1660         },
1661 };
1662
1663 /* l4_wkup -> wd_timer2 */
1664 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
1665         .master         = &omap44xx_l4_wkup_hwmod,
1666         .slave          = &omap44xx_wd_timer2_hwmod,
1667         .clk            = "l4_wkup_clk_mux_ck",
1668         .addr           = omap44xx_wd_timer2_addrs,
1669         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
1670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1671 };
1672
1673 /* wd_timer2 slave ports */
1674 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
1675         &omap44xx_l4_wkup__wd_timer2,
1676 };
1677
1678 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
1679         .name           = "wd_timer2",
1680         .class          = &omap44xx_wd_timer_hwmod_class,
1681         .mpu_irqs       = omap44xx_wd_timer2_irqs,
1682         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
1683         .main_clk       = "wd_timer2_fck",
1684         .prcm = {
1685                 .omap4 = {
1686                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
1687                 },
1688         },
1689         .slaves         = omap44xx_wd_timer2_slaves,
1690         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
1691         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1692 };
1693
1694 /* wd_timer3 */
1695 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
1696 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
1697         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
1698 };
1699
1700 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
1701         {
1702                 .pa_start       = 0x40130000,
1703                 .pa_end         = 0x4013007f,
1704                 .flags          = ADDR_TYPE_RT
1705         },
1706 };
1707
1708 /* l4_abe -> wd_timer3 */
1709 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
1710         .master         = &omap44xx_l4_abe_hwmod,
1711         .slave          = &omap44xx_wd_timer3_hwmod,
1712         .clk            = "ocp_abe_iclk",
1713         .addr           = omap44xx_wd_timer3_addrs,
1714         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
1715         .user           = OCP_USER_MPU,
1716 };
1717
1718 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
1719         {
1720                 .pa_start       = 0x49030000,
1721                 .pa_end         = 0x4903007f,
1722                 .flags          = ADDR_TYPE_RT
1723         },
1724 };
1725
1726 /* l4_abe -> wd_timer3 (dma) */
1727 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
1728         .master         = &omap44xx_l4_abe_hwmod,
1729         .slave          = &omap44xx_wd_timer3_hwmod,
1730         .clk            = "ocp_abe_iclk",
1731         .addr           = omap44xx_wd_timer3_dma_addrs,
1732         .addr_cnt       = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
1733         .user           = OCP_USER_SDMA,
1734 };
1735
1736 /* wd_timer3 slave ports */
1737 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
1738         &omap44xx_l4_abe__wd_timer3,
1739         &omap44xx_l4_abe__wd_timer3_dma,
1740 };
1741
1742 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
1743         .name           = "wd_timer3",
1744         .class          = &omap44xx_wd_timer_hwmod_class,
1745         .mpu_irqs       = omap44xx_wd_timer3_irqs,
1746         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
1747         .main_clk       = "wd_timer3_fck",
1748         .prcm = {
1749                 .omap4 = {
1750                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
1751                 },
1752         },
1753         .slaves         = omap44xx_wd_timer3_slaves,
1754         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
1755         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1756 };
1757
1758
1759 /*
1760  * 'dma' class
1761  * dma controller for data exchange between memory to memory (i.e. internal or
1762  * external memory) and gp peripherals to memory or memory to gp peripherals
1763  */
1764
1765 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
1766         .rev_offs       = 0x0000,
1767         .sysc_offs      = 0x002c,
1768         .syss_offs      = 0x0028,
1769         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1770                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1771                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1772                            SYSS_HAS_RESET_STATUS),
1773         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1774                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1775         .sysc_fields    = &omap_hwmod_sysc_type1,
1776 };
1777
1778 /* dma attributes */
1779 static struct omap_dma_dev_attr dma_dev_attr = {
1780         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1781                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1782         .lch_count = 32,
1783 };
1784
1785 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
1786         .name   = "dma",
1787         .sysc   = &omap44xx_dma_sysc,
1788 };
1789
1790 /* dma_system */
1791 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
1792         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
1793         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
1794         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
1795         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
1796 };
1797
1798 /* dma_system master ports */
1799 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
1800         &omap44xx_dma_system__l3_main_2,
1801 };
1802
1803 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
1804         {
1805                 .pa_start       = 0x4a056000,
1806                 .pa_end         = 0x4a0560ff,
1807                 .flags          = ADDR_TYPE_RT
1808         },
1809 };
1810
1811 /* l4_cfg -> dma_system */
1812 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
1813         .master         = &omap44xx_l4_cfg_hwmod,
1814         .slave          = &omap44xx_dma_system_hwmod,
1815         .clk            = "l4_div_ck",
1816         .addr           = omap44xx_dma_system_addrs,
1817         .addr_cnt       = ARRAY_SIZE(omap44xx_dma_system_addrs),
1818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1819 };
1820
1821 /* dma_system slave ports */
1822 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
1823         &omap44xx_l4_cfg__dma_system,
1824 };
1825
1826 static struct omap_hwmod omap44xx_dma_system_hwmod = {
1827         .name           = "dma_system",
1828         .class          = &omap44xx_dma_hwmod_class,
1829         .mpu_irqs       = omap44xx_dma_system_irqs,
1830         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_dma_system_irqs),
1831         .main_clk       = "l3_div_ck",
1832         .prcm = {
1833                 .omap4 = {
1834                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
1835                 },
1836         },
1837         .slaves         = omap44xx_dma_system_slaves,
1838         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
1839         .masters        = omap44xx_dma_system_masters,
1840         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
1841         .dev_attr       = &dma_dev_attr,
1842         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1843 };
1844
1845 /*
1846  * 'smartreflex' class
1847  * smartreflex module (monitor silicon performance and outputs a measure of
1848  * performance error)
1849  */
1850
1851 /* The IP is not compliant to type1 / type2 scheme */
1852 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1853         .sidle_shift    = 24,
1854         .enwkup_shift   = 26,
1855 };
1856
1857 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
1858         .sysc_offs      = 0x0038,
1859         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1860         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1861                            SIDLE_SMART_WKUP),
1862         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
1863 };
1864
1865 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
1866         .name = "smartreflex",
1867         .sysc = &omap44xx_smartreflex_sysc,
1868         .rev  = 2,
1869 };
1870
1871 /* smartreflex_core */
1872 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
1873 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
1874         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
1875 };
1876
1877 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
1878         {
1879                 .pa_start       = 0x4a0dd000,
1880                 .pa_end         = 0x4a0dd03f,
1881                 .flags          = ADDR_TYPE_RT
1882         },
1883 };
1884
1885 /* l4_cfg -> smartreflex_core */
1886 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
1887         .master         = &omap44xx_l4_cfg_hwmod,
1888         .slave          = &omap44xx_smartreflex_core_hwmod,
1889         .clk            = "l4_div_ck",
1890         .addr           = omap44xx_smartreflex_core_addrs,
1891         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
1892         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1893 };
1894
1895 /* smartreflex_core slave ports */
1896 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
1897         &omap44xx_l4_cfg__smartreflex_core,
1898 };
1899
1900 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
1901         .name           = "smartreflex_core",
1902         .class          = &omap44xx_smartreflex_hwmod_class,
1903         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
1904         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
1905         .main_clk       = "smartreflex_core_fck",
1906         .vdd_name       = "core",
1907         .prcm = {
1908                 .omap4 = {
1909                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
1910                 },
1911         },
1912         .slaves         = omap44xx_smartreflex_core_slaves,
1913         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
1914         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1915 };
1916
1917 /* smartreflex_iva */
1918 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
1919 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
1920         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
1921 };
1922
1923 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
1924         {
1925                 .pa_start       = 0x4a0db000,
1926                 .pa_end         = 0x4a0db03f,
1927                 .flags          = ADDR_TYPE_RT
1928         },
1929 };
1930
1931 /* l4_cfg -> smartreflex_iva */
1932 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
1933         .master         = &omap44xx_l4_cfg_hwmod,
1934         .slave          = &omap44xx_smartreflex_iva_hwmod,
1935         .clk            = "l4_div_ck",
1936         .addr           = omap44xx_smartreflex_iva_addrs,
1937         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
1938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1939 };
1940
1941 /* smartreflex_iva slave ports */
1942 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
1943         &omap44xx_l4_cfg__smartreflex_iva,
1944 };
1945
1946 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
1947         .name           = "smartreflex_iva",
1948         .class          = &omap44xx_smartreflex_hwmod_class,
1949         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
1950         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
1951         .main_clk       = "smartreflex_iva_fck",
1952         .vdd_name       = "iva",
1953         .prcm = {
1954                 .omap4 = {
1955                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
1956                 },
1957         },
1958         .slaves         = omap44xx_smartreflex_iva_slaves,
1959         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
1960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1961 };
1962
1963 /* smartreflex_mpu */
1964 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
1965 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
1966         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
1967 };
1968
1969 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
1970         {
1971                 .pa_start       = 0x4a0d9000,
1972                 .pa_end         = 0x4a0d903f,
1973                 .flags          = ADDR_TYPE_RT
1974         },
1975 };
1976
1977 /* l4_cfg -> smartreflex_mpu */
1978 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
1979         .master         = &omap44xx_l4_cfg_hwmod,
1980         .slave          = &omap44xx_smartreflex_mpu_hwmod,
1981         .clk            = "l4_div_ck",
1982         .addr           = omap44xx_smartreflex_mpu_addrs,
1983         .addr_cnt       = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
1984         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1985 };
1986
1987 /* smartreflex_mpu slave ports */
1988 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
1989         &omap44xx_l4_cfg__smartreflex_mpu,
1990 };
1991
1992 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
1993         .name           = "smartreflex_mpu",
1994         .class          = &omap44xx_smartreflex_hwmod_class,
1995         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
1996         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
1997         .main_clk       = "smartreflex_mpu_fck",
1998         .vdd_name       = "mpu",
1999         .prcm = {
2000                 .omap4 = {
2001                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2002                 },
2003         },
2004         .slaves         = omap44xx_smartreflex_mpu_slaves,
2005         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
2006         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2007 };
2008
2009 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
2010         /* dmm class */
2011         &omap44xx_dmm_hwmod,
2012
2013         /* emif_fw class */
2014         &omap44xx_emif_fw_hwmod,
2015
2016         /* l3 class */
2017         &omap44xx_l3_instr_hwmod,
2018         &omap44xx_l3_main_1_hwmod,
2019         &omap44xx_l3_main_2_hwmod,
2020         &omap44xx_l3_main_3_hwmod,
2021
2022         /* l4 class */
2023         &omap44xx_l4_abe_hwmod,
2024         &omap44xx_l4_cfg_hwmod,
2025         &omap44xx_l4_per_hwmod,
2026         &omap44xx_l4_wkup_hwmod,
2027
2028         /* dma class */
2029         &omap44xx_dma_system_hwmod,
2030
2031         /* mpu_bus class */
2032         &omap44xx_mpu_private_hwmod,
2033
2034         /* dsp class */
2035         &omap44xx_dsp_hwmod,
2036         &omap44xx_dsp_c0_hwmod,
2037
2038         /* gpio class */
2039         &omap44xx_gpio1_hwmod,
2040         &omap44xx_gpio2_hwmod,
2041         &omap44xx_gpio3_hwmod,
2042         &omap44xx_gpio4_hwmod,
2043         &omap44xx_gpio5_hwmod,
2044         &omap44xx_gpio6_hwmod,
2045
2046         /* i2c class */
2047         &omap44xx_i2c1_hwmod,
2048         &omap44xx_i2c2_hwmod,
2049         &omap44xx_i2c3_hwmod,
2050         &omap44xx_i2c4_hwmod,
2051
2052         /* iva class */
2053         &omap44xx_iva_hwmod,
2054         &omap44xx_iva_seq0_hwmod,
2055         &omap44xx_iva_seq1_hwmod,
2056
2057         /* mpu class */
2058         &omap44xx_mpu_hwmod,
2059
2060         /* uart class */
2061         &omap44xx_uart1_hwmod,
2062         &omap44xx_uart2_hwmod,
2063         &omap44xx_uart3_hwmod,
2064         &omap44xx_uart4_hwmod,
2065
2066         /* wd_timer class */
2067         &omap44xx_wd_timer2_hwmod,
2068         &omap44xx_wd_timer3_hwmod,
2069
2070         /* smartreflex class */
2071         &omap44xx_smartreflex_core_hwmod,
2072         &omap44xx_smartreflex_iva_hwmod,
2073         &omap44xx_smartreflex_mpu_hwmod,
2074
2075         NULL,
2076 };
2077
2078 int __init omap44xx_hwmod_init(void)
2079 {
2080         return omap_hwmod_init(omap44xx_hwmods);
2081 }
2082