arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/i2c.h>
  32
  33 #include "omap_hwmod_common_data.h"
  34
  35 #include "cm1_44xx.h"
  36 #include "cm2_44xx.h"
  37 #include "prm44xx.h"
  38 #include "prm-regbits-44xx.h"
  39 #include "wd_timer.h"
  40
  41 /* Base offset for all OMAP4 interrupts external to MPUSS */
  42 #define OMAP44XX_IRQ_GIC_START  32
  43
  44 /* Base offset for all OMAP4 dma requests */
  45 #define OMAP44XX_DMA_REQ_START  1
  46
  47 /* Backward references (IPs with Bus Master capability) */
  48 static struct omap_hwmod omap44xx_aess_hwmod;
  49 static struct omap_hwmod omap44xx_dma_system_hwmod;
  50 static struct omap_hwmod omap44xx_dmm_hwmod;
  51 static struct omap_hwmod omap44xx_dsp_hwmod;
  52 static struct omap_hwmod omap44xx_dss_hwmod;
  53 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  54 static struct omap_hwmod omap44xx_hsi_hwmod;
  55 static struct omap_hwmod omap44xx_ipu_hwmod;
  56 static struct omap_hwmod omap44xx_iss_hwmod;
  57 static struct omap_hwmod omap44xx_iva_hwmod;
  58 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  60 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  62 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  63 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  64 static struct omap_hwmod omap44xx_l4_per_hwmod;
  65 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  66 static struct omap_hwmod omap44xx_mmc1_hwmod;
  67 static struct omap_hwmod omap44xx_mmc2_hwmod;
  68 static struct omap_hwmod omap44xx_mpu_hwmod;
  69 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  70 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  71
  72 /*
  73  * Interconnects omap_hwmod structures
  74  * hwmods that compose the global OMAP interconnect
  75  */
  76
  77 /*
  78  * 'dmm' class
  79  * instance(s): dmm
  80  */
  81 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  82         .name   = "dmm",
  83 };
  84
  85 /* dmm */
  86 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  87         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  88         { .irq = -1 }
  89 };
  90
  91 /* l3_main_1 -> dmm */
  92 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  93         .master         = &omap44xx_l3_main_1_hwmod,
  94         .slave          = &omap44xx_dmm_hwmod,
  95         .clk            = "l3_div_ck",
  96         .user           = OCP_USER_SDMA,
  97 };
  98
  99 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 100         {
 101                 .pa_start       = 0x4e000000,
 102                 .pa_end         = 0x4e0007ff,
 103                 .flags          = ADDR_TYPE_RT
 104         },
 105         { }
 106 };
 107
 108 /* mpu -> dmm */
 109 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 110         .master         = &omap44xx_mpu_hwmod,
 111         .slave          = &omap44xx_dmm_hwmod,
 112         .clk            = "l3_div_ck",
 113         .addr           = omap44xx_dmm_addrs,
 114         .user           = OCP_USER_MPU,
 115 };
 116
 117 /* dmm slave ports */
 118 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 119         &omap44xx_l3_main_1__dmm,
 120         &omap44xx_mpu__dmm,
 121 };
 122
 123 static struct omap_hwmod omap44xx_dmm_hwmod = {
 124         .name           = "dmm",
 125         .class          = &omap44xx_dmm_hwmod_class,
 126         .mpu_irqs       = omap44xx_dmm_irqs,
 127         .slaves         = omap44xx_dmm_slaves,
 128         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 129         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 130 };
 131
 132 /*
 133  * 'emif_fw' class
 134  * instance(s): emif_fw
 135  */
 136 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 137         .name   = "emif_fw",
 138 };
 139
 140 /* emif_fw */
 141 /* dmm -> emif_fw */
 142 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 143         .master         = &omap44xx_dmm_hwmod,
 144         .slave          = &omap44xx_emif_fw_hwmod,
 145         .clk            = "l3_div_ck",
 146         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 147 };
 148
 149 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 150         {
 151                 .pa_start       = 0x4a20c000,
 152                 .pa_end         = 0x4a20c0ff,
 153                 .flags          = ADDR_TYPE_RT
 154         },
 155         { }
 156 };
 157
 158 /* l4_cfg -> emif_fw */
 159 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 160         .master         = &omap44xx_l4_cfg_hwmod,
 161         .slave          = &omap44xx_emif_fw_hwmod,
 162         .clk            = "l4_div_ck",
 163         .addr           = omap44xx_emif_fw_addrs,
 164         .user           = OCP_USER_MPU,
 165 };
 166
 167 /* emif_fw slave ports */
 168 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 169         &omap44xx_dmm__emif_fw,
 170         &omap44xx_l4_cfg__emif_fw,
 171 };
 172
 173 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 174         .name           = "emif_fw",
 175         .class          = &omap44xx_emif_fw_hwmod_class,
 176         .slaves         = omap44xx_emif_fw_slaves,
 177         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 178         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 179 };
 180
 181 /*
 182  * 'l3' class
 183  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 184  */
 185 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 186         .name   = "l3",
 187 };
 188
 189 /* l3_instr */
 190 /* iva -> l3_instr */
 191 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 192         .master         = &omap44xx_iva_hwmod,
 193         .slave          = &omap44xx_l3_instr_hwmod,
 194         .clk            = "l3_div_ck",
 195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 196 };
 197
 198 /* l3_main_3 -> l3_instr */
 199 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 200         .master         = &omap44xx_l3_main_3_hwmod,
 201         .slave          = &omap44xx_l3_instr_hwmod,
 202         .clk            = "l3_div_ck",
 203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 204 };
 205
 206 /* l3_instr slave ports */
 207 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 208         &omap44xx_iva__l3_instr,
 209         &omap44xx_l3_main_3__l3_instr,
 210 };
 211
 212 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 213         .name           = "l3_instr",
 214         .class          = &omap44xx_l3_hwmod_class,
 215         .slaves         = omap44xx_l3_instr_slaves,
 216         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 217         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 218 };
 219
 220 /* l3_main_1 */
 221 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 222         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 223         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 224         { .irq = -1 }
 225 };
 226
 227 /* dsp -> l3_main_1 */
 228 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 229         .master         = &omap44xx_dsp_hwmod,
 230         .slave          = &omap44xx_l3_main_1_hwmod,
 231         .clk            = "l3_div_ck",
 232         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 233 };
 234
 235 /* dss -> l3_main_1 */
 236 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 237         .master         = &omap44xx_dss_hwmod,
 238         .slave          = &omap44xx_l3_main_1_hwmod,
 239         .clk            = "l3_div_ck",
 240         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 241 };
 242
 243 /* l3_main_2 -> l3_main_1 */
 244 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 245         .master         = &omap44xx_l3_main_2_hwmod,
 246         .slave          = &omap44xx_l3_main_1_hwmod,
 247         .clk            = "l3_div_ck",
 248         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 249 };
 250
 251 /* l4_cfg -> l3_main_1 */
 252 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 253         .master         = &omap44xx_l4_cfg_hwmod,
 254         .slave          = &omap44xx_l3_main_1_hwmod,
 255         .clk            = "l4_div_ck",
 256         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 257 };
 258
 259 /* mmc1 -> l3_main_1 */
 260 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 261         .master         = &omap44xx_mmc1_hwmod,
 262         .slave          = &omap44xx_l3_main_1_hwmod,
 263         .clk            = "l3_div_ck",
 264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 265 };
 266
 267 /* mmc2 -> l3_main_1 */
 268 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 269         .master         = &omap44xx_mmc2_hwmod,
 270         .slave          = &omap44xx_l3_main_1_hwmod,
 271         .clk            = "l3_div_ck",
 272         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 273 };
 274
 275 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 276         {
 277                 .pa_start       = 0x44000000,
 278                 .pa_end         = 0x44000fff,
 279                 .flags          = ADDR_TYPE_RT
 280         },
 281         { }
 282 };
 283
 284 /* mpu -> l3_main_1 */
 285 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 286         .master         = &omap44xx_mpu_hwmod,
 287         .slave          = &omap44xx_l3_main_1_hwmod,
 288         .clk            = "l3_div_ck",
 289         .addr           = omap44xx_l3_main_1_addrs,
 290         .user           = OCP_USER_MPU,
 291 };
 292
 293 /* l3_main_1 slave ports */
 294 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 295         &omap44xx_dsp__l3_main_1,
 296         &omap44xx_dss__l3_main_1,
 297         &omap44xx_l3_main_2__l3_main_1,
 298         &omap44xx_l4_cfg__l3_main_1,
 299         &omap44xx_mmc1__l3_main_1,
 300         &omap44xx_mmc2__l3_main_1,
 301         &omap44xx_mpu__l3_main_1,
 302 };
 303
 304 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 305         .name           = "l3_main_1",
 306         .class          = &omap44xx_l3_hwmod_class,
 307         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 308         .slaves         = omap44xx_l3_main_1_slaves,
 309         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 310         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 311 };
 312
 313 /* l3_main_2 */
 314 /* dma_system -> l3_main_2 */
 315 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 316         .master         = &omap44xx_dma_system_hwmod,
 317         .slave          = &omap44xx_l3_main_2_hwmod,
 318         .clk            = "l3_div_ck",
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* hsi -> l3_main_2 */
 323 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 324         .master         = &omap44xx_hsi_hwmod,
 325         .slave          = &omap44xx_l3_main_2_hwmod,
 326         .clk            = "l3_div_ck",
 327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 328 };
 329
 330 /* ipu -> l3_main_2 */
 331 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 332         .master         = &omap44xx_ipu_hwmod,
 333         .slave          = &omap44xx_l3_main_2_hwmod,
 334         .clk            = "l3_div_ck",
 335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 336 };
 337
 338 /* iss -> l3_main_2 */
 339 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 340         .master         = &omap44xx_iss_hwmod,
 341         .slave          = &omap44xx_l3_main_2_hwmod,
 342         .clk            = "l3_div_ck",
 343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 344 };
 345
 346 /* iva -> l3_main_2 */
 347 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 348         .master         = &omap44xx_iva_hwmod,
 349         .slave          = &omap44xx_l3_main_2_hwmod,
 350         .clk            = "l3_div_ck",
 351         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 352 };
 353
 354 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 355         {
 356                 .pa_start       = 0x44800000,
 357                 .pa_end         = 0x44801fff,
 358                 .flags          = ADDR_TYPE_RT
 359         },
 360         { }
 361 };
 362
 363 /* l3_main_1 -> l3_main_2 */
 364 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 365         .master         = &omap44xx_l3_main_1_hwmod,
 366         .slave          = &omap44xx_l3_main_2_hwmod,
 367         .clk            = "l3_div_ck",
 368         .addr           = omap44xx_l3_main_2_addrs,
 369         .user           = OCP_USER_MPU,
 370 };
 371
 372 /* l4_cfg -> l3_main_2 */
 373 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 374         .master         = &omap44xx_l4_cfg_hwmod,
 375         .slave          = &omap44xx_l3_main_2_hwmod,
 376         .clk            = "l4_div_ck",
 377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 378 };
 379
 380 /* usb_otg_hs -> l3_main_2 */
 381 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 382         .master         = &omap44xx_usb_otg_hs_hwmod,
 383         .slave          = &omap44xx_l3_main_2_hwmod,
 384         .clk            = "l3_div_ck",
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* l3_main_2 slave ports */
 389 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 390         &omap44xx_dma_system__l3_main_2,
 391         &omap44xx_hsi__l3_main_2,
 392         &omap44xx_ipu__l3_main_2,
 393         &omap44xx_iss__l3_main_2,
 394         &omap44xx_iva__l3_main_2,
 395         &omap44xx_l3_main_1__l3_main_2,
 396         &omap44xx_l4_cfg__l3_main_2,
 397         &omap44xx_usb_otg_hs__l3_main_2,
 398 };
 399
 400 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 401         .name           = "l3_main_2",
 402         .class          = &omap44xx_l3_hwmod_class,
 403         .slaves         = omap44xx_l3_main_2_slaves,
 404         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 405         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 406 };
 407
 408 /* l3_main_3 */
 409 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 410         {
 411                 .pa_start       = 0x45000000,
 412                 .pa_end         = 0x45000fff,
 413                 .flags          = ADDR_TYPE_RT
 414         },
 415         { }
 416 };
 417
 418 /* l3_main_1 -> l3_main_3 */
 419 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 420         .master         = &omap44xx_l3_main_1_hwmod,
 421         .slave          = &omap44xx_l3_main_3_hwmod,
 422         .clk            = "l3_div_ck",
 423         .addr           = omap44xx_l3_main_3_addrs,
 424         .user           = OCP_USER_MPU,
 425 };
 426
 427 /* l3_main_2 -> l3_main_3 */
 428 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 429         .master         = &omap44xx_l3_main_2_hwmod,
 430         .slave          = &omap44xx_l3_main_3_hwmod,
 431         .clk            = "l3_div_ck",
 432         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 433 };
 434
 435 /* l4_cfg -> l3_main_3 */
 436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 437         .master         = &omap44xx_l4_cfg_hwmod,
 438         .slave          = &omap44xx_l3_main_3_hwmod,
 439         .clk            = "l4_div_ck",
 440         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 441 };
 442
 443 /* l3_main_3 slave ports */
 444 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 445         &omap44xx_l3_main_1__l3_main_3,
 446         &omap44xx_l3_main_2__l3_main_3,
 447         &omap44xx_l4_cfg__l3_main_3,
 448 };
 449
 450 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 451         .name           = "l3_main_3",
 452         .class          = &omap44xx_l3_hwmod_class,
 453         .slaves         = omap44xx_l3_main_3_slaves,
 454         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 455         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 456 };
 457
 458 /*
 459  * 'l4' class
 460  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 461  */
 462 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 463         .name   = "l4",
 464 };
 465
 466 /* l4_abe */
 467 /* aess -> l4_abe */
 468 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 469         .master         = &omap44xx_aess_hwmod,
 470         .slave          = &omap44xx_l4_abe_hwmod,
 471         .clk            = "ocp_abe_iclk",
 472         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 473 };
 474
 475 /* dsp -> l4_abe */
 476 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 477         .master         = &omap44xx_dsp_hwmod,
 478         .slave          = &omap44xx_l4_abe_hwmod,
 479         .clk            = "ocp_abe_iclk",
 480         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 481 };
 482
 483 /* l3_main_1 -> l4_abe */
 484 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 485         .master         = &omap44xx_l3_main_1_hwmod,
 486         .slave          = &omap44xx_l4_abe_hwmod,
 487         .clk            = "l3_div_ck",
 488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 489 };
 490
 491 /* mpu -> l4_abe */
 492 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 493         .master         = &omap44xx_mpu_hwmod,
 494         .slave          = &omap44xx_l4_abe_hwmod,
 495         .clk            = "ocp_abe_iclk",
 496         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 497 };
 498
 499 /* l4_abe slave ports */
 500 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 501         &omap44xx_aess__l4_abe,
 502         &omap44xx_dsp__l4_abe,
 503         &omap44xx_l3_main_1__l4_abe,
 504         &omap44xx_mpu__l4_abe,
 505 };
 506
 507 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 508         .name           = "l4_abe",
 509         .class          = &omap44xx_l4_hwmod_class,
 510         .slaves         = omap44xx_l4_abe_slaves,
 511         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 512         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 513 };
 514
 515 /* l4_cfg */
 516 /* l3_main_1 -> l4_cfg */
 517 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 518         .master         = &omap44xx_l3_main_1_hwmod,
 519         .slave          = &omap44xx_l4_cfg_hwmod,
 520         .clk            = "l3_div_ck",
 521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 522 };
 523
 524 /* l4_cfg slave ports */
 525 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 526         &omap44xx_l3_main_1__l4_cfg,
 527 };
 528
 529 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 530         .name           = "l4_cfg",
 531         .class          = &omap44xx_l4_hwmod_class,
 532         .slaves         = omap44xx_l4_cfg_slaves,
 533         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 534         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 535 };
 536
 537 /* l4_per */
 538 /* l3_main_2 -> l4_per */
 539 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 540         .master         = &omap44xx_l3_main_2_hwmod,
 541         .slave          = &omap44xx_l4_per_hwmod,
 542         .clk            = "l3_div_ck",
 543         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 544 };
 545
 546 /* l4_per slave ports */
 547 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 548         &omap44xx_l3_main_2__l4_per,
 549 };
 550
 551 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 552         .name           = "l4_per",
 553         .class          = &omap44xx_l4_hwmod_class,
 554         .slaves         = omap44xx_l4_per_slaves,
 555         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 556         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 557 };
 558
 559 /* l4_wkup */
 560 /* l4_cfg -> l4_wkup */
 561 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 562         .master         = &omap44xx_l4_cfg_hwmod,
 563         .slave          = &omap44xx_l4_wkup_hwmod,
 564         .clk            = "l4_div_ck",
 565         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 566 };
 567
 568 /* l4_wkup slave ports */
 569 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 570         &omap44xx_l4_cfg__l4_wkup,
 571 };
 572
 573 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 574         .name           = "l4_wkup",
 575         .class          = &omap44xx_l4_hwmod_class,
 576         .slaves         = omap44xx_l4_wkup_slaves,
 577         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 578         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 579 };
 580
 581 /*
 582  * 'mpu_bus' class
 583  * instance(s): mpu_private
 584  */
 585 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 586         .name   = "mpu_bus",
 587 };
 588
 589 /* mpu_private */
 590 /* mpu -> mpu_private */
 591 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 592         .master         = &omap44xx_mpu_hwmod,
 593         .slave          = &omap44xx_mpu_private_hwmod,
 594         .clk            = "l3_div_ck",
 595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 596 };
 597
 598 /* mpu_private slave ports */
 599 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 600         &omap44xx_mpu__mpu_private,
 601 };
 602
 603 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 604         .name           = "mpu_private",
 605         .class          = &omap44xx_mpu_bus_hwmod_class,
 606         .slaves         = omap44xx_mpu_private_slaves,
 607         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 608         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 609 };
 610
 611 /*
 612  * Modules omap_hwmod structures
 613  *
 614  * The following IPs are excluded for the moment because:
 615  * - They do not need an explicit SW control using omap_hwmod API.
 616  * - They still need to be validated with the driver
 617  *   properly adapted to omap_hwmod / omap_device
 618  *
 619  *  c2c
 620  *  c2c_target_fw
 621  *  cm_core
 622  *  cm_core_aon
 623  *  ctrl_module_core
 624  *  ctrl_module_pad_core
 625  *  ctrl_module_pad_wkup
 626  *  ctrl_module_wkup
 627  *  debugss
 628  *  efuse_ctrl_cust
 629  *  efuse_ctrl_std
 630  *  elm
 631  *  emif1
 632  *  emif2
 633  *  fdif
 634  *  gpmc
 635  *  gpu
 636  *  hdq1w
 637  *  mcasp
 638  *  mpu_c0
 639  *  mpu_c1
 640  *  ocmc_ram
 641  *  ocp2scp_usb_phy
 642  *  ocp_wp_noc
 643  *  prcm_mpu
 644  *  prm
 645  *  scrm
 646  *  sl2if
 647  *  slimbus1
 648  *  slimbus2
 649  *  usb_host_fs
 650  *  usb_host_hs
 651  *  usb_phy_cm
 652  *  usb_tll_hs
 653  *  usim
 654  */
 655
 656 /*
 657  * 'aess' class
 658  * audio engine sub system
 659  */
 660
 661 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 662         .rev_offs       = 0x0000,
 663         .sysc_offs      = 0x0010,
 664         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 665         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 666                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 667                            MSTANDBY_SMART_WKUP),
 668         .sysc_fields    = &omap_hwmod_sysc_type2,
 669 };
 670
 671 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 672         .name   = "aess",
 673         .sysc   = &omap44xx_aess_sysc,
 674 };
 675
 676 /* aess */
 677 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 678         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 679         { .irq = -1 }
 680 };
 681
 682 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 683         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 684         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 685         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 686         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 687         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 688         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 689         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 690         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 691         { .dma_req = -1 }
 692 };
 693
 694 /* aess master ports */
 695 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 696         &omap44xx_aess__l4_abe,
 697 };
 698
 699 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 700         {
 701                 .pa_start       = 0x401f1000,
 702                 .pa_end         = 0x401f13ff,
 703                 .flags          = ADDR_TYPE_RT
 704         },
 705         { }
 706 };
 707
 708 /* l4_abe -> aess */
 709 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 710         .master         = &omap44xx_l4_abe_hwmod,
 711         .slave          = &omap44xx_aess_hwmod,
 712         .clk            = "ocp_abe_iclk",
 713         .addr           = omap44xx_aess_addrs,
 714         .user           = OCP_USER_MPU,
 715 };
 716
 717 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 718         {
 719                 .pa_start       = 0x490f1000,
 720                 .pa_end         = 0x490f13ff,
 721                 .flags          = ADDR_TYPE_RT
 722         },
 723         { }
 724 };
 725
 726 /* l4_abe -> aess (dma) */
 727 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 728         .master         = &omap44xx_l4_abe_hwmod,
 729         .slave          = &omap44xx_aess_hwmod,
 730         .clk            = "ocp_abe_iclk",
 731         .addr           = omap44xx_aess_dma_addrs,
 732         .user           = OCP_USER_SDMA,
 733 };
 734
 735 /* aess slave ports */
 736 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 737         &omap44xx_l4_abe__aess,
 738         &omap44xx_l4_abe__aess_dma,
 739 };
 740
 741 static struct omap_hwmod omap44xx_aess_hwmod = {
 742         .name           = "aess",
 743         .class          = &omap44xx_aess_hwmod_class,
 744         .mpu_irqs       = omap44xx_aess_irqs,
 745         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 746         .main_clk       = "aess_fck",
 747         .prcm = {
 748                 .omap4 = {
 749                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 750                 },
 751         },
 752         .slaves         = omap44xx_aess_slaves,
 753         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 754         .masters        = omap44xx_aess_masters,
 755         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 756         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 757 };
 758
 759 /*
 760  * 'bandgap' class
 761  * bangap reference for ldo regulators
 762  */
 763
 764 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 765         .name   = "bandgap",
 766 };
 767
 768 /* bandgap */
 769 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 770         { .role = "fclk", .clk = "bandgap_fclk" },
 771 };
 772
 773 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 774         .name           = "bandgap",
 775         .class          = &omap44xx_bandgap_hwmod_class,
 776         .prcm = {
 777                 .omap4 = {
 778                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 779                 },
 780         },
 781         .opt_clks       = bandgap_opt_clks,
 782         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 783         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 784 };
 785
 786 /*
 787  * 'counter' class
 788  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 789  */
 790
 791 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 792         .rev_offs       = 0x0000,
 793         .sysc_offs      = 0x0004,
 794         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 795         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 796                            SIDLE_SMART_WKUP),
 797         .sysc_fields    = &omap_hwmod_sysc_type1,
 798 };
 799
 800 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 801         .name   = "counter",
 802         .sysc   = &omap44xx_counter_sysc,
 803 };
 804
 805 /* counter_32k */
 806 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 807 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 808         {
 809                 .pa_start       = 0x4a304000,
 810                 .pa_end         = 0x4a30401f,
 811                 .flags          = ADDR_TYPE_RT
 812         },
 813         { }
 814 };
 815
 816 /* l4_wkup -> counter_32k */
 817 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 818         .master         = &omap44xx_l4_wkup_hwmod,
 819         .slave          = &omap44xx_counter_32k_hwmod,
 820         .clk            = "l4_wkup_clk_mux_ck",
 821         .addr           = omap44xx_counter_32k_addrs,
 822         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 823 };
 824
 825 /* counter_32k slave ports */
 826 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 827         &omap44xx_l4_wkup__counter_32k,
 828 };
 829
 830 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 831         .name           = "counter_32k",
 832         .class          = &omap44xx_counter_hwmod_class,
 833         .flags          = HWMOD_SWSUP_SIDLE,
 834         .main_clk       = "sys_32k_ck",
 835         .prcm = {
 836                 .omap4 = {
 837                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 838                 },
 839         },
 840         .slaves         = omap44xx_counter_32k_slaves,
 841         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 842         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 843 };
 844
 845 /*
 846  * 'dma' class
 847  * dma controller for data exchange between memory to memory (i.e. internal or
 848  * external memory) and gp peripherals to memory or memory to gp peripherals
 849  */
 850
 851 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 852         .rev_offs       = 0x0000,
 853         .sysc_offs      = 0x002c,
 854         .syss_offs      = 0x0028,
 855         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 856                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 857                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 858                            SYSS_HAS_RESET_STATUS),
 859         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 860                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 861         .sysc_fields    = &omap_hwmod_sysc_type1,
 862 };
 863
 864 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 865         .name   = "dma",
 866         .sysc   = &omap44xx_dma_sysc,
 867 };
 868
 869 /* dma dev_attr */
 870 static struct omap_dma_dev_attr dma_dev_attr = {
 871         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 872                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 873         .lch_count      = 32,
 874 };
 875
 876 /* dma_system */
 877 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 878         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 879         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 880         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 881         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 882         { .irq = -1 }
 883 };
 884
 885 /* dma_system master ports */
 886 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 887         &omap44xx_dma_system__l3_main_2,
 888 };
 889
 890 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 891         {
 892                 .pa_start       = 0x4a056000,
 893                 .pa_end         = 0x4a056fff,
 894                 .flags          = ADDR_TYPE_RT
 895         },
 896         { }
 897 };
 898
 899 /* l4_cfg -> dma_system */
 900 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 901         .master         = &omap44xx_l4_cfg_hwmod,
 902         .slave          = &omap44xx_dma_system_hwmod,
 903         .clk            = "l4_div_ck",
 904         .addr           = omap44xx_dma_system_addrs,
 905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 906 };
 907
 908 /* dma_system slave ports */
 909 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 910         &omap44xx_l4_cfg__dma_system,
 911 };
 912
 913 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 914         .name           = "dma_system",
 915         .class          = &omap44xx_dma_hwmod_class,
 916         .mpu_irqs       = omap44xx_dma_system_irqs,
 917         .main_clk       = "l3_div_ck",
 918         .prcm = {
 919                 .omap4 = {
 920                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 921                 },
 922         },
 923         .dev_attr       = &dma_dev_attr,
 924         .slaves         = omap44xx_dma_system_slaves,
 925         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 926         .masters        = omap44xx_dma_system_masters,
 927         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 928         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 929 };
 930
 931 /*
 932  * 'dmic' class
 933  * digital microphone controller
 934  */
 935
 936 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 937         .rev_offs       = 0x0000,
 938         .sysc_offs      = 0x0010,
 939         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 940                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 941         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 942                            SIDLE_SMART_WKUP),
 943         .sysc_fields    = &omap_hwmod_sysc_type2,
 944 };
 945
 946 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 947         .name   = "dmic",
 948         .sysc   = &omap44xx_dmic_sysc,
 949 };
 950
 951 /* dmic */
 952 static struct omap_hwmod omap44xx_dmic_hwmod;
 953 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 954         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 955         { .irq = -1 }
 956 };
 957
 958 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 959         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 960         { .dma_req = -1 }
 961 };
 962
 963 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 964         {
 965                 .pa_start       = 0x4012e000,
 966                 .pa_end         = 0x4012e07f,
 967                 .flags          = ADDR_TYPE_RT
 968         },
 969         { }
 970 };
 971
 972 /* l4_abe -> dmic */
 973 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 974         .master         = &omap44xx_l4_abe_hwmod,
 975         .slave          = &omap44xx_dmic_hwmod,
 976         .clk            = "ocp_abe_iclk",
 977         .addr           = omap44xx_dmic_addrs,
 978         .user           = OCP_USER_MPU,
 979 };
 980
 981 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 982         {
 983                 .pa_start       = 0x4902e000,
 984                 .pa_end         = 0x4902e07f,
 985                 .flags          = ADDR_TYPE_RT
 986         },
 987         { }
 988 };
 989
 990 /* l4_abe -> dmic (dma) */
 991 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 992         .master         = &omap44xx_l4_abe_hwmod,
 993         .slave          = &omap44xx_dmic_hwmod,
 994         .clk            = "ocp_abe_iclk",
 995         .addr           = omap44xx_dmic_dma_addrs,
 996         .user           = OCP_USER_SDMA,
 997 };
 998
 999 /* dmic slave ports */
1000 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1001         &omap44xx_l4_abe__dmic,
1002         &omap44xx_l4_abe__dmic_dma,
1003 };
1004
1005 static struct omap_hwmod omap44xx_dmic_hwmod = {
1006         .name           = "dmic",
1007         .class          = &omap44xx_dmic_hwmod_class,
1008         .mpu_irqs       = omap44xx_dmic_irqs,
1009         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1010         .main_clk       = "dmic_fck",
1011         .prcm = {
1012                 .omap4 = {
1013                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1014                 },
1015         },
1016         .slaves         = omap44xx_dmic_slaves,
1017         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1018         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1019 };
1020
1021 /*
1022  * 'dsp' class
1023  * dsp sub-system
1024  */
1025
1026 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1027         .name   = "dsp",
1028 };
1029
1030 /* dsp */
1031 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1032         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1033         { .irq = -1 }
1034 };
1035
1036 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1037         { .name = "mmu_cache", .rst_shift = 1 },
1038 };
1039
1040 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1041         { .name = "dsp", .rst_shift = 0 },
1042 };
1043
1044 /* dsp -> iva */
1045 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1046         .master         = &omap44xx_dsp_hwmod,
1047         .slave          = &omap44xx_iva_hwmod,
1048         .clk            = "dpll_iva_m5x2_ck",
1049 };
1050
1051 /* dsp master ports */
1052 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1053         &omap44xx_dsp__l3_main_1,
1054         &omap44xx_dsp__l4_abe,
1055         &omap44xx_dsp__iva,
1056 };
1057
1058 /* l4_cfg -> dsp */
1059 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1060         .master         = &omap44xx_l4_cfg_hwmod,
1061         .slave          = &omap44xx_dsp_hwmod,
1062         .clk            = "l4_div_ck",
1063         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1064 };
1065
1066 /* dsp slave ports */
1067 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1068         &omap44xx_l4_cfg__dsp,
1069 };
1070
1071 /* Pseudo hwmod for reset control purpose only */
1072 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1073         .name           = "dsp_c0",
1074         .class          = &omap44xx_dsp_hwmod_class,
1075         .flags          = HWMOD_INIT_NO_RESET,
1076         .rst_lines      = omap44xx_dsp_c0_resets,
1077         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1078         .prcm = {
1079                 .omap4 = {
1080                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1081                 },
1082         },
1083         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1084 };
1085
1086 static struct omap_hwmod omap44xx_dsp_hwmod = {
1087         .name           = "dsp",
1088         .class          = &omap44xx_dsp_hwmod_class,
1089         .mpu_irqs       = omap44xx_dsp_irqs,
1090         .rst_lines      = omap44xx_dsp_resets,
1091         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1092         .main_clk       = "dsp_fck",
1093         .prcm = {
1094                 .omap4 = {
1095                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1096                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1097                 },
1098         },
1099         .slaves         = omap44xx_dsp_slaves,
1100         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1101         .masters        = omap44xx_dsp_masters,
1102         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1103         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1104 };
1105
1106 /*
1107  * 'dss' class
1108  * display sub-system
1109  */
1110
1111 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1112         .rev_offs       = 0x0000,
1113         .syss_offs      = 0x0014,
1114         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1115 };
1116
1117 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1118         .name   = "dss",
1119         .sysc   = &omap44xx_dss_sysc,
1120 };
1121
1122 /* dss */
1123 /* dss master ports */
1124 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1125         &omap44xx_dss__l3_main_1,
1126 };
1127
1128 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1129         {
1130                 .pa_start       = 0x58000000,
1131                 .pa_end         = 0x5800007f,
1132                 .flags          = ADDR_TYPE_RT
1133         },
1134         { }
1135 };
1136
1137 /* l3_main_2 -> dss */
1138 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1139         .master         = &omap44xx_l3_main_2_hwmod,
1140         .slave          = &omap44xx_dss_hwmod,
1141         .clk            = "dss_fck",
1142         .addr           = omap44xx_dss_dma_addrs,
1143         .user           = OCP_USER_SDMA,
1144 };
1145
1146 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1147         {
1148                 .pa_start       = 0x48040000,
1149                 .pa_end         = 0x4804007f,
1150                 .flags          = ADDR_TYPE_RT
1151         },
1152         { }
1153 };
1154
1155 /* l4_per -> dss */
1156 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1157         .master         = &omap44xx_l4_per_hwmod,
1158         .slave          = &omap44xx_dss_hwmod,
1159         .clk            = "l4_div_ck",
1160         .addr           = omap44xx_dss_addrs,
1161         .user           = OCP_USER_MPU,
1162 };
1163
1164 /* dss slave ports */
1165 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1166         &omap44xx_l3_main_2__dss,
1167         &omap44xx_l4_per__dss,
1168 };
1169
1170 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1171         { .role = "sys_clk", .clk = "dss_sys_clk" },
1172         { .role = "tv_clk", .clk = "dss_tv_clk" },
1173         { .role = "dss_clk", .clk = "dss_dss_clk" },
1174         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1175 };
1176
1177 static struct omap_hwmod omap44xx_dss_hwmod = {
1178         .name           = "dss_core",
1179         .class          = &omap44xx_dss_hwmod_class,
1180         .main_clk       = "dss_dss_clk",
1181         .prcm = {
1182                 .omap4 = {
1183                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1184                 },
1185         },
1186         .opt_clks       = dss_opt_clks,
1187         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1188         .slaves         = omap44xx_dss_slaves,
1189         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1190         .masters        = omap44xx_dss_masters,
1191         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1192         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1193 };
1194
1195 /*
1196  * 'dispc' class
1197  * display controller
1198  */
1199
1200 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1201         .rev_offs       = 0x0000,
1202         .sysc_offs      = 0x0010,
1203         .syss_offs      = 0x0014,
1204         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1205                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1206                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1207                            SYSS_HAS_RESET_STATUS),
1208         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1209                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1210         .sysc_fields    = &omap_hwmod_sysc_type1,
1211 };
1212
1213 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1214         .name   = "dispc",
1215         .sysc   = &omap44xx_dispc_sysc,
1216 };
1217
1218 /* dss_dispc */
1219 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1220 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1221         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1222         { .irq = -1 }
1223 };
1224
1225 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1226         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1227         { .dma_req = -1 }
1228 };
1229
1230 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1231         {
1232                 .pa_start       = 0x58001000,
1233                 .pa_end         = 0x58001fff,
1234                 .flags          = ADDR_TYPE_RT
1235         },
1236         { }
1237 };
1238
1239 /* l3_main_2 -> dss_dispc */
1240 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1241         .master         = &omap44xx_l3_main_2_hwmod,
1242         .slave          = &omap44xx_dss_dispc_hwmod,
1243         .clk            = "dss_fck",
1244         .addr           = omap44xx_dss_dispc_dma_addrs,
1245         .user           = OCP_USER_SDMA,
1246 };
1247
1248 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1249         {
1250                 .pa_start       = 0x48041000,
1251                 .pa_end         = 0x48041fff,
1252                 .flags          = ADDR_TYPE_RT
1253         },
1254         { }
1255 };
1256
1257 /* l4_per -> dss_dispc */
1258 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1259         .master         = &omap44xx_l4_per_hwmod,
1260         .slave          = &omap44xx_dss_dispc_hwmod,
1261         .clk            = "l4_div_ck",
1262         .addr           = omap44xx_dss_dispc_addrs,
1263         .user           = OCP_USER_MPU,
1264 };
1265
1266 /* dss_dispc slave ports */
1267 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1268         &omap44xx_l3_main_2__dss_dispc,
1269         &omap44xx_l4_per__dss_dispc,
1270 };
1271
1272 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
1273         { .role = "sys_clk", .clk = "dss_sys_clk" },
1274         { .role = "tv_clk", .clk = "dss_tv_clk" },
1275         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1276 };
1277
1278 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1279         .name           = "dss_dispc",
1280         .class          = &omap44xx_dispc_hwmod_class,
1281         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1282         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1283         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1284         .main_clk       = "dss_dss_clk",
1285         .prcm = {
1286                 .omap4 = {
1287                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1288                 },
1289         },
1290         .opt_clks       = dss_dispc_opt_clks,
1291         .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
1292         .slaves         = omap44xx_dss_dispc_slaves,
1293         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1294         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1295 };
1296
1297 /*
1298  * 'dsi' class
1299  * display serial interface controller
1300  */
1301
1302 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1303         .rev_offs       = 0x0000,
1304         .sysc_offs      = 0x0010,
1305         .syss_offs      = 0x0014,
1306         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1307                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1308                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1309         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1310         .sysc_fields    = &omap_hwmod_sysc_type1,
1311 };
1312
1313 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1314         .name   = "dsi",
1315         .sysc   = &omap44xx_dsi_sysc,
1316 };
1317
1318 /* dss_dsi1 */
1319 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1320 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1321         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1322         { .irq = -1 }
1323 };
1324
1325 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1326         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1327         { .dma_req = -1 }
1328 };
1329
1330 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1331         {
1332                 .pa_start       = 0x58004000,
1333                 .pa_end         = 0x580041ff,
1334                 .flags          = ADDR_TYPE_RT
1335         },
1336         { }
1337 };
1338
1339 /* l3_main_2 -> dss_dsi1 */
1340 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1341         .master         = &omap44xx_l3_main_2_hwmod,
1342         .slave          = &omap44xx_dss_dsi1_hwmod,
1343         .clk            = "dss_fck",
1344         .addr           = omap44xx_dss_dsi1_dma_addrs,
1345         .user           = OCP_USER_SDMA,
1346 };
1347
1348 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1349         {
1350                 .pa_start       = 0x48044000,
1351                 .pa_end         = 0x480441ff,
1352                 .flags          = ADDR_TYPE_RT
1353         },
1354         { }
1355 };
1356
1357 /* l4_per -> dss_dsi1 */
1358 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1359         .master         = &omap44xx_l4_per_hwmod,
1360         .slave          = &omap44xx_dss_dsi1_hwmod,
1361         .clk            = "l4_div_ck",
1362         .addr           = omap44xx_dss_dsi1_addrs,
1363         .user           = OCP_USER_MPU,
1364 };
1365
1366 /* dss_dsi1 slave ports */
1367 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1368         &omap44xx_l3_main_2__dss_dsi1,
1369         &omap44xx_l4_per__dss_dsi1,
1370 };
1371
1372 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1373         { .role = "sys_clk", .clk = "dss_sys_clk" },
1374 };
1375
1376 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1377         .name           = "dss_dsi1",
1378         .class          = &omap44xx_dsi_hwmod_class,
1379         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1380         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1381         .main_clk       = "dss_dss_clk",
1382         .prcm = {
1383                 .omap4 = {
1384                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1385                 },
1386         },
1387         .opt_clks       = dss_dsi1_opt_clks,
1388         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1389         .slaves         = omap44xx_dss_dsi1_slaves,
1390         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1391         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1392 };
1393
1394 /* dss_dsi2 */
1395 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1396 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1397         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1398         { .irq = -1 }
1399 };
1400
1401 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1402         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1403         { .dma_req = -1 }
1404 };
1405
1406 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1407         {
1408                 .pa_start       = 0x58005000,
1409                 .pa_end         = 0x580051ff,
1410                 .flags          = ADDR_TYPE_RT
1411         },
1412         { }
1413 };
1414
1415 /* l3_main_2 -> dss_dsi2 */
1416 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1417         .master         = &omap44xx_l3_main_2_hwmod,
1418         .slave          = &omap44xx_dss_dsi2_hwmod,
1419         .clk            = "dss_fck",
1420         .addr           = omap44xx_dss_dsi2_dma_addrs,
1421         .user           = OCP_USER_SDMA,
1422 };
1423
1424 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1425         {
1426                 .pa_start       = 0x48045000,
1427                 .pa_end         = 0x480451ff,
1428                 .flags          = ADDR_TYPE_RT
1429         },
1430         { }
1431 };
1432
1433 /* l4_per -> dss_dsi2 */
1434 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1435         .master         = &omap44xx_l4_per_hwmod,
1436         .slave          = &omap44xx_dss_dsi2_hwmod,
1437         .clk            = "l4_div_ck",
1438         .addr           = omap44xx_dss_dsi2_addrs,
1439         .user           = OCP_USER_MPU,
1440 };
1441
1442 /* dss_dsi2 slave ports */
1443 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1444         &omap44xx_l3_main_2__dss_dsi2,
1445         &omap44xx_l4_per__dss_dsi2,
1446 };
1447
1448 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1449         { .role = "sys_clk", .clk = "dss_sys_clk" },
1450 };
1451
1452 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1453         .name           = "dss_dsi2",
1454         .class          = &omap44xx_dsi_hwmod_class,
1455         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1456         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1457         .main_clk       = "dss_dss_clk",
1458         .prcm = {
1459                 .omap4 = {
1460                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1461                 },
1462         },
1463         .opt_clks       = dss_dsi2_opt_clks,
1464         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1465         .slaves         = omap44xx_dss_dsi2_slaves,
1466         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1467         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1468 };
1469
1470 /*
1471  * 'hdmi' class
1472  * hdmi controller
1473  */
1474
1475 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1476         .rev_offs       = 0x0000,
1477         .sysc_offs      = 0x0010,
1478         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1479                            SYSC_HAS_SOFTRESET),
1480         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1481                            SIDLE_SMART_WKUP),
1482         .sysc_fields    = &omap_hwmod_sysc_type2,
1483 };
1484
1485 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1486         .name   = "hdmi",
1487         .sysc   = &omap44xx_hdmi_sysc,
1488 };
1489
1490 /* dss_hdmi */
1491 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1492 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1493         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1494         { .irq = -1 }
1495 };
1496
1497 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1498         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1499         { .dma_req = -1 }
1500 };
1501
1502 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1503         {
1504                 .pa_start       = 0x58006000,
1505                 .pa_end         = 0x58006fff,
1506                 .flags          = ADDR_TYPE_RT
1507         },
1508         { }
1509 };
1510
1511 /* l3_main_2 -> dss_hdmi */
1512 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1513         .master         = &omap44xx_l3_main_2_hwmod,
1514         .slave          = &omap44xx_dss_hdmi_hwmod,
1515         .clk            = "dss_fck",
1516         .addr           = omap44xx_dss_hdmi_dma_addrs,
1517         .user           = OCP_USER_SDMA,
1518 };
1519
1520 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1521         {
1522                 .pa_start       = 0x48046000,
1523                 .pa_end         = 0x48046fff,
1524                 .flags          = ADDR_TYPE_RT
1525         },
1526         { }
1527 };
1528
1529 /* l4_per -> dss_hdmi */
1530 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1531         .master         = &omap44xx_l4_per_hwmod,
1532         .slave          = &omap44xx_dss_hdmi_hwmod,
1533         .clk            = "l4_div_ck",
1534         .addr           = omap44xx_dss_hdmi_addrs,
1535         .user           = OCP_USER_MPU,
1536 };
1537
1538 /* dss_hdmi slave ports */
1539 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1540         &omap44xx_l3_main_2__dss_hdmi,
1541         &omap44xx_l4_per__dss_hdmi,
1542 };
1543
1544 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1545         { .role = "sys_clk", .clk = "dss_sys_clk" },
1546 };
1547
1548 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1549         .name           = "dss_hdmi",
1550         .class          = &omap44xx_hdmi_hwmod_class,
1551         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1552         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1553         .main_clk       = "dss_dss_clk",
1554         .prcm = {
1555                 .omap4 = {
1556                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1557                 },
1558         },
1559         .opt_clks       = dss_hdmi_opt_clks,
1560         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1561         .slaves         = omap44xx_dss_hdmi_slaves,
1562         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1563         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1564 };
1565
1566 /*
1567  * 'rfbi' class
1568  * remote frame buffer interface
1569  */
1570
1571 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1572         .rev_offs       = 0x0000,
1573         .sysc_offs      = 0x0010,
1574         .syss_offs      = 0x0014,
1575         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1576                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1577         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1578         .sysc_fields    = &omap_hwmod_sysc_type1,
1579 };
1580
1581 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1582         .name   = "rfbi",
1583         .sysc   = &omap44xx_rfbi_sysc,
1584 };
1585
1586 /* dss_rfbi */
1587 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1588 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1589         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1590         { .dma_req = -1 }
1591 };
1592
1593 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1594         {
1595                 .pa_start       = 0x58002000,
1596                 .pa_end         = 0x580020ff,
1597                 .flags          = ADDR_TYPE_RT
1598         },
1599         { }
1600 };
1601
1602 /* l3_main_2 -> dss_rfbi */
1603 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1604         .master         = &omap44xx_l3_main_2_hwmod,
1605         .slave          = &omap44xx_dss_rfbi_hwmod,
1606         .clk            = "dss_fck",
1607         .addr           = omap44xx_dss_rfbi_dma_addrs,
1608         .user           = OCP_USER_SDMA,
1609 };
1610
1611 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1612         {
1613                 .pa_start       = 0x48042000,
1614                 .pa_end         = 0x480420ff,
1615                 .flags          = ADDR_TYPE_RT
1616         },
1617         { }
1618 };
1619
1620 /* l4_per -> dss_rfbi */
1621 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1622         .master         = &omap44xx_l4_per_hwmod,
1623         .slave          = &omap44xx_dss_rfbi_hwmod,
1624         .clk            = "l4_div_ck",
1625         .addr           = omap44xx_dss_rfbi_addrs,
1626         .user           = OCP_USER_MPU,
1627 };
1628
1629 /* dss_rfbi slave ports */
1630 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1631         &omap44xx_l3_main_2__dss_rfbi,
1632         &omap44xx_l4_per__dss_rfbi,
1633 };
1634
1635 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1636         { .role = "ick", .clk = "dss_fck" },
1637 };
1638
1639 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1640         .name           = "dss_rfbi",
1641         .class          = &omap44xx_rfbi_hwmod_class,
1642         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1643         .main_clk       = "dss_dss_clk",
1644         .prcm = {
1645                 .omap4 = {
1646                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1647                 },
1648         },
1649         .opt_clks       = dss_rfbi_opt_clks,
1650         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1651         .slaves         = omap44xx_dss_rfbi_slaves,
1652         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1653         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1654 };
1655
1656 /*
1657  * 'venc' class
1658  * video encoder
1659  */
1660
1661 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1662         .name   = "venc",
1663 };
1664
1665 /* dss_venc */
1666 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1667 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1668         {
1669                 .pa_start       = 0x58003000,
1670                 .pa_end         = 0x580030ff,
1671                 .flags          = ADDR_TYPE_RT
1672         },
1673         { }
1674 };
1675
1676 /* l3_main_2 -> dss_venc */
1677 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1678         .master         = &omap44xx_l3_main_2_hwmod,
1679         .slave          = &omap44xx_dss_venc_hwmod,
1680         .clk            = "dss_fck",
1681         .addr           = omap44xx_dss_venc_dma_addrs,
1682         .user           = OCP_USER_SDMA,
1683 };
1684
1685 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1686         {
1687                 .pa_start       = 0x48043000,
1688                 .pa_end         = 0x480430ff,
1689                 .flags          = ADDR_TYPE_RT
1690         },
1691         { }
1692 };
1693
1694 /* l4_per -> dss_venc */
1695 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1696         .master         = &omap44xx_l4_per_hwmod,
1697         .slave          = &omap44xx_dss_venc_hwmod,
1698         .clk            = "l4_div_ck",
1699         .addr           = omap44xx_dss_venc_addrs,
1700         .user           = OCP_USER_MPU,
1701 };
1702
1703 /* dss_venc slave ports */
1704 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1705         &omap44xx_l3_main_2__dss_venc,
1706         &omap44xx_l4_per__dss_venc,
1707 };
1708
1709 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1710         .name           = "dss_venc",
1711         .class          = &omap44xx_venc_hwmod_class,
1712         .main_clk       = "dss_dss_clk",
1713         .prcm = {
1714                 .omap4 = {
1715                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1716                 },
1717         },
1718         .slaves         = omap44xx_dss_venc_slaves,
1719         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1720         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1721 };
1722
1723 /*
1724  * 'gpio' class
1725  * general purpose io module
1726  */
1727
1728 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1729         .rev_offs       = 0x0000,
1730         .sysc_offs      = 0x0010,
1731         .syss_offs      = 0x0114,
1732         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1733                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1734                            SYSS_HAS_RESET_STATUS),
1735         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1736                            SIDLE_SMART_WKUP),
1737         .sysc_fields    = &omap_hwmod_sysc_type1,
1738 };
1739
1740 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1741         .name   = "gpio",
1742         .sysc   = &omap44xx_gpio_sysc,
1743         .rev    = 2,
1744 };
1745
1746 /* gpio dev_attr */
1747 static struct omap_gpio_dev_attr gpio_dev_attr = {
1748         .bank_width     = 32,
1749         .dbck_flag      = true,
1750 };
1751
1752 /* gpio1 */
1753 static struct omap_hwmod omap44xx_gpio1_hwmod;
1754 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1755         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1756         { .irq = -1 }
1757 };
1758
1759 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1760         {
1761                 .pa_start       = 0x4a310000,
1762                 .pa_end         = 0x4a3101ff,
1763                 .flags          = ADDR_TYPE_RT
1764         },
1765         { }
1766 };
1767
1768 /* l4_wkup -> gpio1 */
1769 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1770         .master         = &omap44xx_l4_wkup_hwmod,
1771         .slave          = &omap44xx_gpio1_hwmod,
1772         .clk            = "l4_wkup_clk_mux_ck",
1773         .addr           = omap44xx_gpio1_addrs,
1774         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1775 };
1776
1777 /* gpio1 slave ports */
1778 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1779         &omap44xx_l4_wkup__gpio1,
1780 };
1781
1782 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1783         { .role = "dbclk", .clk = "gpio1_dbclk" },
1784 };
1785
1786 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1787         .name           = "gpio1",
1788         .class          = &omap44xx_gpio_hwmod_class,
1789         .mpu_irqs       = omap44xx_gpio1_irqs,
1790         .main_clk       = "gpio1_ick",
1791         .prcm = {
1792                 .omap4 = {
1793                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1794                 },
1795         },
1796         .opt_clks       = gpio1_opt_clks,
1797         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1798         .dev_attr       = &gpio_dev_attr,
1799         .slaves         = omap44xx_gpio1_slaves,
1800         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1801         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1802 };
1803
1804 /* gpio2 */
1805 static struct omap_hwmod omap44xx_gpio2_hwmod;
1806 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1807         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1808         { .irq = -1 }
1809 };
1810
1811 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1812         {
1813                 .pa_start       = 0x48055000,
1814                 .pa_end         = 0x480551ff,
1815                 .flags          = ADDR_TYPE_RT
1816         },
1817         { }
1818 };
1819
1820 /* l4_per -> gpio2 */
1821 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1822         .master         = &omap44xx_l4_per_hwmod,
1823         .slave          = &omap44xx_gpio2_hwmod,
1824         .clk            = "l4_div_ck",
1825         .addr           = omap44xx_gpio2_addrs,
1826         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1827 };
1828
1829 /* gpio2 slave ports */
1830 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1831         &omap44xx_l4_per__gpio2,
1832 };
1833
1834 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1835         { .role = "dbclk", .clk = "gpio2_dbclk" },
1836 };
1837
1838 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1839         .name           = "gpio2",
1840         .class          = &omap44xx_gpio_hwmod_class,
1841         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1842         .mpu_irqs       = omap44xx_gpio2_irqs,
1843         .main_clk       = "gpio2_ick",
1844         .prcm = {
1845                 .omap4 = {
1846                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1847                 },
1848         },
1849         .opt_clks       = gpio2_opt_clks,
1850         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1851         .dev_attr       = &gpio_dev_attr,
1852         .slaves         = omap44xx_gpio2_slaves,
1853         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1854         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1855 };
1856
1857 /* gpio3 */
1858 static struct omap_hwmod omap44xx_gpio3_hwmod;
1859 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1860         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1861         { .irq = -1 }
1862 };
1863
1864 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1865         {
1866                 .pa_start       = 0x48057000,
1867                 .pa_end         = 0x480571ff,
1868                 .flags          = ADDR_TYPE_RT
1869         },
1870         { }
1871 };
1872
1873 /* l4_per -> gpio3 */
1874 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1875         .master         = &omap44xx_l4_per_hwmod,
1876         .slave          = &omap44xx_gpio3_hwmod,
1877         .clk            = "l4_div_ck",
1878         .addr           = omap44xx_gpio3_addrs,
1879         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1880 };
1881
1882 /* gpio3 slave ports */
1883 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1884         &omap44xx_l4_per__gpio3,
1885 };
1886
1887 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1888         { .role = "dbclk", .clk = "gpio3_dbclk" },
1889 };
1890
1891 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1892         .name           = "gpio3",
1893         .class          = &omap44xx_gpio_hwmod_class,
1894         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1895         .mpu_irqs       = omap44xx_gpio3_irqs,
1896         .main_clk       = "gpio3_ick",
1897         .prcm = {
1898                 .omap4 = {
1899                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1900                 },
1901         },
1902         .opt_clks       = gpio3_opt_clks,
1903         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1904         .dev_attr       = &gpio_dev_attr,
1905         .slaves         = omap44xx_gpio3_slaves,
1906         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1907         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1908 };
1909
1910 /* gpio4 */
1911 static struct omap_hwmod omap44xx_gpio4_hwmod;
1912 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1913         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1914         { .irq = -1 }
1915 };
1916
1917 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1918         {
1919                 .pa_start       = 0x48059000,
1920                 .pa_end         = 0x480591ff,
1921                 .flags          = ADDR_TYPE_RT
1922         },
1923         { }
1924 };
1925
1926 /* l4_per -> gpio4 */
1927 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1928         .master         = &omap44xx_l4_per_hwmod,
1929         .slave          = &omap44xx_gpio4_hwmod,
1930         .clk            = "l4_div_ck",
1931         .addr           = omap44xx_gpio4_addrs,
1932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1933 };
1934
1935 /* gpio4 slave ports */
1936 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1937         &omap44xx_l4_per__gpio4,
1938 };
1939
1940 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1941         { .role = "dbclk", .clk = "gpio4_dbclk" },
1942 };
1943
1944 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1945         .name           = "gpio4",
1946         .class          = &omap44xx_gpio_hwmod_class,
1947         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1948         .mpu_irqs       = omap44xx_gpio4_irqs,
1949         .main_clk       = "gpio4_ick",
1950         .prcm = {
1951                 .omap4 = {
1952                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1953                 },
1954         },
1955         .opt_clks       = gpio4_opt_clks,
1956         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1957         .dev_attr       = &gpio_dev_attr,
1958         .slaves         = omap44xx_gpio4_slaves,
1959         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1961 };
1962
1963 /* gpio5 */
1964 static struct omap_hwmod omap44xx_gpio5_hwmod;
1965 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1966         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1967         { .irq = -1 }
1968 };
1969
1970 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1971         {
1972                 .pa_start       = 0x4805b000,
1973                 .pa_end         = 0x4805b1ff,
1974                 .flags          = ADDR_TYPE_RT
1975         },
1976         { }
1977 };
1978
1979 /* l4_per -> gpio5 */
1980 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1981         .master         = &omap44xx_l4_per_hwmod,
1982         .slave          = &omap44xx_gpio5_hwmod,
1983         .clk            = "l4_div_ck",
1984         .addr           = omap44xx_gpio5_addrs,
1985         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1986 };
1987
1988 /* gpio5 slave ports */
1989 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1990         &omap44xx_l4_per__gpio5,
1991 };
1992
1993 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1994         { .role = "dbclk", .clk = "gpio5_dbclk" },
1995 };
1996
1997 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1998         .name           = "gpio5",
1999         .class          = &omap44xx_gpio_hwmod_class,
2000         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2001         .mpu_irqs       = omap44xx_gpio5_irqs,
2002         .main_clk       = "gpio5_ick",
2003         .prcm = {
2004                 .omap4 = {
2005                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
2006                 },
2007         },
2008         .opt_clks       = gpio5_opt_clks,
2009         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2010         .dev_attr       = &gpio_dev_attr,
2011         .slaves         = omap44xx_gpio5_slaves,
2012         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2013         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2014 };
2015
2016 /* gpio6 */
2017 static struct omap_hwmod omap44xx_gpio6_hwmod;
2018 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2019         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2020         { .irq = -1 }
2021 };
2022
2023 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2024         {
2025                 .pa_start       = 0x4805d000,
2026                 .pa_end         = 0x4805d1ff,
2027                 .flags          = ADDR_TYPE_RT
2028         },
2029         { }
2030 };
2031
2032 /* l4_per -> gpio6 */
2033 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2034         .master         = &omap44xx_l4_per_hwmod,
2035         .slave          = &omap44xx_gpio6_hwmod,
2036         .clk            = "l4_div_ck",
2037         .addr           = omap44xx_gpio6_addrs,
2038         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2039 };
2040
2041 /* gpio6 slave ports */
2042 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2043         &omap44xx_l4_per__gpio6,
2044 };
2045
2046 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2047         { .role = "dbclk", .clk = "gpio6_dbclk" },
2048 };
2049
2050 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2051         .name           = "gpio6",
2052         .class          = &omap44xx_gpio_hwmod_class,
2053         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2054         .mpu_irqs       = omap44xx_gpio6_irqs,
2055         .main_clk       = "gpio6_ick",
2056         .prcm = {
2057                 .omap4 = {
2058                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2059                 },
2060         },
2061         .opt_clks       = gpio6_opt_clks,
2062         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2063         .dev_attr       = &gpio_dev_attr,
2064         .slaves         = omap44xx_gpio6_slaves,
2065         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2066         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2067 };
2068
2069 /*
2070  * 'hsi' class
2071  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2072  * serial if)
2073  */
2074
2075 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2076         .rev_offs       = 0x0000,
2077         .sysc_offs      = 0x0010,
2078         .syss_offs      = 0x0014,
2079         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2080                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2081                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2082         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2083                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2084                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2085         .sysc_fields    = &omap_hwmod_sysc_type1,
2086 };
2087
2088 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2089         .name   = "hsi",
2090         .sysc   = &omap44xx_hsi_sysc,
2091 };
2092
2093 /* hsi */
2094 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2095         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2096         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2097         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2098         { .irq = -1 }
2099 };
2100
2101 /* hsi master ports */
2102 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2103         &omap44xx_hsi__l3_main_2,
2104 };
2105
2106 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2107         {
2108                 .pa_start       = 0x4a058000,
2109                 .pa_end         = 0x4a05bfff,
2110                 .flags          = ADDR_TYPE_RT
2111         },
2112         { }
2113 };
2114
2115 /* l4_cfg -> hsi */
2116 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2117         .master         = &omap44xx_l4_cfg_hwmod,
2118         .slave          = &omap44xx_hsi_hwmod,
2119         .clk            = "l4_div_ck",
2120         .addr           = omap44xx_hsi_addrs,
2121         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2122 };
2123
2124 /* hsi slave ports */
2125 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2126         &omap44xx_l4_cfg__hsi,
2127 };
2128
2129 static struct omap_hwmod omap44xx_hsi_hwmod = {
2130         .name           = "hsi",
2131         .class          = &omap44xx_hsi_hwmod_class,
2132         .mpu_irqs       = omap44xx_hsi_irqs,
2133         .main_clk       = "hsi_fck",
2134         .prcm = {
2135                 .omap4 = {
2136                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2137                 },
2138         },
2139         .slaves         = omap44xx_hsi_slaves,
2140         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2141         .masters        = omap44xx_hsi_masters,
2142         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2143         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2144 };
2145
2146 /*
2147  * 'i2c' class
2148  * multimaster high-speed i2c controller
2149  */
2150
2151 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2152         .sysc_offs      = 0x0010,
2153         .syss_offs      = 0x0090,
2154         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2155                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2156                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2157         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2158                            SIDLE_SMART_WKUP),
2159         .sysc_fields    = &omap_hwmod_sysc_type1,
2160 };
2161
2162 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2163         .name   = "i2c",
2164         .sysc   = &omap44xx_i2c_sysc,
2165         .rev    = OMAP_I2C_IP_VERSION_2,
2166         .reset  = &omap_i2c_reset,
2167 };
2168
2169 static struct omap_i2c_dev_attr i2c_dev_attr = {
2170         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2171 };
2172
2173 /* i2c1 */
2174 static struct omap_hwmod omap44xx_i2c1_hwmod;
2175 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2176         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2177         { .irq = -1 }
2178 };
2179
2180 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2181         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2182         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2183         { .dma_req = -1 }
2184 };
2185
2186 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2187         {
2188                 .pa_start       = 0x48070000,
2189                 .pa_end         = 0x480700ff,
2190                 .flags          = ADDR_TYPE_RT
2191         },
2192         { }
2193 };
2194
2195 /* l4_per -> i2c1 */
2196 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2197         .master         = &omap44xx_l4_per_hwmod,
2198         .slave          = &omap44xx_i2c1_hwmod,
2199         .clk            = "l4_div_ck",
2200         .addr           = omap44xx_i2c1_addrs,
2201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2202 };
2203
2204 /* i2c1 slave ports */
2205 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2206         &omap44xx_l4_per__i2c1,
2207 };
2208
2209 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2210         .name           = "i2c1",
2211         .class          = &omap44xx_i2c_hwmod_class,
2212         .flags          = HWMOD_16BIT_REG,
2213         .mpu_irqs       = omap44xx_i2c1_irqs,
2214         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2215         .main_clk       = "i2c1_fck",
2216         .prcm = {
2217                 .omap4 = {
2218                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2219                 },
2220         },
2221         .slaves         = omap44xx_i2c1_slaves,
2222         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2223         .dev_attr       = &i2c_dev_attr,
2224         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2225 };
2226
2227 /* i2c2 */
2228 static struct omap_hwmod omap44xx_i2c2_hwmod;
2229 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2230         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2231         { .irq = -1 }
2232 };
2233
2234 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2235         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2236         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2237         { .dma_req = -1 }
2238 };
2239
2240 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2241         {
2242                 .pa_start       = 0x48072000,
2243                 .pa_end         = 0x480720ff,
2244                 .flags          = ADDR_TYPE_RT
2245         },
2246         { }
2247 };
2248
2249 /* l4_per -> i2c2 */
2250 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2251         .master         = &omap44xx_l4_per_hwmod,
2252         .slave          = &omap44xx_i2c2_hwmod,
2253         .clk            = "l4_div_ck",
2254         .addr           = omap44xx_i2c2_addrs,
2255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2256 };
2257
2258 /* i2c2 slave ports */
2259 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2260         &omap44xx_l4_per__i2c2,
2261 };
2262
2263 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2264         .name           = "i2c2",
2265         .class          = &omap44xx_i2c_hwmod_class,
2266         .flags          = HWMOD_16BIT_REG,
2267         .mpu_irqs       = omap44xx_i2c2_irqs,
2268         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2269         .main_clk       = "i2c2_fck",
2270         .prcm = {
2271                 .omap4 = {
2272                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2273                 },
2274         },
2275         .slaves         = omap44xx_i2c2_slaves,
2276         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2277         .dev_attr       = &i2c_dev_attr,
2278         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2279 };
2280
2281 /* i2c3 */
2282 static struct omap_hwmod omap44xx_i2c3_hwmod;
2283 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2284         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2285         { .irq = -1 }
2286 };
2287
2288 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2289         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2290         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2291         { .dma_req = -1 }
2292 };
2293
2294 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2295         {
2296                 .pa_start       = 0x48060000,
2297                 .pa_end         = 0x480600ff,
2298                 .flags          = ADDR_TYPE_RT
2299         },
2300         { }
2301 };
2302
2303 /* l4_per -> i2c3 */
2304 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2305         .master         = &omap44xx_l4_per_hwmod,
2306         .slave          = &omap44xx_i2c3_hwmod,
2307         .clk            = "l4_div_ck",
2308         .addr           = omap44xx_i2c3_addrs,
2309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2310 };
2311
2312 /* i2c3 slave ports */
2313 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2314         &omap44xx_l4_per__i2c3,
2315 };
2316
2317 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2318         .name           = "i2c3",
2319         .class          = &omap44xx_i2c_hwmod_class,
2320         .flags          = HWMOD_16BIT_REG,
2321         .mpu_irqs       = omap44xx_i2c3_irqs,
2322         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2323         .main_clk       = "i2c3_fck",
2324         .prcm = {
2325                 .omap4 = {
2326                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2327                 },
2328         },
2329         .slaves         = omap44xx_i2c3_slaves,
2330         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2331         .dev_attr       = &i2c_dev_attr,
2332         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2333 };
2334
2335 /* i2c4 */
2336 static struct omap_hwmod omap44xx_i2c4_hwmod;
2337 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2338         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2339         { .irq = -1 }
2340 };
2341
2342 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2343         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2344         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2345         { .dma_req = -1 }
2346 };
2347
2348 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2349         {
2350                 .pa_start       = 0x48350000,
2351                 .pa_end         = 0x483500ff,
2352                 .flags          = ADDR_TYPE_RT
2353         },
2354         { }
2355 };
2356
2357 /* l4_per -> i2c4 */
2358 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2359         .master         = &omap44xx_l4_per_hwmod,
2360         .slave          = &omap44xx_i2c4_hwmod,
2361         .clk            = "l4_div_ck",
2362         .addr           = omap44xx_i2c4_addrs,
2363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2364 };
2365
2366 /* i2c4 slave ports */
2367 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2368         &omap44xx_l4_per__i2c4,
2369 };
2370
2371 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2372         .name           = "i2c4",
2373         .class          = &omap44xx_i2c_hwmod_class,
2374         .flags          = HWMOD_16BIT_REG,
2375         .mpu_irqs       = omap44xx_i2c4_irqs,
2376         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2377         .main_clk       = "i2c4_fck",
2378         .prcm = {
2379                 .omap4 = {
2380                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2381                 },
2382         },
2383         .slaves         = omap44xx_i2c4_slaves,
2384         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2385         .dev_attr       = &i2c_dev_attr,
2386         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2387 };
2388
2389 /*
2390  * 'ipu' class
2391  * imaging processor unit
2392  */
2393
2394 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2395         .name   = "ipu",
2396 };
2397
2398 /* ipu */
2399 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2400         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2401         { .irq = -1 }
2402 };
2403
2404 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2405         { .name = "cpu0", .rst_shift = 0 },
2406 };
2407
2408 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2409         { .name = "cpu1", .rst_shift = 1 },
2410 };
2411
2412 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2413         { .name = "mmu_cache", .rst_shift = 2 },
2414 };
2415
2416 /* ipu master ports */
2417 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2418         &omap44xx_ipu__l3_main_2,
2419 };
2420
2421 /* l3_main_2 -> ipu */
2422 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2423         .master         = &omap44xx_l3_main_2_hwmod,
2424         .slave          = &omap44xx_ipu_hwmod,
2425         .clk            = "l3_div_ck",
2426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2427 };
2428
2429 /* ipu slave ports */
2430 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2431         &omap44xx_l3_main_2__ipu,
2432 };
2433
2434 /* Pseudo hwmod for reset control purpose only */
2435 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2436         .name           = "ipu_c0",
2437         .class          = &omap44xx_ipu_hwmod_class,
2438         .flags          = HWMOD_INIT_NO_RESET,
2439         .rst_lines      = omap44xx_ipu_c0_resets,
2440         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2441         .prcm = {
2442                 .omap4 = {
2443                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2444                 },
2445         },
2446         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2447 };
2448
2449 /* Pseudo hwmod for reset control purpose only */
2450 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2451         .name           = "ipu_c1",
2452         .class          = &omap44xx_ipu_hwmod_class,
2453         .flags          = HWMOD_INIT_NO_RESET,
2454         .rst_lines      = omap44xx_ipu_c1_resets,
2455         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2456         .prcm = {
2457                 .omap4 = {
2458                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2459                 },
2460         },
2461         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2462 };
2463
2464 static struct omap_hwmod omap44xx_ipu_hwmod = {
2465         .name           = "ipu",
2466         .class          = &omap44xx_ipu_hwmod_class,
2467         .mpu_irqs       = omap44xx_ipu_irqs,
2468         .rst_lines      = omap44xx_ipu_resets,
2469         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2470         .main_clk       = "ipu_fck",
2471         .prcm = {
2472                 .omap4 = {
2473                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2474                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2475                 },
2476         },
2477         .slaves         = omap44xx_ipu_slaves,
2478         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2479         .masters        = omap44xx_ipu_masters,
2480         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2481         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2482 };
2483
2484 /*
2485  * 'iss' class
2486  * external images sensor pixel data processor
2487  */
2488
2489 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2490         .rev_offs       = 0x0000,
2491         .sysc_offs      = 0x0010,
2492         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2493                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2494         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2495                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2496                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2497         .sysc_fields    = &omap_hwmod_sysc_type2,
2498 };
2499
2500 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2501         .name   = "iss",
2502         .sysc   = &omap44xx_iss_sysc,
2503 };
2504
2505 /* iss */
2506 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2507         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2508         { .irq = -1 }
2509 };
2510
2511 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2512         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2513         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2514         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2515         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2516         { .dma_req = -1 }
2517 };
2518
2519 /* iss master ports */
2520 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2521         &omap44xx_iss__l3_main_2,
2522 };
2523
2524 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2525         {
2526                 .pa_start       = 0x52000000,
2527                 .pa_end         = 0x520000ff,
2528                 .flags          = ADDR_TYPE_RT
2529         },
2530         { }
2531 };
2532
2533 /* l3_main_2 -> iss */
2534 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2535         .master         = &omap44xx_l3_main_2_hwmod,
2536         .slave          = &omap44xx_iss_hwmod,
2537         .clk            = "l3_div_ck",
2538         .addr           = omap44xx_iss_addrs,
2539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2540 };
2541
2542 /* iss slave ports */
2543 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2544         &omap44xx_l3_main_2__iss,
2545 };
2546
2547 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2548         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2549 };
2550
2551 static struct omap_hwmod omap44xx_iss_hwmod = {
2552         .name           = "iss",
2553         .class          = &omap44xx_iss_hwmod_class,
2554         .mpu_irqs       = omap44xx_iss_irqs,
2555         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2556         .main_clk       = "iss_fck",
2557         .prcm = {
2558                 .omap4 = {
2559                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2560                 },
2561         },
2562         .opt_clks       = iss_opt_clks,
2563         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2564         .slaves         = omap44xx_iss_slaves,
2565         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2566         .masters        = omap44xx_iss_masters,
2567         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2568         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2569 };
2570
2571 /*
2572  * 'iva' class
2573  * multi-standard video encoder/decoder hardware accelerator
2574  */
2575
2576 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2577         .name   = "iva",
2578 };
2579
2580 /* iva */
2581 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2582         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2583         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2584         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2585         { .irq = -1 }
2586 };
2587
2588 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2589         { .name = "logic", .rst_shift = 2 },
2590 };
2591
2592 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2593         { .name = "seq0", .rst_shift = 0 },
2594 };
2595
2596 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2597         { .name = "seq1", .rst_shift = 1 },
2598 };
2599
2600 /* iva master ports */
2601 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2602         &omap44xx_iva__l3_main_2,
2603         &omap44xx_iva__l3_instr,
2604 };
2605
2606 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2607         {
2608                 .pa_start       = 0x5a000000,
2609                 .pa_end         = 0x5a07ffff,
2610                 .flags          = ADDR_TYPE_RT
2611         },
2612         { }
2613 };
2614
2615 /* l3_main_2 -> iva */
2616 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2617         .master         = &omap44xx_l3_main_2_hwmod,
2618         .slave          = &omap44xx_iva_hwmod,
2619         .clk            = "l3_div_ck",
2620         .addr           = omap44xx_iva_addrs,
2621         .user           = OCP_USER_MPU,
2622 };
2623
2624 /* iva slave ports */
2625 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2626         &omap44xx_dsp__iva,
2627         &omap44xx_l3_main_2__iva,
2628 };
2629
2630 /* Pseudo hwmod for reset control purpose only */
2631 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2632         .name           = "iva_seq0",
2633         .class          = &omap44xx_iva_hwmod_class,
2634         .flags          = HWMOD_INIT_NO_RESET,
2635         .rst_lines      = omap44xx_iva_seq0_resets,
2636         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2637         .prcm = {
2638                 .omap4 = {
2639                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2640                 },
2641         },
2642         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2643 };
2644
2645 /* Pseudo hwmod for reset control purpose only */
2646 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2647         .name           = "iva_seq1",
2648         .class          = &omap44xx_iva_hwmod_class,
2649         .flags          = HWMOD_INIT_NO_RESET,
2650         .rst_lines      = omap44xx_iva_seq1_resets,
2651         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2652         .prcm = {
2653                 .omap4 = {
2654                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2655                 },
2656         },
2657         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2658 };
2659
2660 static struct omap_hwmod omap44xx_iva_hwmod = {
2661         .name           = "iva",
2662         .class          = &omap44xx_iva_hwmod_class,
2663         .mpu_irqs       = omap44xx_iva_irqs,
2664         .rst_lines      = omap44xx_iva_resets,
2665         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2666         .main_clk       = "iva_fck",
2667         .prcm = {
2668                 .omap4 = {
2669                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2670                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2671                 },
2672         },
2673         .slaves         = omap44xx_iva_slaves,
2674         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2675         .masters        = omap44xx_iva_masters,
2676         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2677         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2678 };
2679
2680 /*
2681  * 'kbd' class
2682  * keyboard controller
2683  */
2684
2685 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2686         .rev_offs       = 0x0000,
2687         .sysc_offs      = 0x0010,
2688         .syss_offs      = 0x0014,
2689         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2690                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2691                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2692                            SYSS_HAS_RESET_STATUS),
2693         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2694         .sysc_fields    = &omap_hwmod_sysc_type1,
2695 };
2696
2697 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2698         .name   = "kbd",
2699         .sysc   = &omap44xx_kbd_sysc,
2700 };
2701
2702 /* kbd */
2703 static struct omap_hwmod omap44xx_kbd_hwmod;
2704 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2705         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2706         { .irq = -1 }
2707 };
2708
2709 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2710         {
2711                 .pa_start       = 0x4a31c000,
2712                 .pa_end         = 0x4a31c07f,
2713                 .flags          = ADDR_TYPE_RT
2714         },
2715         { }
2716 };
2717
2718 /* l4_wkup -> kbd */
2719 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2720         .master         = &omap44xx_l4_wkup_hwmod,
2721         .slave          = &omap44xx_kbd_hwmod,
2722         .clk            = "l4_wkup_clk_mux_ck",
2723         .addr           = omap44xx_kbd_addrs,
2724         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2725 };
2726
2727 /* kbd slave ports */
2728 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2729         &omap44xx_l4_wkup__kbd,
2730 };
2731
2732 static struct omap_hwmod omap44xx_kbd_hwmod = {
2733         .name           = "kbd",
2734         .class          = &omap44xx_kbd_hwmod_class,
2735         .mpu_irqs       = omap44xx_kbd_irqs,
2736         .main_clk       = "kbd_fck",
2737         .prcm = {
2738                 .omap4 = {
2739                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2740                 },
2741         },
2742         .slaves         = omap44xx_kbd_slaves,
2743         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2744         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2745 };
2746
2747 /*
2748  * 'mailbox' class
2749  * mailbox module allowing communication between the on-chip processors using a
2750  * queued mailbox-interrupt mechanism.
2751  */
2752
2753 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2754         .rev_offs       = 0x0000,
2755         .sysc_offs      = 0x0010,
2756         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2757                            SYSC_HAS_SOFTRESET),
2758         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2759         .sysc_fields    = &omap_hwmod_sysc_type2,
2760 };
2761
2762 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2763         .name   = "mailbox",
2764         .sysc   = &omap44xx_mailbox_sysc,
2765 };
2766
2767 /* mailbox */
2768 static struct omap_hwmod omap44xx_mailbox_hwmod;
2769 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2770         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2771         { .irq = -1 }
2772 };
2773
2774 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2775         {
2776                 .pa_start       = 0x4a0f4000,
2777                 .pa_end         = 0x4a0f41ff,
2778                 .flags          = ADDR_TYPE_RT
2779         },
2780         { }
2781 };
2782
2783 /* l4_cfg -> mailbox */
2784 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2785         .master         = &omap44xx_l4_cfg_hwmod,
2786         .slave          = &omap44xx_mailbox_hwmod,
2787         .clk            = "l4_div_ck",
2788         .addr           = omap44xx_mailbox_addrs,
2789         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2790 };
2791
2792 /* mailbox slave ports */
2793 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2794         &omap44xx_l4_cfg__mailbox,
2795 };
2796
2797 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2798         .name           = "mailbox",
2799         .class          = &omap44xx_mailbox_hwmod_class,
2800         .mpu_irqs       = omap44xx_mailbox_irqs,
2801         .prcm = {
2802                 .omap4 = {
2803                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2804                 },
2805         },
2806         .slaves         = omap44xx_mailbox_slaves,
2807         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2808         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2809 };
2810
2811 /*
2812  * 'mcbsp' class
2813  * multi channel buffered serial port controller
2814  */
2815
2816 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2817         .sysc_offs      = 0x008c,
2818         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2819                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2820         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2821         .sysc_fields    = &omap_hwmod_sysc_type1,
2822 };
2823
2824 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2825         .name   = "mcbsp",
2826         .sysc   = &omap44xx_mcbsp_sysc,
2827         .rev    = MCBSP_CONFIG_TYPE4,
2828 };
2829
2830 /* mcbsp1 */
2831 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2832 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2833         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2834         { .irq = -1 }
2835 };
2836
2837 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2838         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2839         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2840         { .dma_req = -1 }
2841 };
2842
2843 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2844         {
2845                 .name           = "mpu",
2846                 .pa_start       = 0x40122000,
2847                 .pa_end         = 0x401220ff,
2848                 .flags          = ADDR_TYPE_RT
2849         },
2850         { }
2851 };
2852
2853 /* l4_abe -> mcbsp1 */
2854 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2855         .master         = &omap44xx_l4_abe_hwmod,
2856         .slave          = &omap44xx_mcbsp1_hwmod,
2857         .clk            = "ocp_abe_iclk",
2858         .addr           = omap44xx_mcbsp1_addrs,
2859         .user           = OCP_USER_MPU,
2860 };
2861
2862 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2863         {
2864                 .name           = "dma",
2865                 .pa_start       = 0x49022000,
2866                 .pa_end         = 0x490220ff,
2867                 .flags          = ADDR_TYPE_RT
2868         },
2869         { }
2870 };
2871
2872 /* l4_abe -> mcbsp1 (dma) */
2873 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2874         .master         = &omap44xx_l4_abe_hwmod,
2875         .slave          = &omap44xx_mcbsp1_hwmod,
2876         .clk            = "ocp_abe_iclk",
2877         .addr           = omap44xx_mcbsp1_dma_addrs,
2878         .user           = OCP_USER_SDMA,
2879 };
2880
2881 /* mcbsp1 slave ports */
2882 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2883         &omap44xx_l4_abe__mcbsp1,
2884         &omap44xx_l4_abe__mcbsp1_dma,
2885 };
2886
2887 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2888         .name           = "mcbsp1",
2889         .class          = &omap44xx_mcbsp_hwmod_class,
2890         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2891         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2892         .main_clk       = "mcbsp1_fck",
2893         .prcm = {
2894                 .omap4 = {
2895                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2896                 },
2897         },
2898         .slaves         = omap44xx_mcbsp1_slaves,
2899         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2900         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2901 };
2902
2903 /* mcbsp2 */
2904 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2905 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2906         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2907         { .irq = -1 }
2908 };
2909
2910 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2911         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2912         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2913         { .dma_req = -1 }
2914 };
2915
2916 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2917         {
2918                 .name           = "mpu",
2919                 .pa_start       = 0x40124000,
2920                 .pa_end         = 0x401240ff,
2921                 .flags          = ADDR_TYPE_RT
2922         },
2923         { }
2924 };
2925
2926 /* l4_abe -> mcbsp2 */
2927 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2928         .master         = &omap44xx_l4_abe_hwmod,
2929         .slave          = &omap44xx_mcbsp2_hwmod,
2930         .clk            = "ocp_abe_iclk",
2931         .addr           = omap44xx_mcbsp2_addrs,
2932         .user           = OCP_USER_MPU,
2933 };
2934
2935 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2936         {
2937                 .name           = "dma",
2938                 .pa_start       = 0x49024000,
2939                 .pa_end         = 0x490240ff,
2940                 .flags          = ADDR_TYPE_RT
2941         },
2942         { }
2943 };
2944
2945 /* l4_abe -> mcbsp2 (dma) */
2946 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2947         .master         = &omap44xx_l4_abe_hwmod,
2948         .slave          = &omap44xx_mcbsp2_hwmod,
2949         .clk            = "ocp_abe_iclk",
2950         .addr           = omap44xx_mcbsp2_dma_addrs,
2951         .user           = OCP_USER_SDMA,
2952 };
2953
2954 /* mcbsp2 slave ports */
2955 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2956         &omap44xx_l4_abe__mcbsp2,
2957         &omap44xx_l4_abe__mcbsp2_dma,
2958 };
2959
2960 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2961         .name           = "mcbsp2",
2962         .class          = &omap44xx_mcbsp_hwmod_class,
2963         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2964         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2965         .main_clk       = "mcbsp2_fck",
2966         .prcm = {
2967                 .omap4 = {
2968                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2969                 },
2970         },
2971         .slaves         = omap44xx_mcbsp2_slaves,
2972         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2973         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2974 };
2975
2976 /* mcbsp3 */
2977 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2978 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2979         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2980         { .irq = -1 }
2981 };
2982
2983 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2984         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2985         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2986         { .dma_req = -1 }
2987 };
2988
2989 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2990         {
2991                 .name           = "mpu",
2992                 .pa_start       = 0x40126000,
2993                 .pa_end         = 0x401260ff,
2994                 .flags          = ADDR_TYPE_RT
2995         },
2996         { }
2997 };
2998
2999 /* l4_abe -> mcbsp3 */
3000 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3001         .master         = &omap44xx_l4_abe_hwmod,
3002         .slave          = &omap44xx_mcbsp3_hwmod,
3003         .clk            = "ocp_abe_iclk",
3004         .addr           = omap44xx_mcbsp3_addrs,
3005         .user           = OCP_USER_MPU,
3006 };
3007
3008 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3009         {
3010                 .name           = "dma",
3011                 .pa_start       = 0x49026000,
3012                 .pa_end         = 0x490260ff,
3013                 .flags          = ADDR_TYPE_RT
3014         },
3015         { }
3016 };
3017
3018 /* l4_abe -> mcbsp3 (dma) */
3019 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3020         .master         = &omap44xx_l4_abe_hwmod,
3021         .slave          = &omap44xx_mcbsp3_hwmod,
3022         .clk            = "ocp_abe_iclk",
3023         .addr           = omap44xx_mcbsp3_dma_addrs,
3024         .user           = OCP_USER_SDMA,
3025 };
3026
3027 /* mcbsp3 slave ports */
3028 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3029         &omap44xx_l4_abe__mcbsp3,
3030         &omap44xx_l4_abe__mcbsp3_dma,
3031 };
3032
3033 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3034         .name           = "mcbsp3",
3035         .class          = &omap44xx_mcbsp_hwmod_class,
3036         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3037         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3038         .main_clk       = "mcbsp3_fck",
3039         .prcm = {
3040                 .omap4 = {
3041                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
3042                 },
3043         },
3044         .slaves         = omap44xx_mcbsp3_slaves,
3045         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3046         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3047 };
3048
3049 /* mcbsp4 */
3050 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3051 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3052         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3053         { .irq = -1 }
3054 };
3055
3056 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3057         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3058         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3059         { .dma_req = -1 }
3060 };
3061
3062 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3063         {
3064                 .pa_start       = 0x48096000,
3065                 .pa_end         = 0x480960ff,
3066                 .flags          = ADDR_TYPE_RT
3067         },
3068         { }
3069 };
3070
3071 /* l4_per -> mcbsp4 */
3072 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3073         .master         = &omap44xx_l4_per_hwmod,
3074         .slave          = &omap44xx_mcbsp4_hwmod,
3075         .clk            = "l4_div_ck",
3076         .addr           = omap44xx_mcbsp4_addrs,
3077         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3078 };
3079
3080 /* mcbsp4 slave ports */
3081 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3082         &omap44xx_l4_per__mcbsp4,
3083 };
3084
3085 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3086         .name           = "mcbsp4",
3087         .class          = &omap44xx_mcbsp_hwmod_class,
3088         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3089         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3090         .main_clk       = "mcbsp4_fck",
3091         .prcm = {
3092                 .omap4 = {
3093                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3094                 },
3095         },
3096         .slaves         = omap44xx_mcbsp4_slaves,
3097         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3098         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3099 };
3100
3101 /*
3102  * 'mcpdm' class
3103  * multi channel pdm controller (proprietary interface with phoenix power
3104  * ic)
3105  */
3106
3107 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3108         .rev_offs       = 0x0000,
3109         .sysc_offs      = 0x0010,
3110         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3111                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3112         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3113                            SIDLE_SMART_WKUP),
3114         .sysc_fields    = &omap_hwmod_sysc_type2,
3115 };
3116
3117 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3118         .name   = "mcpdm",
3119         .sysc   = &omap44xx_mcpdm_sysc,
3120 };
3121
3122 /* mcpdm */
3123 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3124 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3125         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3126         { .irq = -1 }
3127 };
3128
3129 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3130         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3131         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3132         { .dma_req = -1 }
3133 };
3134
3135 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3136         {
3137                 .pa_start       = 0x40132000,
3138                 .pa_end         = 0x4013207f,
3139                 .flags          = ADDR_TYPE_RT
3140         },
3141         { }
3142 };
3143
3144 /* l4_abe -> mcpdm */
3145 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3146         .master         = &omap44xx_l4_abe_hwmod,
3147         .slave          = &omap44xx_mcpdm_hwmod,
3148         .clk            = "ocp_abe_iclk",
3149         .addr           = omap44xx_mcpdm_addrs,
3150         .user           = OCP_USER_MPU,
3151 };
3152
3153 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3154         {
3155                 .pa_start       = 0x49032000,
3156                 .pa_end         = 0x4903207f,
3157                 .flags          = ADDR_TYPE_RT
3158         },
3159         { }
3160 };
3161
3162 /* l4_abe -> mcpdm (dma) */
3163 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3164         .master         = &omap44xx_l4_abe_hwmod,
3165         .slave          = &omap44xx_mcpdm_hwmod,
3166         .clk            = "ocp_abe_iclk",
3167         .addr           = omap44xx_mcpdm_dma_addrs,
3168         .user           = OCP_USER_SDMA,
3169 };
3170
3171 /* mcpdm slave ports */
3172 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3173         &omap44xx_l4_abe__mcpdm,
3174         &omap44xx_l4_abe__mcpdm_dma,
3175 };
3176
3177 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3178         .name           = "mcpdm",
3179         .class          = &omap44xx_mcpdm_hwmod_class,
3180         .mpu_irqs       = omap44xx_mcpdm_irqs,
3181         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3182         .main_clk       = "mcpdm_fck",
3183         .prcm = {
3184                 .omap4 = {
3185                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3186                 },
3187         },
3188         .slaves         = omap44xx_mcpdm_slaves,
3189         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3191 };
3192
3193 /*
3194  * 'mcspi' class
3195  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3196  * bus
3197  */
3198
3199 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3200         .rev_offs       = 0x0000,
3201         .sysc_offs      = 0x0010,
3202         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3203                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3204         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3205                            SIDLE_SMART_WKUP),
3206         .sysc_fields    = &omap_hwmod_sysc_type2,
3207 };
3208
3209 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3210         .name   = "mcspi",
3211         .sysc   = &omap44xx_mcspi_sysc,
3212         .rev    = OMAP4_MCSPI_REV,
3213 };
3214
3215 /* mcspi1 */
3216 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3217 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3218         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3219         { .irq = -1 }
3220 };
3221
3222 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3223         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3224         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3225         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3226         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3227         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3228         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3229         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3230         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3231         { .dma_req = -1 }
3232 };
3233
3234 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3235         {
3236                 .pa_start       = 0x48098000,
3237                 .pa_end         = 0x480981ff,
3238                 .flags          = ADDR_TYPE_RT
3239         },
3240         { }
3241 };
3242
3243 /* l4_per -> mcspi1 */
3244 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3245         .master         = &omap44xx_l4_per_hwmod,
3246         .slave          = &omap44xx_mcspi1_hwmod,
3247         .clk            = "l4_div_ck",
3248         .addr           = omap44xx_mcspi1_addrs,
3249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3250 };
3251
3252 /* mcspi1 slave ports */
3253 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3254         &omap44xx_l4_per__mcspi1,
3255 };
3256
3257 /* mcspi1 dev_attr */
3258 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3259         .num_chipselect = 4,
3260 };
3261
3262 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3263         .name           = "mcspi1",
3264         .class          = &omap44xx_mcspi_hwmod_class,
3265         .mpu_irqs       = omap44xx_mcspi1_irqs,
3266         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3267         .main_clk       = "mcspi1_fck",
3268         .prcm = {
3269                 .omap4 = {
3270                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3271                 },
3272         },
3273         .dev_attr       = &mcspi1_dev_attr,
3274         .slaves         = omap44xx_mcspi1_slaves,
3275         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3276         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3277 };
3278
3279 /* mcspi2 */
3280 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3281 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3282         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3283         { .irq = -1 }
3284 };
3285
3286 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3287         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3288         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3289         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3290         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3291         { .dma_req = -1 }
3292 };
3293
3294 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3295         {
3296                 .pa_start       = 0x4809a000,
3297                 .pa_end         = 0x4809a1ff,
3298                 .flags          = ADDR_TYPE_RT
3299         },
3300         { }
3301 };
3302
3303 /* l4_per -> mcspi2 */
3304 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3305         .master         = &omap44xx_l4_per_hwmod,
3306         .slave          = &omap44xx_mcspi2_hwmod,
3307         .clk            = "l4_div_ck",
3308         .addr           = omap44xx_mcspi2_addrs,
3309         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3310 };
3311
3312 /* mcspi2 slave ports */
3313 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3314         &omap44xx_l4_per__mcspi2,
3315 };
3316
3317 /* mcspi2 dev_attr */
3318 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3319         .num_chipselect = 2,
3320 };
3321
3322 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3323         .name           = "mcspi2",
3324         .class          = &omap44xx_mcspi_hwmod_class,
3325         .mpu_irqs       = omap44xx_mcspi2_irqs,
3326         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3327         .main_clk       = "mcspi2_fck",
3328         .prcm = {
3329                 .omap4 = {
3330                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3331                 },
3332         },
3333         .dev_attr       = &mcspi2_dev_attr,
3334         .slaves         = omap44xx_mcspi2_slaves,
3335         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3336         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3337 };
3338
3339 /* mcspi3 */
3340 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3341 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3342         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3343         { .irq = -1 }
3344 };
3345
3346 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3347         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3348         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3349         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3350         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3351         { .dma_req = -1 }
3352 };
3353
3354 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3355         {
3356                 .pa_start       = 0x480b8000,
3357                 .pa_end         = 0x480b81ff,
3358                 .flags          = ADDR_TYPE_RT
3359         },
3360         { }
3361 };
3362
3363 /* l4_per -> mcspi3 */
3364 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3365         .master         = &omap44xx_l4_per_hwmod,
3366         .slave          = &omap44xx_mcspi3_hwmod,
3367         .clk            = "l4_div_ck",
3368         .addr           = omap44xx_mcspi3_addrs,
3369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3370 };
3371
3372 /* mcspi3 slave ports */
3373 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3374         &omap44xx_l4_per__mcspi3,
3375 };
3376
3377 /* mcspi3 dev_attr */
3378 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3379         .num_chipselect = 2,
3380 };
3381
3382 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3383         .name           = "mcspi3",
3384         .class          = &omap44xx_mcspi_hwmod_class,
3385         .mpu_irqs       = omap44xx_mcspi3_irqs,
3386         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3387         .main_clk       = "mcspi3_fck",
3388         .prcm = {
3389                 .omap4 = {
3390                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3391                 },
3392         },
3393         .dev_attr       = &mcspi3_dev_attr,
3394         .slaves         = omap44xx_mcspi3_slaves,
3395         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3396         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3397 };
3398
3399 /* mcspi4 */
3400 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3401 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3402         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3403         { .irq = -1 }
3404 };
3405
3406 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3407         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3408         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3409         { .dma_req = -1 }
3410 };
3411
3412 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3413         {
3414                 .pa_start       = 0x480ba000,
3415                 .pa_end         = 0x480ba1ff,
3416                 .flags          = ADDR_TYPE_RT
3417         },
3418         { }
3419 };
3420
3421 /* l4_per -> mcspi4 */
3422 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3423         .master         = &omap44xx_l4_per_hwmod,
3424         .slave          = &omap44xx_mcspi4_hwmod,
3425         .clk            = "l4_div_ck",
3426         .addr           = omap44xx_mcspi4_addrs,
3427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3428 };
3429
3430 /* mcspi4 slave ports */
3431 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3432         &omap44xx_l4_per__mcspi4,
3433 };
3434
3435 /* mcspi4 dev_attr */
3436 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3437         .num_chipselect = 1,
3438 };
3439
3440 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3441         .name           = "mcspi4",
3442         .class          = &omap44xx_mcspi_hwmod_class,
3443         .mpu_irqs       = omap44xx_mcspi4_irqs,
3444         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3445         .main_clk       = "mcspi4_fck",
3446         .prcm = {
3447                 .omap4 = {
3448                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3449                 },
3450         },
3451         .dev_attr       = &mcspi4_dev_attr,
3452         .slaves         = omap44xx_mcspi4_slaves,
3453         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3454         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3455 };
3456
3457 /*
3458  * 'mmc' class
3459  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3460  */
3461
3462 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3463         .rev_offs       = 0x0000,
3464         .sysc_offs      = 0x0010,
3465         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3466                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3467                            SYSC_HAS_SOFTRESET),
3468         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3469                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3470                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3471         .sysc_fields    = &omap_hwmod_sysc_type2,
3472 };
3473
3474 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3475         .name   = "mmc",
3476         .sysc   = &omap44xx_mmc_sysc,
3477 };
3478
3479 /* mmc1 */
3480 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3481         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3482         { .irq = -1 }
3483 };
3484
3485 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3486         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3487         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3488         { .dma_req = -1 }
3489 };
3490
3491 /* mmc1 master ports */
3492 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3493         &omap44xx_mmc1__l3_main_1,
3494 };
3495
3496 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3497         {
3498                 .pa_start       = 0x4809c000,
3499                 .pa_end         = 0x4809c3ff,
3500                 .flags          = ADDR_TYPE_RT
3501         },
3502         { }
3503 };
3504
3505 /* l4_per -> mmc1 */
3506 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3507         .master         = &omap44xx_l4_per_hwmod,
3508         .slave          = &omap44xx_mmc1_hwmod,
3509         .clk            = "l4_div_ck",
3510         .addr           = omap44xx_mmc1_addrs,
3511         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3512 };
3513
3514 /* mmc1 slave ports */
3515 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3516         &omap44xx_l4_per__mmc1,
3517 };
3518
3519 /* mmc1 dev_attr */
3520 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3521         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3522 };
3523
3524 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3525         .name           = "mmc1",
3526         .class          = &omap44xx_mmc_hwmod_class,
3527         .mpu_irqs       = omap44xx_mmc1_irqs,
3528         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3529         .main_clk       = "mmc1_fck",
3530         .prcm = {
3531                 .omap4 = {
3532                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3533                 },
3534         },
3535         .dev_attr       = &mmc1_dev_attr,
3536         .slaves         = omap44xx_mmc1_slaves,
3537         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3538         .masters        = omap44xx_mmc1_masters,
3539         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3540         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3541 };
3542
3543 /* mmc2 */
3544 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3545         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3546         { .irq = -1 }
3547 };
3548
3549 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3550         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3551         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3552         { .dma_req = -1 }
3553 };
3554
3555 /* mmc2 master ports */
3556 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3557         &omap44xx_mmc2__l3_main_1,
3558 };
3559
3560 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3561         {
3562                 .pa_start       = 0x480b4000,
3563                 .pa_end         = 0x480b43ff,
3564                 .flags          = ADDR_TYPE_RT
3565         },
3566         { }
3567 };
3568
3569 /* l4_per -> mmc2 */
3570 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3571         .master         = &omap44xx_l4_per_hwmod,
3572         .slave          = &omap44xx_mmc2_hwmod,
3573         .clk            = "l4_div_ck",
3574         .addr           = omap44xx_mmc2_addrs,
3575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3576 };
3577
3578 /* mmc2 slave ports */
3579 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3580         &omap44xx_l4_per__mmc2,
3581 };
3582
3583 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3584         .name           = "mmc2",
3585         .class          = &omap44xx_mmc_hwmod_class,
3586         .mpu_irqs       = omap44xx_mmc2_irqs,
3587         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3588         .main_clk       = "mmc2_fck",
3589         .prcm = {
3590                 .omap4 = {
3591                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3592                 },
3593         },
3594         .slaves         = omap44xx_mmc2_slaves,
3595         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3596         .masters        = omap44xx_mmc2_masters,
3597         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3598         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3599 };
3600
3601 /* mmc3 */
3602 static struct omap_hwmod omap44xx_mmc3_hwmod;
3603 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3604         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3605         { .irq = -1 }
3606 };
3607
3608 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3609         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3610         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3611         { .dma_req = -1 }
3612 };
3613
3614 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3615         {
3616                 .pa_start       = 0x480ad000,
3617                 .pa_end         = 0x480ad3ff,
3618                 .flags          = ADDR_TYPE_RT
3619         },
3620         { }
3621 };
3622
3623 /* l4_per -> mmc3 */
3624 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3625         .master         = &omap44xx_l4_per_hwmod,
3626         .slave          = &omap44xx_mmc3_hwmod,
3627         .clk            = "l4_div_ck",
3628         .addr           = omap44xx_mmc3_addrs,
3629         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3630 };
3631
3632 /* mmc3 slave ports */
3633 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3634         &omap44xx_l4_per__mmc3,
3635 };
3636
3637 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3638         .name           = "mmc3",
3639         .class          = &omap44xx_mmc_hwmod_class,
3640         .mpu_irqs       = omap44xx_mmc3_irqs,
3641         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3642         .main_clk       = "mmc3_fck",
3643         .prcm = {
3644                 .omap4 = {
3645                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3646                 },
3647         },
3648         .slaves         = omap44xx_mmc3_slaves,
3649         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3650         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3651 };
3652
3653 /* mmc4 */
3654 static struct omap_hwmod omap44xx_mmc4_hwmod;
3655 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3656         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3657         { .irq = -1 }
3658 };
3659
3660 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3661         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3662         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3663         { .dma_req = -1 }
3664 };
3665
3666 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3667         {
3668                 .pa_start       = 0x480d1000,
3669                 .pa_end         = 0x480d13ff,
3670                 .flags          = ADDR_TYPE_RT
3671         },
3672         { }
3673 };
3674
3675 /* l4_per -> mmc4 */
3676 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3677         .master         = &omap44xx_l4_per_hwmod,
3678         .slave          = &omap44xx_mmc4_hwmod,
3679         .clk            = "l4_div_ck",
3680         .addr           = omap44xx_mmc4_addrs,
3681         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3682 };
3683
3684 /* mmc4 slave ports */
3685 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3686         &omap44xx_l4_per__mmc4,
3687 };
3688
3689 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3690         .name           = "mmc4",
3691         .class          = &omap44xx_mmc_hwmod_class,
3692         .mpu_irqs       = omap44xx_mmc4_irqs,
3693
3694         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3695         .main_clk       = "mmc4_fck",
3696         .prcm = {
3697                 .omap4 = {
3698                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3699                 },
3700         },
3701         .slaves         = omap44xx_mmc4_slaves,
3702         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3703         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3704 };
3705
3706 /* mmc5 */
3707 static struct omap_hwmod omap44xx_mmc5_hwmod;
3708 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3709         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3710         { .irq = -1 }
3711 };
3712
3713 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3714         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3715         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3716         { .dma_req = -1 }
3717 };
3718
3719 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3720         {
3721                 .pa_start       = 0x480d5000,
3722                 .pa_end         = 0x480d53ff,
3723                 .flags          = ADDR_TYPE_RT
3724         },
3725         { }
3726 };
3727
3728 /* l4_per -> mmc5 */
3729 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3730         .master         = &omap44xx_l4_per_hwmod,
3731         .slave          = &omap44xx_mmc5_hwmod,
3732         .clk            = "l4_div_ck",
3733         .addr           = omap44xx_mmc5_addrs,
3734         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3735 };
3736
3737 /* mmc5 slave ports */
3738 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3739         &omap44xx_l4_per__mmc5,
3740 };
3741
3742 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3743         .name           = "mmc5",
3744         .class          = &omap44xx_mmc_hwmod_class,
3745         .mpu_irqs       = omap44xx_mmc5_irqs,
3746         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3747         .main_clk       = "mmc5_fck",
3748         .prcm = {
3749                 .omap4 = {
3750                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3751                 },
3752         },
3753         .slaves         = omap44xx_mmc5_slaves,
3754         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3755         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3756 };
3757
3758 /*
3759  * 'mpu' class
3760  * mpu sub-system
3761  */
3762
3763 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3764         .name   = "mpu",
3765 };
3766
3767 /* mpu */
3768 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3769         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3770         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3771         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3772         { .irq = -1 }
3773 };
3774
3775 /* mpu master ports */
3776 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3777         &omap44xx_mpu__l3_main_1,
3778         &omap44xx_mpu__l4_abe,
3779         &omap44xx_mpu__dmm,
3780 };
3781
3782 static struct omap_hwmod omap44xx_mpu_hwmod = {
3783         .name           = "mpu",
3784         .class          = &omap44xx_mpu_hwmod_class,
3785         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3786         .mpu_irqs       = omap44xx_mpu_irqs,
3787         .main_clk       = "dpll_mpu_m2_ck",
3788         .prcm = {
3789                 .omap4 = {
3790                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3791                 },
3792         },
3793         .masters        = omap44xx_mpu_masters,
3794         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3795         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3796 };
3797
3798 /*
3799  * 'smartreflex' class
3800  * smartreflex module (monitor silicon performance and outputs a measure of
3801  * performance error)
3802  */
3803
3804 /* The IP is not compliant to type1 / type2 scheme */
3805 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3806         .sidle_shift    = 24,
3807         .enwkup_shift   = 26,
3808 };
3809
3810 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3811         .sysc_offs      = 0x0038,
3812         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3813         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3814                            SIDLE_SMART_WKUP),
3815         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3816 };
3817
3818 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3819         .name   = "smartreflex",
3820         .sysc   = &omap44xx_smartreflex_sysc,
3821         .rev    = 2,
3822 };
3823
3824 /* smartreflex_core */
3825 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3826 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3827         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3828         { .irq = -1 }
3829 };
3830
3831 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3832         {
3833                 .pa_start       = 0x4a0dd000,
3834                 .pa_end         = 0x4a0dd03f,
3835                 .flags          = ADDR_TYPE_RT
3836         },
3837         { }
3838 };
3839
3840 /* l4_cfg -> smartreflex_core */
3841 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3842         .master         = &omap44xx_l4_cfg_hwmod,
3843         .slave          = &omap44xx_smartreflex_core_hwmod,
3844         .clk            = "l4_div_ck",
3845         .addr           = omap44xx_smartreflex_core_addrs,
3846         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3847 };
3848
3849 /* smartreflex_core slave ports */
3850 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3851         &omap44xx_l4_cfg__smartreflex_core,
3852 };
3853
3854 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3855         .name           = "smartreflex_core",
3856         .class          = &omap44xx_smartreflex_hwmod_class,
3857         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3858
3859         .main_clk       = "smartreflex_core_fck",
3860         .vdd_name       = "core",
3861         .prcm = {
3862                 .omap4 = {
3863                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3864                 },
3865         },
3866         .slaves         = omap44xx_smartreflex_core_slaves,
3867         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3868         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3869 };
3870
3871 /* smartreflex_iva */
3872 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3873 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3874         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3875         { .irq = -1 }
3876 };
3877
3878 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3879         {
3880                 .pa_start       = 0x4a0db000,
3881                 .pa_end         = 0x4a0db03f,
3882                 .flags          = ADDR_TYPE_RT
3883         },
3884         { }
3885 };
3886
3887 /* l4_cfg -> smartreflex_iva */
3888 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3889         .master         = &omap44xx_l4_cfg_hwmod,
3890         .slave          = &omap44xx_smartreflex_iva_hwmod,
3891         .clk            = "l4_div_ck",
3892         .addr           = omap44xx_smartreflex_iva_addrs,
3893         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3894 };
3895
3896 /* smartreflex_iva slave ports */
3897 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3898         &omap44xx_l4_cfg__smartreflex_iva,
3899 };
3900
3901 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3902         .name           = "smartreflex_iva",
3903         .class          = &omap44xx_smartreflex_hwmod_class,
3904         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3905         .main_clk       = "smartreflex_iva_fck",
3906         .vdd_name       = "iva",
3907         .prcm = {
3908                 .omap4 = {
3909                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3910                 },
3911         },
3912         .slaves         = omap44xx_smartreflex_iva_slaves,
3913         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3914         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3915 };
3916
3917 /* smartreflex_mpu */
3918 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3919 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3920         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3921         { .irq = -1 }
3922 };
3923
3924 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3925         {
3926                 .pa_start       = 0x4a0d9000,
3927                 .pa_end         = 0x4a0d903f,
3928                 .flags          = ADDR_TYPE_RT
3929         },
3930         { }
3931 };
3932
3933 /* l4_cfg -> smartreflex_mpu */
3934 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3935         .master         = &omap44xx_l4_cfg_hwmod,
3936         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3937         .clk            = "l4_div_ck",
3938         .addr           = omap44xx_smartreflex_mpu_addrs,
3939         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3940 };
3941
3942 /* smartreflex_mpu slave ports */
3943 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3944         &omap44xx_l4_cfg__smartreflex_mpu,
3945 };
3946
3947 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3948         .name           = "smartreflex_mpu",
3949         .class          = &omap44xx_smartreflex_hwmod_class,
3950         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3951         .main_clk       = "smartreflex_mpu_fck",
3952         .vdd_name       = "mpu",
3953         .prcm = {
3954                 .omap4 = {
3955                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3956                 },
3957         },
3958         .slaves         = omap44xx_smartreflex_mpu_slaves,
3959         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3960         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3961 };
3962
3963 /*
3964  * 'spinlock' class
3965  * spinlock provides hardware assistance for synchronizing the processes
3966  * running on multiple processors
3967  */
3968
3969 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3970         .rev_offs       = 0x0000,
3971         .sysc_offs      = 0x0010,
3972         .syss_offs      = 0x0014,
3973         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3974                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3975                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3976         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3977                            SIDLE_SMART_WKUP),
3978         .sysc_fields    = &omap_hwmod_sysc_type1,
3979 };
3980
3981 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3982         .name   = "spinlock",
3983         .sysc   = &omap44xx_spinlock_sysc,
3984 };
3985
3986 /* spinlock */
3987 static struct omap_hwmod omap44xx_spinlock_hwmod;
3988 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3989         {
3990                 .pa_start       = 0x4a0f6000,
3991                 .pa_end         = 0x4a0f6fff,
3992                 .flags          = ADDR_TYPE_RT
3993         },
3994         { }
3995 };
3996
3997 /* l4_cfg -> spinlock */
3998 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3999         .master         = &omap44xx_l4_cfg_hwmod,
4000         .slave          = &omap44xx_spinlock_hwmod,
4001         .clk            = "l4_div_ck",
4002         .addr           = omap44xx_spinlock_addrs,
4003         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4004 };
4005
4006 /* spinlock slave ports */
4007 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4008         &omap44xx_l4_cfg__spinlock,
4009 };
4010
4011 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4012         .name           = "spinlock",
4013         .class          = &omap44xx_spinlock_hwmod_class,
4014         .prcm = {
4015                 .omap4 = {
4016                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
4017                 },
4018         },
4019         .slaves         = omap44xx_spinlock_slaves,
4020         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4021         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4022 };
4023
4024 /*
4025  * 'timer' class
4026  * general purpose timer module with accurate 1ms tick
4027  * This class contains several variants: ['timer_1ms', 'timer']
4028  */
4029
4030 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4031         .rev_offs       = 0x0000,
4032         .sysc_offs      = 0x0010,
4033         .syss_offs      = 0x0014,
4034         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4035                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4036                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4037                            SYSS_HAS_RESET_STATUS),
4038         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4039         .sysc_fields    = &omap_hwmod_sysc_type1,
4040 };
4041
4042 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4043         .name   = "timer",
4044         .sysc   = &omap44xx_timer_1ms_sysc,
4045 };
4046
4047 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4048         .rev_offs       = 0x0000,
4049         .sysc_offs      = 0x0010,
4050         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4051                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4052         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4053                            SIDLE_SMART_WKUP),
4054         .sysc_fields    = &omap_hwmod_sysc_type2,
4055 };
4056
4057 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4058         .name   = "timer",
4059         .sysc   = &omap44xx_timer_sysc,
4060 };
4061
4062 /* timer1 */
4063 static struct omap_hwmod omap44xx_timer1_hwmod;
4064 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4065         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4066         { .irq = -1 }
4067 };
4068
4069 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4070         {
4071                 .pa_start       = 0x4a318000,
4072                 .pa_end         = 0x4a31807f,
4073                 .flags          = ADDR_TYPE_RT
4074         },
4075         { }
4076 };
4077
4078 /* l4_wkup -> timer1 */
4079 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4080         .master         = &omap44xx_l4_wkup_hwmod,
4081         .slave          = &omap44xx_timer1_hwmod,
4082         .clk            = "l4_wkup_clk_mux_ck",
4083         .addr           = omap44xx_timer1_addrs,
4084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4085 };
4086
4087 /* timer1 slave ports */
4088 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4089         &omap44xx_l4_wkup__timer1,
4090 };
4091
4092 static struct omap_hwmod omap44xx_timer1_hwmod = {
4093         .name           = "timer1",
4094         .class          = &omap44xx_timer_1ms_hwmod_class,
4095         .mpu_irqs       = omap44xx_timer1_irqs,
4096         .main_clk       = "timer1_fck",
4097         .prcm = {
4098                 .omap4 = {
4099                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4100                 },
4101         },
4102         .slaves         = omap44xx_timer1_slaves,
4103         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4104         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4105 };
4106
4107 /* timer2 */
4108 static struct omap_hwmod omap44xx_timer2_hwmod;
4109 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4110         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4111         { .irq = -1 }
4112 };
4113
4114 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4115         {
4116                 .pa_start       = 0x48032000,
4117                 .pa_end         = 0x4803207f,
4118                 .flags          = ADDR_TYPE_RT
4119         },
4120         { }
4121 };
4122
4123 /* l4_per -> timer2 */
4124 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4125         .master         = &omap44xx_l4_per_hwmod,
4126         .slave          = &omap44xx_timer2_hwmod,
4127         .clk            = "l4_div_ck",
4128         .addr           = omap44xx_timer2_addrs,
4129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 /* timer2 slave ports */
4133 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4134         &omap44xx_l4_per__timer2,
4135 };
4136
4137 static struct omap_hwmod omap44xx_timer2_hwmod = {
4138         .name           = "timer2",
4139         .class          = &omap44xx_timer_1ms_hwmod_class,
4140         .mpu_irqs       = omap44xx_timer2_irqs,
4141         .main_clk       = "timer2_fck",
4142         .prcm = {
4143                 .omap4 = {
4144                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4145                 },
4146         },
4147         .slaves         = omap44xx_timer2_slaves,
4148         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4149         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4150 };
4151
4152 /* timer3 */
4153 static struct omap_hwmod omap44xx_timer3_hwmod;
4154 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4155         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4156         { .irq = -1 }
4157 };
4158
4159 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4160         {
4161                 .pa_start       = 0x48034000,
4162                 .pa_end         = 0x4803407f,
4163                 .flags          = ADDR_TYPE_RT
4164         },
4165         { }
4166 };
4167
4168 /* l4_per -> timer3 */
4169 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4170         .master         = &omap44xx_l4_per_hwmod,
4171         .slave          = &omap44xx_timer3_hwmod,
4172         .clk            = "l4_div_ck",
4173         .addr           = omap44xx_timer3_addrs,
4174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4175 };
4176
4177 /* timer3 slave ports */
4178 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4179         &omap44xx_l4_per__timer3,
4180 };
4181
4182 static struct omap_hwmod omap44xx_timer3_hwmod = {
4183         .name           = "timer3",
4184         .class          = &omap44xx_timer_hwmod_class,
4185         .mpu_irqs       = omap44xx_timer3_irqs,
4186         .main_clk       = "timer3_fck",
4187         .prcm = {
4188                 .omap4 = {
4189                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4190                 },
4191         },
4192         .slaves         = omap44xx_timer3_slaves,
4193         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4194         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4195 };
4196
4197 /* timer4 */
4198 static struct omap_hwmod omap44xx_timer4_hwmod;
4199 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4200         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4201         { .irq = -1 }
4202 };
4203
4204 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4205         {
4206                 .pa_start       = 0x48036000,
4207                 .pa_end         = 0x4803607f,
4208                 .flags          = ADDR_TYPE_RT
4209         },
4210         { }
4211 };
4212
4213 /* l4_per -> timer4 */
4214 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4215         .master         = &omap44xx_l4_per_hwmod,
4216         .slave          = &omap44xx_timer4_hwmod,
4217         .clk            = "l4_div_ck",
4218         .addr           = omap44xx_timer4_addrs,
4219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4220 };
4221
4222 /* timer4 slave ports */
4223 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4224         &omap44xx_l4_per__timer4,
4225 };
4226
4227 static struct omap_hwmod omap44xx_timer4_hwmod = {
4228         .name           = "timer4",
4229         .class          = &omap44xx_timer_hwmod_class,
4230         .mpu_irqs       = omap44xx_timer4_irqs,
4231         .main_clk       = "timer4_fck",
4232         .prcm = {
4233                 .omap4 = {
4234                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4235                 },
4236         },
4237         .slaves         = omap44xx_timer4_slaves,
4238         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4239         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4240 };
4241
4242 /* timer5 */
4243 static struct omap_hwmod omap44xx_timer5_hwmod;
4244 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4245         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4246         { .irq = -1 }
4247 };
4248
4249 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4250         {
4251                 .pa_start       = 0x40138000,
4252                 .pa_end         = 0x4013807f,
4253                 .flags          = ADDR_TYPE_RT
4254         },
4255         { }
4256 };
4257
4258 /* l4_abe -> timer5 */
4259 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4260         .master         = &omap44xx_l4_abe_hwmod,
4261         .slave          = &omap44xx_timer5_hwmod,
4262         .clk            = "ocp_abe_iclk",
4263         .addr           = omap44xx_timer5_addrs,
4264         .user           = OCP_USER_MPU,
4265 };
4266
4267 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4268         {
4269                 .pa_start       = 0x49038000,
4270                 .pa_end         = 0x4903807f,
4271                 .flags          = ADDR_TYPE_RT
4272         },
4273         { }
4274 };
4275
4276 /* l4_abe -> timer5 (dma) */
4277 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4278         .master         = &omap44xx_l4_abe_hwmod,
4279         .slave          = &omap44xx_timer5_hwmod,
4280         .clk            = "ocp_abe_iclk",
4281         .addr           = omap44xx_timer5_dma_addrs,
4282         .user           = OCP_USER_SDMA,
4283 };
4284
4285 /* timer5 slave ports */
4286 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4287         &omap44xx_l4_abe__timer5,
4288         &omap44xx_l4_abe__timer5_dma,
4289 };
4290
4291 static struct omap_hwmod omap44xx_timer5_hwmod = {
4292         .name           = "timer5",
4293         .class          = &omap44xx_timer_hwmod_class,
4294         .mpu_irqs       = omap44xx_timer5_irqs,
4295         .main_clk       = "timer5_fck",
4296         .prcm = {
4297                 .omap4 = {
4298                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4299                 },
4300         },
4301         .slaves         = omap44xx_timer5_slaves,
4302         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4303         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4304 };
4305
4306 /* timer6 */
4307 static struct omap_hwmod omap44xx_timer6_hwmod;
4308 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4309         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4310         { .irq = -1 }
4311 };
4312
4313 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4314         {
4315                 .pa_start       = 0x4013a000,
4316                 .pa_end         = 0x4013a07f,
4317                 .flags          = ADDR_TYPE_RT
4318         },
4319         { }
4320 };
4321
4322 /* l4_abe -> timer6 */
4323 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4324         .master         = &omap44xx_l4_abe_hwmod,
4325         .slave          = &omap44xx_timer6_hwmod,
4326         .clk            = "ocp_abe_iclk",
4327         .addr           = omap44xx_timer6_addrs,
4328         .user           = OCP_USER_MPU,
4329 };
4330
4331 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4332         {
4333                 .pa_start       = 0x4903a000,
4334                 .pa_end         = 0x4903a07f,
4335                 .flags          = ADDR_TYPE_RT
4336         },
4337         { }
4338 };
4339
4340 /* l4_abe -> timer6 (dma) */
4341 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4342         .master         = &omap44xx_l4_abe_hwmod,
4343         .slave          = &omap44xx_timer6_hwmod,
4344         .clk            = "ocp_abe_iclk",
4345         .addr           = omap44xx_timer6_dma_addrs,
4346         .user           = OCP_USER_SDMA,
4347 };
4348
4349 /* timer6 slave ports */
4350 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4351         &omap44xx_l4_abe__timer6,
4352         &omap44xx_l4_abe__timer6_dma,
4353 };
4354
4355 static struct omap_hwmod omap44xx_timer6_hwmod = {
4356         .name           = "timer6",
4357         .class          = &omap44xx_timer_hwmod_class,
4358         .mpu_irqs       = omap44xx_timer6_irqs,
4359
4360         .main_clk       = "timer6_fck",
4361         .prcm = {
4362                 .omap4 = {
4363                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4364                 },
4365         },
4366         .slaves         = omap44xx_timer6_slaves,
4367         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4368         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4369 };
4370
4371 /* timer7 */
4372 static struct omap_hwmod omap44xx_timer7_hwmod;
4373 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4374         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4375         { .irq = -1 }
4376 };
4377
4378 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4379         {
4380                 .pa_start       = 0x4013c000,
4381                 .pa_end         = 0x4013c07f,
4382                 .flags          = ADDR_TYPE_RT
4383         },
4384         { }
4385 };
4386
4387 /* l4_abe -> timer7 */
4388 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4389         .master         = &omap44xx_l4_abe_hwmod,
4390         .slave          = &omap44xx_timer7_hwmod,
4391         .clk            = "ocp_abe_iclk",
4392         .addr           = omap44xx_timer7_addrs,
4393         .user           = OCP_USER_MPU,
4394 };
4395
4396 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4397         {
4398                 .pa_start       = 0x4903c000,
4399                 .pa_end         = 0x4903c07f,
4400                 .flags          = ADDR_TYPE_RT
4401         },
4402         { }
4403 };
4404
4405 /* l4_abe -> timer7 (dma) */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4407         .master         = &omap44xx_l4_abe_hwmod,
4408         .slave          = &omap44xx_timer7_hwmod,
4409         .clk            = "ocp_abe_iclk",
4410         .addr           = omap44xx_timer7_dma_addrs,
4411         .user           = OCP_USER_SDMA,
4412 };
4413
4414 /* timer7 slave ports */
4415 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4416         &omap44xx_l4_abe__timer7,
4417         &omap44xx_l4_abe__timer7_dma,
4418 };
4419
4420 static struct omap_hwmod omap44xx_timer7_hwmod = {
4421         .name           = "timer7",
4422         .class          = &omap44xx_timer_hwmod_class,
4423         .mpu_irqs       = omap44xx_timer7_irqs,
4424         .main_clk       = "timer7_fck",
4425         .prcm = {
4426                 .omap4 = {
4427                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4428                 },
4429         },
4430         .slaves         = omap44xx_timer7_slaves,
4431         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4432         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4433 };
4434
4435 /* timer8 */
4436 static struct omap_hwmod omap44xx_timer8_hwmod;
4437 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4438         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4439         { .irq = -1 }
4440 };
4441
4442 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4443         {
4444                 .pa_start       = 0x4013e000,
4445                 .pa_end         = 0x4013e07f,
4446                 .flags          = ADDR_TYPE_RT
4447         },
4448         { }
4449 };
4450
4451 /* l4_abe -> timer8 */
4452 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4453         .master         = &omap44xx_l4_abe_hwmod,
4454         .slave          = &omap44xx_timer8_hwmod,
4455         .clk            = "ocp_abe_iclk",
4456         .addr           = omap44xx_timer8_addrs,
4457         .user           = OCP_USER_MPU,
4458 };
4459
4460 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4461         {
4462                 .pa_start       = 0x4903e000,
4463                 .pa_end         = 0x4903e07f,
4464                 .flags          = ADDR_TYPE_RT
4465         },
4466         { }
4467 };
4468
4469 /* l4_abe -> timer8 (dma) */
4470 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4471         .master         = &omap44xx_l4_abe_hwmod,
4472         .slave          = &omap44xx_timer8_hwmod,
4473         .clk            = "ocp_abe_iclk",
4474         .addr           = omap44xx_timer8_dma_addrs,
4475         .user           = OCP_USER_SDMA,
4476 };
4477
4478 /* timer8 slave ports */
4479 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4480         &omap44xx_l4_abe__timer8,
4481         &omap44xx_l4_abe__timer8_dma,
4482 };
4483
4484 static struct omap_hwmod omap44xx_timer8_hwmod = {
4485         .name           = "timer8",
4486         .class          = &omap44xx_timer_hwmod_class,
4487         .mpu_irqs       = omap44xx_timer8_irqs,
4488         .main_clk       = "timer8_fck",
4489         .prcm = {
4490                 .omap4 = {
4491                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4492                 },
4493         },
4494         .slaves         = omap44xx_timer8_slaves,
4495         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4496         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4497 };
4498
4499 /* timer9 */
4500 static struct omap_hwmod omap44xx_timer9_hwmod;
4501 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4502         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4503         { .irq = -1 }
4504 };
4505
4506 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4507         {
4508                 .pa_start       = 0x4803e000,
4509                 .pa_end         = 0x4803e07f,
4510                 .flags          = ADDR_TYPE_RT
4511         },
4512         { }
4513 };
4514
4515 /* l4_per -> timer9 */
4516 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4517         .master         = &omap44xx_l4_per_hwmod,
4518         .slave          = &omap44xx_timer9_hwmod,
4519         .clk            = "l4_div_ck",
4520         .addr           = omap44xx_timer9_addrs,
4521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4522 };
4523
4524 /* timer9 slave ports */
4525 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4526         &omap44xx_l4_per__timer9,
4527 };
4528
4529 static struct omap_hwmod omap44xx_timer9_hwmod = {
4530         .name           = "timer9",
4531         .class          = &omap44xx_timer_hwmod_class,
4532         .mpu_irqs       = omap44xx_timer9_irqs,
4533         .main_clk       = "timer9_fck",
4534         .prcm = {
4535                 .omap4 = {
4536                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4537                 },
4538         },
4539         .slaves         = omap44xx_timer9_slaves,
4540         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4541         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4542 };
4543
4544 /* timer10 */
4545 static struct omap_hwmod omap44xx_timer10_hwmod;
4546 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4547         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4548         { .irq = -1 }
4549 };
4550
4551 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4552         {
4553                 .pa_start       = 0x48086000,
4554                 .pa_end         = 0x4808607f,
4555                 .flags          = ADDR_TYPE_RT
4556         },
4557         { }
4558 };
4559
4560 /* l4_per -> timer10 */
4561 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4562         .master         = &omap44xx_l4_per_hwmod,
4563         .slave          = &omap44xx_timer10_hwmod,
4564         .clk            = "l4_div_ck",
4565         .addr           = omap44xx_timer10_addrs,
4566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4567 };
4568
4569 /* timer10 slave ports */
4570 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4571         &omap44xx_l4_per__timer10,
4572 };
4573
4574 static struct omap_hwmod omap44xx_timer10_hwmod = {
4575         .name           = "timer10",
4576         .class          = &omap44xx_timer_1ms_hwmod_class,
4577         .mpu_irqs       = omap44xx_timer10_irqs,
4578         .main_clk       = "timer10_fck",
4579         .prcm = {
4580                 .omap4 = {
4581                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4582                 },
4583         },
4584         .slaves         = omap44xx_timer10_slaves,
4585         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4586         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4587 };
4588
4589 /* timer11 */
4590 static struct omap_hwmod omap44xx_timer11_hwmod;
4591 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4592         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4593         { .irq = -1 }
4594 };
4595
4596 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4597         {
4598                 .pa_start       = 0x48088000,
4599                 .pa_end         = 0x4808807f,
4600                 .flags          = ADDR_TYPE_RT
4601         },
4602         { }
4603 };
4604
4605 /* l4_per -> timer11 */
4606 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4607         .master         = &omap44xx_l4_per_hwmod,
4608         .slave          = &omap44xx_timer11_hwmod,
4609         .clk            = "l4_div_ck",
4610         .addr           = omap44xx_timer11_addrs,
4611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4612 };
4613
4614 /* timer11 slave ports */
4615 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4616         &omap44xx_l4_per__timer11,
4617 };
4618
4619 static struct omap_hwmod omap44xx_timer11_hwmod = {
4620         .name           = "timer11",
4621         .class          = &omap44xx_timer_hwmod_class,
4622         .mpu_irqs       = omap44xx_timer11_irqs,
4623         .main_clk       = "timer11_fck",
4624         .prcm = {
4625                 .omap4 = {
4626                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4627                 },
4628         },
4629         .slaves         = omap44xx_timer11_slaves,
4630         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4631         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4632 };
4633
4634 /*
4635  * 'uart' class
4636  * universal asynchronous receiver/transmitter (uart)
4637  */
4638
4639 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4640         .rev_offs       = 0x0050,
4641         .sysc_offs      = 0x0054,
4642         .syss_offs      = 0x0058,
4643         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4644                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4645                            SYSS_HAS_RESET_STATUS),
4646         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4647                            SIDLE_SMART_WKUP),
4648         .sysc_fields    = &omap_hwmod_sysc_type1,
4649 };
4650
4651 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4652         .name   = "uart",
4653         .sysc   = &omap44xx_uart_sysc,
4654 };
4655
4656 /* uart1 */
4657 static struct omap_hwmod omap44xx_uart1_hwmod;
4658 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4659         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4660         { .irq = -1 }
4661 };
4662
4663 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4664         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4665         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4666         { .dma_req = -1 }
4667 };
4668
4669 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4670         {
4671                 .pa_start       = 0x4806a000,
4672                 .pa_end         = 0x4806a0ff,
4673                 .flags          = ADDR_TYPE_RT
4674         },
4675         { }
4676 };
4677
4678 /* l4_per -> uart1 */
4679 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4680         .master         = &omap44xx_l4_per_hwmod,
4681         .slave          = &omap44xx_uart1_hwmod,
4682         .clk            = "l4_div_ck",
4683         .addr           = omap44xx_uart1_addrs,
4684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4685 };
4686
4687 /* uart1 slave ports */
4688 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4689         &omap44xx_l4_per__uart1,
4690 };
4691
4692 static struct omap_hwmod omap44xx_uart1_hwmod = {
4693         .name           = "uart1",
4694         .class          = &omap44xx_uart_hwmod_class,
4695         .mpu_irqs       = omap44xx_uart1_irqs,
4696         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4697         .main_clk       = "uart1_fck",
4698         .prcm = {
4699                 .omap4 = {
4700                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4701                 },
4702         },
4703         .slaves         = omap44xx_uart1_slaves,
4704         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4705         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4706 };
4707
4708 /* uart2 */
4709 static struct omap_hwmod omap44xx_uart2_hwmod;
4710 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4711         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4712         { .irq = -1 }
4713 };
4714
4715 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4716         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4717         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4718         { .dma_req = -1 }
4719 };
4720
4721 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4722         {
4723                 .pa_start       = 0x4806c000,
4724                 .pa_end         = 0x4806c0ff,
4725                 .flags          = ADDR_TYPE_RT
4726         },
4727         { }
4728 };
4729
4730 /* l4_per -> uart2 */
4731 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4732         .master         = &omap44xx_l4_per_hwmod,
4733         .slave          = &omap44xx_uart2_hwmod,
4734         .clk            = "l4_div_ck",
4735         .addr           = omap44xx_uart2_addrs,
4736         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4737 };
4738
4739 /* uart2 slave ports */
4740 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4741         &omap44xx_l4_per__uart2,
4742 };
4743
4744 static struct omap_hwmod omap44xx_uart2_hwmod = {
4745         .name           = "uart2",
4746         .class          = &omap44xx_uart_hwmod_class,
4747         .mpu_irqs       = omap44xx_uart2_irqs,
4748         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4749         .main_clk       = "uart2_fck",
4750         .prcm = {
4751                 .omap4 = {
4752                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4753                 },
4754         },
4755         .slaves         = omap44xx_uart2_slaves,
4756         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4757         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4758 };
4759
4760 /* uart3 */
4761 static struct omap_hwmod omap44xx_uart3_hwmod;
4762 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4763         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4764         { .irq = -1 }
4765 };
4766
4767 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4768         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4769         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4770         { .dma_req = -1 }
4771 };
4772
4773 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4774         {
4775                 .pa_start       = 0x48020000,
4776                 .pa_end         = 0x480200ff,
4777                 .flags          = ADDR_TYPE_RT
4778         },
4779         { }
4780 };
4781
4782 /* l4_per -> uart3 */
4783 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4784         .master         = &omap44xx_l4_per_hwmod,
4785         .slave          = &omap44xx_uart3_hwmod,
4786         .clk            = "l4_div_ck",
4787         .addr           = omap44xx_uart3_addrs,
4788         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4789 };
4790
4791 /* uart3 slave ports */
4792 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4793         &omap44xx_l4_per__uart3,
4794 };
4795
4796 static struct omap_hwmod omap44xx_uart3_hwmod = {
4797         .name           = "uart3",
4798         .class          = &omap44xx_uart_hwmod_class,
4799         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4800         .mpu_irqs       = omap44xx_uart3_irqs,
4801         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4802         .main_clk       = "uart3_fck",
4803         .prcm = {
4804                 .omap4 = {
4805                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4806                 },
4807         },
4808         .slaves         = omap44xx_uart3_slaves,
4809         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4810         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4811 };
4812
4813 /* uart4 */
4814 static struct omap_hwmod omap44xx_uart4_hwmod;
4815 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4816         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4817         { .irq = -1 }
4818 };
4819
4820 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4821         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4822         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4823         { .dma_req = -1 }
4824 };
4825
4826 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4827         {
4828                 .pa_start       = 0x4806e000,
4829                 .pa_end         = 0x4806e0ff,
4830                 .flags          = ADDR_TYPE_RT
4831         },
4832         { }
4833 };
4834
4835 /* l4_per -> uart4 */
4836 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4837         .master         = &omap44xx_l4_per_hwmod,
4838         .slave          = &omap44xx_uart4_hwmod,
4839         .clk            = "l4_div_ck",
4840         .addr           = omap44xx_uart4_addrs,
4841         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4842 };
4843
4844 /* uart4 slave ports */
4845 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4846         &omap44xx_l4_per__uart4,
4847 };
4848
4849 static struct omap_hwmod omap44xx_uart4_hwmod = {
4850         .name           = "uart4",
4851         .class          = &omap44xx_uart_hwmod_class,
4852         .mpu_irqs       = omap44xx_uart4_irqs,
4853         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4854         .main_clk       = "uart4_fck",
4855         .prcm = {
4856                 .omap4 = {
4857                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4858                 },
4859         },
4860         .slaves         = omap44xx_uart4_slaves,
4861         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4862         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4863 };
4864
4865 /*
4866  * 'usb_otg_hs' class
4867  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4868  */
4869
4870 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4871         .rev_offs       = 0x0400,
4872         .sysc_offs      = 0x0404,
4873         .syss_offs      = 0x0408,
4874         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4875                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4876                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4877         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4878                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4879                            MSTANDBY_SMART),
4880         .sysc_fields    = &omap_hwmod_sysc_type1,
4881 };
4882
4883 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4884         .name   = "usb_otg_hs",
4885         .sysc   = &omap44xx_usb_otg_hs_sysc,
4886 };
4887
4888 /* usb_otg_hs */
4889 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4890         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4891         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4892         { .irq = -1 }
4893 };
4894
4895 /* usb_otg_hs master ports */
4896 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4897         &omap44xx_usb_otg_hs__l3_main_2,
4898 };
4899
4900 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4901         {
4902                 .pa_start       = 0x4a0ab000,
4903                 .pa_end         = 0x4a0ab003,
4904                 .flags          = ADDR_TYPE_RT
4905         },
4906         { }
4907 };
4908
4909 /* l4_cfg -> usb_otg_hs */
4910 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4911         .master         = &omap44xx_l4_cfg_hwmod,
4912         .slave          = &omap44xx_usb_otg_hs_hwmod,
4913         .clk            = "l4_div_ck",
4914         .addr           = omap44xx_usb_otg_hs_addrs,
4915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4916 };
4917
4918 /* usb_otg_hs slave ports */
4919 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4920         &omap44xx_l4_cfg__usb_otg_hs,
4921 };
4922
4923 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4924         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4925 };
4926
4927 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4928         .name           = "usb_otg_hs",
4929         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4930         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4931         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4932         .main_clk       = "usb_otg_hs_ick",
4933         .prcm = {
4934                 .omap4 = {
4935                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4936                 },
4937         },
4938         .opt_clks       = usb_otg_hs_opt_clks,
4939         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
4940         .slaves         = omap44xx_usb_otg_hs_slaves,
4941         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4942         .masters        = omap44xx_usb_otg_hs_masters,
4943         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4944         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4945 };
4946
4947 /*
4948  * 'wd_timer' class
4949  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4950  * overflow condition
4951  */
4952
4953 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4954         .rev_offs       = 0x0000,
4955         .sysc_offs      = 0x0010,
4956         .syss_offs      = 0x0014,
4957         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4958                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4959         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4960                            SIDLE_SMART_WKUP),
4961         .sysc_fields    = &omap_hwmod_sysc_type1,
4962 };
4963
4964 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4965         .name           = "wd_timer",
4966         .sysc           = &omap44xx_wd_timer_sysc,
4967         .pre_shutdown   = &omap2_wd_timer_disable,
4968 };
4969
4970 /* wd_timer2 */
4971 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4972 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4973         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4974         { .irq = -1 }
4975 };
4976
4977 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4978         {
4979                 .pa_start       = 0x4a314000,
4980                 .pa_end         = 0x4a31407f,
4981                 .flags          = ADDR_TYPE_RT
4982         },
4983         { }
4984 };
4985
4986 /* l4_wkup -> wd_timer2 */
4987 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4988         .master         = &omap44xx_l4_wkup_hwmod,
4989         .slave          = &omap44xx_wd_timer2_hwmod,
4990         .clk            = "l4_wkup_clk_mux_ck",
4991         .addr           = omap44xx_wd_timer2_addrs,
4992         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4993 };
4994
4995 /* wd_timer2 slave ports */
4996 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4997         &omap44xx_l4_wkup__wd_timer2,
4998 };
4999
5000 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5001         .name           = "wd_timer2",
5002         .class          = &omap44xx_wd_timer_hwmod_class,
5003         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5004         .main_clk       = "wd_timer2_fck",
5005         .prcm = {
5006                 .omap4 = {
5007                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
5008                 },
5009         },
5010         .slaves         = omap44xx_wd_timer2_slaves,
5011         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5012         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5013 };
5014
5015 /* wd_timer3 */
5016 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5017 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5018         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5019         { .irq = -1 }
5020 };
5021
5022 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5023         {
5024                 .pa_start       = 0x40130000,
5025                 .pa_end         = 0x4013007f,
5026                 .flags          = ADDR_TYPE_RT
5027         },
5028         { }
5029 };
5030
5031 /* l4_abe -> wd_timer3 */
5032 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5033         .master         = &omap44xx_l4_abe_hwmod,
5034         .slave          = &omap44xx_wd_timer3_hwmod,
5035         .clk            = "ocp_abe_iclk",
5036         .addr           = omap44xx_wd_timer3_addrs,
5037         .user           = OCP_USER_MPU,
5038 };
5039
5040 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5041         {
5042                 .pa_start       = 0x49030000,
5043                 .pa_end         = 0x4903007f,
5044                 .flags          = ADDR_TYPE_RT
5045         },
5046         { }
5047 };
5048
5049 /* l4_abe -> wd_timer3 (dma) */
5050 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5051         .master         = &omap44xx_l4_abe_hwmod,
5052         .slave          = &omap44xx_wd_timer3_hwmod,
5053         .clk            = "ocp_abe_iclk",
5054         .addr           = omap44xx_wd_timer3_dma_addrs,
5055         .user           = OCP_USER_SDMA,
5056 };
5057
5058 /* wd_timer3 slave ports */
5059 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5060         &omap44xx_l4_abe__wd_timer3,
5061         &omap44xx_l4_abe__wd_timer3_dma,
5062 };
5063
5064 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5065         .name           = "wd_timer3",
5066         .class          = &omap44xx_wd_timer_hwmod_class,
5067         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5068         .main_clk       = "wd_timer3_fck",
5069         .prcm = {
5070                 .omap4 = {
5071                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5072                 },
5073         },
5074         .slaves         = omap44xx_wd_timer3_slaves,
5075         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5076         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5077 };
5078
5079 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5080
5081         /* dmm class */
5082         &omap44xx_dmm_hwmod,
5083
5084         /* emif_fw class */
5085         &omap44xx_emif_fw_hwmod,
5086
5087         /* l3 class */
5088         &omap44xx_l3_instr_hwmod,
5089         &omap44xx_l3_main_1_hwmod,
5090         &omap44xx_l3_main_2_hwmod,
5091         &omap44xx_l3_main_3_hwmod,
5092
5093         /* l4 class */
5094         &omap44xx_l4_abe_hwmod,
5095         &omap44xx_l4_cfg_hwmod,
5096         &omap44xx_l4_per_hwmod,
5097         &omap44xx_l4_wkup_hwmod,
5098
5099         /* mpu_bus class */
5100         &omap44xx_mpu_private_hwmod,
5101
5102         /* aess class */
5103 /*      &omap44xx_aess_hwmod, */
5104
5105         /* bandgap class */
5106         &omap44xx_bandgap_hwmod,
5107
5108         /* counter class */
5109 /*      &omap44xx_counter_32k_hwmod, */
5110
5111         /* dma class */
5112         &omap44xx_dma_system_hwmod,
5113
5114         /* dmic class */
5115         &omap44xx_dmic_hwmod,
5116
5117         /* dsp class */
5118         &omap44xx_dsp_hwmod,
5119         &omap44xx_dsp_c0_hwmod,
5120
5121         /* dss class */
5122         &omap44xx_dss_hwmod,
5123         &omap44xx_dss_dispc_hwmod,
5124         &omap44xx_dss_dsi1_hwmod,
5125         &omap44xx_dss_dsi2_hwmod,
5126         &omap44xx_dss_hdmi_hwmod,
5127         &omap44xx_dss_rfbi_hwmod,
5128         &omap44xx_dss_venc_hwmod,
5129
5130         /* gpio class */
5131         &omap44xx_gpio1_hwmod,
5132         &omap44xx_gpio2_hwmod,
5133         &omap44xx_gpio3_hwmod,
5134         &omap44xx_gpio4_hwmod,
5135         &omap44xx_gpio5_hwmod,
5136         &omap44xx_gpio6_hwmod,
5137
5138         /* hsi class */
5139 /*      &omap44xx_hsi_hwmod, */
5140
5141         /* i2c class */
5142         &omap44xx_i2c1_hwmod,
5143         &omap44xx_i2c2_hwmod,
5144         &omap44xx_i2c3_hwmod,
5145         &omap44xx_i2c4_hwmod,
5146
5147         /* ipu class */
5148         &omap44xx_ipu_hwmod,
5149         &omap44xx_ipu_c0_hwmod,
5150         &omap44xx_ipu_c1_hwmod,
5151
5152         /* iss class */
5153 /*      &omap44xx_iss_hwmod, */
5154
5155         /* iva class */
5156         &omap44xx_iva_hwmod,
5157         &omap44xx_iva_seq0_hwmod,
5158         &omap44xx_iva_seq1_hwmod,
5159
5160         /* kbd class */
5161         &omap44xx_kbd_hwmod,
5162
5163         /* mailbox class */
5164         &omap44xx_mailbox_hwmod,
5165
5166         /* mcbsp class */
5167         &omap44xx_mcbsp1_hwmod,
5168         &omap44xx_mcbsp2_hwmod,
5169         &omap44xx_mcbsp3_hwmod,
5170         &omap44xx_mcbsp4_hwmod,
5171
5172         /* mcpdm class */
5173 /*      &omap44xx_mcpdm_hwmod, */
5174
5175         /* mcspi class */
5176         &omap44xx_mcspi1_hwmod,
5177         &omap44xx_mcspi2_hwmod,
5178         &omap44xx_mcspi3_hwmod,
5179         &omap44xx_mcspi4_hwmod,
5180
5181         /* mmc class */
5182         &omap44xx_mmc1_hwmod,
5183         &omap44xx_mmc2_hwmod,
5184         &omap44xx_mmc3_hwmod,
5185         &omap44xx_mmc4_hwmod,
5186         &omap44xx_mmc5_hwmod,
5187
5188         /* mpu class */
5189         &omap44xx_mpu_hwmod,
5190
5191         /* smartreflex class */
5192         &omap44xx_smartreflex_core_hwmod,
5193         &omap44xx_smartreflex_iva_hwmod,
5194         &omap44xx_smartreflex_mpu_hwmod,
5195
5196         /* spinlock class */
5197         &omap44xx_spinlock_hwmod,
5198
5199         /* timer class */
5200         &omap44xx_timer1_hwmod,
5201         &omap44xx_timer2_hwmod,
5202         &omap44xx_timer3_hwmod,
5203         &omap44xx_timer4_hwmod,
5204         &omap44xx_timer5_hwmod,
5205         &omap44xx_timer6_hwmod,
5206         &omap44xx_timer7_hwmod,
5207         &omap44xx_timer8_hwmod,
5208         &omap44xx_timer9_hwmod,
5209         &omap44xx_timer10_hwmod,
5210         &omap44xx_timer11_hwmod,
5211
5212         /* uart class */
5213         &omap44xx_uart1_hwmod,
5214         &omap44xx_uart2_hwmod,
5215         &omap44xx_uart3_hwmod,
5216         &omap44xx_uart4_hwmod,
5217
5218         /* usb_otg_hs class */
5219         &omap44xx_usb_otg_hs_hwmod,
5220
5221         /* wd_timer class */
5222         &omap44xx_wd_timer2_hwmod,
5223         &omap44xx_wd_timer3_hwmod,
5224
5225         NULL,
5226 };
5227
5228 int __init omap44xx_hwmod_init(void)
5229 {
5230         return omap_hwmod_register(omap44xx_hwmods);
5231 }
5232