arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /* Backward references (IPs with Bus Master capability) */
  50 static struct omap_hwmod omap44xx_aess_hwmod;
  51 static struct omap_hwmod omap44xx_dma_system_hwmod;
  52 static struct omap_hwmod omap44xx_dmm_hwmod;
  53 static struct omap_hwmod omap44xx_dsp_hwmod;
  54 static struct omap_hwmod omap44xx_dss_hwmod;
  55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  56 static struct omap_hwmod omap44xx_hsi_hwmod;
  57 static struct omap_hwmod omap44xx_ipu_hwmod;
  58 static struct omap_hwmod omap44xx_iss_hwmod;
  59 static struct omap_hwmod omap44xx_iva_hwmod;
  60 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  62 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  63 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  64 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  65 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  66 static struct omap_hwmod omap44xx_l4_per_hwmod;
  67 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  68 static struct omap_hwmod omap44xx_mmc1_hwmod;
  69 static struct omap_hwmod omap44xx_mmc2_hwmod;
  70 static struct omap_hwmod omap44xx_mpu_hwmod;
  71 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  72 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  73 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
  74 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
  75
  76 /*
  77  * Interconnects omap_hwmod structures
  78  * hwmods that compose the global OMAP interconnect
  79  */
  80
  81 /*
  82  * 'dmm' class
  83  * instance(s): dmm
  84  */
  85 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  86         .name   = "dmm",
  87 };
  88
  89 /* dmm */
  90 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  91         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  92         { .irq = -1 }
  93 };
  94
  95 /* l3_main_1 -> dmm */
  96 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  97         .master         = &omap44xx_l3_main_1_hwmod,
  98         .slave          = &omap44xx_dmm_hwmod,
  99         .clk            = "l3_div_ck",
 100         .user           = OCP_USER_SDMA,
 101 };
 102
 103 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 104         {
 105                 .pa_start       = 0x4e000000,
 106                 .pa_end         = 0x4e0007ff,
 107                 .flags          = ADDR_TYPE_RT
 108         },
 109         { }
 110 };
 111
 112 /* mpu -> dmm */
 113 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 114         .master         = &omap44xx_mpu_hwmod,
 115         .slave          = &omap44xx_dmm_hwmod,
 116         .clk            = "l3_div_ck",
 117         .addr           = omap44xx_dmm_addrs,
 118         .user           = OCP_USER_MPU,
 119 };
 120
 121 /* dmm slave ports */
 122 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 123         &omap44xx_l3_main_1__dmm,
 124         &omap44xx_mpu__dmm,
 125 };
 126
 127 static struct omap_hwmod omap44xx_dmm_hwmod = {
 128         .name           = "dmm",
 129         .class          = &omap44xx_dmm_hwmod_class,
 130         .clkdm_name     = "l3_emif_clkdm",
 131         .prcm = {
 132                 .omap4 = {
 133                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 134                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 135                 },
 136         },
 137         .slaves         = omap44xx_dmm_slaves,
 138         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 139         .mpu_irqs       = omap44xx_dmm_irqs,
 140 };
 141
 142 /*
 143  * 'emif_fw' class
 144  * instance(s): emif_fw
 145  */
 146 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 147         .name   = "emif_fw",
 148 };
 149
 150 /* emif_fw */
 151 /* dmm -> emif_fw */
 152 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 153         .master         = &omap44xx_dmm_hwmod,
 154         .slave          = &omap44xx_emif_fw_hwmod,
 155         .clk            = "l3_div_ck",
 156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 160         {
 161                 .pa_start       = 0x4a20c000,
 162                 .pa_end         = 0x4a20c0ff,
 163                 .flags          = ADDR_TYPE_RT
 164         },
 165         { }
 166 };
 167
 168 /* l4_cfg -> emif_fw */
 169 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 170         .master         = &omap44xx_l4_cfg_hwmod,
 171         .slave          = &omap44xx_emif_fw_hwmod,
 172         .clk            = "l4_div_ck",
 173         .addr           = omap44xx_emif_fw_addrs,
 174         .user           = OCP_USER_MPU,
 175 };
 176
 177 /* emif_fw slave ports */
 178 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 179         &omap44xx_dmm__emif_fw,
 180         &omap44xx_l4_cfg__emif_fw,
 181 };
 182
 183 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 184         .name           = "emif_fw",
 185         .class          = &omap44xx_emif_fw_hwmod_class,
 186         .clkdm_name     = "l3_emif_clkdm",
 187         .prcm = {
 188                 .omap4 = {
 189                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 190                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 191                 },
 192         },
 193         .slaves         = omap44xx_emif_fw_slaves,
 194         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 195 };
 196
 197 /*
 198  * 'l3' class
 199  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 200  */
 201 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 202         .name   = "l3",
 203 };
 204
 205 /* l3_instr */
 206 /* iva -> l3_instr */
 207 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 208         .master         = &omap44xx_iva_hwmod,
 209         .slave          = &omap44xx_l3_instr_hwmod,
 210         .clk            = "l3_div_ck",
 211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 212 };
 213
 214 /* l3_main_3 -> l3_instr */
 215 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 216         .master         = &omap44xx_l3_main_3_hwmod,
 217         .slave          = &omap44xx_l3_instr_hwmod,
 218         .clk            = "l3_div_ck",
 219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 220 };
 221
 222 /* l3_instr slave ports */
 223 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 224         &omap44xx_iva__l3_instr,
 225         &omap44xx_l3_main_3__l3_instr,
 226 };
 227
 228 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 229         .name           = "l3_instr",
 230         .class          = &omap44xx_l3_hwmod_class,
 231         .clkdm_name     = "l3_instr_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 236                         .modulemode   = MODULEMODE_HWCTRL,
 237                 },
 238         },
 239         .slaves         = omap44xx_l3_instr_slaves,
 240         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 241 };
 242
 243 /* l3_main_1 */
 244 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 245         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 246         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 247         { .irq = -1 }
 248 };
 249
 250 /* dsp -> l3_main_1 */
 251 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 252         .master         = &omap44xx_dsp_hwmod,
 253         .slave          = &omap44xx_l3_main_1_hwmod,
 254         .clk            = "l3_div_ck",
 255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 256 };
 257
 258 /* dss -> l3_main_1 */
 259 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 260         .master         = &omap44xx_dss_hwmod,
 261         .slave          = &omap44xx_l3_main_1_hwmod,
 262         .clk            = "l3_div_ck",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* l3_main_2 -> l3_main_1 */
 267 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 268         .master         = &omap44xx_l3_main_2_hwmod,
 269         .slave          = &omap44xx_l3_main_1_hwmod,
 270         .clk            = "l3_div_ck",
 271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 272 };
 273
 274 /* l4_cfg -> l3_main_1 */
 275 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 276         .master         = &omap44xx_l4_cfg_hwmod,
 277         .slave          = &omap44xx_l3_main_1_hwmod,
 278         .clk            = "l4_div_ck",
 279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 280 };
 281
 282 /* mmc1 -> l3_main_1 */
 283 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 284         .master         = &omap44xx_mmc1_hwmod,
 285         .slave          = &omap44xx_l3_main_1_hwmod,
 286         .clk            = "l3_div_ck",
 287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 288 };
 289
 290 /* mmc2 -> l3_main_1 */
 291 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 292         .master         = &omap44xx_mmc2_hwmod,
 293         .slave          = &omap44xx_l3_main_1_hwmod,
 294         .clk            = "l3_div_ck",
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 299         {
 300                 .pa_start       = 0x44000000,
 301                 .pa_end         = 0x44000fff,
 302                 .flags          = ADDR_TYPE_RT
 303         },
 304         { }
 305 };
 306
 307 /* mpu -> l3_main_1 */
 308 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 309         .master         = &omap44xx_mpu_hwmod,
 310         .slave          = &omap44xx_l3_main_1_hwmod,
 311         .clk            = "l3_div_ck",
 312         .addr           = omap44xx_l3_main_1_addrs,
 313         .user           = OCP_USER_MPU,
 314 };
 315
 316 /* l3_main_1 slave ports */
 317 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 318         &omap44xx_dsp__l3_main_1,
 319         &omap44xx_dss__l3_main_1,
 320         &omap44xx_l3_main_2__l3_main_1,
 321         &omap44xx_l4_cfg__l3_main_1,
 322         &omap44xx_mmc1__l3_main_1,
 323         &omap44xx_mmc2__l3_main_1,
 324         &omap44xx_mpu__l3_main_1,
 325 };
 326
 327 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 328         .name           = "l3_main_1",
 329         .class          = &omap44xx_l3_hwmod_class,
 330         .clkdm_name     = "l3_1_clkdm",
 331         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 332         .prcm = {
 333                 .omap4 = {
 334                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 335                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 336                 },
 337         },
 338         .slaves         = omap44xx_l3_main_1_slaves,
 339         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 340 };
 341
 342 /* l3_main_2 */
 343 /* dma_system -> l3_main_2 */
 344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 345         .master         = &omap44xx_dma_system_hwmod,
 346         .slave          = &omap44xx_l3_main_2_hwmod,
 347         .clk            = "l3_div_ck",
 348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 349 };
 350
 351 /* hsi -> l3_main_2 */
 352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 353         .master         = &omap44xx_hsi_hwmod,
 354         .slave          = &omap44xx_l3_main_2_hwmod,
 355         .clk            = "l3_div_ck",
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* ipu -> l3_main_2 */
 360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 361         .master         = &omap44xx_ipu_hwmod,
 362         .slave          = &omap44xx_l3_main_2_hwmod,
 363         .clk            = "l3_div_ck",
 364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 365 };
 366
 367 /* iss -> l3_main_2 */
 368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 369         .master         = &omap44xx_iss_hwmod,
 370         .slave          = &omap44xx_l3_main_2_hwmod,
 371         .clk            = "l3_div_ck",
 372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 373 };
 374
 375 /* iva -> l3_main_2 */
 376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 377         .master         = &omap44xx_iva_hwmod,
 378         .slave          = &omap44xx_l3_main_2_hwmod,
 379         .clk            = "l3_div_ck",
 380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 381 };
 382
 383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 384         {
 385                 .pa_start       = 0x44800000,
 386                 .pa_end         = 0x44801fff,
 387                 .flags          = ADDR_TYPE_RT
 388         },
 389         { }
 390 };
 391
 392 /* l3_main_1 -> l3_main_2 */
 393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 394         .master         = &omap44xx_l3_main_1_hwmod,
 395         .slave          = &omap44xx_l3_main_2_hwmod,
 396         .clk            = "l3_div_ck",
 397         .addr           = omap44xx_l3_main_2_addrs,
 398         .user           = OCP_USER_MPU,
 399 };
 400
 401 /* l4_cfg -> l3_main_2 */
 402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 403         .master         = &omap44xx_l4_cfg_hwmod,
 404         .slave          = &omap44xx_l3_main_2_hwmod,
 405         .clk            = "l4_div_ck",
 406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 407 };
 408
 409 /* usb_otg_hs -> l3_main_2 */
 410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 411         .master         = &omap44xx_usb_otg_hs_hwmod,
 412         .slave          = &omap44xx_l3_main_2_hwmod,
 413         .clk            = "l3_div_ck",
 414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 415 };
 416
 417 /* l3_main_2 slave ports */
 418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 419         &omap44xx_dma_system__l3_main_2,
 420         &omap44xx_hsi__l3_main_2,
 421         &omap44xx_ipu__l3_main_2,
 422         &omap44xx_iss__l3_main_2,
 423         &omap44xx_iva__l3_main_2,
 424         &omap44xx_l3_main_1__l3_main_2,
 425         &omap44xx_l4_cfg__l3_main_2,
 426         &omap44xx_usb_otg_hs__l3_main_2,
 427 };
 428
 429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 430         .name           = "l3_main_2",
 431         .class          = &omap44xx_l3_hwmod_class,
 432         .clkdm_name     = "l3_2_clkdm",
 433         .prcm = {
 434                 .omap4 = {
 435                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 436                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 437                 },
 438         },
 439         .slaves         = omap44xx_l3_main_2_slaves,
 440         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 441 };
 442
 443 /* l3_main_3 */
 444 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 445         {
 446                 .pa_start       = 0x45000000,
 447                 .pa_end         = 0x45000fff,
 448                 .flags          = ADDR_TYPE_RT
 449         },
 450         { }
 451 };
 452
 453 /* l3_main_1 -> l3_main_3 */
 454 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 455         .master         = &omap44xx_l3_main_1_hwmod,
 456         .slave          = &omap44xx_l3_main_3_hwmod,
 457         .clk            = "l3_div_ck",
 458         .addr           = omap44xx_l3_main_3_addrs,
 459         .user           = OCP_USER_MPU,
 460 };
 461
 462 /* l3_main_2 -> l3_main_3 */
 463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 464         .master         = &omap44xx_l3_main_2_hwmod,
 465         .slave          = &omap44xx_l3_main_3_hwmod,
 466         .clk            = "l3_div_ck",
 467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 468 };
 469
 470 /* l4_cfg -> l3_main_3 */
 471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 472         .master         = &omap44xx_l4_cfg_hwmod,
 473         .slave          = &omap44xx_l3_main_3_hwmod,
 474         .clk            = "l4_div_ck",
 475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 476 };
 477
 478 /* l3_main_3 slave ports */
 479 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 480         &omap44xx_l3_main_1__l3_main_3,
 481         &omap44xx_l3_main_2__l3_main_3,
 482         &omap44xx_l4_cfg__l3_main_3,
 483 };
 484
 485 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 486         .name           = "l3_main_3",
 487         .class          = &omap44xx_l3_hwmod_class,
 488         .clkdm_name     = "l3_instr_clkdm",
 489         .prcm = {
 490                 .omap4 = {
 491                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 492                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 493                         .modulemode   = MODULEMODE_HWCTRL,
 494                 },
 495         },
 496         .slaves         = omap44xx_l3_main_3_slaves,
 497         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 498 };
 499
 500 /*
 501  * 'l4' class
 502  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 503  */
 504 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 505         .name   = "l4",
 506 };
 507
 508 /* l4_abe */
 509 /* aess -> l4_abe */
 510 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 511         .master         = &omap44xx_aess_hwmod,
 512         .slave          = &omap44xx_l4_abe_hwmod,
 513         .clk            = "ocp_abe_iclk",
 514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 515 };
 516
 517 /* dsp -> l4_abe */
 518 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 519         .master         = &omap44xx_dsp_hwmod,
 520         .slave          = &omap44xx_l4_abe_hwmod,
 521         .clk            = "ocp_abe_iclk",
 522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 523 };
 524
 525 /* l3_main_1 -> l4_abe */
 526 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 527         .master         = &omap44xx_l3_main_1_hwmod,
 528         .slave          = &omap44xx_l4_abe_hwmod,
 529         .clk            = "l3_div_ck",
 530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 531 };
 532
 533 /* mpu -> l4_abe */
 534 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 535         .master         = &omap44xx_mpu_hwmod,
 536         .slave          = &omap44xx_l4_abe_hwmod,
 537         .clk            = "ocp_abe_iclk",
 538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 539 };
 540
 541 /* l4_abe slave ports */
 542 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 543         &omap44xx_aess__l4_abe,
 544         &omap44xx_dsp__l4_abe,
 545         &omap44xx_l3_main_1__l4_abe,
 546         &omap44xx_mpu__l4_abe,
 547 };
 548
 549 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 550         .name           = "l4_abe",
 551         .class          = &omap44xx_l4_hwmod_class,
 552         .clkdm_name     = "abe_clkdm",
 553         .prcm = {
 554                 .omap4 = {
 555                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 556                 },
 557         },
 558         .slaves         = omap44xx_l4_abe_slaves,
 559         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 560 };
 561
 562 /* l4_cfg */
 563 /* l3_main_1 -> l4_cfg */
 564 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 565         .master         = &omap44xx_l3_main_1_hwmod,
 566         .slave          = &omap44xx_l4_cfg_hwmod,
 567         .clk            = "l3_div_ck",
 568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 569 };
 570
 571 /* l4_cfg slave ports */
 572 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 573         &omap44xx_l3_main_1__l4_cfg,
 574 };
 575
 576 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 577         .name           = "l4_cfg",
 578         .class          = &omap44xx_l4_hwmod_class,
 579         .clkdm_name     = "l4_cfg_clkdm",
 580         .prcm = {
 581                 .omap4 = {
 582                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 583                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 584                 },
 585         },
 586         .slaves         = omap44xx_l4_cfg_slaves,
 587         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 588 };
 589
 590 /* l4_per */
 591 /* l3_main_2 -> l4_per */
 592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 593         .master         = &omap44xx_l3_main_2_hwmod,
 594         .slave          = &omap44xx_l4_per_hwmod,
 595         .clk            = "l3_div_ck",
 596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 597 };
 598
 599 /* l4_per slave ports */
 600 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 601         &omap44xx_l3_main_2__l4_per,
 602 };
 603
 604 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 605         .name           = "l4_per",
 606         .class          = &omap44xx_l4_hwmod_class,
 607         .clkdm_name     = "l4_per_clkdm",
 608         .prcm = {
 609                 .omap4 = {
 610                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 611                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 612                 },
 613         },
 614         .slaves         = omap44xx_l4_per_slaves,
 615         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 616 };
 617
 618 /* l4_wkup */
 619 /* l4_cfg -> l4_wkup */
 620 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 621         .master         = &omap44xx_l4_cfg_hwmod,
 622         .slave          = &omap44xx_l4_wkup_hwmod,
 623         .clk            = "l4_div_ck",
 624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 625 };
 626
 627 /* l4_wkup slave ports */
 628 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 629         &omap44xx_l4_cfg__l4_wkup,
 630 };
 631
 632 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 633         .name           = "l4_wkup",
 634         .class          = &omap44xx_l4_hwmod_class,
 635         .clkdm_name     = "l4_wkup_clkdm",
 636         .prcm = {
 637                 .omap4 = {
 638                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 639                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 640                 },
 641         },
 642         .slaves         = omap44xx_l4_wkup_slaves,
 643         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 644 };
 645
 646 /*
 647  * 'mpu_bus' class
 648  * instance(s): mpu_private
 649  */
 650 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 651         .name   = "mpu_bus",
 652 };
 653
 654 /* mpu_private */
 655 /* mpu -> mpu_private */
 656 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 657         .master         = &omap44xx_mpu_hwmod,
 658         .slave          = &omap44xx_mpu_private_hwmod,
 659         .clk            = "l3_div_ck",
 660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 661 };
 662
 663 /* mpu_private slave ports */
 664 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 665         &omap44xx_mpu__mpu_private,
 666 };
 667
 668 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 669         .name           = "mpu_private",
 670         .class          = &omap44xx_mpu_bus_hwmod_class,
 671         .clkdm_name     = "mpuss_clkdm",
 672         .slaves         = omap44xx_mpu_private_slaves,
 673         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 674 };
 675
 676 /*
 677  * Modules omap_hwmod structures
 678  *
 679  * The following IPs are excluded for the moment because:
 680  * - They do not need an explicit SW control using omap_hwmod API.
 681  * - They still need to be validated with the driver
 682  *   properly adapted to omap_hwmod / omap_device
 683  *
 684  *  c2c
 685  *  c2c_target_fw
 686  *  cm_core
 687  *  cm_core_aon
 688  *  ctrl_module_core
 689  *  ctrl_module_pad_core
 690  *  ctrl_module_pad_wkup
 691  *  ctrl_module_wkup
 692  *  debugss
 693  *  efuse_ctrl_cust
 694  *  efuse_ctrl_std
 695  *  elm
 696  *  emif1
 697  *  emif2
 698  *  fdif
 699  *  gpmc
 700  *  gpu
 701  *  hdq1w
 702  *  mcasp
 703  *  mpu_c0
 704  *  mpu_c1
 705  *  ocmc_ram
 706  *  ocp2scp_usb_phy
 707  *  ocp_wp_noc
 708  *  prcm_mpu
 709  *  prm
 710  *  scrm
 711  *  sl2if
 712  *  slimbus1
 713  *  slimbus2
 714  *  usb_host_fs
 715  *  usb_host_hs
 716  *  usb_phy_cm
 717  *  usb_tll_hs
 718  *  usim
 719  */
 720
 721 /*
 722  * 'aess' class
 723  * audio engine sub system
 724  */
 725
 726 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 727         .rev_offs       = 0x0000,
 728         .sysc_offs      = 0x0010,
 729         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 731                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 732                            MSTANDBY_SMART_WKUP),
 733         .sysc_fields    = &omap_hwmod_sysc_type2,
 734 };
 735
 736 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 737         .name   = "aess",
 738         .sysc   = &omap44xx_aess_sysc,
 739 };
 740
 741 /* aess */
 742 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 743         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 744         { .irq = -1 }
 745 };
 746
 747 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 748         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 749         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 750         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 751         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 752         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 753         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 754         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 755         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 756         { .dma_req = -1 }
 757 };
 758
 759 /* aess master ports */
 760 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 761         &omap44xx_aess__l4_abe,
 762 };
 763
 764 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 765         {
 766                 .pa_start       = 0x401f1000,
 767                 .pa_end         = 0x401f13ff,
 768                 .flags          = ADDR_TYPE_RT
 769         },
 770         { }
 771 };
 772
 773 /* l4_abe -> aess */
 774 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 775         .master         = &omap44xx_l4_abe_hwmod,
 776         .slave          = &omap44xx_aess_hwmod,
 777         .clk            = "ocp_abe_iclk",
 778         .addr           = omap44xx_aess_addrs,
 779         .user           = OCP_USER_MPU,
 780 };
 781
 782 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 783         {
 784                 .pa_start       = 0x490f1000,
 785                 .pa_end         = 0x490f13ff,
 786                 .flags          = ADDR_TYPE_RT
 787         },
 788         { }
 789 };
 790
 791 /* l4_abe -> aess (dma) */
 792 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 793         .master         = &omap44xx_l4_abe_hwmod,
 794         .slave          = &omap44xx_aess_hwmod,
 795         .clk            = "ocp_abe_iclk",
 796         .addr           = omap44xx_aess_dma_addrs,
 797         .user           = OCP_USER_SDMA,
 798 };
 799
 800 /* aess slave ports */
 801 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 802         &omap44xx_l4_abe__aess,
 803         &omap44xx_l4_abe__aess_dma,
 804 };
 805
 806 static struct omap_hwmod omap44xx_aess_hwmod = {
 807         .name           = "aess",
 808         .class          = &omap44xx_aess_hwmod_class,
 809         .clkdm_name     = "abe_clkdm",
 810         .mpu_irqs       = omap44xx_aess_irqs,
 811         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 812         .main_clk       = "aess_fck",
 813         .prcm = {
 814                 .omap4 = {
 815                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 816                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 817                         .modulemode   = MODULEMODE_SWCTRL,
 818                 },
 819         },
 820         .slaves         = omap44xx_aess_slaves,
 821         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 822         .masters        = omap44xx_aess_masters,
 823         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 824 };
 825
 826 /*
 827  * 'bandgap' class
 828  * bangap reference for ldo regulators
 829  */
 830
 831 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 832         .name   = "bandgap",
 833 };
 834
 835 /* bandgap */
 836 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 837         { .role = "fclk", .clk = "bandgap_fclk" },
 838 };
 839
 840 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 841         .name           = "bandgap",
 842         .class          = &omap44xx_bandgap_hwmod_class,
 843         .clkdm_name     = "l4_wkup_clkdm",
 844         .prcm = {
 845                 .omap4 = {
 846                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 847                 },
 848         },
 849         .opt_clks       = bandgap_opt_clks,
 850         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 851 };
 852
 853 /*
 854  * 'counter' class
 855  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 856  */
 857
 858 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 859         .rev_offs       = 0x0000,
 860         .sysc_offs      = 0x0004,
 861         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 862         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 863                            SIDLE_SMART_WKUP),
 864         .sysc_fields    = &omap_hwmod_sysc_type1,
 865 };
 866
 867 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 868         .name   = "counter",
 869         .sysc   = &omap44xx_counter_sysc,
 870 };
 871
 872 /* counter_32k */
 873 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 874 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 875         {
 876                 .pa_start       = 0x4a304000,
 877                 .pa_end         = 0x4a30401f,
 878                 .flags          = ADDR_TYPE_RT
 879         },
 880         { }
 881 };
 882
 883 /* l4_wkup -> counter_32k */
 884 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 885         .master         = &omap44xx_l4_wkup_hwmod,
 886         .slave          = &omap44xx_counter_32k_hwmod,
 887         .clk            = "l4_wkup_clk_mux_ck",
 888         .addr           = omap44xx_counter_32k_addrs,
 889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 890 };
 891
 892 /* counter_32k slave ports */
 893 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 894         &omap44xx_l4_wkup__counter_32k,
 895 };
 896
 897 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 898         .name           = "counter_32k",
 899         .class          = &omap44xx_counter_hwmod_class,
 900         .clkdm_name     = "l4_wkup_clkdm",
 901         .flags          = HWMOD_SWSUP_SIDLE,
 902         .main_clk       = "sys_32k_ck",
 903         .prcm = {
 904                 .omap4 = {
 905                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 906                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 907                 },
 908         },
 909         .slaves         = omap44xx_counter_32k_slaves,
 910         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 911 };
 912
 913 /*
 914  * 'dma' class
 915  * dma controller for data exchange between memory to memory (i.e. internal or
 916  * external memory) and gp peripherals to memory or memory to gp peripherals
 917  */
 918
 919 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 920         .rev_offs       = 0x0000,
 921         .sysc_offs      = 0x002c,
 922         .syss_offs      = 0x0028,
 923         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 924                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 925                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 926                            SYSS_HAS_RESET_STATUS),
 927         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 928                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 929         .sysc_fields    = &omap_hwmod_sysc_type1,
 930 };
 931
 932 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 933         .name   = "dma",
 934         .sysc   = &omap44xx_dma_sysc,
 935 };
 936
 937 /* dma dev_attr */
 938 static struct omap_dma_dev_attr dma_dev_attr = {
 939         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 940                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 941         .lch_count      = 32,
 942 };
 943
 944 /* dma_system */
 945 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 946         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 947         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 948         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 949         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 950         { .irq = -1 }
 951 };
 952
 953 /* dma_system master ports */
 954 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 955         &omap44xx_dma_system__l3_main_2,
 956 };
 957
 958 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 959         {
 960                 .pa_start       = 0x4a056000,
 961                 .pa_end         = 0x4a056fff,
 962                 .flags          = ADDR_TYPE_RT
 963         },
 964         { }
 965 };
 966
 967 /* l4_cfg -> dma_system */
 968 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 969         .master         = &omap44xx_l4_cfg_hwmod,
 970         .slave          = &omap44xx_dma_system_hwmod,
 971         .clk            = "l4_div_ck",
 972         .addr           = omap44xx_dma_system_addrs,
 973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 974 };
 975
 976 /* dma_system slave ports */
 977 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 978         &omap44xx_l4_cfg__dma_system,
 979 };
 980
 981 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 982         .name           = "dma_system",
 983         .class          = &omap44xx_dma_hwmod_class,
 984         .clkdm_name     = "l3_dma_clkdm",
 985         .mpu_irqs       = omap44xx_dma_system_irqs,
 986         .main_clk       = "l3_div_ck",
 987         .prcm = {
 988                 .omap4 = {
 989                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 990                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 991                 },
 992         },
 993         .dev_attr       = &dma_dev_attr,
 994         .slaves         = omap44xx_dma_system_slaves,
 995         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 996         .masters        = omap44xx_dma_system_masters,
 997         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 998 };
 999
1000 /*
1001  * 'dmic' class
1002  * digital microphone controller
1003  */
1004
1005 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1006         .rev_offs       = 0x0000,
1007         .sysc_offs      = 0x0010,
1008         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1009                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1011                            SIDLE_SMART_WKUP),
1012         .sysc_fields    = &omap_hwmod_sysc_type2,
1013 };
1014
1015 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1016         .name   = "dmic",
1017         .sysc   = &omap44xx_dmic_sysc,
1018 };
1019
1020 /* dmic */
1021 static struct omap_hwmod omap44xx_dmic_hwmod;
1022 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1024         { .irq = -1 }
1025 };
1026
1027 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1028         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1029         { .dma_req = -1 }
1030 };
1031
1032 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033         {
1034                 .name           = "mpu",
1035                 .pa_start       = 0x4012e000,
1036                 .pa_end         = 0x4012e07f,
1037                 .flags          = ADDR_TYPE_RT
1038         },
1039         { }
1040 };
1041
1042 /* l4_abe -> dmic */
1043 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1044         .master         = &omap44xx_l4_abe_hwmod,
1045         .slave          = &omap44xx_dmic_hwmod,
1046         .clk            = "ocp_abe_iclk",
1047         .addr           = omap44xx_dmic_addrs,
1048         .user           = OCP_USER_MPU,
1049 };
1050
1051 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1052         {
1053                 .name           = "dma",
1054                 .pa_start       = 0x4902e000,
1055                 .pa_end         = 0x4902e07f,
1056                 .flags          = ADDR_TYPE_RT
1057         },
1058         { }
1059 };
1060
1061 /* l4_abe -> dmic (dma) */
1062 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1063         .master         = &omap44xx_l4_abe_hwmod,
1064         .slave          = &omap44xx_dmic_hwmod,
1065         .clk            = "ocp_abe_iclk",
1066         .addr           = omap44xx_dmic_dma_addrs,
1067         .user           = OCP_USER_SDMA,
1068 };
1069
1070 /* dmic slave ports */
1071 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1072         &omap44xx_l4_abe__dmic,
1073         &omap44xx_l4_abe__dmic_dma,
1074 };
1075
1076 static struct omap_hwmod omap44xx_dmic_hwmod = {
1077         .name           = "dmic",
1078         .class          = &omap44xx_dmic_hwmod_class,
1079         .clkdm_name     = "abe_clkdm",
1080         .mpu_irqs       = omap44xx_dmic_irqs,
1081         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1082         .main_clk       = "dmic_fck",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1086                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090         .slaves         = omap44xx_dmic_slaves,
1091         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1092 };
1093
1094 /*
1095  * 'dsp' class
1096  * dsp sub-system
1097  */
1098
1099 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1100         .name   = "dsp",
1101 };
1102
1103 /* dsp */
1104 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1105         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1106         { .irq = -1 }
1107 };
1108
1109 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110         { .name = "mmu_cache", .rst_shift = 1 },
1111 };
1112
1113 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1114         { .name = "dsp", .rst_shift = 0 },
1115 };
1116
1117 /* dsp -> iva */
1118 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1119         .master         = &omap44xx_dsp_hwmod,
1120         .slave          = &omap44xx_iva_hwmod,
1121         .clk            = "dpll_iva_m5x2_ck",
1122 };
1123
1124 /* dsp master ports */
1125 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1126         &omap44xx_dsp__l3_main_1,
1127         &omap44xx_dsp__l4_abe,
1128         &omap44xx_dsp__iva,
1129 };
1130
1131 /* l4_cfg -> dsp */
1132 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1133         .master         = &omap44xx_l4_cfg_hwmod,
1134         .slave          = &omap44xx_dsp_hwmod,
1135         .clk            = "l4_div_ck",
1136         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1137 };
1138
1139 /* dsp slave ports */
1140 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1141         &omap44xx_l4_cfg__dsp,
1142 };
1143
1144 /* Pseudo hwmod for reset control purpose only */
1145 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1146         .name           = "dsp_c0",
1147         .class          = &omap44xx_dsp_hwmod_class,
1148         .clkdm_name     = "tesla_clkdm",
1149         .flags          = HWMOD_INIT_NO_RESET,
1150         .rst_lines      = omap44xx_dsp_c0_resets,
1151         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1152         .prcm = {
1153                 .omap4 = {
1154                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1155                 },
1156         },
1157 };
1158
1159 static struct omap_hwmod omap44xx_dsp_hwmod = {
1160         .name           = "dsp",
1161         .class          = &omap44xx_dsp_hwmod_class,
1162         .clkdm_name     = "tesla_clkdm",
1163         .mpu_irqs       = omap44xx_dsp_irqs,
1164         .rst_lines      = omap44xx_dsp_resets,
1165         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1166         .main_clk       = "dsp_fck",
1167         .prcm = {
1168                 .omap4 = {
1169                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1170                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1171                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1172                         .modulemode   = MODULEMODE_HWCTRL,
1173                 },
1174         },
1175         .slaves         = omap44xx_dsp_slaves,
1176         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1177         .masters        = omap44xx_dsp_masters,
1178         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1179 };
1180
1181 /*
1182  * 'dss' class
1183  * display sub-system
1184  */
1185
1186 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1187         .rev_offs       = 0x0000,
1188         .syss_offs      = 0x0014,
1189         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1190 };
1191
1192 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1193         .name   = "dss",
1194         .sysc   = &omap44xx_dss_sysc,
1195         .reset  = omap_dss_reset,
1196 };
1197
1198 /* dss */
1199 /* dss master ports */
1200 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1201         &omap44xx_dss__l3_main_1,
1202 };
1203
1204 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1205         {
1206                 .pa_start       = 0x58000000,
1207                 .pa_end         = 0x5800007f,
1208                 .flags          = ADDR_TYPE_RT
1209         },
1210         { }
1211 };
1212
1213 /* l3_main_2 -> dss */
1214 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1215         .master         = &omap44xx_l3_main_2_hwmod,
1216         .slave          = &omap44xx_dss_hwmod,
1217         .clk            = "dss_fck",
1218         .addr           = omap44xx_dss_dma_addrs,
1219         .user           = OCP_USER_SDMA,
1220 };
1221
1222 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1223         {
1224                 .pa_start       = 0x48040000,
1225                 .pa_end         = 0x4804007f,
1226                 .flags          = ADDR_TYPE_RT
1227         },
1228         { }
1229 };
1230
1231 /* l4_per -> dss */
1232 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1233         .master         = &omap44xx_l4_per_hwmod,
1234         .slave          = &omap44xx_dss_hwmod,
1235         .clk            = "l4_div_ck",
1236         .addr           = omap44xx_dss_addrs,
1237         .user           = OCP_USER_MPU,
1238 };
1239
1240 /* dss slave ports */
1241 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1242         &omap44xx_l3_main_2__dss,
1243         &omap44xx_l4_per__dss,
1244 };
1245
1246 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1247         { .role = "sys_clk", .clk = "dss_sys_clk" },
1248         { .role = "tv_clk", .clk = "dss_tv_clk" },
1249         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1250 };
1251
1252 static struct omap_hwmod omap44xx_dss_hwmod = {
1253         .name           = "dss_core",
1254         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1255         .class          = &omap44xx_dss_hwmod_class,
1256         .clkdm_name     = "l3_dss_clkdm",
1257         .main_clk       = "dss_dss_clk",
1258         .prcm = {
1259                 .omap4 = {
1260                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1261                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1262                 },
1263         },
1264         .opt_clks       = dss_opt_clks,
1265         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1266         .slaves         = omap44xx_dss_slaves,
1267         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1268         .masters        = omap44xx_dss_masters,
1269         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1270 };
1271
1272 /*
1273  * 'dispc' class
1274  * display controller
1275  */
1276
1277 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1278         .rev_offs       = 0x0000,
1279         .sysc_offs      = 0x0010,
1280         .syss_offs      = 0x0014,
1281         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1282                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1283                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1284                            SYSS_HAS_RESET_STATUS),
1285         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1286                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1287         .sysc_fields    = &omap_hwmod_sysc_type1,
1288 };
1289
1290 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1291         .name   = "dispc",
1292         .sysc   = &omap44xx_dispc_sysc,
1293 };
1294
1295 /* dss_dispc */
1296 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1297 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1298         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1299         { .irq = -1 }
1300 };
1301
1302 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1303         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1304         { .dma_req = -1 }
1305 };
1306
1307 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1308         {
1309                 .pa_start       = 0x58001000,
1310                 .pa_end         = 0x58001fff,
1311                 .flags          = ADDR_TYPE_RT
1312         },
1313         { }
1314 };
1315
1316 /* l3_main_2 -> dss_dispc */
1317 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1318         .master         = &omap44xx_l3_main_2_hwmod,
1319         .slave          = &omap44xx_dss_dispc_hwmod,
1320         .clk            = "dss_fck",
1321         .addr           = omap44xx_dss_dispc_dma_addrs,
1322         .user           = OCP_USER_SDMA,
1323 };
1324
1325 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1326         {
1327                 .pa_start       = 0x48041000,
1328                 .pa_end         = 0x48041fff,
1329                 .flags          = ADDR_TYPE_RT
1330         },
1331         { }
1332 };
1333
1334 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1335         .manager_count          = 3,
1336         .has_framedonetv_irq    = 1
1337 };
1338
1339 /* l4_per -> dss_dispc */
1340 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1341         .master         = &omap44xx_l4_per_hwmod,
1342         .slave          = &omap44xx_dss_dispc_hwmod,
1343         .clk            = "l4_div_ck",
1344         .addr           = omap44xx_dss_dispc_addrs,
1345         .user           = OCP_USER_MPU,
1346 };
1347
1348 /* dss_dispc slave ports */
1349 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1350         &omap44xx_l3_main_2__dss_dispc,
1351         &omap44xx_l4_per__dss_dispc,
1352 };
1353
1354 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1355         .name           = "dss_dispc",
1356         .class          = &omap44xx_dispc_hwmod_class,
1357         .clkdm_name     = "l3_dss_clkdm",
1358         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1359         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1360         .main_clk       = "dss_dss_clk",
1361         .prcm = {
1362                 .omap4 = {
1363                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1364                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1365                 },
1366         },
1367         .slaves         = omap44xx_dss_dispc_slaves,
1368         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1369         .dev_attr       = &omap44xx_dss_dispc_dev_attr
1370 };
1371
1372 /*
1373  * 'dsi' class
1374  * display serial interface controller
1375  */
1376
1377 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1378         .rev_offs       = 0x0000,
1379         .sysc_offs      = 0x0010,
1380         .syss_offs      = 0x0014,
1381         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1382                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1383                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1384         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1385         .sysc_fields    = &omap_hwmod_sysc_type1,
1386 };
1387
1388 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1389         .name   = "dsi",
1390         .sysc   = &omap44xx_dsi_sysc,
1391 };
1392
1393 /* dss_dsi1 */
1394 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1395 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1396         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1397         { .irq = -1 }
1398 };
1399
1400 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1401         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1402         { .dma_req = -1 }
1403 };
1404
1405 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1406         {
1407                 .pa_start       = 0x58004000,
1408                 .pa_end         = 0x580041ff,
1409                 .flags          = ADDR_TYPE_RT
1410         },
1411         { }
1412 };
1413
1414 /* l3_main_2 -> dss_dsi1 */
1415 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1416         .master         = &omap44xx_l3_main_2_hwmod,
1417         .slave          = &omap44xx_dss_dsi1_hwmod,
1418         .clk            = "dss_fck",
1419         .addr           = omap44xx_dss_dsi1_dma_addrs,
1420         .user           = OCP_USER_SDMA,
1421 };
1422
1423 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1424         {
1425                 .pa_start       = 0x48044000,
1426                 .pa_end         = 0x480441ff,
1427                 .flags          = ADDR_TYPE_RT
1428         },
1429         { }
1430 };
1431
1432 /* l4_per -> dss_dsi1 */
1433 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1434         .master         = &omap44xx_l4_per_hwmod,
1435         .slave          = &omap44xx_dss_dsi1_hwmod,
1436         .clk            = "l4_div_ck",
1437         .addr           = omap44xx_dss_dsi1_addrs,
1438         .user           = OCP_USER_MPU,
1439 };
1440
1441 /* dss_dsi1 slave ports */
1442 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1443         &omap44xx_l3_main_2__dss_dsi1,
1444         &omap44xx_l4_per__dss_dsi1,
1445 };
1446
1447 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1448         { .role = "sys_clk", .clk = "dss_sys_clk" },
1449 };
1450
1451 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1452         .name           = "dss_dsi1",
1453         .class          = &omap44xx_dsi_hwmod_class,
1454         .clkdm_name     = "l3_dss_clkdm",
1455         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1456         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1457         .main_clk       = "dss_dss_clk",
1458         .prcm = {
1459                 .omap4 = {
1460                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1461                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1462                 },
1463         },
1464         .opt_clks       = dss_dsi1_opt_clks,
1465         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1466         .slaves         = omap44xx_dss_dsi1_slaves,
1467         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1468 };
1469
1470 /* dss_dsi2 */
1471 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1472 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1473         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1474         { .irq = -1 }
1475 };
1476
1477 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1478         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1479         { .dma_req = -1 }
1480 };
1481
1482 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1483         {
1484                 .pa_start       = 0x58005000,
1485                 .pa_end         = 0x580051ff,
1486                 .flags          = ADDR_TYPE_RT
1487         },
1488         { }
1489 };
1490
1491 /* l3_main_2 -> dss_dsi2 */
1492 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1493         .master         = &omap44xx_l3_main_2_hwmod,
1494         .slave          = &omap44xx_dss_dsi2_hwmod,
1495         .clk            = "dss_fck",
1496         .addr           = omap44xx_dss_dsi2_dma_addrs,
1497         .user           = OCP_USER_SDMA,
1498 };
1499
1500 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1501         {
1502                 .pa_start       = 0x48045000,
1503                 .pa_end         = 0x480451ff,
1504                 .flags          = ADDR_TYPE_RT
1505         },
1506         { }
1507 };
1508
1509 /* l4_per -> dss_dsi2 */
1510 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1511         .master         = &omap44xx_l4_per_hwmod,
1512         .slave          = &omap44xx_dss_dsi2_hwmod,
1513         .clk            = "l4_div_ck",
1514         .addr           = omap44xx_dss_dsi2_addrs,
1515         .user           = OCP_USER_MPU,
1516 };
1517
1518 /* dss_dsi2 slave ports */
1519 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1520         &omap44xx_l3_main_2__dss_dsi2,
1521         &omap44xx_l4_per__dss_dsi2,
1522 };
1523
1524 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1525         { .role = "sys_clk", .clk = "dss_sys_clk" },
1526 };
1527
1528 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1529         .name           = "dss_dsi2",
1530         .class          = &omap44xx_dsi_hwmod_class,
1531         .clkdm_name     = "l3_dss_clkdm",
1532         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1533         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1534         .main_clk       = "dss_dss_clk",
1535         .prcm = {
1536                 .omap4 = {
1537                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1538                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1539                 },
1540         },
1541         .opt_clks       = dss_dsi2_opt_clks,
1542         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1543         .slaves         = omap44xx_dss_dsi2_slaves,
1544         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1545 };
1546
1547 /*
1548  * 'hdmi' class
1549  * hdmi controller
1550  */
1551
1552 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1553         .rev_offs       = 0x0000,
1554         .sysc_offs      = 0x0010,
1555         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1556                            SYSC_HAS_SOFTRESET),
1557         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1558                            SIDLE_SMART_WKUP),
1559         .sysc_fields    = &omap_hwmod_sysc_type2,
1560 };
1561
1562 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1563         .name   = "hdmi",
1564         .sysc   = &omap44xx_hdmi_sysc,
1565 };
1566
1567 /* dss_hdmi */
1568 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1569 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1570         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1571         { .irq = -1 }
1572 };
1573
1574 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1575         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1576         { .dma_req = -1 }
1577 };
1578
1579 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1580         {
1581                 .pa_start       = 0x58006000,
1582                 .pa_end         = 0x58006fff,
1583                 .flags          = ADDR_TYPE_RT
1584         },
1585         { }
1586 };
1587
1588 /* l3_main_2 -> dss_hdmi */
1589 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1590         .master         = &omap44xx_l3_main_2_hwmod,
1591         .slave          = &omap44xx_dss_hdmi_hwmod,
1592         .clk            = "dss_fck",
1593         .addr           = omap44xx_dss_hdmi_dma_addrs,
1594         .user           = OCP_USER_SDMA,
1595 };
1596
1597 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1598         {
1599                 .pa_start       = 0x48046000,
1600                 .pa_end         = 0x48046fff,
1601                 .flags          = ADDR_TYPE_RT
1602         },
1603         { }
1604 };
1605
1606 /* l4_per -> dss_hdmi */
1607 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1608         .master         = &omap44xx_l4_per_hwmod,
1609         .slave          = &omap44xx_dss_hdmi_hwmod,
1610         .clk            = "l4_div_ck",
1611         .addr           = omap44xx_dss_hdmi_addrs,
1612         .user           = OCP_USER_MPU,
1613 };
1614
1615 /* dss_hdmi slave ports */
1616 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1617         &omap44xx_l3_main_2__dss_hdmi,
1618         &omap44xx_l4_per__dss_hdmi,
1619 };
1620
1621 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1622         { .role = "sys_clk", .clk = "dss_sys_clk" },
1623 };
1624
1625 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1626         .name           = "dss_hdmi",
1627         .class          = &omap44xx_hdmi_hwmod_class,
1628         .clkdm_name     = "l3_dss_clkdm",
1629         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1630         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1631         .main_clk       = "dss_48mhz_clk",
1632         .prcm = {
1633                 .omap4 = {
1634                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1635                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1636                 },
1637         },
1638         .opt_clks       = dss_hdmi_opt_clks,
1639         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1640         .slaves         = omap44xx_dss_hdmi_slaves,
1641         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1642 };
1643
1644 /*
1645  * 'rfbi' class
1646  * remote frame buffer interface
1647  */
1648
1649 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1650         .rev_offs       = 0x0000,
1651         .sysc_offs      = 0x0010,
1652         .syss_offs      = 0x0014,
1653         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1654                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1655         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1656         .sysc_fields    = &omap_hwmod_sysc_type1,
1657 };
1658
1659 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1660         .name   = "rfbi",
1661         .sysc   = &omap44xx_rfbi_sysc,
1662 };
1663
1664 /* dss_rfbi */
1665 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1666 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1667         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1668         { .dma_req = -1 }
1669 };
1670
1671 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1672         {
1673                 .pa_start       = 0x58002000,
1674                 .pa_end         = 0x580020ff,
1675                 .flags          = ADDR_TYPE_RT
1676         },
1677         { }
1678 };
1679
1680 /* l3_main_2 -> dss_rfbi */
1681 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1682         .master         = &omap44xx_l3_main_2_hwmod,
1683         .slave          = &omap44xx_dss_rfbi_hwmod,
1684         .clk            = "dss_fck",
1685         .addr           = omap44xx_dss_rfbi_dma_addrs,
1686         .user           = OCP_USER_SDMA,
1687 };
1688
1689 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1690         {
1691                 .pa_start       = 0x48042000,
1692                 .pa_end         = 0x480420ff,
1693                 .flags          = ADDR_TYPE_RT
1694         },
1695         { }
1696 };
1697
1698 /* l4_per -> dss_rfbi */
1699 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1700         .master         = &omap44xx_l4_per_hwmod,
1701         .slave          = &omap44xx_dss_rfbi_hwmod,
1702         .clk            = "l4_div_ck",
1703         .addr           = omap44xx_dss_rfbi_addrs,
1704         .user           = OCP_USER_MPU,
1705 };
1706
1707 /* dss_rfbi slave ports */
1708 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1709         &omap44xx_l3_main_2__dss_rfbi,
1710         &omap44xx_l4_per__dss_rfbi,
1711 };
1712
1713 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1714         { .role = "ick", .clk = "dss_fck" },
1715 };
1716
1717 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1718         .name           = "dss_rfbi",
1719         .class          = &omap44xx_rfbi_hwmod_class,
1720         .clkdm_name     = "l3_dss_clkdm",
1721         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1722         .main_clk       = "dss_dss_clk",
1723         .prcm = {
1724                 .omap4 = {
1725                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1726                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1727                 },
1728         },
1729         .opt_clks       = dss_rfbi_opt_clks,
1730         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1731         .slaves         = omap44xx_dss_rfbi_slaves,
1732         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1733 };
1734
1735 /*
1736  * 'venc' class
1737  * video encoder
1738  */
1739
1740 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1741         .name   = "venc",
1742 };
1743
1744 /* dss_venc */
1745 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1746 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1747         {
1748                 .pa_start       = 0x58003000,
1749                 .pa_end         = 0x580030ff,
1750                 .flags          = ADDR_TYPE_RT
1751         },
1752         { }
1753 };
1754
1755 /* l3_main_2 -> dss_venc */
1756 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1757         .master         = &omap44xx_l3_main_2_hwmod,
1758         .slave          = &omap44xx_dss_venc_hwmod,
1759         .clk            = "dss_fck",
1760         .addr           = omap44xx_dss_venc_dma_addrs,
1761         .user           = OCP_USER_SDMA,
1762 };
1763
1764 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1765         {
1766                 .pa_start       = 0x48043000,
1767                 .pa_end         = 0x480430ff,
1768                 .flags          = ADDR_TYPE_RT
1769         },
1770         { }
1771 };
1772
1773 /* l4_per -> dss_venc */
1774 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1775         .master         = &omap44xx_l4_per_hwmod,
1776         .slave          = &omap44xx_dss_venc_hwmod,
1777         .clk            = "l4_div_ck",
1778         .addr           = omap44xx_dss_venc_addrs,
1779         .user           = OCP_USER_MPU,
1780 };
1781
1782 /* dss_venc slave ports */
1783 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1784         &omap44xx_l3_main_2__dss_venc,
1785         &omap44xx_l4_per__dss_venc,
1786 };
1787
1788 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1789         .name           = "dss_venc",
1790         .class          = &omap44xx_venc_hwmod_class,
1791         .clkdm_name     = "l3_dss_clkdm",
1792         .main_clk       = "dss_tv_clk",
1793         .prcm = {
1794                 .omap4 = {
1795                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1796                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1797                 },
1798         },
1799         .slaves         = omap44xx_dss_venc_slaves,
1800         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1801 };
1802
1803 /*
1804  * 'gpio' class
1805  * general purpose io module
1806  */
1807
1808 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1809         .rev_offs       = 0x0000,
1810         .sysc_offs      = 0x0010,
1811         .syss_offs      = 0x0114,
1812         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1813                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1814                            SYSS_HAS_RESET_STATUS),
1815         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1816                            SIDLE_SMART_WKUP),
1817         .sysc_fields    = &omap_hwmod_sysc_type1,
1818 };
1819
1820 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1821         .name   = "gpio",
1822         .sysc   = &omap44xx_gpio_sysc,
1823         .rev    = 2,
1824 };
1825
1826 /* gpio dev_attr */
1827 static struct omap_gpio_dev_attr gpio_dev_attr = {
1828         .bank_width     = 32,
1829         .dbck_flag      = true,
1830 };
1831
1832 /* gpio1 */
1833 static struct omap_hwmod omap44xx_gpio1_hwmod;
1834 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1835         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1836         { .irq = -1 }
1837 };
1838
1839 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1840         {
1841                 .pa_start       = 0x4a310000,
1842                 .pa_end         = 0x4a3101ff,
1843                 .flags          = ADDR_TYPE_RT
1844         },
1845         { }
1846 };
1847
1848 /* l4_wkup -> gpio1 */
1849 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1850         .master         = &omap44xx_l4_wkup_hwmod,
1851         .slave          = &omap44xx_gpio1_hwmod,
1852         .clk            = "l4_wkup_clk_mux_ck",
1853         .addr           = omap44xx_gpio1_addrs,
1854         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1855 };
1856
1857 /* gpio1 slave ports */
1858 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1859         &omap44xx_l4_wkup__gpio1,
1860 };
1861
1862 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1863         { .role = "dbclk", .clk = "gpio1_dbclk" },
1864 };
1865
1866 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1867         .name           = "gpio1",
1868         .class          = &omap44xx_gpio_hwmod_class,
1869         .clkdm_name     = "l4_wkup_clkdm",
1870         .mpu_irqs       = omap44xx_gpio1_irqs,
1871         .main_clk       = "gpio1_ick",
1872         .prcm = {
1873                 .omap4 = {
1874                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1875                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1876                         .modulemode   = MODULEMODE_HWCTRL,
1877                 },
1878         },
1879         .opt_clks       = gpio1_opt_clks,
1880         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1881         .dev_attr       = &gpio_dev_attr,
1882         .slaves         = omap44xx_gpio1_slaves,
1883         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1884 };
1885
1886 /* gpio2 */
1887 static struct omap_hwmod omap44xx_gpio2_hwmod;
1888 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1889         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1890         { .irq = -1 }
1891 };
1892
1893 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1894         {
1895                 .pa_start       = 0x48055000,
1896                 .pa_end         = 0x480551ff,
1897                 .flags          = ADDR_TYPE_RT
1898         },
1899         { }
1900 };
1901
1902 /* l4_per -> gpio2 */
1903 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1904         .master         = &omap44xx_l4_per_hwmod,
1905         .slave          = &omap44xx_gpio2_hwmod,
1906         .clk            = "l4_div_ck",
1907         .addr           = omap44xx_gpio2_addrs,
1908         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1909 };
1910
1911 /* gpio2 slave ports */
1912 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1913         &omap44xx_l4_per__gpio2,
1914 };
1915
1916 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1917         { .role = "dbclk", .clk = "gpio2_dbclk" },
1918 };
1919
1920 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1921         .name           = "gpio2",
1922         .class          = &omap44xx_gpio_hwmod_class,
1923         .clkdm_name     = "l4_per_clkdm",
1924         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1925         .mpu_irqs       = omap44xx_gpio2_irqs,
1926         .main_clk       = "gpio2_ick",
1927         .prcm = {
1928                 .omap4 = {
1929                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1930                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1931                         .modulemode   = MODULEMODE_HWCTRL,
1932                 },
1933         },
1934         .opt_clks       = gpio2_opt_clks,
1935         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1936         .dev_attr       = &gpio_dev_attr,
1937         .slaves         = omap44xx_gpio2_slaves,
1938         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1939 };
1940
1941 /* gpio3 */
1942 static struct omap_hwmod omap44xx_gpio3_hwmod;
1943 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1944         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1945         { .irq = -1 }
1946 };
1947
1948 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1949         {
1950                 .pa_start       = 0x48057000,
1951                 .pa_end         = 0x480571ff,
1952                 .flags          = ADDR_TYPE_RT
1953         },
1954         { }
1955 };
1956
1957 /* l4_per -> gpio3 */
1958 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1959         .master         = &omap44xx_l4_per_hwmod,
1960         .slave          = &omap44xx_gpio3_hwmod,
1961         .clk            = "l4_div_ck",
1962         .addr           = omap44xx_gpio3_addrs,
1963         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1964 };
1965
1966 /* gpio3 slave ports */
1967 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1968         &omap44xx_l4_per__gpio3,
1969 };
1970
1971 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1972         { .role = "dbclk", .clk = "gpio3_dbclk" },
1973 };
1974
1975 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1976         .name           = "gpio3",
1977         .class          = &omap44xx_gpio_hwmod_class,
1978         .clkdm_name     = "l4_per_clkdm",
1979         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1980         .mpu_irqs       = omap44xx_gpio3_irqs,
1981         .main_clk       = "gpio3_ick",
1982         .prcm = {
1983                 .omap4 = {
1984                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1985                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1986                         .modulemode   = MODULEMODE_HWCTRL,
1987                 },
1988         },
1989         .opt_clks       = gpio3_opt_clks,
1990         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1991         .dev_attr       = &gpio_dev_attr,
1992         .slaves         = omap44xx_gpio3_slaves,
1993         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1994 };
1995
1996 /* gpio4 */
1997 static struct omap_hwmod omap44xx_gpio4_hwmod;
1998 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1999         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2000         { .irq = -1 }
2001 };
2002
2003 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2004         {
2005                 .pa_start       = 0x48059000,
2006                 .pa_end         = 0x480591ff,
2007                 .flags          = ADDR_TYPE_RT
2008         },
2009         { }
2010 };
2011
2012 /* l4_per -> gpio4 */
2013 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2014         .master         = &omap44xx_l4_per_hwmod,
2015         .slave          = &omap44xx_gpio4_hwmod,
2016         .clk            = "l4_div_ck",
2017         .addr           = omap44xx_gpio4_addrs,
2018         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2019 };
2020
2021 /* gpio4 slave ports */
2022 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2023         &omap44xx_l4_per__gpio4,
2024 };
2025
2026 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2027         { .role = "dbclk", .clk = "gpio4_dbclk" },
2028 };
2029
2030 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2031         .name           = "gpio4",
2032         .class          = &omap44xx_gpio_hwmod_class,
2033         .clkdm_name     = "l4_per_clkdm",
2034         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2035         .mpu_irqs       = omap44xx_gpio4_irqs,
2036         .main_clk       = "gpio4_ick",
2037         .prcm = {
2038                 .omap4 = {
2039                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2040                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2041                         .modulemode   = MODULEMODE_HWCTRL,
2042                 },
2043         },
2044         .opt_clks       = gpio4_opt_clks,
2045         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2046         .dev_attr       = &gpio_dev_attr,
2047         .slaves         = omap44xx_gpio4_slaves,
2048         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2049 };
2050
2051 /* gpio5 */
2052 static struct omap_hwmod omap44xx_gpio5_hwmod;
2053 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2054         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2055         { .irq = -1 }
2056 };
2057
2058 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2059         {
2060                 .pa_start       = 0x4805b000,
2061                 .pa_end         = 0x4805b1ff,
2062                 .flags          = ADDR_TYPE_RT
2063         },
2064         { }
2065 };
2066
2067 /* l4_per -> gpio5 */
2068 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2069         .master         = &omap44xx_l4_per_hwmod,
2070         .slave          = &omap44xx_gpio5_hwmod,
2071         .clk            = "l4_div_ck",
2072         .addr           = omap44xx_gpio5_addrs,
2073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2074 };
2075
2076 /* gpio5 slave ports */
2077 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2078         &omap44xx_l4_per__gpio5,
2079 };
2080
2081 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2082         { .role = "dbclk", .clk = "gpio5_dbclk" },
2083 };
2084
2085 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2086         .name           = "gpio5",
2087         .class          = &omap44xx_gpio_hwmod_class,
2088         .clkdm_name     = "l4_per_clkdm",
2089         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2090         .mpu_irqs       = omap44xx_gpio5_irqs,
2091         .main_clk       = "gpio5_ick",
2092         .prcm = {
2093                 .omap4 = {
2094                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2095                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2096                         .modulemode   = MODULEMODE_HWCTRL,
2097                 },
2098         },
2099         .opt_clks       = gpio5_opt_clks,
2100         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2101         .dev_attr       = &gpio_dev_attr,
2102         .slaves         = omap44xx_gpio5_slaves,
2103         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2104 };
2105
2106 /* gpio6 */
2107 static struct omap_hwmod omap44xx_gpio6_hwmod;
2108 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2109         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2110         { .irq = -1 }
2111 };
2112
2113 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2114         {
2115                 .pa_start       = 0x4805d000,
2116                 .pa_end         = 0x4805d1ff,
2117                 .flags          = ADDR_TYPE_RT
2118         },
2119         { }
2120 };
2121
2122 /* l4_per -> gpio6 */
2123 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2124         .master         = &omap44xx_l4_per_hwmod,
2125         .slave          = &omap44xx_gpio6_hwmod,
2126         .clk            = "l4_div_ck",
2127         .addr           = omap44xx_gpio6_addrs,
2128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2129 };
2130
2131 /* gpio6 slave ports */
2132 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2133         &omap44xx_l4_per__gpio6,
2134 };
2135
2136 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2137         { .role = "dbclk", .clk = "gpio6_dbclk" },
2138 };
2139
2140 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2141         .name           = "gpio6",
2142         .class          = &omap44xx_gpio_hwmod_class,
2143         .clkdm_name     = "l4_per_clkdm",
2144         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2145         .mpu_irqs       = omap44xx_gpio6_irqs,
2146         .main_clk       = "gpio6_ick",
2147         .prcm = {
2148                 .omap4 = {
2149                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2150                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2151                         .modulemode   = MODULEMODE_HWCTRL,
2152                 },
2153         },
2154         .opt_clks       = gpio6_opt_clks,
2155         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2156         .dev_attr       = &gpio_dev_attr,
2157         .slaves         = omap44xx_gpio6_slaves,
2158         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2159 };
2160
2161 /*
2162  * 'hsi' class
2163  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2164  * serial if)
2165  */
2166
2167 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2168         .rev_offs       = 0x0000,
2169         .sysc_offs      = 0x0010,
2170         .syss_offs      = 0x0014,
2171         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2172                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2173                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2174         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2175                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2176                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2177         .sysc_fields    = &omap_hwmod_sysc_type1,
2178 };
2179
2180 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2181         .name   = "hsi",
2182         .sysc   = &omap44xx_hsi_sysc,
2183 };
2184
2185 /* hsi */
2186 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2187         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2188         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2189         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2190         { .irq = -1 }
2191 };
2192
2193 /* hsi master ports */
2194 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2195         &omap44xx_hsi__l3_main_2,
2196 };
2197
2198 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2199         {
2200                 .pa_start       = 0x4a058000,
2201                 .pa_end         = 0x4a05bfff,
2202                 .flags          = ADDR_TYPE_RT
2203         },
2204         { }
2205 };
2206
2207 /* l4_cfg -> hsi */
2208 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2209         .master         = &omap44xx_l4_cfg_hwmod,
2210         .slave          = &omap44xx_hsi_hwmod,
2211         .clk            = "l4_div_ck",
2212         .addr           = omap44xx_hsi_addrs,
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* hsi slave ports */
2217 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2218         &omap44xx_l4_cfg__hsi,
2219 };
2220
2221 static struct omap_hwmod omap44xx_hsi_hwmod = {
2222         .name           = "hsi",
2223         .class          = &omap44xx_hsi_hwmod_class,
2224         .clkdm_name     = "l3_init_clkdm",
2225         .mpu_irqs       = omap44xx_hsi_irqs,
2226         .main_clk       = "hsi_fck",
2227         .prcm = {
2228                 .omap4 = {
2229                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2230                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2231                         .modulemode   = MODULEMODE_HWCTRL,
2232                 },
2233         },
2234         .slaves         = omap44xx_hsi_slaves,
2235         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2236         .masters        = omap44xx_hsi_masters,
2237         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2238 };
2239
2240 /*
2241  * 'i2c' class
2242  * multimaster high-speed i2c controller
2243  */
2244
2245 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2246         .sysc_offs      = 0x0010,
2247         .syss_offs      = 0x0090,
2248         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2249                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2250                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2251         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2252                            SIDLE_SMART_WKUP),
2253         .clockact       = CLOCKACT_TEST_ICLK,
2254         .sysc_fields    = &omap_hwmod_sysc_type1,
2255 };
2256
2257 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2258         .name   = "i2c",
2259         .sysc   = &omap44xx_i2c_sysc,
2260         .rev    = OMAP_I2C_IP_VERSION_2,
2261         .reset  = &omap_i2c_reset,
2262 };
2263
2264 static struct omap_i2c_dev_attr i2c_dev_attr = {
2265         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2266 };
2267
2268 /* i2c1 */
2269 static struct omap_hwmod omap44xx_i2c1_hwmod;
2270 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2271         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2272         { .irq = -1 }
2273 };
2274
2275 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2276         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2277         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2278         { .dma_req = -1 }
2279 };
2280
2281 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2282         {
2283                 .pa_start       = 0x48070000,
2284                 .pa_end         = 0x480700ff,
2285                 .flags          = ADDR_TYPE_RT
2286         },
2287         { }
2288 };
2289
2290 /* l4_per -> i2c1 */
2291 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2292         .master         = &omap44xx_l4_per_hwmod,
2293         .slave          = &omap44xx_i2c1_hwmod,
2294         .clk            = "l4_div_ck",
2295         .addr           = omap44xx_i2c1_addrs,
2296         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2297 };
2298
2299 /* i2c1 slave ports */
2300 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2301         &omap44xx_l4_per__i2c1,
2302 };
2303
2304 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2305         .name           = "i2c1",
2306         .class          = &omap44xx_i2c_hwmod_class,
2307         .clkdm_name     = "l4_per_clkdm",
2308         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2309         .mpu_irqs       = omap44xx_i2c1_irqs,
2310         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2311         .main_clk       = "i2c1_fck",
2312         .prcm = {
2313                 .omap4 = {
2314                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2315                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2316                         .modulemode   = MODULEMODE_SWCTRL,
2317                 },
2318         },
2319         .slaves         = omap44xx_i2c1_slaves,
2320         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2321         .dev_attr       = &i2c_dev_attr,
2322 };
2323
2324 /* i2c2 */
2325 static struct omap_hwmod omap44xx_i2c2_hwmod;
2326 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2327         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2328         { .irq = -1 }
2329 };
2330
2331 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2332         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2333         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2334         { .dma_req = -1 }
2335 };
2336
2337 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2338         {
2339                 .pa_start       = 0x48072000,
2340                 .pa_end         = 0x480720ff,
2341                 .flags          = ADDR_TYPE_RT
2342         },
2343         { }
2344 };
2345
2346 /* l4_per -> i2c2 */
2347 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2348         .master         = &omap44xx_l4_per_hwmod,
2349         .slave          = &omap44xx_i2c2_hwmod,
2350         .clk            = "l4_div_ck",
2351         .addr           = omap44xx_i2c2_addrs,
2352         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2353 };
2354
2355 /* i2c2 slave ports */
2356 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2357         &omap44xx_l4_per__i2c2,
2358 };
2359
2360 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2361         .name           = "i2c2",
2362         .class          = &omap44xx_i2c_hwmod_class,
2363         .clkdm_name     = "l4_per_clkdm",
2364         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2365         .mpu_irqs       = omap44xx_i2c2_irqs,
2366         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2367         .main_clk       = "i2c2_fck",
2368         .prcm = {
2369                 .omap4 = {
2370                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2371                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2372                         .modulemode   = MODULEMODE_SWCTRL,
2373                 },
2374         },
2375         .slaves         = omap44xx_i2c2_slaves,
2376         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2377         .dev_attr       = &i2c_dev_attr,
2378 };
2379
2380 /* i2c3 */
2381 static struct omap_hwmod omap44xx_i2c3_hwmod;
2382 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2383         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2384         { .irq = -1 }
2385 };
2386
2387 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2388         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2389         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2390         { .dma_req = -1 }
2391 };
2392
2393 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2394         {
2395                 .pa_start       = 0x48060000,
2396                 .pa_end         = 0x480600ff,
2397                 .flags          = ADDR_TYPE_RT
2398         },
2399         { }
2400 };
2401
2402 /* l4_per -> i2c3 */
2403 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2404         .master         = &omap44xx_l4_per_hwmod,
2405         .slave          = &omap44xx_i2c3_hwmod,
2406         .clk            = "l4_div_ck",
2407         .addr           = omap44xx_i2c3_addrs,
2408         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2409 };
2410
2411 /* i2c3 slave ports */
2412 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2413         &omap44xx_l4_per__i2c3,
2414 };
2415
2416 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2417         .name           = "i2c3",
2418         .class          = &omap44xx_i2c_hwmod_class,
2419         .clkdm_name     = "l4_per_clkdm",
2420         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2421         .mpu_irqs       = omap44xx_i2c3_irqs,
2422         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2423         .main_clk       = "i2c3_fck",
2424         .prcm = {
2425                 .omap4 = {
2426                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2427                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2428                         .modulemode   = MODULEMODE_SWCTRL,
2429                 },
2430         },
2431         .slaves         = omap44xx_i2c3_slaves,
2432         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2433         .dev_attr       = &i2c_dev_attr,
2434 };
2435
2436 /* i2c4 */
2437 static struct omap_hwmod omap44xx_i2c4_hwmod;
2438 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2439         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2440         { .irq = -1 }
2441 };
2442
2443 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2444         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2445         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2446         { .dma_req = -1 }
2447 };
2448
2449 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2450         {
2451                 .pa_start       = 0x48350000,
2452                 .pa_end         = 0x483500ff,
2453                 .flags          = ADDR_TYPE_RT
2454         },
2455         { }
2456 };
2457
2458 /* l4_per -> i2c4 */
2459 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2460         .master         = &omap44xx_l4_per_hwmod,
2461         .slave          = &omap44xx_i2c4_hwmod,
2462         .clk            = "l4_div_ck",
2463         .addr           = omap44xx_i2c4_addrs,
2464         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2465 };
2466
2467 /* i2c4 slave ports */
2468 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2469         &omap44xx_l4_per__i2c4,
2470 };
2471
2472 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2473         .name           = "i2c4",
2474         .class          = &omap44xx_i2c_hwmod_class,
2475         .clkdm_name     = "l4_per_clkdm",
2476         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2477         .mpu_irqs       = omap44xx_i2c4_irqs,
2478         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2479         .main_clk       = "i2c4_fck",
2480         .prcm = {
2481                 .omap4 = {
2482                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2483                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2484                         .modulemode   = MODULEMODE_SWCTRL,
2485                 },
2486         },
2487         .slaves         = omap44xx_i2c4_slaves,
2488         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2489         .dev_attr       = &i2c_dev_attr,
2490 };
2491
2492 /*
2493  * 'ipu' class
2494  * imaging processor unit
2495  */
2496
2497 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2498         .name   = "ipu",
2499 };
2500
2501 /* ipu */
2502 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2503         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2504         { .irq = -1 }
2505 };
2506
2507 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2508         { .name = "cpu0", .rst_shift = 0 },
2509 };
2510
2511 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2512         { .name = "cpu1", .rst_shift = 1 },
2513 };
2514
2515 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2516         { .name = "mmu_cache", .rst_shift = 2 },
2517 };
2518
2519 /* ipu master ports */
2520 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2521         &omap44xx_ipu__l3_main_2,
2522 };
2523
2524 /* l3_main_2 -> ipu */
2525 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2526         .master         = &omap44xx_l3_main_2_hwmod,
2527         .slave          = &omap44xx_ipu_hwmod,
2528         .clk            = "l3_div_ck",
2529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2530 };
2531
2532 /* ipu slave ports */
2533 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2534         &omap44xx_l3_main_2__ipu,
2535 };
2536
2537 /* Pseudo hwmod for reset control purpose only */
2538 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2539         .name           = "ipu_c0",
2540         .class          = &omap44xx_ipu_hwmod_class,
2541         .clkdm_name     = "ducati_clkdm",
2542         .flags          = HWMOD_INIT_NO_RESET,
2543         .rst_lines      = omap44xx_ipu_c0_resets,
2544         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2545         .prcm = {
2546                 .omap4 = {
2547                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548                 },
2549         },
2550 };
2551
2552 /* Pseudo hwmod for reset control purpose only */
2553 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2554         .name           = "ipu_c1",
2555         .class          = &omap44xx_ipu_hwmod_class,
2556         .clkdm_name     = "ducati_clkdm",
2557         .flags          = HWMOD_INIT_NO_RESET,
2558         .rst_lines      = omap44xx_ipu_c1_resets,
2559         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2560         .prcm = {
2561                 .omap4 = {
2562                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563                 },
2564         },
2565 };
2566
2567 static struct omap_hwmod omap44xx_ipu_hwmod = {
2568         .name           = "ipu",
2569         .class          = &omap44xx_ipu_hwmod_class,
2570         .clkdm_name     = "ducati_clkdm",
2571         .mpu_irqs       = omap44xx_ipu_irqs,
2572         .rst_lines      = omap44xx_ipu_resets,
2573         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2574         .main_clk       = "ipu_fck",
2575         .prcm = {
2576                 .omap4 = {
2577                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2578                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2579                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2580                         .modulemode   = MODULEMODE_HWCTRL,
2581                 },
2582         },
2583         .slaves         = omap44xx_ipu_slaves,
2584         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2585         .masters        = omap44xx_ipu_masters,
2586         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2587 };
2588
2589 /*
2590  * 'iss' class
2591  * external images sensor pixel data processor
2592  */
2593
2594 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2595         .rev_offs       = 0x0000,
2596         .sysc_offs      = 0x0010,
2597         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2598                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2599         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2600                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2601                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2602         .sysc_fields    = &omap_hwmod_sysc_type2,
2603 };
2604
2605 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2606         .name   = "iss",
2607         .sysc   = &omap44xx_iss_sysc,
2608 };
2609
2610 /* iss */
2611 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2612         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2613         { .irq = -1 }
2614 };
2615
2616 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2617         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2618         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2619         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2620         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2621         { .dma_req = -1 }
2622 };
2623
2624 /* iss master ports */
2625 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2626         &omap44xx_iss__l3_main_2,
2627 };
2628
2629 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2630         {
2631                 .pa_start       = 0x52000000,
2632                 .pa_end         = 0x520000ff,
2633                 .flags          = ADDR_TYPE_RT
2634         },
2635         { }
2636 };
2637
2638 /* l3_main_2 -> iss */
2639 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2640         .master         = &omap44xx_l3_main_2_hwmod,
2641         .slave          = &omap44xx_iss_hwmod,
2642         .clk            = "l3_div_ck",
2643         .addr           = omap44xx_iss_addrs,
2644         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2645 };
2646
2647 /* iss slave ports */
2648 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2649         &omap44xx_l3_main_2__iss,
2650 };
2651
2652 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2653         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2654 };
2655
2656 static struct omap_hwmod omap44xx_iss_hwmod = {
2657         .name           = "iss",
2658         .class          = &omap44xx_iss_hwmod_class,
2659         .clkdm_name     = "iss_clkdm",
2660         .mpu_irqs       = omap44xx_iss_irqs,
2661         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2662         .main_clk       = "iss_fck",
2663         .prcm = {
2664                 .omap4 = {
2665                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2666                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2667                         .modulemode   = MODULEMODE_SWCTRL,
2668                 },
2669         },
2670         .opt_clks       = iss_opt_clks,
2671         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2672         .slaves         = omap44xx_iss_slaves,
2673         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2674         .masters        = omap44xx_iss_masters,
2675         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2676 };
2677
2678 /*
2679  * 'iva' class
2680  * multi-standard video encoder/decoder hardware accelerator
2681  */
2682
2683 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2684         .name   = "iva",
2685 };
2686
2687 /* iva */
2688 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2689         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2690         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2691         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2692         { .irq = -1 }
2693 };
2694
2695 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2696         { .name = "logic", .rst_shift = 2 },
2697 };
2698
2699 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2700         { .name = "seq0", .rst_shift = 0 },
2701 };
2702
2703 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2704         { .name = "seq1", .rst_shift = 1 },
2705 };
2706
2707 /* iva master ports */
2708 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2709         &omap44xx_iva__l3_main_2,
2710         &omap44xx_iva__l3_instr,
2711 };
2712
2713 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2714         {
2715                 .pa_start       = 0x5a000000,
2716                 .pa_end         = 0x5a07ffff,
2717                 .flags          = ADDR_TYPE_RT
2718         },
2719         { }
2720 };
2721
2722 /* l3_main_2 -> iva */
2723 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2724         .master         = &omap44xx_l3_main_2_hwmod,
2725         .slave          = &omap44xx_iva_hwmod,
2726         .clk            = "l3_div_ck",
2727         .addr           = omap44xx_iva_addrs,
2728         .user           = OCP_USER_MPU,
2729 };
2730
2731 /* iva slave ports */
2732 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2733         &omap44xx_dsp__iva,
2734         &omap44xx_l3_main_2__iva,
2735 };
2736
2737 /* Pseudo hwmod for reset control purpose only */
2738 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2739         .name           = "iva_seq0",
2740         .class          = &omap44xx_iva_hwmod_class,
2741         .clkdm_name     = "ivahd_clkdm",
2742         .flags          = HWMOD_INIT_NO_RESET,
2743         .rst_lines      = omap44xx_iva_seq0_resets,
2744         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2745         .prcm = {
2746                 .omap4 = {
2747                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2748                 },
2749         },
2750 };
2751
2752 /* Pseudo hwmod for reset control purpose only */
2753 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2754         .name           = "iva_seq1",
2755         .class          = &omap44xx_iva_hwmod_class,
2756         .clkdm_name     = "ivahd_clkdm",
2757         .flags          = HWMOD_INIT_NO_RESET,
2758         .rst_lines      = omap44xx_iva_seq1_resets,
2759         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2760         .prcm = {
2761                 .omap4 = {
2762                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2763                 },
2764         },
2765 };
2766
2767 static struct omap_hwmod omap44xx_iva_hwmod = {
2768         .name           = "iva",
2769         .class          = &omap44xx_iva_hwmod_class,
2770         .clkdm_name     = "ivahd_clkdm",
2771         .mpu_irqs       = omap44xx_iva_irqs,
2772         .rst_lines      = omap44xx_iva_resets,
2773         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2774         .main_clk       = "iva_fck",
2775         .prcm = {
2776                 .omap4 = {
2777                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2778                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2779                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2780                         .modulemode   = MODULEMODE_HWCTRL,
2781                 },
2782         },
2783         .slaves         = omap44xx_iva_slaves,
2784         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2785         .masters        = omap44xx_iva_masters,
2786         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2787 };
2788
2789 /*
2790  * 'kbd' class
2791  * keyboard controller
2792  */
2793
2794 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2795         .rev_offs       = 0x0000,
2796         .sysc_offs      = 0x0010,
2797         .syss_offs      = 0x0014,
2798         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2799                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2800                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2801                            SYSS_HAS_RESET_STATUS),
2802         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2803         .sysc_fields    = &omap_hwmod_sysc_type1,
2804 };
2805
2806 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2807         .name   = "kbd",
2808         .sysc   = &omap44xx_kbd_sysc,
2809 };
2810
2811 /* kbd */
2812 static struct omap_hwmod omap44xx_kbd_hwmod;
2813 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2814         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2815         { .irq = -1 }
2816 };
2817
2818 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2819         {
2820                 .pa_start       = 0x4a31c000,
2821                 .pa_end         = 0x4a31c07f,
2822                 .flags          = ADDR_TYPE_RT
2823         },
2824         { }
2825 };
2826
2827 /* l4_wkup -> kbd */
2828 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2829         .master         = &omap44xx_l4_wkup_hwmod,
2830         .slave          = &omap44xx_kbd_hwmod,
2831         .clk            = "l4_wkup_clk_mux_ck",
2832         .addr           = omap44xx_kbd_addrs,
2833         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2834 };
2835
2836 /* kbd slave ports */
2837 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2838         &omap44xx_l4_wkup__kbd,
2839 };
2840
2841 static struct omap_hwmod omap44xx_kbd_hwmod = {
2842         .name           = "kbd",
2843         .class          = &omap44xx_kbd_hwmod_class,
2844         .clkdm_name     = "l4_wkup_clkdm",
2845         .mpu_irqs       = omap44xx_kbd_irqs,
2846         .main_clk       = "kbd_fck",
2847         .prcm = {
2848                 .omap4 = {
2849                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2850                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2851                         .modulemode   = MODULEMODE_SWCTRL,
2852                 },
2853         },
2854         .slaves         = omap44xx_kbd_slaves,
2855         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2856 };
2857
2858 /*
2859  * 'mailbox' class
2860  * mailbox module allowing communication between the on-chip processors using a
2861  * queued mailbox-interrupt mechanism.
2862  */
2863
2864 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2865         .rev_offs       = 0x0000,
2866         .sysc_offs      = 0x0010,
2867         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2868                            SYSC_HAS_SOFTRESET),
2869         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2870         .sysc_fields    = &omap_hwmod_sysc_type2,
2871 };
2872
2873 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2874         .name   = "mailbox",
2875         .sysc   = &omap44xx_mailbox_sysc,
2876 };
2877
2878 /* mailbox */
2879 static struct omap_hwmod omap44xx_mailbox_hwmod;
2880 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2881         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2882         { .irq = -1 }
2883 };
2884
2885 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2886         {
2887                 .pa_start       = 0x4a0f4000,
2888                 .pa_end         = 0x4a0f41ff,
2889                 .flags          = ADDR_TYPE_RT
2890         },
2891         { }
2892 };
2893
2894 /* l4_cfg -> mailbox */
2895 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2896         .master         = &omap44xx_l4_cfg_hwmod,
2897         .slave          = &omap44xx_mailbox_hwmod,
2898         .clk            = "l4_div_ck",
2899         .addr           = omap44xx_mailbox_addrs,
2900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2901 };
2902
2903 /* mailbox slave ports */
2904 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2905         &omap44xx_l4_cfg__mailbox,
2906 };
2907
2908 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2909         .name           = "mailbox",
2910         .class          = &omap44xx_mailbox_hwmod_class,
2911         .clkdm_name     = "l4_cfg_clkdm",
2912         .mpu_irqs       = omap44xx_mailbox_irqs,
2913         .prcm = {
2914                 .omap4 = {
2915                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2916                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2917                 },
2918         },
2919         .slaves         = omap44xx_mailbox_slaves,
2920         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2921 };
2922
2923 /*
2924  * 'mcbsp' class
2925  * multi channel buffered serial port controller
2926  */
2927
2928 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2929         .sysc_offs      = 0x008c,
2930         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2931                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2932         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2933         .sysc_fields    = &omap_hwmod_sysc_type1,
2934 };
2935
2936 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2937         .name   = "mcbsp",
2938         .sysc   = &omap44xx_mcbsp_sysc,
2939         .rev    = MCBSP_CONFIG_TYPE4,
2940 };
2941
2942 /* mcbsp1 */
2943 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2944 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2945         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2946         { .irq = -1 }
2947 };
2948
2949 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2950         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2951         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2952         { .dma_req = -1 }
2953 };
2954
2955 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2956         {
2957                 .name           = "mpu",
2958                 .pa_start       = 0x40122000,
2959                 .pa_end         = 0x401220ff,
2960                 .flags          = ADDR_TYPE_RT
2961         },
2962         { }
2963 };
2964
2965 /* l4_abe -> mcbsp1 */
2966 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2967         .master         = &omap44xx_l4_abe_hwmod,
2968         .slave          = &omap44xx_mcbsp1_hwmod,
2969         .clk            = "ocp_abe_iclk",
2970         .addr           = omap44xx_mcbsp1_addrs,
2971         .user           = OCP_USER_MPU,
2972 };
2973
2974 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2975         {
2976                 .name           = "dma",
2977                 .pa_start       = 0x49022000,
2978                 .pa_end         = 0x490220ff,
2979                 .flags          = ADDR_TYPE_RT
2980         },
2981         { }
2982 };
2983
2984 /* l4_abe -> mcbsp1 (dma) */
2985 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2986         .master         = &omap44xx_l4_abe_hwmod,
2987         .slave          = &omap44xx_mcbsp1_hwmod,
2988         .clk            = "ocp_abe_iclk",
2989         .addr           = omap44xx_mcbsp1_dma_addrs,
2990         .user           = OCP_USER_SDMA,
2991 };
2992
2993 /* mcbsp1 slave ports */
2994 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2995         &omap44xx_l4_abe__mcbsp1,
2996         &omap44xx_l4_abe__mcbsp1_dma,
2997 };
2998
2999 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
3000         { .role = "pad_fck", .clk = "pad_clks_ck" },
3001         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
3002 };
3003
3004 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
3005         .name           = "mcbsp1",
3006         .class          = &omap44xx_mcbsp_hwmod_class,
3007         .clkdm_name     = "abe_clkdm",
3008         .mpu_irqs       = omap44xx_mcbsp1_irqs,
3009         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
3010         .main_clk       = "mcbsp1_fck",
3011         .prcm = {
3012                 .omap4 = {
3013                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3014                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3015                         .modulemode   = MODULEMODE_SWCTRL,
3016                 },
3017         },
3018         .slaves         = omap44xx_mcbsp1_slaves,
3019         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3020         .opt_clks       = mcbsp1_opt_clks,
3021         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
3022 };
3023
3024 /* mcbsp2 */
3025 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3026 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3027         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3028         { .irq = -1 }
3029 };
3030
3031 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3032         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3033         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3034         { .dma_req = -1 }
3035 };
3036
3037 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3038         {
3039                 .name           = "mpu",
3040                 .pa_start       = 0x40124000,
3041                 .pa_end         = 0x401240ff,
3042                 .flags          = ADDR_TYPE_RT
3043         },
3044         { }
3045 };
3046
3047 /* l4_abe -> mcbsp2 */
3048 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3049         .master         = &omap44xx_l4_abe_hwmod,
3050         .slave          = &omap44xx_mcbsp2_hwmod,
3051         .clk            = "ocp_abe_iclk",
3052         .addr           = omap44xx_mcbsp2_addrs,
3053         .user           = OCP_USER_MPU,
3054 };
3055
3056 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3057         {
3058                 .name           = "dma",
3059                 .pa_start       = 0x49024000,
3060                 .pa_end         = 0x490240ff,
3061                 .flags          = ADDR_TYPE_RT
3062         },
3063         { }
3064 };
3065
3066 /* l4_abe -> mcbsp2 (dma) */
3067 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3068         .master         = &omap44xx_l4_abe_hwmod,
3069         .slave          = &omap44xx_mcbsp2_hwmod,
3070         .clk            = "ocp_abe_iclk",
3071         .addr           = omap44xx_mcbsp2_dma_addrs,
3072         .user           = OCP_USER_SDMA,
3073 };
3074
3075 /* mcbsp2 slave ports */
3076 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3077         &omap44xx_l4_abe__mcbsp2,
3078         &omap44xx_l4_abe__mcbsp2_dma,
3079 };
3080
3081 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
3082         { .role = "pad_fck", .clk = "pad_clks_ck" },
3083         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
3084 };
3085
3086 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3087         .name           = "mcbsp2",
3088         .class          = &omap44xx_mcbsp_hwmod_class,
3089         .clkdm_name     = "abe_clkdm",
3090         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3091         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3092         .main_clk       = "mcbsp2_fck",
3093         .prcm = {
3094                 .omap4 = {
3095                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3096                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3097                         .modulemode   = MODULEMODE_SWCTRL,
3098                 },
3099         },
3100         .slaves         = omap44xx_mcbsp2_slaves,
3101         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3102         .opt_clks       = mcbsp2_opt_clks,
3103         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
3104 };
3105
3106 /* mcbsp3 */
3107 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3108 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3109         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3110         { .irq = -1 }
3111 };
3112
3113 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3114         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3115         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3116         { .dma_req = -1 }
3117 };
3118
3119 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3120         {
3121                 .name           = "mpu",
3122                 .pa_start       = 0x40126000,
3123                 .pa_end         = 0x401260ff,
3124                 .flags          = ADDR_TYPE_RT
3125         },
3126         { }
3127 };
3128
3129 /* l4_abe -> mcbsp3 */
3130 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3131         .master         = &omap44xx_l4_abe_hwmod,
3132         .slave          = &omap44xx_mcbsp3_hwmod,
3133         .clk            = "ocp_abe_iclk",
3134         .addr           = omap44xx_mcbsp3_addrs,
3135         .user           = OCP_USER_MPU,
3136 };
3137
3138 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3139         {
3140                 .name           = "dma",
3141                 .pa_start       = 0x49026000,
3142                 .pa_end         = 0x490260ff,
3143                 .flags          = ADDR_TYPE_RT
3144         },
3145         { }
3146 };
3147
3148 /* l4_abe -> mcbsp3 (dma) */
3149 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3150         .master         = &omap44xx_l4_abe_hwmod,
3151         .slave          = &omap44xx_mcbsp3_hwmod,
3152         .clk            = "ocp_abe_iclk",
3153         .addr           = omap44xx_mcbsp3_dma_addrs,
3154         .user           = OCP_USER_SDMA,
3155 };
3156
3157 /* mcbsp3 slave ports */
3158 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3159         &omap44xx_l4_abe__mcbsp3,
3160         &omap44xx_l4_abe__mcbsp3_dma,
3161 };
3162
3163 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
3164         { .role = "pad_fck", .clk = "pad_clks_ck" },
3165         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
3166 };
3167
3168 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3169         .name           = "mcbsp3",
3170         .class          = &omap44xx_mcbsp_hwmod_class,
3171         .clkdm_name     = "abe_clkdm",
3172         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3173         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3174         .main_clk       = "mcbsp3_fck",
3175         .prcm = {
3176                 .omap4 = {
3177                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3178                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3179                         .modulemode   = MODULEMODE_SWCTRL,
3180                 },
3181         },
3182         .slaves         = omap44xx_mcbsp3_slaves,
3183         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3184         .opt_clks       = mcbsp3_opt_clks,
3185         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
3186 };
3187
3188 /* mcbsp4 */
3189 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3190 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3191         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3192         { .irq = -1 }
3193 };
3194
3195 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3196         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3197         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3198         { .dma_req = -1 }
3199 };
3200
3201 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3202         {
3203                 .pa_start       = 0x48096000,
3204                 .pa_end         = 0x480960ff,
3205                 .flags          = ADDR_TYPE_RT
3206         },
3207         { }
3208 };
3209
3210 /* l4_per -> mcbsp4 */
3211 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3212         .master         = &omap44xx_l4_per_hwmod,
3213         .slave          = &omap44xx_mcbsp4_hwmod,
3214         .clk            = "l4_div_ck",
3215         .addr           = omap44xx_mcbsp4_addrs,
3216         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3217 };
3218
3219 /* mcbsp4 slave ports */
3220 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3221         &omap44xx_l4_per__mcbsp4,
3222 };
3223
3224 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
3225         { .role = "pad_fck", .clk = "pad_clks_ck" },
3226         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
3227 };
3228
3229 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3230         .name           = "mcbsp4",
3231         .class          = &omap44xx_mcbsp_hwmod_class,
3232         .clkdm_name     = "l4_per_clkdm",
3233         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3234         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3235         .main_clk       = "mcbsp4_fck",
3236         .prcm = {
3237                 .omap4 = {
3238                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3239                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3240                         .modulemode   = MODULEMODE_SWCTRL,
3241                 },
3242         },
3243         .slaves         = omap44xx_mcbsp4_slaves,
3244         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3245         .opt_clks       = mcbsp4_opt_clks,
3246         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
3247 };
3248
3249 /*
3250  * 'mcpdm' class
3251  * multi channel pdm controller (proprietary interface with phoenix power
3252  * ic)
3253  */
3254
3255 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3256         .rev_offs       = 0x0000,
3257         .sysc_offs      = 0x0010,
3258         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3259                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3261                            SIDLE_SMART_WKUP),
3262         .sysc_fields    = &omap_hwmod_sysc_type2,
3263 };
3264
3265 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3266         .name   = "mcpdm",
3267         .sysc   = &omap44xx_mcpdm_sysc,
3268 };
3269
3270 /* mcpdm */
3271 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3272 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3273         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3274         { .irq = -1 }
3275 };
3276
3277 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3278         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3279         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3280         { .dma_req = -1 }
3281 };
3282
3283 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3284         {
3285                 .pa_start       = 0x40132000,
3286                 .pa_end         = 0x4013207f,
3287                 .flags          = ADDR_TYPE_RT
3288         },
3289         { }
3290 };
3291
3292 /* l4_abe -> mcpdm */
3293 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3294         .master         = &omap44xx_l4_abe_hwmod,
3295         .slave          = &omap44xx_mcpdm_hwmod,
3296         .clk            = "ocp_abe_iclk",
3297         .addr           = omap44xx_mcpdm_addrs,
3298         .user           = OCP_USER_MPU,
3299 };
3300
3301 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3302         {
3303                 .pa_start       = 0x49032000,
3304                 .pa_end         = 0x4903207f,
3305                 .flags          = ADDR_TYPE_RT
3306         },
3307         { }
3308 };
3309
3310 /* l4_abe -> mcpdm (dma) */
3311 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3312         .master         = &omap44xx_l4_abe_hwmod,
3313         .slave          = &omap44xx_mcpdm_hwmod,
3314         .clk            = "ocp_abe_iclk",
3315         .addr           = omap44xx_mcpdm_dma_addrs,
3316         .user           = OCP_USER_SDMA,
3317 };
3318
3319 /* mcpdm slave ports */
3320 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3321         &omap44xx_l4_abe__mcpdm,
3322         &omap44xx_l4_abe__mcpdm_dma,
3323 };
3324
3325 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3326         .name           = "mcpdm",
3327         .class          = &omap44xx_mcpdm_hwmod_class,
3328         .clkdm_name     = "abe_clkdm",
3329         .mpu_irqs       = omap44xx_mcpdm_irqs,
3330         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3331         .main_clk       = "mcpdm_fck",
3332         .prcm = {
3333                 .omap4 = {
3334                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3335                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3336                         .modulemode   = MODULEMODE_SWCTRL,
3337                 },
3338         },
3339         .slaves         = omap44xx_mcpdm_slaves,
3340         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3341 };
3342
3343 /*
3344  * 'mcspi' class
3345  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3346  * bus
3347  */
3348
3349 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3350         .rev_offs       = 0x0000,
3351         .sysc_offs      = 0x0010,
3352         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3353                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3354         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3355                            SIDLE_SMART_WKUP),
3356         .sysc_fields    = &omap_hwmod_sysc_type2,
3357 };
3358
3359 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3360         .name   = "mcspi",
3361         .sysc   = &omap44xx_mcspi_sysc,
3362         .rev    = OMAP4_MCSPI_REV,
3363 };
3364
3365 /* mcspi1 */
3366 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3367 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3368         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3369         { .irq = -1 }
3370 };
3371
3372 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3373         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3374         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3375         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3376         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3377         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3378         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3379         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3380         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3381         { .dma_req = -1 }
3382 };
3383
3384 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3385         {
3386                 .pa_start       = 0x48098000,
3387                 .pa_end         = 0x480981ff,
3388                 .flags          = ADDR_TYPE_RT
3389         },
3390         { }
3391 };
3392
3393 /* l4_per -> mcspi1 */
3394 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3395         .master         = &omap44xx_l4_per_hwmod,
3396         .slave          = &omap44xx_mcspi1_hwmod,
3397         .clk            = "l4_div_ck",
3398         .addr           = omap44xx_mcspi1_addrs,
3399         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3401
3402 /* mcspi1 slave ports */
3403 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3404         &omap44xx_l4_per__mcspi1,
3405 };
3406
3407 /* mcspi1 dev_attr */
3408 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3409         .num_chipselect = 4,
3410 };
3411
3412 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3413         .name           = "mcspi1",
3414         .class          = &omap44xx_mcspi_hwmod_class,
3415         .clkdm_name     = "l4_per_clkdm",
3416         .mpu_irqs       = omap44xx_mcspi1_irqs,
3417         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3418         .main_clk       = "mcspi1_fck",
3419         .prcm = {
3420                 .omap4 = {
3421                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3422                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3423                         .modulemode   = MODULEMODE_SWCTRL,
3424                 },
3425         },
3426         .dev_attr       = &mcspi1_dev_attr,
3427         .slaves         = omap44xx_mcspi1_slaves,
3428         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3429 };
3430
3431 /* mcspi2 */
3432 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3433 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3434         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3435         { .irq = -1 }
3436 };
3437
3438 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3439         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3440         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3441         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3442         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3443         { .dma_req = -1 }
3444 };
3445
3446 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3447         {
3448                 .pa_start       = 0x4809a000,
3449                 .pa_end         = 0x4809a1ff,
3450                 .flags          = ADDR_TYPE_RT
3451         },
3452         { }
3453 };
3454
3455 /* l4_per -> mcspi2 */
3456 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3457         .master         = &omap44xx_l4_per_hwmod,
3458         .slave          = &omap44xx_mcspi2_hwmod,
3459         .clk            = "l4_div_ck",
3460         .addr           = omap44xx_mcspi2_addrs,
3461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3462 };
3463
3464 /* mcspi2 slave ports */
3465 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3466         &omap44xx_l4_per__mcspi2,
3467 };
3468
3469 /* mcspi2 dev_attr */
3470 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3471         .num_chipselect = 2,
3472 };
3473
3474 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3475         .name           = "mcspi2",
3476         .class          = &omap44xx_mcspi_hwmod_class,
3477         .clkdm_name     = "l4_per_clkdm",
3478         .mpu_irqs       = omap44xx_mcspi2_irqs,
3479         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3480         .main_clk       = "mcspi2_fck",
3481         .prcm = {
3482                 .omap4 = {
3483                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3484                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3485                         .modulemode   = MODULEMODE_SWCTRL,
3486                 },
3487         },
3488         .dev_attr       = &mcspi2_dev_attr,
3489         .slaves         = omap44xx_mcspi2_slaves,
3490         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3491 };
3492
3493 /* mcspi3 */
3494 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3495 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3496         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3497         { .irq = -1 }
3498 };
3499
3500 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3501         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3502         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3503         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3504         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3505         { .dma_req = -1 }
3506 };
3507
3508 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3509         {
3510                 .pa_start       = 0x480b8000,
3511                 .pa_end         = 0x480b81ff,
3512                 .flags          = ADDR_TYPE_RT
3513         },
3514         { }
3515 };
3516
3517 /* l4_per -> mcspi3 */
3518 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3519         .master         = &omap44xx_l4_per_hwmod,
3520         .slave          = &omap44xx_mcspi3_hwmod,
3521         .clk            = "l4_div_ck",
3522         .addr           = omap44xx_mcspi3_addrs,
3523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3524 };
3525
3526 /* mcspi3 slave ports */
3527 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3528         &omap44xx_l4_per__mcspi3,
3529 };
3530
3531 /* mcspi3 dev_attr */
3532 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3533         .num_chipselect = 2,
3534 };
3535
3536 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3537         .name           = "mcspi3",
3538         .class          = &omap44xx_mcspi_hwmod_class,
3539         .clkdm_name     = "l4_per_clkdm",
3540         .mpu_irqs       = omap44xx_mcspi3_irqs,
3541         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3542         .main_clk       = "mcspi3_fck",
3543         .prcm = {
3544                 .omap4 = {
3545                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3546                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3547                         .modulemode   = MODULEMODE_SWCTRL,
3548                 },
3549         },
3550         .dev_attr       = &mcspi3_dev_attr,
3551         .slaves         = omap44xx_mcspi3_slaves,
3552         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3553 };
3554
3555 /* mcspi4 */
3556 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3557 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3558         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3559         { .irq = -1 }
3560 };
3561
3562 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3563         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3564         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3565         { .dma_req = -1 }
3566 };
3567
3568 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3569         {
3570                 .pa_start       = 0x480ba000,
3571                 .pa_end         = 0x480ba1ff,
3572                 .flags          = ADDR_TYPE_RT
3573         },
3574         { }
3575 };
3576
3577 /* l4_per -> mcspi4 */
3578 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3579         .master         = &omap44xx_l4_per_hwmod,
3580         .slave          = &omap44xx_mcspi4_hwmod,
3581         .clk            = "l4_div_ck",
3582         .addr           = omap44xx_mcspi4_addrs,
3583         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3584 };
3585
3586 /* mcspi4 slave ports */
3587 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3588         &omap44xx_l4_per__mcspi4,
3589 };
3590
3591 /* mcspi4 dev_attr */
3592 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3593         .num_chipselect = 1,
3594 };
3595
3596 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3597         .name           = "mcspi4",
3598         .class          = &omap44xx_mcspi_hwmod_class,
3599         .clkdm_name     = "l4_per_clkdm",
3600         .mpu_irqs       = omap44xx_mcspi4_irqs,
3601         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3602         .main_clk       = "mcspi4_fck",
3603         .prcm = {
3604                 .omap4 = {
3605                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3606                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3607                         .modulemode   = MODULEMODE_SWCTRL,
3608                 },
3609         },
3610         .dev_attr       = &mcspi4_dev_attr,
3611         .slaves         = omap44xx_mcspi4_slaves,
3612         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3613 };
3614
3615 /*
3616  * 'mmc' class
3617  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3618  */
3619
3620 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3621         .rev_offs       = 0x0000,
3622         .sysc_offs      = 0x0010,
3623         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3624                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3625                            SYSC_HAS_SOFTRESET),
3626         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3627                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3628                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3629         .sysc_fields    = &omap_hwmod_sysc_type2,
3630 };
3631
3632 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3633         .name   = "mmc",
3634         .sysc   = &omap44xx_mmc_sysc,
3635 };
3636
3637 /* mmc1 */
3638 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3639         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3640         { .irq = -1 }
3641 };
3642
3643 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3644         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3645         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3646         { .dma_req = -1 }
3647 };
3648
3649 /* mmc1 master ports */
3650 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3651         &omap44xx_mmc1__l3_main_1,
3652 };
3653
3654 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3655         {
3656                 .pa_start       = 0x4809c000,
3657                 .pa_end         = 0x4809c3ff,
3658                 .flags          = ADDR_TYPE_RT
3659         },
3660         { }
3661 };
3662
3663 /* l4_per -> mmc1 */
3664 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3665         .master         = &omap44xx_l4_per_hwmod,
3666         .slave          = &omap44xx_mmc1_hwmod,
3667         .clk            = "l4_div_ck",
3668         .addr           = omap44xx_mmc1_addrs,
3669         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3670 };
3671
3672 /* mmc1 slave ports */
3673 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3674         &omap44xx_l4_per__mmc1,
3675 };
3676
3677 /* mmc1 dev_attr */
3678 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3679         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3680 };
3681
3682 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3683         .name           = "mmc1",
3684         .class          = &omap44xx_mmc_hwmod_class,
3685         .clkdm_name     = "l3_init_clkdm",
3686         .mpu_irqs       = omap44xx_mmc1_irqs,
3687         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3688         .main_clk       = "mmc1_fck",
3689         .prcm = {
3690                 .omap4 = {
3691                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3692                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3693                         .modulemode   = MODULEMODE_SWCTRL,
3694                 },
3695         },
3696         .dev_attr       = &mmc1_dev_attr,
3697         .slaves         = omap44xx_mmc1_slaves,
3698         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3699         .masters        = omap44xx_mmc1_masters,
3700         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3701 };
3702
3703 /* mmc2 */
3704 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3705         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3706         { .irq = -1 }
3707 };
3708
3709 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3710         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3711         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3712         { .dma_req = -1 }
3713 };
3714
3715 /* mmc2 master ports */
3716 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3717         &omap44xx_mmc2__l3_main_1,
3718 };
3719
3720 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3721         {
3722                 .pa_start       = 0x480b4000,
3723                 .pa_end         = 0x480b43ff,
3724                 .flags          = ADDR_TYPE_RT
3725         },
3726         { }
3727 };
3728
3729 /* l4_per -> mmc2 */
3730 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3731         .master         = &omap44xx_l4_per_hwmod,
3732         .slave          = &omap44xx_mmc2_hwmod,
3733         .clk            = "l4_div_ck",
3734         .addr           = omap44xx_mmc2_addrs,
3735         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3736 };
3737
3738 /* mmc2 slave ports */
3739 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3740         &omap44xx_l4_per__mmc2,
3741 };
3742
3743 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3744         .name           = "mmc2",
3745         .class          = &omap44xx_mmc_hwmod_class,
3746         .clkdm_name     = "l3_init_clkdm",
3747         .mpu_irqs       = omap44xx_mmc2_irqs,
3748         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3749         .main_clk       = "mmc2_fck",
3750         .prcm = {
3751                 .omap4 = {
3752                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3753                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3754                         .modulemode   = MODULEMODE_SWCTRL,
3755                 },
3756         },
3757         .slaves         = omap44xx_mmc2_slaves,
3758         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3759         .masters        = omap44xx_mmc2_masters,
3760         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3761 };
3762
3763 /* mmc3 */
3764 static struct omap_hwmod omap44xx_mmc3_hwmod;
3765 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3766         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3767         { .irq = -1 }
3768 };
3769
3770 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3771         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3772         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3773         { .dma_req = -1 }
3774 };
3775
3776 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3777         {
3778                 .pa_start       = 0x480ad000,
3779                 .pa_end         = 0x480ad3ff,
3780                 .flags          = ADDR_TYPE_RT
3781         },
3782         { }
3783 };
3784
3785 /* l4_per -> mmc3 */
3786 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3787         .master         = &omap44xx_l4_per_hwmod,
3788         .slave          = &omap44xx_mmc3_hwmod,
3789         .clk            = "l4_div_ck",
3790         .addr           = omap44xx_mmc3_addrs,
3791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3792 };
3793
3794 /* mmc3 slave ports */
3795 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3796         &omap44xx_l4_per__mmc3,
3797 };
3798
3799 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3800         .name           = "mmc3",
3801         .class          = &omap44xx_mmc_hwmod_class,
3802         .clkdm_name     = "l4_per_clkdm",
3803         .mpu_irqs       = omap44xx_mmc3_irqs,
3804         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3805         .main_clk       = "mmc3_fck",
3806         .prcm = {
3807                 .omap4 = {
3808                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3809                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3810                         .modulemode   = MODULEMODE_SWCTRL,
3811                 },
3812         },
3813         .slaves         = omap44xx_mmc3_slaves,
3814         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3815 };
3816
3817 /* mmc4 */
3818 static struct omap_hwmod omap44xx_mmc4_hwmod;
3819 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3820         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3821         { .irq = -1 }
3822 };
3823
3824 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3825         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3826         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3827         { .dma_req = -1 }
3828 };
3829
3830 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3831         {
3832                 .pa_start       = 0x480d1000,
3833                 .pa_end         = 0x480d13ff,
3834                 .flags          = ADDR_TYPE_RT
3835         },
3836         { }
3837 };
3838
3839 /* l4_per -> mmc4 */
3840 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3841         .master         = &omap44xx_l4_per_hwmod,
3842         .slave          = &omap44xx_mmc4_hwmod,
3843         .clk            = "l4_div_ck",
3844         .addr           = omap44xx_mmc4_addrs,
3845         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3846 };
3847
3848 /* mmc4 slave ports */
3849 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3850         &omap44xx_l4_per__mmc4,
3851 };
3852
3853 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3854         .name           = "mmc4",
3855         .class          = &omap44xx_mmc_hwmod_class,
3856         .clkdm_name     = "l4_per_clkdm",
3857         .mpu_irqs       = omap44xx_mmc4_irqs,
3858
3859         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3860         .main_clk       = "mmc4_fck",
3861         .prcm = {
3862                 .omap4 = {
3863                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3864                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3865                         .modulemode   = MODULEMODE_SWCTRL,
3866                 },
3867         },
3868         .slaves         = omap44xx_mmc4_slaves,
3869         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3870 };
3871
3872 /* mmc5 */
3873 static struct omap_hwmod omap44xx_mmc5_hwmod;
3874 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3875         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3876         { .irq = -1 }
3877 };
3878
3879 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3880         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3881         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3882         { .dma_req = -1 }
3883 };
3884
3885 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3886         {
3887                 .pa_start       = 0x480d5000,
3888                 .pa_end         = 0x480d53ff,
3889                 .flags          = ADDR_TYPE_RT
3890         },
3891         { }
3892 };
3893
3894 /* l4_per -> mmc5 */
3895 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3896         .master         = &omap44xx_l4_per_hwmod,
3897         .slave          = &omap44xx_mmc5_hwmod,
3898         .clk            = "l4_div_ck",
3899         .addr           = omap44xx_mmc5_addrs,
3900         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3901 };
3902
3903 /* mmc5 slave ports */
3904 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3905         &omap44xx_l4_per__mmc5,
3906 };
3907
3908 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3909         .name           = "mmc5",
3910         .class          = &omap44xx_mmc_hwmod_class,
3911         .clkdm_name     = "l4_per_clkdm",
3912         .mpu_irqs       = omap44xx_mmc5_irqs,
3913         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3914         .main_clk       = "mmc5_fck",
3915         .prcm = {
3916                 .omap4 = {
3917                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3918                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3919                         .modulemode   = MODULEMODE_SWCTRL,
3920                 },
3921         },
3922         .slaves         = omap44xx_mmc5_slaves,
3923         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3924 };
3925
3926 /*
3927  * 'mpu' class
3928  * mpu sub-system
3929  */
3930
3931 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3932         .name   = "mpu",
3933 };
3934
3935 /* mpu */
3936 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3937         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3938         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3939         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3940         { .irq = -1 }
3941 };
3942
3943 /* mpu master ports */
3944 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3945         &omap44xx_mpu__l3_main_1,
3946         &omap44xx_mpu__l4_abe,
3947         &omap44xx_mpu__dmm,
3948 };
3949
3950 static struct omap_hwmod omap44xx_mpu_hwmod = {
3951         .name           = "mpu",
3952         .class          = &omap44xx_mpu_hwmod_class,
3953         .clkdm_name     = "mpuss_clkdm",
3954         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3955         .mpu_irqs       = omap44xx_mpu_irqs,
3956         .main_clk       = "dpll_mpu_m2_ck",
3957         .prcm = {
3958                 .omap4 = {
3959                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3960                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3961                 },
3962         },
3963         .masters        = omap44xx_mpu_masters,
3964         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3965 };
3966
3967 /*
3968  * 'smartreflex' class
3969  * smartreflex module (monitor silicon performance and outputs a measure of
3970  * performance error)
3971  */
3972
3973 /* The IP is not compliant to type1 / type2 scheme */
3974 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3975         .sidle_shift    = 24,
3976         .enwkup_shift   = 26,
3977 };
3978
3979 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3980         .sysc_offs      = 0x0038,
3981         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3983                            SIDLE_SMART_WKUP),
3984         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3985 };
3986
3987 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3988         .name   = "smartreflex",
3989         .sysc   = &omap44xx_smartreflex_sysc,
3990         .rev    = 2,
3991 };
3992
3993 /* smartreflex_core */
3994 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
3995         .sensor_voltdm_name   = "core",
3996 };
3997
3998 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3999 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
4000         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
4001         { .irq = -1 }
4002 };
4003
4004 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4005         {
4006                 .pa_start       = 0x4a0dd000,
4007                 .pa_end         = 0x4a0dd03f,
4008                 .flags          = ADDR_TYPE_RT
4009         },
4010         { }
4011 };
4012
4013 /* l4_cfg -> smartreflex_core */
4014 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4015         .master         = &omap44xx_l4_cfg_hwmod,
4016         .slave          = &omap44xx_smartreflex_core_hwmod,
4017         .clk            = "l4_div_ck",
4018         .addr           = omap44xx_smartreflex_core_addrs,
4019         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4020 };
4021
4022 /* smartreflex_core slave ports */
4023 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
4024         &omap44xx_l4_cfg__smartreflex_core,
4025 };
4026
4027 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
4028         .name           = "smartreflex_core",
4029         .class          = &omap44xx_smartreflex_hwmod_class,
4030         .clkdm_name     = "l4_ao_clkdm",
4031         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
4032
4033         .main_clk       = "smartreflex_core_fck",
4034         .prcm = {
4035                 .omap4 = {
4036                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4037                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4038                         .modulemode   = MODULEMODE_SWCTRL,
4039                 },
4040         },
4041         .slaves         = omap44xx_smartreflex_core_slaves,
4042         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4043         .dev_attr       = &smartreflex_core_dev_attr,
4044 };
4045
4046 /* smartreflex_iva */
4047 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
4048         .sensor_voltdm_name     = "iva",
4049 };
4050
4051 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4052 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4053         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4054         { .irq = -1 }
4055 };
4056
4057 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4058         {
4059                 .pa_start       = 0x4a0db000,
4060                 .pa_end         = 0x4a0db03f,
4061                 .flags          = ADDR_TYPE_RT
4062         },
4063         { }
4064 };
4065
4066 /* l4_cfg -> smartreflex_iva */
4067 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4068         .master         = &omap44xx_l4_cfg_hwmod,
4069         .slave          = &omap44xx_smartreflex_iva_hwmod,
4070         .clk            = "l4_div_ck",
4071         .addr           = omap44xx_smartreflex_iva_addrs,
4072         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4073 };
4074
4075 /* smartreflex_iva slave ports */
4076 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4077         &omap44xx_l4_cfg__smartreflex_iva,
4078 };
4079
4080 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4081         .name           = "smartreflex_iva",
4082         .class          = &omap44xx_smartreflex_hwmod_class,
4083         .clkdm_name     = "l4_ao_clkdm",
4084         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4085         .main_clk       = "smartreflex_iva_fck",
4086         .prcm = {
4087                 .omap4 = {
4088                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4089                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4090                         .modulemode   = MODULEMODE_SWCTRL,
4091                 },
4092         },
4093         .slaves         = omap44xx_smartreflex_iva_slaves,
4094         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4095         .dev_attr       = &smartreflex_iva_dev_attr,
4096 };
4097
4098 /* smartreflex_mpu */
4099 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4100         .sensor_voltdm_name     = "mpu",
4101 };
4102
4103 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4104 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4105         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4106         { .irq = -1 }
4107 };
4108
4109 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4110         {
4111                 .pa_start       = 0x4a0d9000,
4112                 .pa_end         = 0x4a0d903f,
4113                 .flags          = ADDR_TYPE_RT
4114         },
4115         { }
4116 };
4117
4118 /* l4_cfg -> smartreflex_mpu */
4119 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4120         .master         = &omap44xx_l4_cfg_hwmod,
4121         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4122         .clk            = "l4_div_ck",
4123         .addr           = omap44xx_smartreflex_mpu_addrs,
4124         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4125 };
4126
4127 /* smartreflex_mpu slave ports */
4128 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4129         &omap44xx_l4_cfg__smartreflex_mpu,
4130 };
4131
4132 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4133         .name           = "smartreflex_mpu",
4134         .class          = &omap44xx_smartreflex_hwmod_class,
4135         .clkdm_name     = "l4_ao_clkdm",
4136         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4137         .main_clk       = "smartreflex_mpu_fck",
4138         .prcm = {
4139                 .omap4 = {
4140                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4141                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4142                         .modulemode   = MODULEMODE_SWCTRL,
4143                 },
4144         },
4145         .slaves         = omap44xx_smartreflex_mpu_slaves,
4146         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4147         .dev_attr       = &smartreflex_mpu_dev_attr,
4148 };
4149
4150 /*
4151  * 'spinlock' class
4152  * spinlock provides hardware assistance for synchronizing the processes
4153  * running on multiple processors
4154  */
4155
4156 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4157         .rev_offs       = 0x0000,
4158         .sysc_offs      = 0x0010,
4159         .syss_offs      = 0x0014,
4160         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4161                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4162                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4163         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4164                            SIDLE_SMART_WKUP),
4165         .sysc_fields    = &omap_hwmod_sysc_type1,
4166 };
4167
4168 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4169         .name   = "spinlock",
4170         .sysc   = &omap44xx_spinlock_sysc,
4171 };
4172
4173 /* spinlock */
4174 static struct omap_hwmod omap44xx_spinlock_hwmod;
4175 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4176         {
4177                 .pa_start       = 0x4a0f6000,
4178                 .pa_end         = 0x4a0f6fff,
4179                 .flags          = ADDR_TYPE_RT
4180         },
4181         { }
4182 };
4183
4184 /* l4_cfg -> spinlock */
4185 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4186         .master         = &omap44xx_l4_cfg_hwmod,
4187         .slave          = &omap44xx_spinlock_hwmod,
4188         .clk            = "l4_div_ck",
4189         .addr           = omap44xx_spinlock_addrs,
4190         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4191 };
4192
4193 /* spinlock slave ports */
4194 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4195         &omap44xx_l4_cfg__spinlock,
4196 };
4197
4198 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4199         .name           = "spinlock",
4200         .class          = &omap44xx_spinlock_hwmod_class,
4201         .clkdm_name     = "l4_cfg_clkdm",
4202         .prcm = {
4203                 .omap4 = {
4204                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4205                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4206                 },
4207         },
4208         .slaves         = omap44xx_spinlock_slaves,
4209         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4210 };
4211
4212 /*
4213  * 'timer' class
4214  * general purpose timer module with accurate 1ms tick
4215  * This class contains several variants: ['timer_1ms', 'timer']
4216  */
4217
4218 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4219         .rev_offs       = 0x0000,
4220         .sysc_offs      = 0x0010,
4221         .syss_offs      = 0x0014,
4222         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4223                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4224                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4225                            SYSS_HAS_RESET_STATUS),
4226         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4227         .sysc_fields    = &omap_hwmod_sysc_type1,
4228 };
4229
4230 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4231         .name   = "timer",
4232         .sysc   = &omap44xx_timer_1ms_sysc,
4233 };
4234
4235 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4236         .rev_offs       = 0x0000,
4237         .sysc_offs      = 0x0010,
4238         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4239                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4240         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4241                            SIDLE_SMART_WKUP),
4242         .sysc_fields    = &omap_hwmod_sysc_type2,
4243 };
4244
4245 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4246         .name   = "timer",
4247         .sysc   = &omap44xx_timer_sysc,
4248 };
4249
4250 /* always-on timers dev attribute */
4251 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4252         .timer_capability       = OMAP_TIMER_ALWON,
4253 };
4254
4255 /* pwm timers dev attribute */
4256 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4257         .timer_capability       = OMAP_TIMER_HAS_PWM,
4258 };
4259
4260 /* timer1 */
4261 static struct omap_hwmod omap44xx_timer1_hwmod;
4262 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4263         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4264         { .irq = -1 }
4265 };
4266
4267 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4268         {
4269                 .pa_start       = 0x4a318000,
4270                 .pa_end         = 0x4a31807f,
4271                 .flags          = ADDR_TYPE_RT
4272         },
4273         { }
4274 };
4275
4276 /* l4_wkup -> timer1 */
4277 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4278         .master         = &omap44xx_l4_wkup_hwmod,
4279         .slave          = &omap44xx_timer1_hwmod,
4280         .clk            = "l4_wkup_clk_mux_ck",
4281         .addr           = omap44xx_timer1_addrs,
4282         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4283 };
4284
4285 /* timer1 slave ports */
4286 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4287         &omap44xx_l4_wkup__timer1,
4288 };
4289
4290 static struct omap_hwmod omap44xx_timer1_hwmod = {
4291         .name           = "timer1",
4292         .class          = &omap44xx_timer_1ms_hwmod_class,
4293         .clkdm_name     = "l4_wkup_clkdm",
4294         .mpu_irqs       = omap44xx_timer1_irqs,
4295         .main_clk       = "timer1_fck",
4296         .prcm = {
4297                 .omap4 = {
4298                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4299                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4300                         .modulemode   = MODULEMODE_SWCTRL,
4301                 },
4302         },
4303         .dev_attr       = &capability_alwon_dev_attr,
4304         .slaves         = omap44xx_timer1_slaves,
4305         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4306 };
4307
4308 /* timer2 */
4309 static struct omap_hwmod omap44xx_timer2_hwmod;
4310 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4311         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4312         { .irq = -1 }
4313 };
4314
4315 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4316         {
4317                 .pa_start       = 0x48032000,
4318                 .pa_end         = 0x4803207f,
4319                 .flags          = ADDR_TYPE_RT
4320         },
4321         { }
4322 };
4323
4324 /* l4_per -> timer2 */
4325 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4326         .master         = &omap44xx_l4_per_hwmod,
4327         .slave          = &omap44xx_timer2_hwmod,
4328         .clk            = "l4_div_ck",
4329         .addr           = omap44xx_timer2_addrs,
4330         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4331 };
4332
4333 /* timer2 slave ports */
4334 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4335         &omap44xx_l4_per__timer2,
4336 };
4337
4338 static struct omap_hwmod omap44xx_timer2_hwmod = {
4339         .name           = "timer2",
4340         .class          = &omap44xx_timer_1ms_hwmod_class,
4341         .clkdm_name     = "l4_per_clkdm",
4342         .mpu_irqs       = omap44xx_timer2_irqs,
4343         .main_clk       = "timer2_fck",
4344         .prcm = {
4345                 .omap4 = {
4346                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4347                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4348                         .modulemode   = MODULEMODE_SWCTRL,
4349                 },
4350         },
4351         .dev_attr       = &capability_alwon_dev_attr,
4352         .slaves         = omap44xx_timer2_slaves,
4353         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4354 };
4355
4356 /* timer3 */
4357 static struct omap_hwmod omap44xx_timer3_hwmod;
4358 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4359         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4360         { .irq = -1 }
4361 };
4362
4363 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4364         {
4365                 .pa_start       = 0x48034000,
4366                 .pa_end         = 0x4803407f,
4367                 .flags          = ADDR_TYPE_RT
4368         },
4369         { }
4370 };
4371
4372 /* l4_per -> timer3 */
4373 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4374         .master         = &omap44xx_l4_per_hwmod,
4375         .slave          = &omap44xx_timer3_hwmod,
4376         .clk            = "l4_div_ck",
4377         .addr           = omap44xx_timer3_addrs,
4378         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4379 };
4380
4381 /* timer3 slave ports */
4382 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4383         &omap44xx_l4_per__timer3,
4384 };
4385
4386 static struct omap_hwmod omap44xx_timer3_hwmod = {
4387         .name           = "timer3",
4388         .class          = &omap44xx_timer_hwmod_class,
4389         .clkdm_name     = "l4_per_clkdm",
4390         .mpu_irqs       = omap44xx_timer3_irqs,
4391         .main_clk       = "timer3_fck",
4392         .prcm = {
4393                 .omap4 = {
4394                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4395                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4396                         .modulemode   = MODULEMODE_SWCTRL,
4397                 },
4398         },
4399         .dev_attr       = &capability_alwon_dev_attr,
4400         .slaves         = omap44xx_timer3_slaves,
4401         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4402 };
4403
4404 /* timer4 */
4405 static struct omap_hwmod omap44xx_timer4_hwmod;
4406 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4407         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4408         { .irq = -1 }
4409 };
4410
4411 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4412         {
4413                 .pa_start       = 0x48036000,
4414                 .pa_end         = 0x4803607f,
4415                 .flags          = ADDR_TYPE_RT
4416         },
4417         { }
4418 };
4419
4420 /* l4_per -> timer4 */
4421 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4422         .master         = &omap44xx_l4_per_hwmod,
4423         .slave          = &omap44xx_timer4_hwmod,
4424         .clk            = "l4_div_ck",
4425         .addr           = omap44xx_timer4_addrs,
4426         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4427 };
4428
4429 /* timer4 slave ports */
4430 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4431         &omap44xx_l4_per__timer4,
4432 };
4433
4434 static struct omap_hwmod omap44xx_timer4_hwmod = {
4435         .name           = "timer4",
4436         .class          = &omap44xx_timer_hwmod_class,
4437         .clkdm_name     = "l4_per_clkdm",
4438         .mpu_irqs       = omap44xx_timer4_irqs,
4439         .main_clk       = "timer4_fck",
4440         .prcm = {
4441                 .omap4 = {
4442                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4443                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4444                         .modulemode   = MODULEMODE_SWCTRL,
4445                 },
4446         },
4447         .dev_attr       = &capability_alwon_dev_attr,
4448         .slaves         = omap44xx_timer4_slaves,
4449         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4450 };
4451
4452 /* timer5 */
4453 static struct omap_hwmod omap44xx_timer5_hwmod;
4454 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4455         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4456         { .irq = -1 }
4457 };
4458
4459 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4460         {
4461                 .pa_start       = 0x40138000,
4462                 .pa_end         = 0x4013807f,
4463                 .flags          = ADDR_TYPE_RT
4464         },
4465         { }
4466 };
4467
4468 /* l4_abe -> timer5 */
4469 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4470         .master         = &omap44xx_l4_abe_hwmod,
4471         .slave          = &omap44xx_timer5_hwmod,
4472         .clk            = "ocp_abe_iclk",
4473         .addr           = omap44xx_timer5_addrs,
4474         .user           = OCP_USER_MPU,
4475 };
4476
4477 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4478         {
4479                 .pa_start       = 0x49038000,
4480                 .pa_end         = 0x4903807f,
4481                 .flags          = ADDR_TYPE_RT
4482         },
4483         { }
4484 };
4485
4486 /* l4_abe -> timer5 (dma) */
4487 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4488         .master         = &omap44xx_l4_abe_hwmod,
4489         .slave          = &omap44xx_timer5_hwmod,
4490         .clk            = "ocp_abe_iclk",
4491         .addr           = omap44xx_timer5_dma_addrs,
4492         .user           = OCP_USER_SDMA,
4493 };
4494
4495 /* timer5 slave ports */
4496 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4497         &omap44xx_l4_abe__timer5,
4498         &omap44xx_l4_abe__timer5_dma,
4499 };
4500
4501 static struct omap_hwmod omap44xx_timer5_hwmod = {
4502         .name           = "timer5",
4503         .class          = &omap44xx_timer_hwmod_class,
4504         .clkdm_name     = "abe_clkdm",
4505         .mpu_irqs       = omap44xx_timer5_irqs,
4506         .main_clk       = "timer5_fck",
4507         .prcm = {
4508                 .omap4 = {
4509                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4510                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4511                         .modulemode   = MODULEMODE_SWCTRL,
4512                 },
4513         },
4514         .dev_attr       = &capability_alwon_dev_attr,
4515         .slaves         = omap44xx_timer5_slaves,
4516         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4517 };
4518
4519 /* timer6 */
4520 static struct omap_hwmod omap44xx_timer6_hwmod;
4521 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4522         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4523         { .irq = -1 }
4524 };
4525
4526 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4527         {
4528                 .pa_start       = 0x4013a000,
4529                 .pa_end         = 0x4013a07f,
4530                 .flags          = ADDR_TYPE_RT
4531         },
4532         { }
4533 };
4534
4535 /* l4_abe -> timer6 */
4536 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4537         .master         = &omap44xx_l4_abe_hwmod,
4538         .slave          = &omap44xx_timer6_hwmod,
4539         .clk            = "ocp_abe_iclk",
4540         .addr           = omap44xx_timer6_addrs,
4541         .user           = OCP_USER_MPU,
4542 };
4543
4544 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4545         {
4546                 .pa_start       = 0x4903a000,
4547                 .pa_end         = 0x4903a07f,
4548                 .flags          = ADDR_TYPE_RT
4549         },
4550         { }
4551 };
4552
4553 /* l4_abe -> timer6 (dma) */
4554 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4555         .master         = &omap44xx_l4_abe_hwmod,
4556         .slave          = &omap44xx_timer6_hwmod,
4557         .clk            = "ocp_abe_iclk",
4558         .addr           = omap44xx_timer6_dma_addrs,
4559         .user           = OCP_USER_SDMA,
4560 };
4561
4562 /* timer6 slave ports */
4563 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4564         &omap44xx_l4_abe__timer6,
4565         &omap44xx_l4_abe__timer6_dma,
4566 };
4567
4568 static struct omap_hwmod omap44xx_timer6_hwmod = {
4569         .name           = "timer6",
4570         .class          = &omap44xx_timer_hwmod_class,
4571         .clkdm_name     = "abe_clkdm",
4572         .mpu_irqs       = omap44xx_timer6_irqs,
4573
4574         .main_clk       = "timer6_fck",
4575         .prcm = {
4576                 .omap4 = {
4577                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4578                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4579                         .modulemode   = MODULEMODE_SWCTRL,
4580                 },
4581         },
4582         .dev_attr       = &capability_alwon_dev_attr,
4583         .slaves         = omap44xx_timer6_slaves,
4584         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4585 };
4586
4587 /* timer7 */
4588 static struct omap_hwmod omap44xx_timer7_hwmod;
4589 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4590         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4591         { .irq = -1 }
4592 };
4593
4594 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4595         {
4596                 .pa_start       = 0x4013c000,
4597                 .pa_end         = 0x4013c07f,
4598                 .flags          = ADDR_TYPE_RT
4599         },
4600         { }
4601 };
4602
4603 /* l4_abe -> timer7 */
4604 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4605         .master         = &omap44xx_l4_abe_hwmod,
4606         .slave          = &omap44xx_timer7_hwmod,
4607         .clk            = "ocp_abe_iclk",
4608         .addr           = omap44xx_timer7_addrs,
4609         .user           = OCP_USER_MPU,
4610 };
4611
4612 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4613         {
4614                 .pa_start       = 0x4903c000,
4615                 .pa_end         = 0x4903c07f,
4616                 .flags          = ADDR_TYPE_RT
4617         },
4618         { }
4619 };
4620
4621 /* l4_abe -> timer7 (dma) */
4622 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4623         .master         = &omap44xx_l4_abe_hwmod,
4624         .slave          = &omap44xx_timer7_hwmod,
4625         .clk            = "ocp_abe_iclk",
4626         .addr           = omap44xx_timer7_dma_addrs,
4627         .user           = OCP_USER_SDMA,
4628 };
4629
4630 /* timer7 slave ports */
4631 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4632         &omap44xx_l4_abe__timer7,
4633         &omap44xx_l4_abe__timer7_dma,
4634 };
4635
4636 static struct omap_hwmod omap44xx_timer7_hwmod = {
4637         .name           = "timer7",
4638         .class          = &omap44xx_timer_hwmod_class,
4639         .clkdm_name     = "abe_clkdm",
4640         .mpu_irqs       = omap44xx_timer7_irqs,
4641         .main_clk       = "timer7_fck",
4642         .prcm = {
4643                 .omap4 = {
4644                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4645                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4646                         .modulemode   = MODULEMODE_SWCTRL,
4647                 },
4648         },
4649         .dev_attr       = &capability_alwon_dev_attr,
4650         .slaves         = omap44xx_timer7_slaves,
4651         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4652 };
4653
4654 /* timer8 */
4655 static struct omap_hwmod omap44xx_timer8_hwmod;
4656 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4657         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4658         { .irq = -1 }
4659 };
4660
4661 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4662         {
4663                 .pa_start       = 0x4013e000,
4664                 .pa_end         = 0x4013e07f,
4665                 .flags          = ADDR_TYPE_RT
4666         },
4667         { }
4668 };
4669
4670 /* l4_abe -> timer8 */
4671 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4672         .master         = &omap44xx_l4_abe_hwmod,
4673         .slave          = &omap44xx_timer8_hwmod,
4674         .clk            = "ocp_abe_iclk",
4675         .addr           = omap44xx_timer8_addrs,
4676         .user           = OCP_USER_MPU,
4677 };
4678
4679 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4680         {
4681                 .pa_start       = 0x4903e000,
4682                 .pa_end         = 0x4903e07f,
4683                 .flags          = ADDR_TYPE_RT
4684         },
4685         { }
4686 };
4687
4688 /* l4_abe -> timer8 (dma) */
4689 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4690         .master         = &omap44xx_l4_abe_hwmod,
4691         .slave          = &omap44xx_timer8_hwmod,
4692         .clk            = "ocp_abe_iclk",
4693         .addr           = omap44xx_timer8_dma_addrs,
4694         .user           = OCP_USER_SDMA,
4695 };
4696
4697 /* timer8 slave ports */
4698 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4699         &omap44xx_l4_abe__timer8,
4700         &omap44xx_l4_abe__timer8_dma,
4701 };
4702
4703 static struct omap_hwmod omap44xx_timer8_hwmod = {
4704         .name           = "timer8",
4705         .class          = &omap44xx_timer_hwmod_class,
4706         .clkdm_name     = "abe_clkdm",
4707         .mpu_irqs       = omap44xx_timer8_irqs,
4708         .main_clk       = "timer8_fck",
4709         .prcm = {
4710                 .omap4 = {
4711                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4712                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4713                         .modulemode   = MODULEMODE_SWCTRL,
4714                 },
4715         },
4716         .dev_attr       = &capability_pwm_dev_attr,
4717         .slaves         = omap44xx_timer8_slaves,
4718         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4719 };
4720
4721 /* timer9 */
4722 static struct omap_hwmod omap44xx_timer9_hwmod;
4723 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4724         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4725         { .irq = -1 }
4726 };
4727
4728 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4729         {
4730                 .pa_start       = 0x4803e000,
4731                 .pa_end         = 0x4803e07f,
4732                 .flags          = ADDR_TYPE_RT
4733         },
4734         { }
4735 };
4736
4737 /* l4_per -> timer9 */
4738 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4739         .master         = &omap44xx_l4_per_hwmod,
4740         .slave          = &omap44xx_timer9_hwmod,
4741         .clk            = "l4_div_ck",
4742         .addr           = omap44xx_timer9_addrs,
4743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4744 };
4745
4746 /* timer9 slave ports */
4747 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4748         &omap44xx_l4_per__timer9,
4749 };
4750
4751 static struct omap_hwmod omap44xx_timer9_hwmod = {
4752         .name           = "timer9",
4753         .class          = &omap44xx_timer_hwmod_class,
4754         .clkdm_name     = "l4_per_clkdm",
4755         .mpu_irqs       = omap44xx_timer9_irqs,
4756         .main_clk       = "timer9_fck",
4757         .prcm = {
4758                 .omap4 = {
4759                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4760                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4761                         .modulemode   = MODULEMODE_SWCTRL,
4762                 },
4763         },
4764         .dev_attr       = &capability_pwm_dev_attr,
4765         .slaves         = omap44xx_timer9_slaves,
4766         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4767 };
4768
4769 /* timer10 */
4770 static struct omap_hwmod omap44xx_timer10_hwmod;
4771 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4772         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4773         { .irq = -1 }
4774 };
4775
4776 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4777         {
4778                 .pa_start       = 0x48086000,
4779                 .pa_end         = 0x4808607f,
4780                 .flags          = ADDR_TYPE_RT
4781         },
4782         { }
4783 };
4784
4785 /* l4_per -> timer10 */
4786 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4787         .master         = &omap44xx_l4_per_hwmod,
4788         .slave          = &omap44xx_timer10_hwmod,
4789         .clk            = "l4_div_ck",
4790         .addr           = omap44xx_timer10_addrs,
4791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4792 };
4793
4794 /* timer10 slave ports */
4795 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4796         &omap44xx_l4_per__timer10,
4797 };
4798
4799 static struct omap_hwmod omap44xx_timer10_hwmod = {
4800         .name           = "timer10",
4801         .class          = &omap44xx_timer_1ms_hwmod_class,
4802         .clkdm_name     = "l4_per_clkdm",
4803         .mpu_irqs       = omap44xx_timer10_irqs,
4804         .main_clk       = "timer10_fck",
4805         .prcm = {
4806                 .omap4 = {
4807                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4808                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4809                         .modulemode   = MODULEMODE_SWCTRL,
4810                 },
4811         },
4812         .dev_attr       = &capability_pwm_dev_attr,
4813         .slaves         = omap44xx_timer10_slaves,
4814         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4815 };
4816
4817 /* timer11 */
4818 static struct omap_hwmod omap44xx_timer11_hwmod;
4819 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4820         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4821         { .irq = -1 }
4822 };
4823
4824 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4825         {
4826                 .pa_start       = 0x48088000,
4827                 .pa_end         = 0x4808807f,
4828                 .flags          = ADDR_TYPE_RT
4829         },
4830         { }
4831 };
4832
4833 /* l4_per -> timer11 */
4834 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4835         .master         = &omap44xx_l4_per_hwmod,
4836         .slave          = &omap44xx_timer11_hwmod,
4837         .clk            = "l4_div_ck",
4838         .addr           = omap44xx_timer11_addrs,
4839         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4840 };
4841
4842 /* timer11 slave ports */
4843 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4844         &omap44xx_l4_per__timer11,
4845 };
4846
4847 static struct omap_hwmod omap44xx_timer11_hwmod = {
4848         .name           = "timer11",
4849         .class          = &omap44xx_timer_hwmod_class,
4850         .clkdm_name     = "l4_per_clkdm",
4851         .mpu_irqs       = omap44xx_timer11_irqs,
4852         .main_clk       = "timer11_fck",
4853         .prcm = {
4854                 .omap4 = {
4855                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4856                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4857                         .modulemode   = MODULEMODE_SWCTRL,
4858                 },
4859         },
4860         .dev_attr       = &capability_pwm_dev_attr,
4861         .slaves         = omap44xx_timer11_slaves,
4862         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4863 };
4864
4865 /*
4866  * 'uart' class
4867  * universal asynchronous receiver/transmitter (uart)
4868  */
4869
4870 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4871         .rev_offs       = 0x0050,
4872         .sysc_offs      = 0x0054,
4873         .syss_offs      = 0x0058,
4874         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4875                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4876                            SYSS_HAS_RESET_STATUS),
4877         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4878                            SIDLE_SMART_WKUP),
4879         .sysc_fields    = &omap_hwmod_sysc_type1,
4880 };
4881
4882 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4883         .name   = "uart",
4884         .sysc   = &omap44xx_uart_sysc,
4885 };
4886
4887 /* uart1 */
4888 static struct omap_hwmod omap44xx_uart1_hwmod;
4889 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4890         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4891         { .irq = -1 }
4892 };
4893
4894 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4895         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4896         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4897         { .dma_req = -1 }
4898 };
4899
4900 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4901         {
4902                 .pa_start       = 0x4806a000,
4903                 .pa_end         = 0x4806a0ff,
4904                 .flags          = ADDR_TYPE_RT
4905         },
4906         { }
4907 };
4908
4909 /* l4_per -> uart1 */
4910 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4911         .master         = &omap44xx_l4_per_hwmod,
4912         .slave          = &omap44xx_uart1_hwmod,
4913         .clk            = "l4_div_ck",
4914         .addr           = omap44xx_uart1_addrs,
4915         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4916 };
4917
4918 /* uart1 slave ports */
4919 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4920         &omap44xx_l4_per__uart1,
4921 };
4922
4923 static struct omap_hwmod omap44xx_uart1_hwmod = {
4924         .name           = "uart1",
4925         .class          = &omap44xx_uart_hwmod_class,
4926         .clkdm_name     = "l4_per_clkdm",
4927         .mpu_irqs       = omap44xx_uart1_irqs,
4928         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4929         .main_clk       = "uart1_fck",
4930         .prcm = {
4931                 .omap4 = {
4932                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4933                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4934                         .modulemode   = MODULEMODE_SWCTRL,
4935                 },
4936         },
4937         .slaves         = omap44xx_uart1_slaves,
4938         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4939 };
4940
4941 /* uart2 */
4942 static struct omap_hwmod omap44xx_uart2_hwmod;
4943 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4944         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4945         { .irq = -1 }
4946 };
4947
4948 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4949         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4950         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4951         { .dma_req = -1 }
4952 };
4953
4954 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4955         {
4956                 .pa_start       = 0x4806c000,
4957                 .pa_end         = 0x4806c0ff,
4958                 .flags          = ADDR_TYPE_RT
4959         },
4960         { }
4961 };
4962
4963 /* l4_per -> uart2 */
4964 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4965         .master         = &omap44xx_l4_per_hwmod,
4966         .slave          = &omap44xx_uart2_hwmod,
4967         .clk            = "l4_div_ck",
4968         .addr           = omap44xx_uart2_addrs,
4969         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4970 };
4971
4972 /* uart2 slave ports */
4973 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4974         &omap44xx_l4_per__uart2,
4975 };
4976
4977 static struct omap_hwmod omap44xx_uart2_hwmod = {
4978         .name           = "uart2",
4979         .class          = &omap44xx_uart_hwmod_class,
4980         .clkdm_name     = "l4_per_clkdm",
4981         .mpu_irqs       = omap44xx_uart2_irqs,
4982         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4983         .main_clk       = "uart2_fck",
4984         .prcm = {
4985                 .omap4 = {
4986                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4987                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4988                         .modulemode   = MODULEMODE_SWCTRL,
4989                 },
4990         },
4991         .slaves         = omap44xx_uart2_slaves,
4992         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4993 };
4994
4995 /* uart3 */
4996 static struct omap_hwmod omap44xx_uart3_hwmod;
4997 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4998         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4999         { .irq = -1 }
5000 };
5001
5002 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
5003         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
5004         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
5005         { .dma_req = -1 }
5006 };
5007
5008 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
5009         {
5010                 .pa_start       = 0x48020000,
5011                 .pa_end         = 0x480200ff,
5012                 .flags          = ADDR_TYPE_RT
5013         },
5014         { }
5015 };
5016
5017 /* l4_per -> uart3 */
5018 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
5019         .master         = &omap44xx_l4_per_hwmod,
5020         .slave          = &omap44xx_uart3_hwmod,
5021         .clk            = "l4_div_ck",
5022         .addr           = omap44xx_uart3_addrs,
5023         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5024 };
5025
5026 /* uart3 slave ports */
5027 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
5028         &omap44xx_l4_per__uart3,
5029 };
5030
5031 static struct omap_hwmod omap44xx_uart3_hwmod = {
5032         .name           = "uart3",
5033         .class          = &omap44xx_uart_hwmod_class,
5034         .clkdm_name     = "l4_per_clkdm",
5035         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5036         .mpu_irqs       = omap44xx_uart3_irqs,
5037         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
5038         .main_clk       = "uart3_fck",
5039         .prcm = {
5040                 .omap4 = {
5041                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5042                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5043                         .modulemode   = MODULEMODE_SWCTRL,
5044                 },
5045         },
5046         .slaves         = omap44xx_uart3_slaves,
5047         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
5048 };
5049
5050 /* uart4 */
5051 static struct omap_hwmod omap44xx_uart4_hwmod;
5052 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5053         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5054         { .irq = -1 }
5055 };
5056
5057 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5058         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5059         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5060         { .dma_req = -1 }
5061 };
5062
5063 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5064         {
5065                 .pa_start       = 0x4806e000,
5066                 .pa_end         = 0x4806e0ff,
5067                 .flags          = ADDR_TYPE_RT
5068         },
5069         { }
5070 };
5071
5072 /* l4_per -> uart4 */
5073 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5074         .master         = &omap44xx_l4_per_hwmod,
5075         .slave          = &omap44xx_uart4_hwmod,
5076         .clk            = "l4_div_ck",
5077         .addr           = omap44xx_uart4_addrs,
5078         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5079 };
5080
5081 /* uart4 slave ports */
5082 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5083         &omap44xx_l4_per__uart4,
5084 };
5085
5086 static struct omap_hwmod omap44xx_uart4_hwmod = {
5087         .name           = "uart4",
5088         .class          = &omap44xx_uart_hwmod_class,
5089         .clkdm_name     = "l4_per_clkdm",
5090         .mpu_irqs       = omap44xx_uart4_irqs,
5091         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5092         .main_clk       = "uart4_fck",
5093         .prcm = {
5094                 .omap4 = {
5095                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5096                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5097                         .modulemode   = MODULEMODE_SWCTRL,
5098                 },
5099         },
5100         .slaves         = omap44xx_uart4_slaves,
5101         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5102 };
5103
5104 /*
5105  * 'usb_otg_hs' class
5106  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5107  */
5108
5109 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5110         .rev_offs       = 0x0400,
5111         .sysc_offs      = 0x0404,
5112         .syss_offs      = 0x0408,
5113         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5114                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5115                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5116         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5117                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5118                            MSTANDBY_SMART),
5119         .sysc_fields    = &omap_hwmod_sysc_type1,
5120 };
5121
5122 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5123         .name   = "usb_otg_hs",
5124         .sysc   = &omap44xx_usb_otg_hs_sysc,
5125 };
5126
5127 /* usb_otg_hs */
5128 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5129         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5130         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5131         { .irq = -1 }
5132 };
5133
5134 /* usb_otg_hs master ports */
5135 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5136         &omap44xx_usb_otg_hs__l3_main_2,
5137 };
5138
5139 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5140         {
5141                 .pa_start       = 0x4a0ab000,
5142                 .pa_end         = 0x4a0ab003,
5143                 .flags          = ADDR_TYPE_RT
5144         },
5145         { }
5146 };
5147
5148 /* l4_cfg -> usb_otg_hs */
5149 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5150         .master         = &omap44xx_l4_cfg_hwmod,
5151         .slave          = &omap44xx_usb_otg_hs_hwmod,
5152         .clk            = "l4_div_ck",
5153         .addr           = omap44xx_usb_otg_hs_addrs,
5154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5155 };
5156
5157 /* usb_otg_hs slave ports */
5158 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5159         &omap44xx_l4_cfg__usb_otg_hs,
5160 };
5161
5162 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5163         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5164 };
5165
5166 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5167         .name           = "usb_otg_hs",
5168         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5169         .clkdm_name     = "l3_init_clkdm",
5170         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5171         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5172         .main_clk       = "usb_otg_hs_ick",
5173         .prcm = {
5174                 .omap4 = {
5175                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5176                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5177                         .modulemode   = MODULEMODE_HWCTRL,
5178                 },
5179         },
5180         .opt_clks       = usb_otg_hs_opt_clks,
5181         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5182         .slaves         = omap44xx_usb_otg_hs_slaves,
5183         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5184         .masters        = omap44xx_usb_otg_hs_masters,
5185         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5186 };
5187
5188 /*
5189  * 'wd_timer' class
5190  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5191  * overflow condition
5192  */
5193
5194 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5195         .rev_offs       = 0x0000,
5196         .sysc_offs      = 0x0010,
5197         .syss_offs      = 0x0014,
5198         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5199                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5200         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5201                            SIDLE_SMART_WKUP),
5202         .sysc_fields    = &omap_hwmod_sysc_type1,
5203 };
5204
5205 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5206         .name           = "wd_timer",
5207         .sysc           = &omap44xx_wd_timer_sysc,
5208         .pre_shutdown   = &omap2_wd_timer_disable,
5209 };
5210
5211 /* wd_timer2 */
5212 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5213 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5214         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5215         { .irq = -1 }
5216 };
5217
5218 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5219         {
5220                 .pa_start       = 0x4a314000,
5221                 .pa_end         = 0x4a31407f,
5222                 .flags          = ADDR_TYPE_RT
5223         },
5224         { }
5225 };
5226
5227 /* l4_wkup -> wd_timer2 */
5228 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5229         .master         = &omap44xx_l4_wkup_hwmod,
5230         .slave          = &omap44xx_wd_timer2_hwmod,
5231         .clk            = "l4_wkup_clk_mux_ck",
5232         .addr           = omap44xx_wd_timer2_addrs,
5233         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5234 };
5235
5236 /* wd_timer2 slave ports */
5237 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5238         &omap44xx_l4_wkup__wd_timer2,
5239 };
5240
5241 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5242         .name           = "wd_timer2",
5243         .class          = &omap44xx_wd_timer_hwmod_class,
5244         .clkdm_name     = "l4_wkup_clkdm",
5245         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5246         .main_clk       = "wd_timer2_fck",
5247         .prcm = {
5248                 .omap4 = {
5249                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5250                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5251                         .modulemode   = MODULEMODE_SWCTRL,
5252                 },
5253         },
5254         .slaves         = omap44xx_wd_timer2_slaves,
5255         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5256 };
5257
5258 /* wd_timer3 */
5259 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5260 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5261         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5262         { .irq = -1 }
5263 };
5264
5265 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5266         {
5267                 .pa_start       = 0x40130000,
5268                 .pa_end         = 0x4013007f,
5269                 .flags          = ADDR_TYPE_RT
5270         },
5271         { }
5272 };
5273
5274 /* l4_abe -> wd_timer3 */
5275 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5276         .master         = &omap44xx_l4_abe_hwmod,
5277         .slave          = &omap44xx_wd_timer3_hwmod,
5278         .clk            = "ocp_abe_iclk",
5279         .addr           = omap44xx_wd_timer3_addrs,
5280         .user           = OCP_USER_MPU,
5281 };
5282
5283 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5284         {
5285                 .pa_start       = 0x49030000,
5286                 .pa_end         = 0x4903007f,
5287                 .flags          = ADDR_TYPE_RT
5288         },
5289         { }
5290 };
5291
5292 /* l4_abe -> wd_timer3 (dma) */
5293 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5294         .master         = &omap44xx_l4_abe_hwmod,
5295         .slave          = &omap44xx_wd_timer3_hwmod,
5296         .clk            = "ocp_abe_iclk",
5297         .addr           = omap44xx_wd_timer3_dma_addrs,
5298         .user           = OCP_USER_SDMA,
5299 };
5300
5301 /* wd_timer3 slave ports */
5302 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5303         &omap44xx_l4_abe__wd_timer3,
5304         &omap44xx_l4_abe__wd_timer3_dma,
5305 };
5306
5307 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5308         .name           = "wd_timer3",
5309         .class          = &omap44xx_wd_timer_hwmod_class,
5310         .clkdm_name     = "abe_clkdm",
5311         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5312         .main_clk       = "wd_timer3_fck",
5313         .prcm = {
5314                 .omap4 = {
5315                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5316                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5317                         .modulemode   = MODULEMODE_SWCTRL,
5318                 },
5319         },
5320         .slaves         = omap44xx_wd_timer3_slaves,
5321         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5322 };
5323
5324 /*
5325  * 'usb_host_hs' class
5326  * high-speed multi-port usb host controller
5327  */
5328 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5329         .master         = &omap44xx_usb_host_hs_hwmod,
5330         .slave          = &omap44xx_l3_main_2_hwmod,
5331         .clk            = "l3_div_ck",
5332         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5333 };
5334
5335 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5336         .rev_offs       = 0x0000,
5337         .sysc_offs      = 0x0010,
5338         .syss_offs      = 0x0014,
5339         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5340                            SYSC_HAS_SOFTRESET),
5341         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5342                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5343                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5344         .sysc_fields    = &omap_hwmod_sysc_type2,
5345 };
5346
5347 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5348         .name = "usb_host_hs",
5349         .sysc = &omap44xx_usb_host_hs_sysc,
5350 };
5351
5352 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5353         &omap44xx_usb_host_hs__l3_main_2,
5354 };
5355
5356 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5357         {
5358                 .name           = "uhh",
5359                 .pa_start       = 0x4a064000,
5360                 .pa_end         = 0x4a0647ff,
5361                 .flags          = ADDR_TYPE_RT
5362         },
5363         {
5364                 .name           = "ohci",
5365                 .pa_start       = 0x4a064800,
5366                 .pa_end         = 0x4a064bff,
5367         },
5368         {
5369                 .name           = "ehci",
5370                 .pa_start       = 0x4a064c00,
5371                 .pa_end         = 0x4a064fff,
5372         },
5373         {}
5374 };
5375
5376 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5377         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5378         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5379         { .irq = -1 }
5380 };
5381
5382 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5383         .master         = &omap44xx_l4_cfg_hwmod,
5384         .slave          = &omap44xx_usb_host_hs_hwmod,
5385         .clk            = "l4_div_ck",
5386         .addr           = omap44xx_usb_host_hs_addrs,
5387         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5388 };
5389
5390 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5391         &omap44xx_l4_cfg__usb_host_hs,
5392 };
5393
5394 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5395         .name           = "usb_host_hs",
5396         .class          = &omap44xx_usb_host_hs_hwmod_class,
5397         .clkdm_name     = "l3_init_clkdm",
5398         .main_clk       = "usb_host_hs_fck",
5399         .prcm = {
5400                 .omap4 = {
5401                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5402                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5403                         .modulemode   = MODULEMODE_SWCTRL,
5404                 },
5405         },
5406         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
5407         .slaves         = omap44xx_usb_host_hs_slaves,
5408         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5409         .masters        = omap44xx_usb_host_hs_masters,
5410         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5411
5412         /*
5413          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5414          * id: i660
5415          *
5416          * Description:
5417          * In the following configuration :
5418          * - USBHOST module is set to smart-idle mode
5419          * - PRCM asserts idle_req to the USBHOST module ( This typically
5420          *   happens when the system is going to a low power mode : all ports
5421          *   have been suspended, the master part of the USBHOST module has
5422          *   entered the standby state, and SW has cut the functional clocks)
5423          * - an USBHOST interrupt occurs before the module is able to answer
5424          *   idle_ack, typically a remote wakeup IRQ.
5425          * Then the USB HOST module will enter a deadlock situation where it
5426          * is no more accessible nor functional.
5427          *
5428          * Workaround:
5429          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5430          */
5431
5432         /*
5433          * Errata: USB host EHCI may stall when entering smart-standby mode
5434          * Id: i571
5435          *
5436          * Description:
5437          * When the USBHOST module is set to smart-standby mode, and when it is
5438          * ready to enter the standby state (i.e. all ports are suspended and
5439          * all attached devices are in suspend mode), then it can wrongly assert
5440          * the Mstandby signal too early while there are still some residual OCP
5441          * transactions ongoing. If this condition occurs, the internal state
5442          * machine may go to an undefined state and the USB link may be stuck
5443          * upon the next resume.
5444          *
5445          * Workaround:
5446          * Don't use smart standby; use only force standby,
5447          * hence HWMOD_SWSUP_MSTANDBY
5448          */
5449
5450         /*
5451          * During system boot; If the hwmod framework resets the module
5452          * the module will have smart idle settings; which can lead to deadlock
5453          * (above Errata Id:i660); so, dont reset the module during boot;
5454          * Use HWMOD_INIT_NO_RESET.
5455          */
5456
5457         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5458                           HWMOD_INIT_NO_RESET,
5459 };
5460
5461 /*
5462  * 'usb_tll_hs' class
5463  * usb_tll_hs module is the adapter on the usb_host_hs ports
5464  */
5465 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5466         .rev_offs       = 0x0000,
5467         .sysc_offs      = 0x0010,
5468         .syss_offs      = 0x0014,
5469         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5470                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5471                            SYSC_HAS_AUTOIDLE),
5472         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5473         .sysc_fields    = &omap_hwmod_sysc_type1,
5474 };
5475
5476 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5477         .name = "usb_tll_hs",
5478         .sysc = &omap44xx_usb_tll_hs_sysc,
5479 };
5480
5481 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5482         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5483         { .irq = -1 }
5484 };
5485
5486 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5487         {
5488                 .name           = "tll",
5489                 .pa_start       = 0x4a062000,
5490                 .pa_end         = 0x4a063fff,
5491                 .flags          = ADDR_TYPE_RT
5492         },
5493         {}
5494 };
5495
5496 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5497         .master         = &omap44xx_l4_cfg_hwmod,
5498         .slave          = &omap44xx_usb_tll_hs_hwmod,
5499         .clk            = "l4_div_ck",
5500         .addr           = omap44xx_usb_tll_hs_addrs,
5501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5502 };
5503
5504 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5505         &omap44xx_l4_cfg__usb_tll_hs,
5506 };
5507
5508 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5509         .name           = "usb_tll_hs",
5510         .class          = &omap44xx_usb_tll_hs_hwmod_class,
5511         .clkdm_name     = "l3_init_clkdm",
5512         .main_clk       = "usb_tll_hs_ick",
5513         .prcm = {
5514                 .omap4 = {
5515                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5516                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5517                         .modulemode   = MODULEMODE_HWCTRL,
5518                 },
5519         },
5520         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
5521         .slaves         = omap44xx_usb_tll_hs_slaves,
5522         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5523 };
5524
5525 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5526
5527         /* dmm class */
5528         &omap44xx_dmm_hwmod,
5529
5530         /* emif_fw class */
5531         &omap44xx_emif_fw_hwmod,
5532
5533         /* l3 class */
5534         &omap44xx_l3_instr_hwmod,
5535         &omap44xx_l3_main_1_hwmod,
5536         &omap44xx_l3_main_2_hwmod,
5537         &omap44xx_l3_main_3_hwmod,
5538
5539         /* l4 class */
5540         &omap44xx_l4_abe_hwmod,
5541         &omap44xx_l4_cfg_hwmod,
5542         &omap44xx_l4_per_hwmod,
5543         &omap44xx_l4_wkup_hwmod,
5544
5545         /* mpu_bus class */
5546         &omap44xx_mpu_private_hwmod,
5547
5548         /* aess class */
5549 /*      &omap44xx_aess_hwmod, */
5550
5551         /* bandgap class */
5552         &omap44xx_bandgap_hwmod,
5553
5554         /* counter class */
5555 /*      &omap44xx_counter_32k_hwmod, */
5556
5557         /* dma class */
5558         &omap44xx_dma_system_hwmod,
5559
5560         /* dmic class */
5561         &omap44xx_dmic_hwmod,
5562
5563         /* dsp class */
5564         &omap44xx_dsp_hwmod,
5565         &omap44xx_dsp_c0_hwmod,
5566
5567         /* dss class */
5568         &omap44xx_dss_hwmod,
5569         &omap44xx_dss_dispc_hwmod,
5570         &omap44xx_dss_dsi1_hwmod,
5571         &omap44xx_dss_dsi2_hwmod,
5572         &omap44xx_dss_hdmi_hwmod,
5573         &omap44xx_dss_rfbi_hwmod,
5574         &omap44xx_dss_venc_hwmod,
5575
5576         /* gpio class */
5577         &omap44xx_gpio1_hwmod,
5578         &omap44xx_gpio2_hwmod,
5579         &omap44xx_gpio3_hwmod,
5580         &omap44xx_gpio4_hwmod,
5581         &omap44xx_gpio5_hwmod,
5582         &omap44xx_gpio6_hwmod,
5583
5584         /* hsi class */
5585 /*      &omap44xx_hsi_hwmod, */
5586
5587         /* i2c class */
5588         &omap44xx_i2c1_hwmod,
5589         &omap44xx_i2c2_hwmod,
5590         &omap44xx_i2c3_hwmod,
5591         &omap44xx_i2c4_hwmod,
5592
5593         /* ipu class */
5594         &omap44xx_ipu_hwmod,
5595         &omap44xx_ipu_c0_hwmod,
5596         &omap44xx_ipu_c1_hwmod,
5597
5598         /* iss class */
5599 /*      &omap44xx_iss_hwmod, */
5600
5601         /* iva class */
5602         &omap44xx_iva_hwmod,
5603         &omap44xx_iva_seq0_hwmod,
5604         &omap44xx_iva_seq1_hwmod,
5605
5606         /* kbd class */
5607         &omap44xx_kbd_hwmod,
5608
5609         /* mailbox class */
5610         &omap44xx_mailbox_hwmod,
5611
5612         /* mcbsp class */
5613         &omap44xx_mcbsp1_hwmod,
5614         &omap44xx_mcbsp2_hwmod,
5615         &omap44xx_mcbsp3_hwmod,
5616         &omap44xx_mcbsp4_hwmod,
5617
5618         /* mcpdm class */
5619         &omap44xx_mcpdm_hwmod,
5620
5621         /* mcspi class */
5622         &omap44xx_mcspi1_hwmod,
5623         &omap44xx_mcspi2_hwmod,
5624         &omap44xx_mcspi3_hwmod,
5625         &omap44xx_mcspi4_hwmod,
5626
5627         /* mmc class */
5628         &omap44xx_mmc1_hwmod,
5629         &omap44xx_mmc2_hwmod,
5630         &omap44xx_mmc3_hwmod,
5631         &omap44xx_mmc4_hwmod,
5632         &omap44xx_mmc5_hwmod,
5633
5634         /* mpu class */
5635         &omap44xx_mpu_hwmod,
5636
5637         /* smartreflex class */
5638         &omap44xx_smartreflex_core_hwmod,
5639         &omap44xx_smartreflex_iva_hwmod,
5640         &omap44xx_smartreflex_mpu_hwmod,
5641
5642         /* spinlock class */
5643         &omap44xx_spinlock_hwmod,
5644
5645         /* timer class */
5646         &omap44xx_timer1_hwmod,
5647         &omap44xx_timer2_hwmod,
5648         &omap44xx_timer3_hwmod,
5649         &omap44xx_timer4_hwmod,
5650         &omap44xx_timer5_hwmod,
5651         &omap44xx_timer6_hwmod,
5652         &omap44xx_timer7_hwmod,
5653         &omap44xx_timer8_hwmod,
5654         &omap44xx_timer9_hwmod,
5655         &omap44xx_timer10_hwmod,
5656         &omap44xx_timer11_hwmod,
5657
5658         /* uart class */
5659         &omap44xx_uart1_hwmod,
5660         &omap44xx_uart2_hwmod,
5661         &omap44xx_uart3_hwmod,
5662         &omap44xx_uart4_hwmod,
5663
5664         /* usb host class */
5665         &omap44xx_usb_host_hs_hwmod,
5666         &omap44xx_usb_tll_hs_hwmod,
5667
5668         /* usb_otg_hs class */
5669         &omap44xx_usb_otg_hs_hwmod,
5670
5671         /* wd_timer class */
5672         &omap44xx_wd_timer2_hwmod,
5673         &omap44xx_wd_timer3_hwmod,
5674         NULL,
5675 };
5676
5677 int __init omap44xx_hwmod_init(void)
5678 {
5679         return omap_hwmod_register(omap44xx_hwmods);
5680 }
5681