arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /* Backward references (IPs with Bus Master capability) */
  50 static struct omap_hwmod omap44xx_aess_hwmod;
  51 static struct omap_hwmod omap44xx_dma_system_hwmod;
  52 static struct omap_hwmod omap44xx_dmm_hwmod;
  53 static struct omap_hwmod omap44xx_dsp_hwmod;
  54 static struct omap_hwmod omap44xx_dss_hwmod;
  55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  56 static struct omap_hwmod omap44xx_hsi_hwmod;
  57 static struct omap_hwmod omap44xx_ipu_hwmod;
  58 static struct omap_hwmod omap44xx_iss_hwmod;
  59 static struct omap_hwmod omap44xx_iva_hwmod;
  60 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  62 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  63 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  64 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  65 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  66 static struct omap_hwmod omap44xx_l4_per_hwmod;
  67 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  68 static struct omap_hwmod omap44xx_mmc1_hwmod;
  69 static struct omap_hwmod omap44xx_mmc2_hwmod;
  70 static struct omap_hwmod omap44xx_mpu_hwmod;
  71 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  72 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  73 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
  74 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
  75
  76 /*
  77  * Interconnects omap_hwmod structures
  78  * hwmods that compose the global OMAP interconnect
  79  */
  80
  81 /*
  82  * 'dmm' class
  83  * instance(s): dmm
  84  */
  85 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  86         .name   = "dmm",
  87 };
  88
  89 /* dmm */
  90 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  91         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  92         { .irq = -1 }
  93 };
  94
  95 /* l3_main_1 -> dmm */
  96 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  97         .master         = &omap44xx_l3_main_1_hwmod,
  98         .slave          = &omap44xx_dmm_hwmod,
  99         .clk            = "l3_div_ck",
 100         .user           = OCP_USER_SDMA,
 101 };
 102
 103 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 104         {
 105                 .pa_start       = 0x4e000000,
 106                 .pa_end         = 0x4e0007ff,
 107                 .flags          = ADDR_TYPE_RT
 108         },
 109         { }
 110 };
 111
 112 /* mpu -> dmm */
 113 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 114         .master         = &omap44xx_mpu_hwmod,
 115         .slave          = &omap44xx_dmm_hwmod,
 116         .clk            = "l3_div_ck",
 117         .addr           = omap44xx_dmm_addrs,
 118         .user           = OCP_USER_MPU,
 119 };
 120
 121 static struct omap_hwmod omap44xx_dmm_hwmod = {
 122         .name           = "dmm",
 123         .class          = &omap44xx_dmm_hwmod_class,
 124         .clkdm_name     = "l3_emif_clkdm",
 125         .prcm = {
 126                 .omap4 = {
 127                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 128                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 129                 },
 130         },
 131         .mpu_irqs       = omap44xx_dmm_irqs,
 132 };
 133
 134 /*
 135  * 'emif_fw' class
 136  * instance(s): emif_fw
 137  */
 138 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 139         .name   = "emif_fw",
 140 };
 141
 142 /* emif_fw */
 143 /* dmm -> emif_fw */
 144 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 145         .master         = &omap44xx_dmm_hwmod,
 146         .slave          = &omap44xx_emif_fw_hwmod,
 147         .clk            = "l3_div_ck",
 148         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 149 };
 150
 151 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 152         {
 153                 .pa_start       = 0x4a20c000,
 154                 .pa_end         = 0x4a20c0ff,
 155                 .flags          = ADDR_TYPE_RT
 156         },
 157         { }
 158 };
 159
 160 /* l4_cfg -> emif_fw */
 161 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 162         .master         = &omap44xx_l4_cfg_hwmod,
 163         .slave          = &omap44xx_emif_fw_hwmod,
 164         .clk            = "l4_div_ck",
 165         .addr           = omap44xx_emif_fw_addrs,
 166         .user           = OCP_USER_MPU,
 167 };
 168
 169 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 170         .name           = "emif_fw",
 171         .class          = &omap44xx_emif_fw_hwmod_class,
 172         .clkdm_name     = "l3_emif_clkdm",
 173         .prcm = {
 174                 .omap4 = {
 175                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 176                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 177                 },
 178         },
 179 };
 180
 181 /*
 182  * 'l3' class
 183  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 184  */
 185 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 186         .name   = "l3",
 187 };
 188
 189 /* l3_instr */
 190 /* iva -> l3_instr */
 191 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 192         .master         = &omap44xx_iva_hwmod,
 193         .slave          = &omap44xx_l3_instr_hwmod,
 194         .clk            = "l3_div_ck",
 195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 196 };
 197
 198 /* l3_main_3 -> l3_instr */
 199 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 200         .master         = &omap44xx_l3_main_3_hwmod,
 201         .slave          = &omap44xx_l3_instr_hwmod,
 202         .clk            = "l3_div_ck",
 203         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 204 };
 205
 206 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 207         .name           = "l3_instr",
 208         .class          = &omap44xx_l3_hwmod_class,
 209         .clkdm_name     = "l3_instr_clkdm",
 210         .prcm = {
 211                 .omap4 = {
 212                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 213                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 214                         .modulemode   = MODULEMODE_HWCTRL,
 215                 },
 216         },
 217 };
 218
 219 /* l3_main_1 */
 220 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 221         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 222         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 223         { .irq = -1 }
 224 };
 225
 226 /* dsp -> l3_main_1 */
 227 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 228         .master         = &omap44xx_dsp_hwmod,
 229         .slave          = &omap44xx_l3_main_1_hwmod,
 230         .clk            = "l3_div_ck",
 231         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 232 };
 233
 234 /* dss -> l3_main_1 */
 235 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 236         .master         = &omap44xx_dss_hwmod,
 237         .slave          = &omap44xx_l3_main_1_hwmod,
 238         .clk            = "l3_div_ck",
 239         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 240 };
 241
 242 /* l3_main_2 -> l3_main_1 */
 243 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 244         .master         = &omap44xx_l3_main_2_hwmod,
 245         .slave          = &omap44xx_l3_main_1_hwmod,
 246         .clk            = "l3_div_ck",
 247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 248 };
 249
 250 /* l4_cfg -> l3_main_1 */
 251 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 252         .master         = &omap44xx_l4_cfg_hwmod,
 253         .slave          = &omap44xx_l3_main_1_hwmod,
 254         .clk            = "l4_div_ck",
 255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 256 };
 257
 258 /* mmc1 -> l3_main_1 */
 259 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 260         .master         = &omap44xx_mmc1_hwmod,
 261         .slave          = &omap44xx_l3_main_1_hwmod,
 262         .clk            = "l3_div_ck",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* mmc2 -> l3_main_1 */
 267 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 268         .master         = &omap44xx_mmc2_hwmod,
 269         .slave          = &omap44xx_l3_main_1_hwmod,
 270         .clk            = "l3_div_ck",
 271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 272 };
 273
 274 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 275         {
 276                 .pa_start       = 0x44000000,
 277                 .pa_end         = 0x44000fff,
 278                 .flags          = ADDR_TYPE_RT
 279         },
 280         { }
 281 };
 282
 283 /* mpu -> l3_main_1 */
 284 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 285         .master         = &omap44xx_mpu_hwmod,
 286         .slave          = &omap44xx_l3_main_1_hwmod,
 287         .clk            = "l3_div_ck",
 288         .addr           = omap44xx_l3_main_1_addrs,
 289         .user           = OCP_USER_MPU,
 290 };
 291
 292 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 293         .name           = "l3_main_1",
 294         .class          = &omap44xx_l3_hwmod_class,
 295         .clkdm_name     = "l3_1_clkdm",
 296         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 297         .prcm = {
 298                 .omap4 = {
 299                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 300                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 301                 },
 302         },
 303 };
 304
 305 /* l3_main_2 */
 306 /* dma_system -> l3_main_2 */
 307 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 308         .master         = &omap44xx_dma_system_hwmod,
 309         .slave          = &omap44xx_l3_main_2_hwmod,
 310         .clk            = "l3_div_ck",
 311         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 312 };
 313
 314 /* hsi -> l3_main_2 */
 315 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 316         .master         = &omap44xx_hsi_hwmod,
 317         .slave          = &omap44xx_l3_main_2_hwmod,
 318         .clk            = "l3_div_ck",
 319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 320 };
 321
 322 /* ipu -> l3_main_2 */
 323 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 324         .master         = &omap44xx_ipu_hwmod,
 325         .slave          = &omap44xx_l3_main_2_hwmod,
 326         .clk            = "l3_div_ck",
 327         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 328 };
 329
 330 /* iss -> l3_main_2 */
 331 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 332         .master         = &omap44xx_iss_hwmod,
 333         .slave          = &omap44xx_l3_main_2_hwmod,
 334         .clk            = "l3_div_ck",
 335         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 336 };
 337
 338 /* iva -> l3_main_2 */
 339 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 340         .master         = &omap44xx_iva_hwmod,
 341         .slave          = &omap44xx_l3_main_2_hwmod,
 342         .clk            = "l3_div_ck",
 343         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 344 };
 345
 346 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 347         {
 348                 .pa_start       = 0x44800000,
 349                 .pa_end         = 0x44801fff,
 350                 .flags          = ADDR_TYPE_RT
 351         },
 352         { }
 353 };
 354
 355 /* l3_main_1 -> l3_main_2 */
 356 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 357         .master         = &omap44xx_l3_main_1_hwmod,
 358         .slave          = &omap44xx_l3_main_2_hwmod,
 359         .clk            = "l3_div_ck",
 360         .addr           = omap44xx_l3_main_2_addrs,
 361         .user           = OCP_USER_MPU,
 362 };
 363
 364 /* l4_cfg -> l3_main_2 */
 365 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 366         .master         = &omap44xx_l4_cfg_hwmod,
 367         .slave          = &omap44xx_l3_main_2_hwmod,
 368         .clk            = "l4_div_ck",
 369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 370 };
 371
 372 /* usb_otg_hs -> l3_main_2 */
 373 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 374         .master         = &omap44xx_usb_otg_hs_hwmod,
 375         .slave          = &omap44xx_l3_main_2_hwmod,
 376         .clk            = "l3_div_ck",
 377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 378 };
 379
 380 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 381         .name           = "l3_main_2",
 382         .class          = &omap44xx_l3_hwmod_class,
 383         .clkdm_name     = "l3_2_clkdm",
 384         .prcm = {
 385                 .omap4 = {
 386                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 387                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 388                 },
 389         },
 390 };
 391
 392 /* l3_main_3 */
 393 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 394         {
 395                 .pa_start       = 0x45000000,
 396                 .pa_end         = 0x45000fff,
 397                 .flags          = ADDR_TYPE_RT
 398         },
 399         { }
 400 };
 401
 402 /* l3_main_1 -> l3_main_3 */
 403 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 404         .master         = &omap44xx_l3_main_1_hwmod,
 405         .slave          = &omap44xx_l3_main_3_hwmod,
 406         .clk            = "l3_div_ck",
 407         .addr           = omap44xx_l3_main_3_addrs,
 408         .user           = OCP_USER_MPU,
 409 };
 410
 411 /* l3_main_2 -> l3_main_3 */
 412 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 413         .master         = &omap44xx_l3_main_2_hwmod,
 414         .slave          = &omap44xx_l3_main_3_hwmod,
 415         .clk            = "l3_div_ck",
 416         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 417 };
 418
 419 /* l4_cfg -> l3_main_3 */
 420 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 421         .master         = &omap44xx_l4_cfg_hwmod,
 422         .slave          = &omap44xx_l3_main_3_hwmod,
 423         .clk            = "l4_div_ck",
 424         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 425 };
 426
 427 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 428         .name           = "l3_main_3",
 429         .class          = &omap44xx_l3_hwmod_class,
 430         .clkdm_name     = "l3_instr_clkdm",
 431         .prcm = {
 432                 .omap4 = {
 433                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 434                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 435                         .modulemode   = MODULEMODE_HWCTRL,
 436                 },
 437         },
 438 };
 439
 440 /*
 441  * 'l4' class
 442  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 443  */
 444 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 445         .name   = "l4",
 446 };
 447
 448 /* l4_abe */
 449 /* aess -> l4_abe */
 450 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 451         .master         = &omap44xx_aess_hwmod,
 452         .slave          = &omap44xx_l4_abe_hwmod,
 453         .clk            = "ocp_abe_iclk",
 454         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 455 };
 456
 457 /* dsp -> l4_abe */
 458 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 459         .master         = &omap44xx_dsp_hwmod,
 460         .slave          = &omap44xx_l4_abe_hwmod,
 461         .clk            = "ocp_abe_iclk",
 462         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 463 };
 464
 465 /* l3_main_1 -> l4_abe */
 466 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 467         .master         = &omap44xx_l3_main_1_hwmod,
 468         .slave          = &omap44xx_l4_abe_hwmod,
 469         .clk            = "l3_div_ck",
 470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 471 };
 472
 473 /* mpu -> l4_abe */
 474 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 475         .master         = &omap44xx_mpu_hwmod,
 476         .slave          = &omap44xx_l4_abe_hwmod,
 477         .clk            = "ocp_abe_iclk",
 478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 479 };
 480
 481 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 482         .name           = "l4_abe",
 483         .class          = &omap44xx_l4_hwmod_class,
 484         .clkdm_name     = "abe_clkdm",
 485         .prcm = {
 486                 .omap4 = {
 487                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 488                 },
 489         },
 490 };
 491
 492 /* l4_cfg */
 493 /* l3_main_1 -> l4_cfg */
 494 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 495         .master         = &omap44xx_l3_main_1_hwmod,
 496         .slave          = &omap44xx_l4_cfg_hwmod,
 497         .clk            = "l3_div_ck",
 498         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 499 };
 500
 501 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 502         .name           = "l4_cfg",
 503         .class          = &omap44xx_l4_hwmod_class,
 504         .clkdm_name     = "l4_cfg_clkdm",
 505         .prcm = {
 506                 .omap4 = {
 507                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 508                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 509                 },
 510         },
 511 };
 512
 513 /* l4_per */
 514 /* l3_main_2 -> l4_per */
 515 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 516         .master         = &omap44xx_l3_main_2_hwmod,
 517         .slave          = &omap44xx_l4_per_hwmod,
 518         .clk            = "l3_div_ck",
 519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 520 };
 521
 522 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 523         .name           = "l4_per",
 524         .class          = &omap44xx_l4_hwmod_class,
 525         .clkdm_name     = "l4_per_clkdm",
 526         .prcm = {
 527                 .omap4 = {
 528                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 529                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 530                 },
 531         },
 532 };
 533
 534 /* l4_wkup */
 535 /* l4_cfg -> l4_wkup */
 536 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 537         .master         = &omap44xx_l4_cfg_hwmod,
 538         .slave          = &omap44xx_l4_wkup_hwmod,
 539         .clk            = "l4_div_ck",
 540         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 541 };
 542
 543 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 544         .name           = "l4_wkup",
 545         .class          = &omap44xx_l4_hwmod_class,
 546         .clkdm_name     = "l4_wkup_clkdm",
 547         .prcm = {
 548                 .omap4 = {
 549                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 550                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 551                 },
 552         },
 553 };
 554
 555 /*
 556  * 'mpu_bus' class
 557  * instance(s): mpu_private
 558  */
 559 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 560         .name   = "mpu_bus",
 561 };
 562
 563 /* mpu_private */
 564 /* mpu -> mpu_private */
 565 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 566         .master         = &omap44xx_mpu_hwmod,
 567         .slave          = &omap44xx_mpu_private_hwmod,
 568         .clk            = "l3_div_ck",
 569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 570 };
 571
 572 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 573         .name           = "mpu_private",
 574         .class          = &omap44xx_mpu_bus_hwmod_class,
 575         .clkdm_name     = "mpuss_clkdm",
 576 };
 577
 578 /*
 579  * Modules omap_hwmod structures
 580  *
 581  * The following IPs are excluded for the moment because:
 582  * - They do not need an explicit SW control using omap_hwmod API.
 583  * - They still need to be validated with the driver
 584  *   properly adapted to omap_hwmod / omap_device
 585  *
 586  *  c2c
 587  *  c2c_target_fw
 588  *  cm_core
 589  *  cm_core_aon
 590  *  ctrl_module_core
 591  *  ctrl_module_pad_core
 592  *  ctrl_module_pad_wkup
 593  *  ctrl_module_wkup
 594  *  debugss
 595  *  efuse_ctrl_cust
 596  *  efuse_ctrl_std
 597  *  elm
 598  *  emif1
 599  *  emif2
 600  *  fdif
 601  *  gpmc
 602  *  gpu
 603  *  hdq1w
 604  *  mcasp
 605  *  mpu_c0
 606  *  mpu_c1
 607  *  ocmc_ram
 608  *  ocp2scp_usb_phy
 609  *  ocp_wp_noc
 610  *  prcm_mpu
 611  *  prm
 612  *  scrm
 613  *  sl2if
 614  *  slimbus1
 615  *  slimbus2
 616  *  usb_host_fs
 617  *  usb_host_hs
 618  *  usb_phy_cm
 619  *  usb_tll_hs
 620  *  usim
 621  */
 622
 623 /*
 624  * 'aess' class
 625  * audio engine sub system
 626  */
 627
 628 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 629         .rev_offs       = 0x0000,
 630         .sysc_offs      = 0x0010,
 631         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 632         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 633                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 634                            MSTANDBY_SMART_WKUP),
 635         .sysc_fields    = &omap_hwmod_sysc_type2,
 636 };
 637
 638 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 639         .name   = "aess",
 640         .sysc   = &omap44xx_aess_sysc,
 641 };
 642
 643 /* aess */
 644 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 645         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 646         { .irq = -1 }
 647 };
 648
 649 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 650         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 651         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 652         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 653         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 654         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 655         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 656         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 657         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 658         { .dma_req = -1 }
 659 };
 660
 661 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 662         {
 663                 .pa_start       = 0x401f1000,
 664                 .pa_end         = 0x401f13ff,
 665                 .flags          = ADDR_TYPE_RT
 666         },
 667         { }
 668 };
 669
 670 /* l4_abe -> aess */
 671 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 672         .master         = &omap44xx_l4_abe_hwmod,
 673         .slave          = &omap44xx_aess_hwmod,
 674         .clk            = "ocp_abe_iclk",
 675         .addr           = omap44xx_aess_addrs,
 676         .user           = OCP_USER_MPU,
 677 };
 678
 679 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 680         {
 681                 .pa_start       = 0x490f1000,
 682                 .pa_end         = 0x490f13ff,
 683                 .flags          = ADDR_TYPE_RT
 684         },
 685         { }
 686 };
 687
 688 /* l4_abe -> aess (dma) */
 689 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 690         .master         = &omap44xx_l4_abe_hwmod,
 691         .slave          = &omap44xx_aess_hwmod,
 692         .clk            = "ocp_abe_iclk",
 693         .addr           = omap44xx_aess_dma_addrs,
 694         .user           = OCP_USER_SDMA,
 695 };
 696
 697 static struct omap_hwmod omap44xx_aess_hwmod = {
 698         .name           = "aess",
 699         .class          = &omap44xx_aess_hwmod_class,
 700         .clkdm_name     = "abe_clkdm",
 701         .mpu_irqs       = omap44xx_aess_irqs,
 702         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 703         .main_clk       = "aess_fck",
 704         .prcm = {
 705                 .omap4 = {
 706                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 707                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 708                         .modulemode   = MODULEMODE_SWCTRL,
 709                 },
 710         },
 711 };
 712
 713 /*
 714  * 'counter' class
 715  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 716  */
 717
 718 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 719         .rev_offs       = 0x0000,
 720         .sysc_offs      = 0x0004,
 721         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 722         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 723                            SIDLE_SMART_WKUP),
 724         .sysc_fields    = &omap_hwmod_sysc_type1,
 725 };
 726
 727 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 728         .name   = "counter",
 729         .sysc   = &omap44xx_counter_sysc,
 730 };
 731
 732 /* counter_32k */
 733 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 734 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 735         {
 736                 .pa_start       = 0x4a304000,
 737                 .pa_end         = 0x4a30401f,
 738                 .flags          = ADDR_TYPE_RT
 739         },
 740         { }
 741 };
 742
 743 /* l4_wkup -> counter_32k */
 744 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 745         .master         = &omap44xx_l4_wkup_hwmod,
 746         .slave          = &omap44xx_counter_32k_hwmod,
 747         .clk            = "l4_wkup_clk_mux_ck",
 748         .addr           = omap44xx_counter_32k_addrs,
 749         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 750 };
 751
 752 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 753         .name           = "counter_32k",
 754         .class          = &omap44xx_counter_hwmod_class,
 755         .clkdm_name     = "l4_wkup_clkdm",
 756         .flags          = HWMOD_SWSUP_SIDLE,
 757         .main_clk       = "sys_32k_ck",
 758         .prcm = {
 759                 .omap4 = {
 760                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 761                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 762                 },
 763         },
 764 };
 765
 766 /*
 767  * 'dma' class
 768  * dma controller for data exchange between memory to memory (i.e. internal or
 769  * external memory) and gp peripherals to memory or memory to gp peripherals
 770  */
 771
 772 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 773         .rev_offs       = 0x0000,
 774         .sysc_offs      = 0x002c,
 775         .syss_offs      = 0x0028,
 776         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 777                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 778                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 779                            SYSS_HAS_RESET_STATUS),
 780         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 781                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 782         .sysc_fields    = &omap_hwmod_sysc_type1,
 783 };
 784
 785 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 786         .name   = "dma",
 787         .sysc   = &omap44xx_dma_sysc,
 788 };
 789
 790 /* dma dev_attr */
 791 static struct omap_dma_dev_attr dma_dev_attr = {
 792         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 793                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 794         .lch_count      = 32,
 795 };
 796
 797 /* dma_system */
 798 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 799         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 800         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 801         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 802         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 803         { .irq = -1 }
 804 };
 805
 806 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 807         {
 808                 .pa_start       = 0x4a056000,
 809                 .pa_end         = 0x4a056fff,
 810                 .flags          = ADDR_TYPE_RT
 811         },
 812         { }
 813 };
 814
 815 /* l4_cfg -> dma_system */
 816 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 817         .master         = &omap44xx_l4_cfg_hwmod,
 818         .slave          = &omap44xx_dma_system_hwmod,
 819         .clk            = "l4_div_ck",
 820         .addr           = omap44xx_dma_system_addrs,
 821         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 822 };
 823
 824 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 825         .name           = "dma_system",
 826         .class          = &omap44xx_dma_hwmod_class,
 827         .clkdm_name     = "l3_dma_clkdm",
 828         .mpu_irqs       = omap44xx_dma_system_irqs,
 829         .main_clk       = "l3_div_ck",
 830         .prcm = {
 831                 .omap4 = {
 832                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 833                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 834                 },
 835         },
 836         .dev_attr       = &dma_dev_attr,
 837 };
 838
 839 /*
 840  * 'dmic' class
 841  * digital microphone controller
 842  */
 843
 844 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 845         .rev_offs       = 0x0000,
 846         .sysc_offs      = 0x0010,
 847         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 848                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 849         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 850                            SIDLE_SMART_WKUP),
 851         .sysc_fields    = &omap_hwmod_sysc_type2,
 852 };
 853
 854 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 855         .name   = "dmic",
 856         .sysc   = &omap44xx_dmic_sysc,
 857 };
 858
 859 /* dmic */
 860 static struct omap_hwmod omap44xx_dmic_hwmod;
 861 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 862         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 863         { .irq = -1 }
 864 };
 865
 866 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 867         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 868         { .dma_req = -1 }
 869 };
 870
 871 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 872         {
 873                 .name           = "mpu",
 874                 .pa_start       = 0x4012e000,
 875                 .pa_end         = 0x4012e07f,
 876                 .flags          = ADDR_TYPE_RT
 877         },
 878         { }
 879 };
 880
 881 /* l4_abe -> dmic */
 882 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 883         .master         = &omap44xx_l4_abe_hwmod,
 884         .slave          = &omap44xx_dmic_hwmod,
 885         .clk            = "ocp_abe_iclk",
 886         .addr           = omap44xx_dmic_addrs,
 887         .user           = OCP_USER_MPU,
 888 };
 889
 890 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 891         {
 892                 .name           = "dma",
 893                 .pa_start       = 0x4902e000,
 894                 .pa_end         = 0x4902e07f,
 895                 .flags          = ADDR_TYPE_RT
 896         },
 897         { }
 898 };
 899
 900 /* l4_abe -> dmic (dma) */
 901 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 902         .master         = &omap44xx_l4_abe_hwmod,
 903         .slave          = &omap44xx_dmic_hwmod,
 904         .clk            = "ocp_abe_iclk",
 905         .addr           = omap44xx_dmic_dma_addrs,
 906         .user           = OCP_USER_SDMA,
 907 };
 908
 909 static struct omap_hwmod omap44xx_dmic_hwmod = {
 910         .name           = "dmic",
 911         .class          = &omap44xx_dmic_hwmod_class,
 912         .clkdm_name     = "abe_clkdm",
 913         .mpu_irqs       = omap44xx_dmic_irqs,
 914         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
 915         .main_clk       = "dmic_fck",
 916         .prcm = {
 917                 .omap4 = {
 918                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 919                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 920                         .modulemode   = MODULEMODE_SWCTRL,
 921                 },
 922         },
 923 };
 924
 925 /*
 926  * 'dsp' class
 927  * dsp sub-system
 928  */
 929
 930 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 931         .name   = "dsp",
 932 };
 933
 934 /* dsp */
 935 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 936         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
 937         { .irq = -1 }
 938 };
 939
 940 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 941         { .name = "dsp", .rst_shift = 0 },
 942         { .name = "mmu_cache", .rst_shift = 1 },
 943 };
 944
 945 /* dsp -> iva */
 946 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 947         .master         = &omap44xx_dsp_hwmod,
 948         .slave          = &omap44xx_iva_hwmod,
 949         .clk            = "dpll_iva_m5x2_ck",
 950         .user           = OCP_USER_DSP,
 951 };
 952
 953 /* l4_cfg -> dsp */
 954 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
 955         .master         = &omap44xx_l4_cfg_hwmod,
 956         .slave          = &omap44xx_dsp_hwmod,
 957         .clk            = "l4_div_ck",
 958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 959 };
 960
 961 static struct omap_hwmod omap44xx_dsp_hwmod = {
 962         .name           = "dsp",
 963         .class          = &omap44xx_dsp_hwmod_class,
 964         .clkdm_name     = "tesla_clkdm",
 965         .mpu_irqs       = omap44xx_dsp_irqs,
 966         .rst_lines      = omap44xx_dsp_resets,
 967         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
 968         .main_clk       = "dsp_fck",
 969         .prcm = {
 970                 .omap4 = {
 971                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 972                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 973                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 974                         .modulemode   = MODULEMODE_HWCTRL,
 975                 },
 976         },
 977 };
 978
 979 /*
 980  * 'dss' class
 981  * display sub-system
 982  */
 983
 984 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 985         .rev_offs       = 0x0000,
 986         .syss_offs      = 0x0014,
 987         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 988 };
 989
 990 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 991         .name   = "dss",
 992         .sysc   = &omap44xx_dss_sysc,
 993         .reset  = omap_dss_reset,
 994 };
 995
 996 /* dss */
 997 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
 998         {
 999                 .pa_start       = 0x58000000,
1000                 .pa_end         = 0x5800007f,
1001                 .flags          = ADDR_TYPE_RT
1002         },
1003         { }
1004 };
1005
1006 /* l3_main_2 -> dss */
1007 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1008         .master         = &omap44xx_l3_main_2_hwmod,
1009         .slave          = &omap44xx_dss_hwmod,
1010         .clk            = "dss_fck",
1011         .addr           = omap44xx_dss_dma_addrs,
1012         .user           = OCP_USER_SDMA,
1013 };
1014
1015 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1016         {
1017                 .pa_start       = 0x48040000,
1018                 .pa_end         = 0x4804007f,
1019                 .flags          = ADDR_TYPE_RT
1020         },
1021         { }
1022 };
1023
1024 /* l4_per -> dss */
1025 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1026         .master         = &omap44xx_l4_per_hwmod,
1027         .slave          = &omap44xx_dss_hwmod,
1028         .clk            = "l4_div_ck",
1029         .addr           = omap44xx_dss_addrs,
1030         .user           = OCP_USER_MPU,
1031 };
1032
1033 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1034         { .role = "sys_clk", .clk = "dss_sys_clk" },
1035         { .role = "tv_clk", .clk = "dss_tv_clk" },
1036         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1037 };
1038
1039 static struct omap_hwmod omap44xx_dss_hwmod = {
1040         .name           = "dss_core",
1041         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1042         .class          = &omap44xx_dss_hwmod_class,
1043         .clkdm_name     = "l3_dss_clkdm",
1044         .main_clk       = "dss_dss_clk",
1045         .prcm = {
1046                 .omap4 = {
1047                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1048                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1049                 },
1050         },
1051         .opt_clks       = dss_opt_clks,
1052         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1053 };
1054
1055 /*
1056  * 'dispc' class
1057  * display controller
1058  */
1059
1060 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1061         .rev_offs       = 0x0000,
1062         .sysc_offs      = 0x0010,
1063         .syss_offs      = 0x0014,
1064         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1065                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1066                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1067                            SYSS_HAS_RESET_STATUS),
1068         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1069                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1070         .sysc_fields    = &omap_hwmod_sysc_type1,
1071 };
1072
1073 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1074         .name   = "dispc",
1075         .sysc   = &omap44xx_dispc_sysc,
1076 };
1077
1078 /* dss_dispc */
1079 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1080 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1081         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1082         { .irq = -1 }
1083 };
1084
1085 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1086         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1087         { .dma_req = -1 }
1088 };
1089
1090 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1091         {
1092                 .pa_start       = 0x58001000,
1093                 .pa_end         = 0x58001fff,
1094                 .flags          = ADDR_TYPE_RT
1095         },
1096         { }
1097 };
1098
1099 /* l3_main_2 -> dss_dispc */
1100 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1101         .master         = &omap44xx_l3_main_2_hwmod,
1102         .slave          = &omap44xx_dss_dispc_hwmod,
1103         .clk            = "dss_fck",
1104         .addr           = omap44xx_dss_dispc_dma_addrs,
1105         .user           = OCP_USER_SDMA,
1106 };
1107
1108 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1109         {
1110                 .pa_start       = 0x48041000,
1111                 .pa_end         = 0x48041fff,
1112                 .flags          = ADDR_TYPE_RT
1113         },
1114         { }
1115 };
1116
1117 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1118         .manager_count          = 3,
1119         .has_framedonetv_irq    = 1
1120 };
1121
1122 /* l4_per -> dss_dispc */
1123 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1124         .master         = &omap44xx_l4_per_hwmod,
1125         .slave          = &omap44xx_dss_dispc_hwmod,
1126         .clk            = "l4_div_ck",
1127         .addr           = omap44xx_dss_dispc_addrs,
1128         .user           = OCP_USER_MPU,
1129 };
1130
1131 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1132         .name           = "dss_dispc",
1133         .class          = &omap44xx_dispc_hwmod_class,
1134         .clkdm_name     = "l3_dss_clkdm",
1135         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1136         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1137         .main_clk       = "dss_dss_clk",
1138         .prcm = {
1139                 .omap4 = {
1140                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1141                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1142                 },
1143         },
1144         .dev_attr       = &omap44xx_dss_dispc_dev_attr
1145 };
1146
1147 /*
1148  * 'dsi' class
1149  * display serial interface controller
1150  */
1151
1152 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1153         .rev_offs       = 0x0000,
1154         .sysc_offs      = 0x0010,
1155         .syss_offs      = 0x0014,
1156         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1157                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1158                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1160         .sysc_fields    = &omap_hwmod_sysc_type1,
1161 };
1162
1163 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1164         .name   = "dsi",
1165         .sysc   = &omap44xx_dsi_sysc,
1166 };
1167
1168 /* dss_dsi1 */
1169 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1170 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1171         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1172         { .irq = -1 }
1173 };
1174
1175 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1176         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1177         { .dma_req = -1 }
1178 };
1179
1180 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1181         {
1182                 .pa_start       = 0x58004000,
1183                 .pa_end         = 0x580041ff,
1184                 .flags          = ADDR_TYPE_RT
1185         },
1186         { }
1187 };
1188
1189 /* l3_main_2 -> dss_dsi1 */
1190 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1191         .master         = &omap44xx_l3_main_2_hwmod,
1192         .slave          = &omap44xx_dss_dsi1_hwmod,
1193         .clk            = "dss_fck",
1194         .addr           = omap44xx_dss_dsi1_dma_addrs,
1195         .user           = OCP_USER_SDMA,
1196 };
1197
1198 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1199         {
1200                 .pa_start       = 0x48044000,
1201                 .pa_end         = 0x480441ff,
1202                 .flags          = ADDR_TYPE_RT
1203         },
1204         { }
1205 };
1206
1207 /* l4_per -> dss_dsi1 */
1208 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1209         .master         = &omap44xx_l4_per_hwmod,
1210         .slave          = &omap44xx_dss_dsi1_hwmod,
1211         .clk            = "l4_div_ck",
1212         .addr           = omap44xx_dss_dsi1_addrs,
1213         .user           = OCP_USER_MPU,
1214 };
1215
1216 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1217         { .role = "sys_clk", .clk = "dss_sys_clk" },
1218 };
1219
1220 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1221         .name           = "dss_dsi1",
1222         .class          = &omap44xx_dsi_hwmod_class,
1223         .clkdm_name     = "l3_dss_clkdm",
1224         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1225         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1226         .main_clk       = "dss_dss_clk",
1227         .prcm = {
1228                 .omap4 = {
1229                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1230                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1231                 },
1232         },
1233         .opt_clks       = dss_dsi1_opt_clks,
1234         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1235 };
1236
1237 /* dss_dsi2 */
1238 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1239 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1240         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1241         { .irq = -1 }
1242 };
1243
1244 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1245         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1246         { .dma_req = -1 }
1247 };
1248
1249 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1250         {
1251                 .pa_start       = 0x58005000,
1252                 .pa_end         = 0x580051ff,
1253                 .flags          = ADDR_TYPE_RT
1254         },
1255         { }
1256 };
1257
1258 /* l3_main_2 -> dss_dsi2 */
1259 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1260         .master         = &omap44xx_l3_main_2_hwmod,
1261         .slave          = &omap44xx_dss_dsi2_hwmod,
1262         .clk            = "dss_fck",
1263         .addr           = omap44xx_dss_dsi2_dma_addrs,
1264         .user           = OCP_USER_SDMA,
1265 };
1266
1267 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1268         {
1269                 .pa_start       = 0x48045000,
1270                 .pa_end         = 0x480451ff,
1271                 .flags          = ADDR_TYPE_RT
1272         },
1273         { }
1274 };
1275
1276 /* l4_per -> dss_dsi2 */
1277 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1278         .master         = &omap44xx_l4_per_hwmod,
1279         .slave          = &omap44xx_dss_dsi2_hwmod,
1280         .clk            = "l4_div_ck",
1281         .addr           = omap44xx_dss_dsi2_addrs,
1282         .user           = OCP_USER_MPU,
1283 };
1284
1285 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1286         { .role = "sys_clk", .clk = "dss_sys_clk" },
1287 };
1288
1289 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1290         .name           = "dss_dsi2",
1291         .class          = &omap44xx_dsi_hwmod_class,
1292         .clkdm_name     = "l3_dss_clkdm",
1293         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1294         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1295         .main_clk       = "dss_dss_clk",
1296         .prcm = {
1297                 .omap4 = {
1298                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1299                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1300                 },
1301         },
1302         .opt_clks       = dss_dsi2_opt_clks,
1303         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1304 };
1305
1306 /*
1307  * 'hdmi' class
1308  * hdmi controller
1309  */
1310
1311 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1312         .rev_offs       = 0x0000,
1313         .sysc_offs      = 0x0010,
1314         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1315                            SYSC_HAS_SOFTRESET),
1316         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1317                            SIDLE_SMART_WKUP),
1318         .sysc_fields    = &omap_hwmod_sysc_type2,
1319 };
1320
1321 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1322         .name   = "hdmi",
1323         .sysc   = &omap44xx_hdmi_sysc,
1324 };
1325
1326 /* dss_hdmi */
1327 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1328 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1329         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1330         { .irq = -1 }
1331 };
1332
1333 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1334         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1335         { .dma_req = -1 }
1336 };
1337
1338 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1339         {
1340                 .pa_start       = 0x58006000,
1341                 .pa_end         = 0x58006fff,
1342                 .flags          = ADDR_TYPE_RT
1343         },
1344         { }
1345 };
1346
1347 /* l3_main_2 -> dss_hdmi */
1348 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1349         .master         = &omap44xx_l3_main_2_hwmod,
1350         .slave          = &omap44xx_dss_hdmi_hwmod,
1351         .clk            = "dss_fck",
1352         .addr           = omap44xx_dss_hdmi_dma_addrs,
1353         .user           = OCP_USER_SDMA,
1354 };
1355
1356 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1357         {
1358                 .pa_start       = 0x48046000,
1359                 .pa_end         = 0x48046fff,
1360                 .flags          = ADDR_TYPE_RT
1361         },
1362         { }
1363 };
1364
1365 /* l4_per -> dss_hdmi */
1366 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1367         .master         = &omap44xx_l4_per_hwmod,
1368         .slave          = &omap44xx_dss_hdmi_hwmod,
1369         .clk            = "l4_div_ck",
1370         .addr           = omap44xx_dss_hdmi_addrs,
1371         .user           = OCP_USER_MPU,
1372 };
1373
1374 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1375         { .role = "sys_clk", .clk = "dss_sys_clk" },
1376 };
1377
1378 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1379         .name           = "dss_hdmi",
1380         .class          = &omap44xx_hdmi_hwmod_class,
1381         .clkdm_name     = "l3_dss_clkdm",
1382         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1383         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1384         .main_clk       = "dss_48mhz_clk",
1385         .prcm = {
1386                 .omap4 = {
1387                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1388                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1389                 },
1390         },
1391         .opt_clks       = dss_hdmi_opt_clks,
1392         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1393 };
1394
1395 /*
1396  * 'rfbi' class
1397  * remote frame buffer interface
1398  */
1399
1400 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1401         .rev_offs       = 0x0000,
1402         .sysc_offs      = 0x0010,
1403         .syss_offs      = 0x0014,
1404         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1405                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1407         .sysc_fields    = &omap_hwmod_sysc_type1,
1408 };
1409
1410 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1411         .name   = "rfbi",
1412         .sysc   = &omap44xx_rfbi_sysc,
1413 };
1414
1415 /* dss_rfbi */
1416 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1417 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1418         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1419         { .dma_req = -1 }
1420 };
1421
1422 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1423         {
1424                 .pa_start       = 0x58002000,
1425                 .pa_end         = 0x580020ff,
1426                 .flags          = ADDR_TYPE_RT
1427         },
1428         { }
1429 };
1430
1431 /* l3_main_2 -> dss_rfbi */
1432 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1433         .master         = &omap44xx_l3_main_2_hwmod,
1434         .slave          = &omap44xx_dss_rfbi_hwmod,
1435         .clk            = "dss_fck",
1436         .addr           = omap44xx_dss_rfbi_dma_addrs,
1437         .user           = OCP_USER_SDMA,
1438 };
1439
1440 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1441         {
1442                 .pa_start       = 0x48042000,
1443                 .pa_end         = 0x480420ff,
1444                 .flags          = ADDR_TYPE_RT
1445         },
1446         { }
1447 };
1448
1449 /* l4_per -> dss_rfbi */
1450 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1451         .master         = &omap44xx_l4_per_hwmod,
1452         .slave          = &omap44xx_dss_rfbi_hwmod,
1453         .clk            = "l4_div_ck",
1454         .addr           = omap44xx_dss_rfbi_addrs,
1455         .user           = OCP_USER_MPU,
1456 };
1457
1458 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1459         { .role = "ick", .clk = "dss_fck" },
1460 };
1461
1462 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1463         .name           = "dss_rfbi",
1464         .class          = &omap44xx_rfbi_hwmod_class,
1465         .clkdm_name     = "l3_dss_clkdm",
1466         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1467         .main_clk       = "dss_dss_clk",
1468         .prcm = {
1469                 .omap4 = {
1470                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1471                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1472                 },
1473         },
1474         .opt_clks       = dss_rfbi_opt_clks,
1475         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1476 };
1477
1478 /*
1479  * 'venc' class
1480  * video encoder
1481  */
1482
1483 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1484         .name   = "venc",
1485 };
1486
1487 /* dss_venc */
1488 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1489 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1490         {
1491                 .pa_start       = 0x58003000,
1492                 .pa_end         = 0x580030ff,
1493                 .flags          = ADDR_TYPE_RT
1494         },
1495         { }
1496 };
1497
1498 /* l3_main_2 -> dss_venc */
1499 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1500         .master         = &omap44xx_l3_main_2_hwmod,
1501         .slave          = &omap44xx_dss_venc_hwmod,
1502         .clk            = "dss_fck",
1503         .addr           = omap44xx_dss_venc_dma_addrs,
1504         .user           = OCP_USER_SDMA,
1505 };
1506
1507 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1508         {
1509                 .pa_start       = 0x48043000,
1510                 .pa_end         = 0x480430ff,
1511                 .flags          = ADDR_TYPE_RT
1512         },
1513         { }
1514 };
1515
1516 /* l4_per -> dss_venc */
1517 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1518         .master         = &omap44xx_l4_per_hwmod,
1519         .slave          = &omap44xx_dss_venc_hwmod,
1520         .clk            = "l4_div_ck",
1521         .addr           = omap44xx_dss_venc_addrs,
1522         .user           = OCP_USER_MPU,
1523 };
1524
1525 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1526         .name           = "dss_venc",
1527         .class          = &omap44xx_venc_hwmod_class,
1528         .clkdm_name     = "l3_dss_clkdm",
1529         .main_clk       = "dss_tv_clk",
1530         .prcm = {
1531                 .omap4 = {
1532                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1533                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1534                 },
1535         },
1536 };
1537
1538 /*
1539  * 'gpio' class
1540  * general purpose io module
1541  */
1542
1543 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1544         .rev_offs       = 0x0000,
1545         .sysc_offs      = 0x0010,
1546         .syss_offs      = 0x0114,
1547         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1548                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1549                            SYSS_HAS_RESET_STATUS),
1550         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1551                            SIDLE_SMART_WKUP),
1552         .sysc_fields    = &omap_hwmod_sysc_type1,
1553 };
1554
1555 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1556         .name   = "gpio",
1557         .sysc   = &omap44xx_gpio_sysc,
1558         .rev    = 2,
1559 };
1560
1561 /* gpio dev_attr */
1562 static struct omap_gpio_dev_attr gpio_dev_attr = {
1563         .bank_width     = 32,
1564         .dbck_flag      = true,
1565 };
1566
1567 /* gpio1 */
1568 static struct omap_hwmod omap44xx_gpio1_hwmod;
1569 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1570         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1571         { .irq = -1 }
1572 };
1573
1574 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1575         {
1576                 .pa_start       = 0x4a310000,
1577                 .pa_end         = 0x4a3101ff,
1578                 .flags          = ADDR_TYPE_RT
1579         },
1580         { }
1581 };
1582
1583 /* l4_wkup -> gpio1 */
1584 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1585         .master         = &omap44xx_l4_wkup_hwmod,
1586         .slave          = &omap44xx_gpio1_hwmod,
1587         .clk            = "l4_wkup_clk_mux_ck",
1588         .addr           = omap44xx_gpio1_addrs,
1589         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1590 };
1591
1592 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1593         { .role = "dbclk", .clk = "gpio1_dbclk" },
1594 };
1595
1596 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1597         .name           = "gpio1",
1598         .class          = &omap44xx_gpio_hwmod_class,
1599         .clkdm_name     = "l4_wkup_clkdm",
1600         .mpu_irqs       = omap44xx_gpio1_irqs,
1601         .main_clk       = "gpio1_ick",
1602         .prcm = {
1603                 .omap4 = {
1604                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1605                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1606                         .modulemode   = MODULEMODE_HWCTRL,
1607                 },
1608         },
1609         .opt_clks       = gpio1_opt_clks,
1610         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1611         .dev_attr       = &gpio_dev_attr,
1612 };
1613
1614 /* gpio2 */
1615 static struct omap_hwmod omap44xx_gpio2_hwmod;
1616 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1617         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1618         { .irq = -1 }
1619 };
1620
1621 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1622         {
1623                 .pa_start       = 0x48055000,
1624                 .pa_end         = 0x480551ff,
1625                 .flags          = ADDR_TYPE_RT
1626         },
1627         { }
1628 };
1629
1630 /* l4_per -> gpio2 */
1631 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1632         .master         = &omap44xx_l4_per_hwmod,
1633         .slave          = &omap44xx_gpio2_hwmod,
1634         .clk            = "l4_div_ck",
1635         .addr           = omap44xx_gpio2_addrs,
1636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1637 };
1638
1639 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1640         { .role = "dbclk", .clk = "gpio2_dbclk" },
1641 };
1642
1643 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1644         .name           = "gpio2",
1645         .class          = &omap44xx_gpio_hwmod_class,
1646         .clkdm_name     = "l4_per_clkdm",
1647         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1648         .mpu_irqs       = omap44xx_gpio2_irqs,
1649         .main_clk       = "gpio2_ick",
1650         .prcm = {
1651                 .omap4 = {
1652                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1653                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1654                         .modulemode   = MODULEMODE_HWCTRL,
1655                 },
1656         },
1657         .opt_clks       = gpio2_opt_clks,
1658         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1659         .dev_attr       = &gpio_dev_attr,
1660 };
1661
1662 /* gpio3 */
1663 static struct omap_hwmod omap44xx_gpio3_hwmod;
1664 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1665         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1666         { .irq = -1 }
1667 };
1668
1669 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1670         {
1671                 .pa_start       = 0x48057000,
1672                 .pa_end         = 0x480571ff,
1673                 .flags          = ADDR_TYPE_RT
1674         },
1675         { }
1676 };
1677
1678 /* l4_per -> gpio3 */
1679 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1680         .master         = &omap44xx_l4_per_hwmod,
1681         .slave          = &omap44xx_gpio3_hwmod,
1682         .clk            = "l4_div_ck",
1683         .addr           = omap44xx_gpio3_addrs,
1684         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1685 };
1686
1687 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1688         { .role = "dbclk", .clk = "gpio3_dbclk" },
1689 };
1690
1691 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1692         .name           = "gpio3",
1693         .class          = &omap44xx_gpio_hwmod_class,
1694         .clkdm_name     = "l4_per_clkdm",
1695         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1696         .mpu_irqs       = omap44xx_gpio3_irqs,
1697         .main_clk       = "gpio3_ick",
1698         .prcm = {
1699                 .omap4 = {
1700                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1701                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1702                         .modulemode   = MODULEMODE_HWCTRL,
1703                 },
1704         },
1705         .opt_clks       = gpio3_opt_clks,
1706         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1707         .dev_attr       = &gpio_dev_attr,
1708 };
1709
1710 /* gpio4 */
1711 static struct omap_hwmod omap44xx_gpio4_hwmod;
1712 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1713         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1714         { .irq = -1 }
1715 };
1716
1717 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1718         {
1719                 .pa_start       = 0x48059000,
1720                 .pa_end         = 0x480591ff,
1721                 .flags          = ADDR_TYPE_RT
1722         },
1723         { }
1724 };
1725
1726 /* l4_per -> gpio4 */
1727 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1728         .master         = &omap44xx_l4_per_hwmod,
1729         .slave          = &omap44xx_gpio4_hwmod,
1730         .clk            = "l4_div_ck",
1731         .addr           = omap44xx_gpio4_addrs,
1732         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1733 };
1734
1735 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1736         { .role = "dbclk", .clk = "gpio4_dbclk" },
1737 };
1738
1739 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1740         .name           = "gpio4",
1741         .class          = &omap44xx_gpio_hwmod_class,
1742         .clkdm_name     = "l4_per_clkdm",
1743         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1744         .mpu_irqs       = omap44xx_gpio4_irqs,
1745         .main_clk       = "gpio4_ick",
1746         .prcm = {
1747                 .omap4 = {
1748                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1749                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1750                         .modulemode   = MODULEMODE_HWCTRL,
1751                 },
1752         },
1753         .opt_clks       = gpio4_opt_clks,
1754         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1755         .dev_attr       = &gpio_dev_attr,
1756 };
1757
1758 /* gpio5 */
1759 static struct omap_hwmod omap44xx_gpio5_hwmod;
1760 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1761         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1762         { .irq = -1 }
1763 };
1764
1765 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1766         {
1767                 .pa_start       = 0x4805b000,
1768                 .pa_end         = 0x4805b1ff,
1769                 .flags          = ADDR_TYPE_RT
1770         },
1771         { }
1772 };
1773
1774 /* l4_per -> gpio5 */
1775 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1776         .master         = &omap44xx_l4_per_hwmod,
1777         .slave          = &omap44xx_gpio5_hwmod,
1778         .clk            = "l4_div_ck",
1779         .addr           = omap44xx_gpio5_addrs,
1780         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1781 };
1782
1783 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1784         { .role = "dbclk", .clk = "gpio5_dbclk" },
1785 };
1786
1787 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1788         .name           = "gpio5",
1789         .class          = &omap44xx_gpio_hwmod_class,
1790         .clkdm_name     = "l4_per_clkdm",
1791         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1792         .mpu_irqs       = omap44xx_gpio5_irqs,
1793         .main_clk       = "gpio5_ick",
1794         .prcm = {
1795                 .omap4 = {
1796                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1797                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1798                         .modulemode   = MODULEMODE_HWCTRL,
1799                 },
1800         },
1801         .opt_clks       = gpio5_opt_clks,
1802         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1803         .dev_attr       = &gpio_dev_attr,
1804 };
1805
1806 /* gpio6 */
1807 static struct omap_hwmod omap44xx_gpio6_hwmod;
1808 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1809         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1810         { .irq = -1 }
1811 };
1812
1813 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1814         {
1815                 .pa_start       = 0x4805d000,
1816                 .pa_end         = 0x4805d1ff,
1817                 .flags          = ADDR_TYPE_RT
1818         },
1819         { }
1820 };
1821
1822 /* l4_per -> gpio6 */
1823 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1824         .master         = &omap44xx_l4_per_hwmod,
1825         .slave          = &omap44xx_gpio6_hwmod,
1826         .clk            = "l4_div_ck",
1827         .addr           = omap44xx_gpio6_addrs,
1828         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1829 };
1830
1831 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1832         { .role = "dbclk", .clk = "gpio6_dbclk" },
1833 };
1834
1835 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1836         .name           = "gpio6",
1837         .class          = &omap44xx_gpio_hwmod_class,
1838         .clkdm_name     = "l4_per_clkdm",
1839         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1840         .mpu_irqs       = omap44xx_gpio6_irqs,
1841         .main_clk       = "gpio6_ick",
1842         .prcm = {
1843                 .omap4 = {
1844                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1845                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1846                         .modulemode   = MODULEMODE_HWCTRL,
1847                 },
1848         },
1849         .opt_clks       = gpio6_opt_clks,
1850         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1851         .dev_attr       = &gpio_dev_attr,
1852 };
1853
1854 /*
1855  * 'hsi' class
1856  * mipi high-speed synchronous serial interface (multichannel and full-duplex
1857  * serial if)
1858  */
1859
1860 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1861         .rev_offs       = 0x0000,
1862         .sysc_offs      = 0x0010,
1863         .syss_offs      = 0x0014,
1864         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1865                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1866                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1867         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1868                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1869                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1870         .sysc_fields    = &omap_hwmod_sysc_type1,
1871 };
1872
1873 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1874         .name   = "hsi",
1875         .sysc   = &omap44xx_hsi_sysc,
1876 };
1877
1878 /* hsi */
1879 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
1880         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
1881         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
1882         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
1883         { .irq = -1 }
1884 };
1885
1886 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
1887         {
1888                 .pa_start       = 0x4a058000,
1889                 .pa_end         = 0x4a05bfff,
1890                 .flags          = ADDR_TYPE_RT
1891         },
1892         { }
1893 };
1894
1895 /* l4_cfg -> hsi */
1896 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
1897         .master         = &omap44xx_l4_cfg_hwmod,
1898         .slave          = &omap44xx_hsi_hwmod,
1899         .clk            = "l4_div_ck",
1900         .addr           = omap44xx_hsi_addrs,
1901         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1902 };
1903
1904 static struct omap_hwmod omap44xx_hsi_hwmod = {
1905         .name           = "hsi",
1906         .class          = &omap44xx_hsi_hwmod_class,
1907         .clkdm_name     = "l3_init_clkdm",
1908         .mpu_irqs       = omap44xx_hsi_irqs,
1909         .main_clk       = "hsi_fck",
1910         .prcm = {
1911                 .omap4 = {
1912                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1913                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1914                         .modulemode   = MODULEMODE_HWCTRL,
1915                 },
1916         },
1917 };
1918
1919 /*
1920  * 'i2c' class
1921  * multimaster high-speed i2c controller
1922  */
1923
1924 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1925         .sysc_offs      = 0x0010,
1926         .syss_offs      = 0x0090,
1927         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1928                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1929                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1930         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1931                            SIDLE_SMART_WKUP),
1932         .clockact       = CLOCKACT_TEST_ICLK,
1933         .sysc_fields    = &omap_hwmod_sysc_type1,
1934 };
1935
1936 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1937         .name   = "i2c",
1938         .sysc   = &omap44xx_i2c_sysc,
1939         .rev    = OMAP_I2C_IP_VERSION_2,
1940         .reset  = &omap_i2c_reset,
1941 };
1942
1943 static struct omap_i2c_dev_attr i2c_dev_attr = {
1944         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1945 };
1946
1947 /* i2c1 */
1948 static struct omap_hwmod omap44xx_i2c1_hwmod;
1949 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
1950         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
1951         { .irq = -1 }
1952 };
1953
1954 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
1955         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
1956         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
1957         { .dma_req = -1 }
1958 };
1959
1960 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
1961         {
1962                 .pa_start       = 0x48070000,
1963                 .pa_end         = 0x480700ff,
1964                 .flags          = ADDR_TYPE_RT
1965         },
1966         { }
1967 };
1968
1969 /* l4_per -> i2c1 */
1970 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
1971         .master         = &omap44xx_l4_per_hwmod,
1972         .slave          = &omap44xx_i2c1_hwmod,
1973         .clk            = "l4_div_ck",
1974         .addr           = omap44xx_i2c1_addrs,
1975         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1976 };
1977
1978 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1979         .name           = "i2c1",
1980         .class          = &omap44xx_i2c_hwmod_class,
1981         .clkdm_name     = "l4_per_clkdm",
1982         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1983         .mpu_irqs       = omap44xx_i2c1_irqs,
1984         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
1985         .main_clk       = "i2c1_fck",
1986         .prcm = {
1987                 .omap4 = {
1988                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1989                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1990                         .modulemode   = MODULEMODE_SWCTRL,
1991                 },
1992         },
1993         .dev_attr       = &i2c_dev_attr,
1994 };
1995
1996 /* i2c2 */
1997 static struct omap_hwmod omap44xx_i2c2_hwmod;
1998 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
1999         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2000         { .irq = -1 }
2001 };
2002
2003 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2004         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2005         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2006         { .dma_req = -1 }
2007 };
2008
2009 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2010         {
2011                 .pa_start       = 0x48072000,
2012                 .pa_end         = 0x480720ff,
2013                 .flags          = ADDR_TYPE_RT
2014         },
2015         { }
2016 };
2017
2018 /* l4_per -> i2c2 */
2019 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2020         .master         = &omap44xx_l4_per_hwmod,
2021         .slave          = &omap44xx_i2c2_hwmod,
2022         .clk            = "l4_div_ck",
2023         .addr           = omap44xx_i2c2_addrs,
2024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2025 };
2026
2027 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2028         .name           = "i2c2",
2029         .class          = &omap44xx_i2c_hwmod_class,
2030         .clkdm_name     = "l4_per_clkdm",
2031         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2032         .mpu_irqs       = omap44xx_i2c2_irqs,
2033         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2034         .main_clk       = "i2c2_fck",
2035         .prcm = {
2036                 .omap4 = {
2037                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2038                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2039                         .modulemode   = MODULEMODE_SWCTRL,
2040                 },
2041         },
2042         .dev_attr       = &i2c_dev_attr,
2043 };
2044
2045 /* i2c3 */
2046 static struct omap_hwmod omap44xx_i2c3_hwmod;
2047 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2048         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2049         { .irq = -1 }
2050 };
2051
2052 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2053         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2054         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2055         { .dma_req = -1 }
2056 };
2057
2058 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2059         {
2060                 .pa_start       = 0x48060000,
2061                 .pa_end         = 0x480600ff,
2062                 .flags          = ADDR_TYPE_RT
2063         },
2064         { }
2065 };
2066
2067 /* l4_per -> i2c3 */
2068 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2069         .master         = &omap44xx_l4_per_hwmod,
2070         .slave          = &omap44xx_i2c3_hwmod,
2071         .clk            = "l4_div_ck",
2072         .addr           = omap44xx_i2c3_addrs,
2073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2074 };
2075
2076 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2077         .name           = "i2c3",
2078         .class          = &omap44xx_i2c_hwmod_class,
2079         .clkdm_name     = "l4_per_clkdm",
2080         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2081         .mpu_irqs       = omap44xx_i2c3_irqs,
2082         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2083         .main_clk       = "i2c3_fck",
2084         .prcm = {
2085                 .omap4 = {
2086                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2087                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2088                         .modulemode   = MODULEMODE_SWCTRL,
2089                 },
2090         },
2091         .dev_attr       = &i2c_dev_attr,
2092 };
2093
2094 /* i2c4 */
2095 static struct omap_hwmod omap44xx_i2c4_hwmod;
2096 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2097         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2098         { .irq = -1 }
2099 };
2100
2101 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2102         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2103         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2104         { .dma_req = -1 }
2105 };
2106
2107 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2108         {
2109                 .pa_start       = 0x48350000,
2110                 .pa_end         = 0x483500ff,
2111                 .flags          = ADDR_TYPE_RT
2112         },
2113         { }
2114 };
2115
2116 /* l4_per -> i2c4 */
2117 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2118         .master         = &omap44xx_l4_per_hwmod,
2119         .slave          = &omap44xx_i2c4_hwmod,
2120         .clk            = "l4_div_ck",
2121         .addr           = omap44xx_i2c4_addrs,
2122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124
2125 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2126         .name           = "i2c4",
2127         .class          = &omap44xx_i2c_hwmod_class,
2128         .clkdm_name     = "l4_per_clkdm",
2129         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2130         .mpu_irqs       = omap44xx_i2c4_irqs,
2131         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2132         .main_clk       = "i2c4_fck",
2133         .prcm = {
2134                 .omap4 = {
2135                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2136                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2137                         .modulemode   = MODULEMODE_SWCTRL,
2138                 },
2139         },
2140         .dev_attr       = &i2c_dev_attr,
2141 };
2142
2143 /*
2144  * 'ipu' class
2145  * imaging processor unit
2146  */
2147
2148 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2149         .name   = "ipu",
2150 };
2151
2152 /* ipu */
2153 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2154         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2155         { .irq = -1 }
2156 };
2157
2158 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2159         { .name = "cpu0", .rst_shift = 0 },
2160         { .name = "cpu1", .rst_shift = 1 },
2161         { .name = "mmu_cache", .rst_shift = 2 },
2162 };
2163
2164 /* l3_main_2 -> ipu */
2165 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2166         .master         = &omap44xx_l3_main_2_hwmod,
2167         .slave          = &omap44xx_ipu_hwmod,
2168         .clk            = "l3_div_ck",
2169         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2170 };
2171
2172 static struct omap_hwmod omap44xx_ipu_hwmod = {
2173         .name           = "ipu",
2174         .class          = &omap44xx_ipu_hwmod_class,
2175         .clkdm_name     = "ducati_clkdm",
2176         .mpu_irqs       = omap44xx_ipu_irqs,
2177         .rst_lines      = omap44xx_ipu_resets,
2178         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2179         .main_clk       = "ipu_fck",
2180         .prcm = {
2181                 .omap4 = {
2182                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2183                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2184                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2185                         .modulemode   = MODULEMODE_HWCTRL,
2186                 },
2187         },
2188 };
2189
2190 /*
2191  * 'iss' class
2192  * external images sensor pixel data processor
2193  */
2194
2195 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2196         .rev_offs       = 0x0000,
2197         .sysc_offs      = 0x0010,
2198         /*
2199          * ISS needs 100 OCP clk cycles delay after a softreset before
2200          * accessing sysconfig again.
2201          * The lowest frequency at the moment for L3 bus is 100 MHz, so
2202          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
2203          *
2204          * TODO: Indicate errata when available.
2205          */
2206         .srst_udelay    = 2,
2207         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2208                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2209         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2210                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2211                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2212         .sysc_fields    = &omap_hwmod_sysc_type2,
2213 };
2214
2215 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2216         .name   = "iss",
2217         .sysc   = &omap44xx_iss_sysc,
2218 };
2219
2220 /* iss */
2221 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2222         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2223         { .irq = -1 }
2224 };
2225
2226 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2227         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2228         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2229         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2230         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2231         { .dma_req = -1 }
2232 };
2233
2234 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2235         {
2236                 .pa_start       = 0x52000000,
2237                 .pa_end         = 0x520000ff,
2238                 .flags          = ADDR_TYPE_RT
2239         },
2240         { }
2241 };
2242
2243 /* l3_main_2 -> iss */
2244 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2245         .master         = &omap44xx_l3_main_2_hwmod,
2246         .slave          = &omap44xx_iss_hwmod,
2247         .clk            = "l3_div_ck",
2248         .addr           = omap44xx_iss_addrs,
2249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2250 };
2251
2252 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2253         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2254 };
2255
2256 static struct omap_hwmod omap44xx_iss_hwmod = {
2257         .name           = "iss",
2258         .class          = &omap44xx_iss_hwmod_class,
2259         .clkdm_name     = "iss_clkdm",
2260         .mpu_irqs       = omap44xx_iss_irqs,
2261         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2262         .main_clk       = "iss_fck",
2263         .prcm = {
2264                 .omap4 = {
2265                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2266                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2267                         .modulemode   = MODULEMODE_SWCTRL,
2268                 },
2269         },
2270         .opt_clks       = iss_opt_clks,
2271         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2272 };
2273
2274 /*
2275  * 'iva' class
2276  * multi-standard video encoder/decoder hardware accelerator
2277  */
2278
2279 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2280         .name   = "iva",
2281 };
2282
2283 /* iva */
2284 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2285         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2286         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2287         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2288         { .irq = -1 }
2289 };
2290
2291 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2292         { .name = "seq0", .rst_shift = 0 },
2293         { .name = "seq1", .rst_shift = 1 },
2294         { .name = "logic", .rst_shift = 2 },
2295 };
2296
2297 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2298         {
2299                 .pa_start       = 0x5a000000,
2300                 .pa_end         = 0x5a07ffff,
2301                 .flags          = ADDR_TYPE_RT
2302         },
2303         { }
2304 };
2305
2306 /* l3_main_2 -> iva */
2307 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2308         .master         = &omap44xx_l3_main_2_hwmod,
2309         .slave          = &omap44xx_iva_hwmod,
2310         .clk            = "l3_div_ck",
2311         .addr           = omap44xx_iva_addrs,
2312         .user           = OCP_USER_MPU,
2313 };
2314
2315 static struct omap_hwmod omap44xx_iva_hwmod = {
2316         .name           = "iva",
2317         .class          = &omap44xx_iva_hwmod_class,
2318         .clkdm_name     = "ivahd_clkdm",
2319         .mpu_irqs       = omap44xx_iva_irqs,
2320         .rst_lines      = omap44xx_iva_resets,
2321         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2322         .main_clk       = "iva_fck",
2323         .prcm = {
2324                 .omap4 = {
2325                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2326                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2327                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2328                         .modulemode   = MODULEMODE_HWCTRL,
2329                 },
2330         },
2331 };
2332
2333 /*
2334  * 'kbd' class
2335  * keyboard controller
2336  */
2337
2338 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2339         .rev_offs       = 0x0000,
2340         .sysc_offs      = 0x0010,
2341         .syss_offs      = 0x0014,
2342         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2343                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2344                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2345                            SYSS_HAS_RESET_STATUS),
2346         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2347         .sysc_fields    = &omap_hwmod_sysc_type1,
2348 };
2349
2350 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2351         .name   = "kbd",
2352         .sysc   = &omap44xx_kbd_sysc,
2353 };
2354
2355 /* kbd */
2356 static struct omap_hwmod omap44xx_kbd_hwmod;
2357 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2358         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2359         { .irq = -1 }
2360 };
2361
2362 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2363         {
2364                 .pa_start       = 0x4a31c000,
2365                 .pa_end         = 0x4a31c07f,
2366                 .flags          = ADDR_TYPE_RT
2367         },
2368         { }
2369 };
2370
2371 /* l4_wkup -> kbd */
2372 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2373         .master         = &omap44xx_l4_wkup_hwmod,
2374         .slave          = &omap44xx_kbd_hwmod,
2375         .clk            = "l4_wkup_clk_mux_ck",
2376         .addr           = omap44xx_kbd_addrs,
2377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2378 };
2379
2380 static struct omap_hwmod omap44xx_kbd_hwmod = {
2381         .name           = "kbd",
2382         .class          = &omap44xx_kbd_hwmod_class,
2383         .clkdm_name     = "l4_wkup_clkdm",
2384         .mpu_irqs       = omap44xx_kbd_irqs,
2385         .main_clk       = "kbd_fck",
2386         .prcm = {
2387                 .omap4 = {
2388                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2389                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2390                         .modulemode   = MODULEMODE_SWCTRL,
2391                 },
2392         },
2393 };
2394
2395 /*
2396  * 'mailbox' class
2397  * mailbox module allowing communication between the on-chip processors using a
2398  * queued mailbox-interrupt mechanism.
2399  */
2400
2401 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2402         .rev_offs       = 0x0000,
2403         .sysc_offs      = 0x0010,
2404         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2405                            SYSC_HAS_SOFTRESET),
2406         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2407         .sysc_fields    = &omap_hwmod_sysc_type2,
2408 };
2409
2410 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2411         .name   = "mailbox",
2412         .sysc   = &omap44xx_mailbox_sysc,
2413 };
2414
2415 /* mailbox */
2416 static struct omap_hwmod omap44xx_mailbox_hwmod;
2417 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2418         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2419         { .irq = -1 }
2420 };
2421
2422 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2423         {
2424                 .pa_start       = 0x4a0f4000,
2425                 .pa_end         = 0x4a0f41ff,
2426                 .flags          = ADDR_TYPE_RT
2427         },
2428         { }
2429 };
2430
2431 /* l4_cfg -> mailbox */
2432 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2433         .master         = &omap44xx_l4_cfg_hwmod,
2434         .slave          = &omap44xx_mailbox_hwmod,
2435         .clk            = "l4_div_ck",
2436         .addr           = omap44xx_mailbox_addrs,
2437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2438 };
2439
2440 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2441         .name           = "mailbox",
2442         .class          = &omap44xx_mailbox_hwmod_class,
2443         .clkdm_name     = "l4_cfg_clkdm",
2444         .mpu_irqs       = omap44xx_mailbox_irqs,
2445         .prcm = {
2446                 .omap4 = {
2447                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2448                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2449                 },
2450         },
2451 };
2452
2453 /*
2454  * 'mcbsp' class
2455  * multi channel buffered serial port controller
2456  */
2457
2458 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2459         .sysc_offs      = 0x008c,
2460         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2461                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2462         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2463         .sysc_fields    = &omap_hwmod_sysc_type1,
2464 };
2465
2466 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2467         .name   = "mcbsp",
2468         .sysc   = &omap44xx_mcbsp_sysc,
2469         .rev    = MCBSP_CONFIG_TYPE4,
2470 };
2471
2472 /* mcbsp1 */
2473 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2474 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2475         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2476         { .irq = -1 }
2477 };
2478
2479 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2480         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2481         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2482         { .dma_req = -1 }
2483 };
2484
2485 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2486         {
2487                 .name           = "mpu",
2488                 .pa_start       = 0x40122000,
2489                 .pa_end         = 0x401220ff,
2490                 .flags          = ADDR_TYPE_RT
2491         },
2492         { }
2493 };
2494
2495 /* l4_abe -> mcbsp1 */
2496 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2497         .master         = &omap44xx_l4_abe_hwmod,
2498         .slave          = &omap44xx_mcbsp1_hwmod,
2499         .clk            = "ocp_abe_iclk",
2500         .addr           = omap44xx_mcbsp1_addrs,
2501         .user           = OCP_USER_MPU,
2502 };
2503
2504 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2505         {
2506                 .name           = "dma",
2507                 .pa_start       = 0x49022000,
2508                 .pa_end         = 0x490220ff,
2509                 .flags          = ADDR_TYPE_RT
2510         },
2511         { }
2512 };
2513
2514 /* l4_abe -> mcbsp1 (dma) */
2515 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2516         .master         = &omap44xx_l4_abe_hwmod,
2517         .slave          = &omap44xx_mcbsp1_hwmod,
2518         .clk            = "ocp_abe_iclk",
2519         .addr           = omap44xx_mcbsp1_dma_addrs,
2520         .user           = OCP_USER_SDMA,
2521 };
2522
2523
2524 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
2525         { .role = "pad_fck", .clk = "pad_clks_ck" },
2526         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
2527 };
2528
2529 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2530         .name           = "mcbsp1",
2531         .class          = &omap44xx_mcbsp_hwmod_class,
2532         .clkdm_name     = "abe_clkdm",
2533         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2534         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2535         .main_clk       = "mcbsp1_fck",
2536         .prcm = {
2537                 .omap4 = {
2538                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
2539                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2540                         .modulemode   = MODULEMODE_SWCTRL,
2541                 },
2542         },
2543         .opt_clks       = mcbsp1_opt_clks,
2544         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
2545 };
2546
2547 /* mcbsp2 */
2548 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2549 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2550         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2551         { .irq = -1 }
2552 };
2553
2554 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2555         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2556         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2557         { .dma_req = -1 }
2558 };
2559
2560 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2561         {
2562                 .name           = "mpu",
2563                 .pa_start       = 0x40124000,
2564                 .pa_end         = 0x401240ff,
2565                 .flags          = ADDR_TYPE_RT
2566         },
2567         { }
2568 };
2569
2570 /* l4_abe -> mcbsp2 */
2571 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2572         .master         = &omap44xx_l4_abe_hwmod,
2573         .slave          = &omap44xx_mcbsp2_hwmod,
2574         .clk            = "ocp_abe_iclk",
2575         .addr           = omap44xx_mcbsp2_addrs,
2576         .user           = OCP_USER_MPU,
2577 };
2578
2579 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2580         {
2581                 .name           = "dma",
2582                 .pa_start       = 0x49024000,
2583                 .pa_end         = 0x490240ff,
2584                 .flags          = ADDR_TYPE_RT
2585         },
2586         { }
2587 };
2588
2589 /* l4_abe -> mcbsp2 (dma) */
2590 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2591         .master         = &omap44xx_l4_abe_hwmod,
2592         .slave          = &omap44xx_mcbsp2_hwmod,
2593         .clk            = "ocp_abe_iclk",
2594         .addr           = omap44xx_mcbsp2_dma_addrs,
2595         .user           = OCP_USER_SDMA,
2596 };
2597
2598 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
2599         { .role = "pad_fck", .clk = "pad_clks_ck" },
2600         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
2601 };
2602
2603 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2604         .name           = "mcbsp2",
2605         .class          = &omap44xx_mcbsp_hwmod_class,
2606         .clkdm_name     = "abe_clkdm",
2607         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2608         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2609         .main_clk       = "mcbsp2_fck",
2610         .prcm = {
2611                 .omap4 = {
2612                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
2613                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
2614                         .modulemode   = MODULEMODE_SWCTRL,
2615                 },
2616         },
2617         .opt_clks       = mcbsp2_opt_clks,
2618         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
2619 };
2620
2621 /* mcbsp3 */
2622 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2623 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2624         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2625         { .irq = -1 }
2626 };
2627
2628 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2629         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2630         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2631         { .dma_req = -1 }
2632 };
2633
2634 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2635         {
2636                 .name           = "mpu",
2637                 .pa_start       = 0x40126000,
2638                 .pa_end         = 0x401260ff,
2639                 .flags          = ADDR_TYPE_RT
2640         },
2641         { }
2642 };
2643
2644 /* l4_abe -> mcbsp3 */
2645 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2646         .master         = &omap44xx_l4_abe_hwmod,
2647         .slave          = &omap44xx_mcbsp3_hwmod,
2648         .clk            = "ocp_abe_iclk",
2649         .addr           = omap44xx_mcbsp3_addrs,
2650         .user           = OCP_USER_MPU,
2651 };
2652
2653 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2654         {
2655                 .name           = "dma",
2656                 .pa_start       = 0x49026000,
2657                 .pa_end         = 0x490260ff,
2658                 .flags          = ADDR_TYPE_RT
2659         },
2660         { }
2661 };
2662
2663 /* l4_abe -> mcbsp3 (dma) */
2664 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2665         .master         = &omap44xx_l4_abe_hwmod,
2666         .slave          = &omap44xx_mcbsp3_hwmod,
2667         .clk            = "ocp_abe_iclk",
2668         .addr           = omap44xx_mcbsp3_dma_addrs,
2669         .user           = OCP_USER_SDMA,
2670 };
2671
2672 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
2673         { .role = "pad_fck", .clk = "pad_clks_ck" },
2674         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
2675 };
2676
2677 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2678         .name           = "mcbsp3",
2679         .class          = &omap44xx_mcbsp_hwmod_class,
2680         .clkdm_name     = "abe_clkdm",
2681         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2682         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2683         .main_clk       = "mcbsp3_fck",
2684         .prcm = {
2685                 .omap4 = {
2686                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
2687                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
2688                         .modulemode   = MODULEMODE_SWCTRL,
2689                 },
2690         },
2691         .opt_clks       = mcbsp3_opt_clks,
2692         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
2693 };
2694
2695 /* mcbsp4 */
2696 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
2697 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
2698         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
2699         { .irq = -1 }
2700 };
2701
2702 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
2703         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
2704         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
2705         { .dma_req = -1 }
2706 };
2707
2708 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
2709         {
2710                 .pa_start       = 0x48096000,
2711                 .pa_end         = 0x480960ff,
2712                 .flags          = ADDR_TYPE_RT
2713         },
2714         { }
2715 };
2716
2717 /* l4_per -> mcbsp4 */
2718 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
2719         .master         = &omap44xx_l4_per_hwmod,
2720         .slave          = &omap44xx_mcbsp4_hwmod,
2721         .clk            = "l4_div_ck",
2722         .addr           = omap44xx_mcbsp4_addrs,
2723         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2724 };
2725
2726 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
2727         { .role = "pad_fck", .clk = "pad_clks_ck" },
2728         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
2729 };
2730
2731 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
2732         .name           = "mcbsp4",
2733         .class          = &omap44xx_mcbsp_hwmod_class,
2734         .clkdm_name     = "l4_per_clkdm",
2735         .mpu_irqs       = omap44xx_mcbsp4_irqs,
2736         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
2737         .main_clk       = "mcbsp4_fck",
2738         .prcm = {
2739                 .omap4 = {
2740                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
2741                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
2742                         .modulemode   = MODULEMODE_SWCTRL,
2743                 },
2744         },
2745         .opt_clks       = mcbsp4_opt_clks,
2746         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
2747 };
2748
2749 /*
2750  * 'mcpdm' class
2751  * multi channel pdm controller (proprietary interface with phoenix power
2752  * ic)
2753  */
2754
2755 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
2756         .rev_offs       = 0x0000,
2757         .sysc_offs      = 0x0010,
2758         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2759                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2760         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2761                            SIDLE_SMART_WKUP),
2762         .sysc_fields    = &omap_hwmod_sysc_type2,
2763 };
2764
2765 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
2766         .name   = "mcpdm",
2767         .sysc   = &omap44xx_mcpdm_sysc,
2768 };
2769
2770 /* mcpdm */
2771 static struct omap_hwmod omap44xx_mcpdm_hwmod;
2772 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
2773         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
2774         { .irq = -1 }
2775 };
2776
2777 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
2778         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
2779         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
2780         { .dma_req = -1 }
2781 };
2782
2783 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
2784         {
2785                 .pa_start       = 0x40132000,
2786                 .pa_end         = 0x4013207f,
2787                 .flags          = ADDR_TYPE_RT
2788         },
2789         { }
2790 };
2791
2792 /* l4_abe -> mcpdm */
2793 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
2794         .master         = &omap44xx_l4_abe_hwmod,
2795         .slave          = &omap44xx_mcpdm_hwmod,
2796         .clk            = "ocp_abe_iclk",
2797         .addr           = omap44xx_mcpdm_addrs,
2798         .user           = OCP_USER_MPU,
2799 };
2800
2801 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
2802         {
2803                 .pa_start       = 0x49032000,
2804                 .pa_end         = 0x4903207f,
2805                 .flags          = ADDR_TYPE_RT
2806         },
2807         { }
2808 };
2809
2810 /* l4_abe -> mcpdm (dma) */
2811 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
2812         .master         = &omap44xx_l4_abe_hwmod,
2813         .slave          = &omap44xx_mcpdm_hwmod,
2814         .clk            = "ocp_abe_iclk",
2815         .addr           = omap44xx_mcpdm_dma_addrs,
2816         .user           = OCP_USER_SDMA,
2817 };
2818
2819 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
2820         .name           = "mcpdm",
2821         .class          = &omap44xx_mcpdm_hwmod_class,
2822         .clkdm_name     = "abe_clkdm",
2823         .mpu_irqs       = omap44xx_mcpdm_irqs,
2824         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
2825         .main_clk       = "mcpdm_fck",
2826         .prcm = {
2827                 .omap4 = {
2828                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
2829                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
2830                         .modulemode   = MODULEMODE_SWCTRL,
2831                 },
2832         },
2833 };
2834
2835 /*
2836  * 'mcspi' class
2837  * multichannel serial port interface (mcspi) / master/slave synchronous serial
2838  * bus
2839  */
2840
2841 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
2842         .rev_offs       = 0x0000,
2843         .sysc_offs      = 0x0010,
2844         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2845                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2846         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2847                            SIDLE_SMART_WKUP),
2848         .sysc_fields    = &omap_hwmod_sysc_type2,
2849 };
2850
2851 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
2852         .name   = "mcspi",
2853         .sysc   = &omap44xx_mcspi_sysc,
2854         .rev    = OMAP4_MCSPI_REV,
2855 };
2856
2857 /* mcspi1 */
2858 static struct omap_hwmod omap44xx_mcspi1_hwmod;
2859 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
2860         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
2861         { .irq = -1 }
2862 };
2863
2864 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
2865         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
2866         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
2867         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
2868         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
2869         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
2870         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
2871         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
2872         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
2873         { .dma_req = -1 }
2874 };
2875
2876 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
2877         {
2878                 .pa_start       = 0x48098000,
2879                 .pa_end         = 0x480981ff,
2880                 .flags          = ADDR_TYPE_RT
2881         },
2882         { }
2883 };
2884
2885 /* l4_per -> mcspi1 */
2886 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
2887         .master         = &omap44xx_l4_per_hwmod,
2888         .slave          = &omap44xx_mcspi1_hwmod,
2889         .clk            = "l4_div_ck",
2890         .addr           = omap44xx_mcspi1_addrs,
2891         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2892 };
2893
2894 /* mcspi1 dev_attr */
2895 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
2896         .num_chipselect = 4,
2897 };
2898
2899 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
2900         .name           = "mcspi1",
2901         .class          = &omap44xx_mcspi_hwmod_class,
2902         .clkdm_name     = "l4_per_clkdm",
2903         .mpu_irqs       = omap44xx_mcspi1_irqs,
2904         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
2905         .main_clk       = "mcspi1_fck",
2906         .prcm = {
2907                 .omap4 = {
2908                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
2909                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
2910                         .modulemode   = MODULEMODE_SWCTRL,
2911                 },
2912         },
2913         .dev_attr       = &mcspi1_dev_attr,
2914 };
2915
2916 /* mcspi2 */
2917 static struct omap_hwmod omap44xx_mcspi2_hwmod;
2918 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
2919         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
2920         { .irq = -1 }
2921 };
2922
2923 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
2924         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
2925         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
2926         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
2927         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
2928         { .dma_req = -1 }
2929 };
2930
2931 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
2932         {
2933                 .pa_start       = 0x4809a000,
2934                 .pa_end         = 0x4809a1ff,
2935                 .flags          = ADDR_TYPE_RT
2936         },
2937         { }
2938 };
2939
2940 /* l4_per -> mcspi2 */
2941 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
2942         .master         = &omap44xx_l4_per_hwmod,
2943         .slave          = &omap44xx_mcspi2_hwmod,
2944         .clk            = "l4_div_ck",
2945         .addr           = omap44xx_mcspi2_addrs,
2946         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2947 };
2948
2949 /* mcspi2 dev_attr */
2950 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
2951         .num_chipselect = 2,
2952 };
2953
2954 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
2955         .name           = "mcspi2",
2956         .class          = &omap44xx_mcspi_hwmod_class,
2957         .clkdm_name     = "l4_per_clkdm",
2958         .mpu_irqs       = omap44xx_mcspi2_irqs,
2959         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
2960         .main_clk       = "mcspi2_fck",
2961         .prcm = {
2962                 .omap4 = {
2963                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
2964                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
2965                         .modulemode   = MODULEMODE_SWCTRL,
2966                 },
2967         },
2968         .dev_attr       = &mcspi2_dev_attr,
2969 };
2970
2971 /* mcspi3 */
2972 static struct omap_hwmod omap44xx_mcspi3_hwmod;
2973 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
2974         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
2975         { .irq = -1 }
2976 };
2977
2978 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
2979         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
2980         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
2981         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
2982         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
2983         { .dma_req = -1 }
2984 };
2985
2986 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
2987         {
2988                 .pa_start       = 0x480b8000,
2989                 .pa_end         = 0x480b81ff,
2990                 .flags          = ADDR_TYPE_RT
2991         },
2992         { }
2993 };
2994
2995 /* l4_per -> mcspi3 */
2996 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
2997         .master         = &omap44xx_l4_per_hwmod,
2998         .slave          = &omap44xx_mcspi3_hwmod,
2999         .clk            = "l4_div_ck",
3000         .addr           = omap44xx_mcspi3_addrs,
3001         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3002 };
3003
3004 /* mcspi3 dev_attr */
3005 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3006         .num_chipselect = 2,
3007 };
3008
3009 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3010         .name           = "mcspi3",
3011         .class          = &omap44xx_mcspi_hwmod_class,
3012         .clkdm_name     = "l4_per_clkdm",
3013         .mpu_irqs       = omap44xx_mcspi3_irqs,
3014         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3015         .main_clk       = "mcspi3_fck",
3016         .prcm = {
3017                 .omap4 = {
3018                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3019                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3020                         .modulemode   = MODULEMODE_SWCTRL,
3021                 },
3022         },
3023         .dev_attr       = &mcspi3_dev_attr,
3024 };
3025
3026 /* mcspi4 */
3027 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3028 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3029         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3030         { .irq = -1 }
3031 };
3032
3033 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3034         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3035         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3036         { .dma_req = -1 }
3037 };
3038
3039 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3040         {
3041                 .pa_start       = 0x480ba000,
3042                 .pa_end         = 0x480ba1ff,
3043                 .flags          = ADDR_TYPE_RT
3044         },
3045         { }
3046 };
3047
3048 /* l4_per -> mcspi4 */
3049 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3050         .master         = &omap44xx_l4_per_hwmod,
3051         .slave          = &omap44xx_mcspi4_hwmod,
3052         .clk            = "l4_div_ck",
3053         .addr           = omap44xx_mcspi4_addrs,
3054         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3055 };
3056
3057 /* mcspi4 dev_attr */
3058 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3059         .num_chipselect = 1,
3060 };
3061
3062 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3063         .name           = "mcspi4",
3064         .class          = &omap44xx_mcspi_hwmod_class,
3065         .clkdm_name     = "l4_per_clkdm",
3066         .mpu_irqs       = omap44xx_mcspi4_irqs,
3067         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3068         .main_clk       = "mcspi4_fck",
3069         .prcm = {
3070                 .omap4 = {
3071                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3072                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3073                         .modulemode   = MODULEMODE_SWCTRL,
3074                 },
3075         },
3076         .dev_attr       = &mcspi4_dev_attr,
3077 };
3078
3079 /*
3080  * 'mmc' class
3081  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3082  */
3083
3084 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3085         .rev_offs       = 0x0000,
3086         .sysc_offs      = 0x0010,
3087         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3088                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3089                            SYSC_HAS_SOFTRESET),
3090         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3091                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3092                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3093         .sysc_fields    = &omap_hwmod_sysc_type2,
3094 };
3095
3096 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3097         .name   = "mmc",
3098         .sysc   = &omap44xx_mmc_sysc,
3099 };
3100
3101 /* mmc1 */
3102 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3103         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3104         { .irq = -1 }
3105 };
3106
3107 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3108         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3109         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3110         { .dma_req = -1 }
3111 };
3112
3113 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3114         {
3115                 .pa_start       = 0x4809c000,
3116                 .pa_end         = 0x4809c3ff,
3117                 .flags          = ADDR_TYPE_RT
3118         },
3119         { }
3120 };
3121
3122 /* l4_per -> mmc1 */
3123 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3124         .master         = &omap44xx_l4_per_hwmod,
3125         .slave          = &omap44xx_mmc1_hwmod,
3126         .clk            = "l4_div_ck",
3127         .addr           = omap44xx_mmc1_addrs,
3128         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3129 };
3130
3131 /* mmc1 dev_attr */
3132 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3133         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3134 };
3135
3136 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3137         .name           = "mmc1",
3138         .class          = &omap44xx_mmc_hwmod_class,
3139         .clkdm_name     = "l3_init_clkdm",
3140         .mpu_irqs       = omap44xx_mmc1_irqs,
3141         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3142         .main_clk       = "mmc1_fck",
3143         .prcm = {
3144                 .omap4 = {
3145                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3146                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3147                         .modulemode   = MODULEMODE_SWCTRL,
3148                 },
3149         },
3150         .dev_attr       = &mmc1_dev_attr,
3151 };
3152
3153 /* mmc2 */
3154 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3155         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3156         { .irq = -1 }
3157 };
3158
3159 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3160         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3161         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3162         { .dma_req = -1 }
3163 };
3164
3165 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3166         {
3167                 .pa_start       = 0x480b4000,
3168                 .pa_end         = 0x480b43ff,
3169                 .flags          = ADDR_TYPE_RT
3170         },
3171         { }
3172 };
3173
3174 /* l4_per -> mmc2 */
3175 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3176         .master         = &omap44xx_l4_per_hwmod,
3177         .slave          = &omap44xx_mmc2_hwmod,
3178         .clk            = "l4_div_ck",
3179         .addr           = omap44xx_mmc2_addrs,
3180         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3181 };
3182
3183 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3184         .name           = "mmc2",
3185         .class          = &omap44xx_mmc_hwmod_class,
3186         .clkdm_name     = "l3_init_clkdm",
3187         .mpu_irqs       = omap44xx_mmc2_irqs,
3188         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3189         .main_clk       = "mmc2_fck",
3190         .prcm = {
3191                 .omap4 = {
3192                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3193                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3194                         .modulemode   = MODULEMODE_SWCTRL,
3195                 },
3196         },
3197 };
3198
3199 /* mmc3 */
3200 static struct omap_hwmod omap44xx_mmc3_hwmod;
3201 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3202         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3203         { .irq = -1 }
3204 };
3205
3206 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3207         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3208         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3209         { .dma_req = -1 }
3210 };
3211
3212 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3213         {
3214                 .pa_start       = 0x480ad000,
3215                 .pa_end         = 0x480ad3ff,
3216                 .flags          = ADDR_TYPE_RT
3217         },
3218         { }
3219 };
3220
3221 /* l4_per -> mmc3 */
3222 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3223         .master         = &omap44xx_l4_per_hwmod,
3224         .slave          = &omap44xx_mmc3_hwmod,
3225         .clk            = "l4_div_ck",
3226         .addr           = omap44xx_mmc3_addrs,
3227         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3228 };
3229
3230 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3231         .name           = "mmc3",
3232         .class          = &omap44xx_mmc_hwmod_class,
3233         .clkdm_name     = "l4_per_clkdm",
3234         .mpu_irqs       = omap44xx_mmc3_irqs,
3235         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3236         .main_clk       = "mmc3_fck",
3237         .prcm = {
3238                 .omap4 = {
3239                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3240                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3241                         .modulemode   = MODULEMODE_SWCTRL,
3242                 },
3243         },
3244 };
3245
3246 /* mmc4 */
3247 static struct omap_hwmod omap44xx_mmc4_hwmod;
3248 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3249         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3250         { .irq = -1 }
3251 };
3252
3253 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3254         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3255         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3256         { .dma_req = -1 }
3257 };
3258
3259 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3260         {
3261                 .pa_start       = 0x480d1000,
3262                 .pa_end         = 0x480d13ff,
3263                 .flags          = ADDR_TYPE_RT
3264         },
3265         { }
3266 };
3267
3268 /* l4_per -> mmc4 */
3269 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3270         .master         = &omap44xx_l4_per_hwmod,
3271         .slave          = &omap44xx_mmc4_hwmod,
3272         .clk            = "l4_div_ck",
3273         .addr           = omap44xx_mmc4_addrs,
3274         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3275 };
3276
3277 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3278         .name           = "mmc4",
3279         .class          = &omap44xx_mmc_hwmod_class,
3280         .clkdm_name     = "l4_per_clkdm",
3281         .mpu_irqs       = omap44xx_mmc4_irqs,
3282
3283         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3284         .main_clk       = "mmc4_fck",
3285         .prcm = {
3286                 .omap4 = {
3287                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3288                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3289                         .modulemode   = MODULEMODE_SWCTRL,
3290                 },
3291         },
3292 };
3293
3294 /* mmc5 */
3295 static struct omap_hwmod omap44xx_mmc5_hwmod;
3296 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3297         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3298         { .irq = -1 }
3299 };
3300
3301 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3302         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3303         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3304         { .dma_req = -1 }
3305 };
3306
3307 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3308         {
3309                 .pa_start       = 0x480d5000,
3310                 .pa_end         = 0x480d53ff,
3311                 .flags          = ADDR_TYPE_RT
3312         },
3313         { }
3314 };
3315
3316 /* l4_per -> mmc5 */
3317 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3318         .master         = &omap44xx_l4_per_hwmod,
3319         .slave          = &omap44xx_mmc5_hwmod,
3320         .clk            = "l4_div_ck",
3321         .addr           = omap44xx_mmc5_addrs,
3322         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3323 };
3324
3325 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3326         .name           = "mmc5",
3327         .class          = &omap44xx_mmc_hwmod_class,
3328         .clkdm_name     = "l4_per_clkdm",
3329         .mpu_irqs       = omap44xx_mmc5_irqs,
3330         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3331         .main_clk       = "mmc5_fck",
3332         .prcm = {
3333                 .omap4 = {
3334                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3335                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3336                         .modulemode   = MODULEMODE_SWCTRL,
3337                 },
3338         },
3339 };
3340
3341 /*
3342  * 'mpu' class
3343  * mpu sub-system
3344  */
3345
3346 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3347         .name   = "mpu",
3348 };
3349
3350 /* mpu */
3351 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3352         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3353         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3354         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3355         { .irq = -1 }
3356 };
3357
3358 static struct omap_hwmod omap44xx_mpu_hwmod = {
3359         .name           = "mpu",
3360         .class          = &omap44xx_mpu_hwmod_class,
3361         .clkdm_name     = "mpuss_clkdm",
3362         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3363         .mpu_irqs       = omap44xx_mpu_irqs,
3364         .main_clk       = "dpll_mpu_m2_ck",
3365         .prcm = {
3366                 .omap4 = {
3367                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3368                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3369                 },
3370         },
3371 };
3372
3373 /*
3374  * 'smartreflex' class
3375  * smartreflex module (monitor silicon performance and outputs a measure of
3376  * performance error)
3377  */
3378
3379 /* The IP is not compliant to type1 / type2 scheme */
3380 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3381         .sidle_shift    = 24,
3382         .enwkup_shift   = 26,
3383 };
3384
3385 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3386         .sysc_offs      = 0x0038,
3387         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3388         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3389                            SIDLE_SMART_WKUP),
3390         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3391 };
3392
3393 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3394         .name   = "smartreflex",
3395         .sysc   = &omap44xx_smartreflex_sysc,
3396         .rev    = 2,
3397 };
3398
3399 /* smartreflex_core */
3400 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
3401         .sensor_voltdm_name   = "core",
3402 };
3403
3404 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3405 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3406         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3407         { .irq = -1 }
3408 };
3409
3410 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3411         {
3412                 .pa_start       = 0x4a0dd000,
3413                 .pa_end         = 0x4a0dd03f,
3414                 .flags          = ADDR_TYPE_RT
3415         },
3416         { }
3417 };
3418
3419 /* l4_cfg -> smartreflex_core */
3420 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3421         .master         = &omap44xx_l4_cfg_hwmod,
3422         .slave          = &omap44xx_smartreflex_core_hwmod,
3423         .clk            = "l4_div_ck",
3424         .addr           = omap44xx_smartreflex_core_addrs,
3425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3426 };
3427
3428 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3429         .name           = "smartreflex_core",
3430         .class          = &omap44xx_smartreflex_hwmod_class,
3431         .clkdm_name     = "l4_ao_clkdm",
3432         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3433
3434         .main_clk       = "smartreflex_core_fck",
3435         .prcm = {
3436                 .omap4 = {
3437                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
3438                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
3439                         .modulemode   = MODULEMODE_SWCTRL,
3440                 },
3441         },
3442         .dev_attr       = &smartreflex_core_dev_attr,
3443 };
3444
3445 /* smartreflex_iva */
3446 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3447         .sensor_voltdm_name     = "iva",
3448 };
3449
3450 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3451 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3452         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3453         { .irq = -1 }
3454 };
3455
3456 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3457         {
3458                 .pa_start       = 0x4a0db000,
3459                 .pa_end         = 0x4a0db03f,
3460                 .flags          = ADDR_TYPE_RT
3461         },
3462         { }
3463 };
3464
3465 /* l4_cfg -> smartreflex_iva */
3466 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3467         .master         = &omap44xx_l4_cfg_hwmod,
3468         .slave          = &omap44xx_smartreflex_iva_hwmod,
3469         .clk            = "l4_div_ck",
3470         .addr           = omap44xx_smartreflex_iva_addrs,
3471         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3472 };
3473
3474 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3475         .name           = "smartreflex_iva",
3476         .class          = &omap44xx_smartreflex_hwmod_class,
3477         .clkdm_name     = "l4_ao_clkdm",
3478         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3479         .main_clk       = "smartreflex_iva_fck",
3480         .prcm = {
3481                 .omap4 = {
3482                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
3483                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
3484                         .modulemode   = MODULEMODE_SWCTRL,
3485                 },
3486         },
3487         .dev_attr       = &smartreflex_iva_dev_attr,
3488 };
3489
3490 /* smartreflex_mpu */
3491 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
3492         .sensor_voltdm_name     = "mpu",
3493 };
3494
3495 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3496 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3497         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3498         { .irq = -1 }
3499 };
3500
3501 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3502         {
3503                 .pa_start       = 0x4a0d9000,
3504                 .pa_end         = 0x4a0d903f,
3505                 .flags          = ADDR_TYPE_RT
3506         },
3507         { }
3508 };
3509
3510 /* l4_cfg -> smartreflex_mpu */
3511 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3512         .master         = &omap44xx_l4_cfg_hwmod,
3513         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3514         .clk            = "l4_div_ck",
3515         .addr           = omap44xx_smartreflex_mpu_addrs,
3516         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3517 };
3518
3519 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3520         .name           = "smartreflex_mpu",
3521         .class          = &omap44xx_smartreflex_hwmod_class,
3522         .clkdm_name     = "l4_ao_clkdm",
3523         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3524         .main_clk       = "smartreflex_mpu_fck",
3525         .prcm = {
3526                 .omap4 = {
3527                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
3528                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
3529                         .modulemode   = MODULEMODE_SWCTRL,
3530                 },
3531         },
3532         .dev_attr       = &smartreflex_mpu_dev_attr,
3533 };
3534
3535 /*
3536  * 'spinlock' class
3537  * spinlock provides hardware assistance for synchronizing the processes
3538  * running on multiple processors
3539  */
3540
3541 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3542         .rev_offs       = 0x0000,
3543         .sysc_offs      = 0x0010,
3544         .syss_offs      = 0x0014,
3545         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3546                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3547                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3549                            SIDLE_SMART_WKUP),
3550         .sysc_fields    = &omap_hwmod_sysc_type1,
3551 };
3552
3553 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3554         .name   = "spinlock",
3555         .sysc   = &omap44xx_spinlock_sysc,
3556 };
3557
3558 /* spinlock */
3559 static struct omap_hwmod omap44xx_spinlock_hwmod;
3560 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3561         {
3562                 .pa_start       = 0x4a0f6000,
3563                 .pa_end         = 0x4a0f6fff,
3564                 .flags          = ADDR_TYPE_RT
3565         },
3566         { }
3567 };
3568
3569 /* l4_cfg -> spinlock */
3570 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3571         .master         = &omap44xx_l4_cfg_hwmod,
3572         .slave          = &omap44xx_spinlock_hwmod,
3573         .clk            = "l4_div_ck",
3574         .addr           = omap44xx_spinlock_addrs,
3575         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3576 };
3577
3578 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3579         .name           = "spinlock",
3580         .class          = &omap44xx_spinlock_hwmod_class,
3581         .clkdm_name     = "l4_cfg_clkdm",
3582         .prcm = {
3583                 .omap4 = {
3584                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
3585                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
3586                 },
3587         },
3588 };
3589
3590 /*
3591  * 'timer' class
3592  * general purpose timer module with accurate 1ms tick
3593  * This class contains several variants: ['timer_1ms', 'timer']
3594  */
3595
3596 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3597         .rev_offs       = 0x0000,
3598         .sysc_offs      = 0x0010,
3599         .syss_offs      = 0x0014,
3600         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3601                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3602                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3603                            SYSS_HAS_RESET_STATUS),
3604         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3605         .sysc_fields    = &omap_hwmod_sysc_type1,
3606 };
3607
3608 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3609         .name   = "timer",
3610         .sysc   = &omap44xx_timer_1ms_sysc,
3611 };
3612
3613 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
3614         .rev_offs       = 0x0000,
3615         .sysc_offs      = 0x0010,
3616         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3617                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3618         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3619                            SIDLE_SMART_WKUP),
3620         .sysc_fields    = &omap_hwmod_sysc_type2,
3621 };
3622
3623 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
3624         .name   = "timer",
3625         .sysc   = &omap44xx_timer_sysc,
3626 };
3627
3628 /* always-on timers dev attribute */
3629 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
3630         .timer_capability       = OMAP_TIMER_ALWON,
3631 };
3632
3633 /* pwm timers dev attribute */
3634 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
3635         .timer_capability       = OMAP_TIMER_HAS_PWM,
3636 };
3637
3638 /* timer1 */
3639 static struct omap_hwmod omap44xx_timer1_hwmod;
3640 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
3641         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
3642         { .irq = -1 }
3643 };
3644
3645 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
3646         {
3647                 .pa_start       = 0x4a318000,
3648                 .pa_end         = 0x4a31807f,
3649                 .flags          = ADDR_TYPE_RT
3650         },
3651         { }
3652 };
3653
3654 /* l4_wkup -> timer1 */
3655 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3656         .master         = &omap44xx_l4_wkup_hwmod,
3657         .slave          = &omap44xx_timer1_hwmod,
3658         .clk            = "l4_wkup_clk_mux_ck",
3659         .addr           = omap44xx_timer1_addrs,
3660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3661 };
3662
3663 static struct omap_hwmod omap44xx_timer1_hwmod = {
3664         .name           = "timer1",
3665         .class          = &omap44xx_timer_1ms_hwmod_class,
3666         .clkdm_name     = "l4_wkup_clkdm",
3667         .mpu_irqs       = omap44xx_timer1_irqs,
3668         .main_clk       = "timer1_fck",
3669         .prcm = {
3670                 .omap4 = {
3671                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
3672                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
3673                         .modulemode   = MODULEMODE_SWCTRL,
3674                 },
3675         },
3676         .dev_attr       = &capability_alwon_dev_attr,
3677 };
3678
3679 /* timer2 */
3680 static struct omap_hwmod omap44xx_timer2_hwmod;
3681 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
3682         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
3683         { .irq = -1 }
3684 };
3685
3686 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
3687         {
3688                 .pa_start       = 0x48032000,
3689                 .pa_end         = 0x4803207f,
3690                 .flags          = ADDR_TYPE_RT
3691         },
3692         { }
3693 };
3694
3695 /* l4_per -> timer2 */
3696 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3697         .master         = &omap44xx_l4_per_hwmod,
3698         .slave          = &omap44xx_timer2_hwmod,
3699         .clk            = "l4_div_ck",
3700         .addr           = omap44xx_timer2_addrs,
3701         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3702 };
3703
3704 static struct omap_hwmod omap44xx_timer2_hwmod = {
3705         .name           = "timer2",
3706         .class          = &omap44xx_timer_1ms_hwmod_class,
3707         .clkdm_name     = "l4_per_clkdm",
3708         .mpu_irqs       = omap44xx_timer2_irqs,
3709         .main_clk       = "timer2_fck",
3710         .prcm = {
3711                 .omap4 = {
3712                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
3713                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
3714                         .modulemode   = MODULEMODE_SWCTRL,
3715                 },
3716         },
3717         .dev_attr       = &capability_alwon_dev_attr,
3718 };
3719
3720 /* timer3 */
3721 static struct omap_hwmod omap44xx_timer3_hwmod;
3722 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
3723         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
3724         { .irq = -1 }
3725 };
3726
3727 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
3728         {
3729                 .pa_start       = 0x48034000,
3730                 .pa_end         = 0x4803407f,
3731                 .flags          = ADDR_TYPE_RT
3732         },
3733         { }
3734 };
3735
3736 /* l4_per -> timer3 */
3737 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
3738         .master         = &omap44xx_l4_per_hwmod,
3739         .slave          = &omap44xx_timer3_hwmod,
3740         .clk            = "l4_div_ck",
3741         .addr           = omap44xx_timer3_addrs,
3742         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3743 };
3744
3745 static struct omap_hwmod omap44xx_timer3_hwmod = {
3746         .name           = "timer3",
3747         .class          = &omap44xx_timer_hwmod_class,
3748         .clkdm_name     = "l4_per_clkdm",
3749         .mpu_irqs       = omap44xx_timer3_irqs,
3750         .main_clk       = "timer3_fck",
3751         .prcm = {
3752                 .omap4 = {
3753                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
3754                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
3755                         .modulemode   = MODULEMODE_SWCTRL,
3756                 },
3757         },
3758         .dev_attr       = &capability_alwon_dev_attr,
3759 };
3760
3761 /* timer4 */
3762 static struct omap_hwmod omap44xx_timer4_hwmod;
3763 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
3764         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
3765         { .irq = -1 }
3766 };
3767
3768 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
3769         {
3770                 .pa_start       = 0x48036000,
3771                 .pa_end         = 0x4803607f,
3772                 .flags          = ADDR_TYPE_RT
3773         },
3774         { }
3775 };
3776
3777 /* l4_per -> timer4 */
3778 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
3779         .master         = &omap44xx_l4_per_hwmod,
3780         .slave          = &omap44xx_timer4_hwmod,
3781         .clk            = "l4_div_ck",
3782         .addr           = omap44xx_timer4_addrs,
3783         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3784 };
3785
3786 static struct omap_hwmod omap44xx_timer4_hwmod = {
3787         .name           = "timer4",
3788         .class          = &omap44xx_timer_hwmod_class,
3789         .clkdm_name     = "l4_per_clkdm",
3790         .mpu_irqs       = omap44xx_timer4_irqs,
3791         .main_clk       = "timer4_fck",
3792         .prcm = {
3793                 .omap4 = {
3794                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
3795                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
3796                         .modulemode   = MODULEMODE_SWCTRL,
3797                 },
3798         },
3799         .dev_attr       = &capability_alwon_dev_attr,
3800 };
3801
3802 /* timer5 */
3803 static struct omap_hwmod omap44xx_timer5_hwmod;
3804 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
3805         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
3806         { .irq = -1 }
3807 };
3808
3809 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
3810         {
3811                 .pa_start       = 0x40138000,
3812                 .pa_end         = 0x4013807f,
3813                 .flags          = ADDR_TYPE_RT
3814         },
3815         { }
3816 };
3817
3818 /* l4_abe -> timer5 */
3819 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
3820         .master         = &omap44xx_l4_abe_hwmod,
3821         .slave          = &omap44xx_timer5_hwmod,
3822         .clk            = "ocp_abe_iclk",
3823         .addr           = omap44xx_timer5_addrs,
3824         .user           = OCP_USER_MPU,
3825 };
3826
3827 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
3828         {
3829                 .pa_start       = 0x49038000,
3830                 .pa_end         = 0x4903807f,
3831                 .flags          = ADDR_TYPE_RT
3832         },
3833         { }
3834 };
3835
3836 /* l4_abe -> timer5 (dma) */
3837 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
3838         .master         = &omap44xx_l4_abe_hwmod,
3839         .slave          = &omap44xx_timer5_hwmod,
3840         .clk            = "ocp_abe_iclk",
3841         .addr           = omap44xx_timer5_dma_addrs,
3842         .user           = OCP_USER_SDMA,
3843 };
3844
3845 static struct omap_hwmod omap44xx_timer5_hwmod = {
3846         .name           = "timer5",
3847         .class          = &omap44xx_timer_hwmod_class,
3848         .clkdm_name     = "abe_clkdm",
3849         .mpu_irqs       = omap44xx_timer5_irqs,
3850         .main_clk       = "timer5_fck",
3851         .prcm = {
3852                 .omap4 = {
3853                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
3854                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
3855                         .modulemode   = MODULEMODE_SWCTRL,
3856                 },
3857         },
3858         .dev_attr       = &capability_alwon_dev_attr,
3859 };
3860
3861 /* timer6 */
3862 static struct omap_hwmod omap44xx_timer6_hwmod;
3863 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
3864         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
3865         { .irq = -1 }
3866 };
3867
3868 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
3869         {
3870                 .pa_start       = 0x4013a000,
3871                 .pa_end         = 0x4013a07f,
3872                 .flags          = ADDR_TYPE_RT
3873         },
3874         { }
3875 };
3876
3877 /* l4_abe -> timer6 */
3878 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
3879         .master         = &omap44xx_l4_abe_hwmod,
3880         .slave          = &omap44xx_timer6_hwmod,
3881         .clk            = "ocp_abe_iclk",
3882         .addr           = omap44xx_timer6_addrs,
3883         .user           = OCP_USER_MPU,
3884 };
3885
3886 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
3887         {
3888                 .pa_start       = 0x4903a000,
3889                 .pa_end         = 0x4903a07f,
3890                 .flags          = ADDR_TYPE_RT
3891         },
3892         { }
3893 };
3894
3895 /* l4_abe -> timer6 (dma) */
3896 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
3897         .master         = &omap44xx_l4_abe_hwmod,
3898         .slave          = &omap44xx_timer6_hwmod,
3899         .clk            = "ocp_abe_iclk",
3900         .addr           = omap44xx_timer6_dma_addrs,
3901         .user           = OCP_USER_SDMA,
3902 };
3903
3904 static struct omap_hwmod omap44xx_timer6_hwmod = {
3905         .name           = "timer6",
3906         .class          = &omap44xx_timer_hwmod_class,
3907         .clkdm_name     = "abe_clkdm",
3908         .mpu_irqs       = omap44xx_timer6_irqs,
3909
3910         .main_clk       = "timer6_fck",
3911         .prcm = {
3912                 .omap4 = {
3913                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
3914                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
3915                         .modulemode   = MODULEMODE_SWCTRL,
3916                 },
3917         },
3918         .dev_attr       = &capability_alwon_dev_attr,
3919 };
3920
3921 /* timer7 */
3922 static struct omap_hwmod omap44xx_timer7_hwmod;
3923 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
3924         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
3925         { .irq = -1 }
3926 };
3927
3928 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
3929         {
3930                 .pa_start       = 0x4013c000,
3931                 .pa_end         = 0x4013c07f,
3932                 .flags          = ADDR_TYPE_RT
3933         },
3934         { }
3935 };
3936
3937 /* l4_abe -> timer7 */
3938 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
3939         .master         = &omap44xx_l4_abe_hwmod,
3940         .slave          = &omap44xx_timer7_hwmod,
3941         .clk            = "ocp_abe_iclk",
3942         .addr           = omap44xx_timer7_addrs,
3943         .user           = OCP_USER_MPU,
3944 };
3945
3946 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
3947         {
3948                 .pa_start       = 0x4903c000,
3949                 .pa_end         = 0x4903c07f,
3950                 .flags          = ADDR_TYPE_RT
3951         },
3952         { }
3953 };
3954
3955 /* l4_abe -> timer7 (dma) */
3956 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
3957         .master         = &omap44xx_l4_abe_hwmod,
3958         .slave          = &omap44xx_timer7_hwmod,
3959         .clk            = "ocp_abe_iclk",
3960         .addr           = omap44xx_timer7_dma_addrs,
3961         .user           = OCP_USER_SDMA,
3962 };
3963
3964 static struct omap_hwmod omap44xx_timer7_hwmod = {
3965         .name           = "timer7",
3966         .class          = &omap44xx_timer_hwmod_class,
3967         .clkdm_name     = "abe_clkdm",
3968         .mpu_irqs       = omap44xx_timer7_irqs,
3969         .main_clk       = "timer7_fck",
3970         .prcm = {
3971                 .omap4 = {
3972                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
3973                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
3974                         .modulemode   = MODULEMODE_SWCTRL,
3975                 },
3976         },
3977         .dev_attr       = &capability_alwon_dev_attr,
3978 };
3979
3980 /* timer8 */
3981 static struct omap_hwmod omap44xx_timer8_hwmod;
3982 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
3983         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
3984         { .irq = -1 }
3985 };
3986
3987 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
3988         {
3989                 .pa_start       = 0x4013e000,
3990                 .pa_end         = 0x4013e07f,
3991                 .flags          = ADDR_TYPE_RT
3992         },
3993         { }
3994 };
3995
3996 /* l4_abe -> timer8 */
3997 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
3998         .master         = &omap44xx_l4_abe_hwmod,
3999         .slave          = &omap44xx_timer8_hwmod,
4000         .clk            = "ocp_abe_iclk",
4001         .addr           = omap44xx_timer8_addrs,
4002         .user           = OCP_USER_MPU,
4003 };
4004
4005 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4006         {
4007                 .pa_start       = 0x4903e000,
4008                 .pa_end         = 0x4903e07f,
4009                 .flags          = ADDR_TYPE_RT
4010         },
4011         { }
4012 };
4013
4014 /* l4_abe -> timer8 (dma) */
4015 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4016         .master         = &omap44xx_l4_abe_hwmod,
4017         .slave          = &omap44xx_timer8_hwmod,
4018         .clk            = "ocp_abe_iclk",
4019         .addr           = omap44xx_timer8_dma_addrs,
4020         .user           = OCP_USER_SDMA,
4021 };
4022
4023 static struct omap_hwmod omap44xx_timer8_hwmod = {
4024         .name           = "timer8",
4025         .class          = &omap44xx_timer_hwmod_class,
4026         .clkdm_name     = "abe_clkdm",
4027         .mpu_irqs       = omap44xx_timer8_irqs,
4028         .main_clk       = "timer8_fck",
4029         .prcm = {
4030                 .omap4 = {
4031                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4032                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4033                         .modulemode   = MODULEMODE_SWCTRL,
4034                 },
4035         },
4036         .dev_attr       = &capability_pwm_dev_attr,
4037 };
4038
4039 /* timer9 */
4040 static struct omap_hwmod omap44xx_timer9_hwmod;
4041 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4042         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4043         { .irq = -1 }
4044 };
4045
4046 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4047         {
4048                 .pa_start       = 0x4803e000,
4049                 .pa_end         = 0x4803e07f,
4050                 .flags          = ADDR_TYPE_RT
4051         },
4052         { }
4053 };
4054
4055 /* l4_per -> timer9 */
4056 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4057         .master         = &omap44xx_l4_per_hwmod,
4058         .slave          = &omap44xx_timer9_hwmod,
4059         .clk            = "l4_div_ck",
4060         .addr           = omap44xx_timer9_addrs,
4061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4062 };
4063
4064 static struct omap_hwmod omap44xx_timer9_hwmod = {
4065         .name           = "timer9",
4066         .class          = &omap44xx_timer_hwmod_class,
4067         .clkdm_name     = "l4_per_clkdm",
4068         .mpu_irqs       = omap44xx_timer9_irqs,
4069         .main_clk       = "timer9_fck",
4070         .prcm = {
4071                 .omap4 = {
4072                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4073                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4074                         .modulemode   = MODULEMODE_SWCTRL,
4075                 },
4076         },
4077         .dev_attr       = &capability_pwm_dev_attr,
4078 };
4079
4080 /* timer10 */
4081 static struct omap_hwmod omap44xx_timer10_hwmod;
4082 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4083         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4084         { .irq = -1 }
4085 };
4086
4087 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4088         {
4089                 .pa_start       = 0x48086000,
4090                 .pa_end         = 0x4808607f,
4091                 .flags          = ADDR_TYPE_RT
4092         },
4093         { }
4094 };
4095
4096 /* l4_per -> timer10 */
4097 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4098         .master         = &omap44xx_l4_per_hwmod,
4099         .slave          = &omap44xx_timer10_hwmod,
4100         .clk            = "l4_div_ck",
4101         .addr           = omap44xx_timer10_addrs,
4102         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4103 };
4104
4105 static struct omap_hwmod omap44xx_timer10_hwmod = {
4106         .name           = "timer10",
4107         .class          = &omap44xx_timer_1ms_hwmod_class,
4108         .clkdm_name     = "l4_per_clkdm",
4109         .mpu_irqs       = omap44xx_timer10_irqs,
4110         .main_clk       = "timer10_fck",
4111         .prcm = {
4112                 .omap4 = {
4113                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4114                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4115                         .modulemode   = MODULEMODE_SWCTRL,
4116                 },
4117         },
4118         .dev_attr       = &capability_pwm_dev_attr,
4119 };
4120
4121 /* timer11 */
4122 static struct omap_hwmod omap44xx_timer11_hwmod;
4123 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4124         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4125         { .irq = -1 }
4126 };
4127
4128 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4129         {
4130                 .pa_start       = 0x48088000,
4131                 .pa_end         = 0x4808807f,
4132                 .flags          = ADDR_TYPE_RT
4133         },
4134         { }
4135 };
4136
4137 /* l4_per -> timer11 */
4138 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4139         .master         = &omap44xx_l4_per_hwmod,
4140         .slave          = &omap44xx_timer11_hwmod,
4141         .clk            = "l4_div_ck",
4142         .addr           = omap44xx_timer11_addrs,
4143         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4144 };
4145
4146 static struct omap_hwmod omap44xx_timer11_hwmod = {
4147         .name           = "timer11",
4148         .class          = &omap44xx_timer_hwmod_class,
4149         .clkdm_name     = "l4_per_clkdm",
4150         .mpu_irqs       = omap44xx_timer11_irqs,
4151         .main_clk       = "timer11_fck",
4152         .prcm = {
4153                 .omap4 = {
4154                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4155                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4156                         .modulemode   = MODULEMODE_SWCTRL,
4157                 },
4158         },
4159         .dev_attr       = &capability_pwm_dev_attr,
4160 };
4161
4162 /*
4163  * 'uart' class
4164  * universal asynchronous receiver/transmitter (uart)
4165  */
4166
4167 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4168         .rev_offs       = 0x0050,
4169         .sysc_offs      = 0x0054,
4170         .syss_offs      = 0x0058,
4171         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4172                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4173                            SYSS_HAS_RESET_STATUS),
4174         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4175                            SIDLE_SMART_WKUP),
4176         .sysc_fields    = &omap_hwmod_sysc_type1,
4177 };
4178
4179 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4180         .name   = "uart",
4181         .sysc   = &omap44xx_uart_sysc,
4182 };
4183
4184 /* uart1 */
4185 static struct omap_hwmod omap44xx_uart1_hwmod;
4186 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4187         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4188         { .irq = -1 }
4189 };
4190
4191 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4192         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4193         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4194         { .dma_req = -1 }
4195 };
4196
4197 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4198         {
4199                 .pa_start       = 0x4806a000,
4200                 .pa_end         = 0x4806a0ff,
4201                 .flags          = ADDR_TYPE_RT
4202         },
4203         { }
4204 };
4205
4206 /* l4_per -> uart1 */
4207 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4208         .master         = &omap44xx_l4_per_hwmod,
4209         .slave          = &omap44xx_uart1_hwmod,
4210         .clk            = "l4_div_ck",
4211         .addr           = omap44xx_uart1_addrs,
4212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4213 };
4214
4215 static struct omap_hwmod omap44xx_uart1_hwmod = {
4216         .name           = "uart1",
4217         .class          = &omap44xx_uart_hwmod_class,
4218         .clkdm_name     = "l4_per_clkdm",
4219         .mpu_irqs       = omap44xx_uart1_irqs,
4220         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4221         .main_clk       = "uart1_fck",
4222         .prcm = {
4223                 .omap4 = {
4224                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4225                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4226                         .modulemode   = MODULEMODE_SWCTRL,
4227                 },
4228         },
4229 };
4230
4231 /* uart2 */
4232 static struct omap_hwmod omap44xx_uart2_hwmod;
4233 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4234         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4235         { .irq = -1 }
4236 };
4237
4238 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4239         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4240         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4241         { .dma_req = -1 }
4242 };
4243
4244 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4245         {
4246                 .pa_start       = 0x4806c000,
4247                 .pa_end         = 0x4806c0ff,
4248                 .flags          = ADDR_TYPE_RT
4249         },
4250         { }
4251 };
4252
4253 /* l4_per -> uart2 */
4254 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4255         .master         = &omap44xx_l4_per_hwmod,
4256         .slave          = &omap44xx_uart2_hwmod,
4257         .clk            = "l4_div_ck",
4258         .addr           = omap44xx_uart2_addrs,
4259         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4260 };
4261
4262 static struct omap_hwmod omap44xx_uart2_hwmod = {
4263         .name           = "uart2",
4264         .class          = &omap44xx_uart_hwmod_class,
4265         .clkdm_name     = "l4_per_clkdm",
4266         .mpu_irqs       = omap44xx_uart2_irqs,
4267         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4268         .main_clk       = "uart2_fck",
4269         .prcm = {
4270                 .omap4 = {
4271                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4272                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4273                         .modulemode   = MODULEMODE_SWCTRL,
4274                 },
4275         },
4276 };
4277
4278 /* uart3 */
4279 static struct omap_hwmod omap44xx_uart3_hwmod;
4280 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4281         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4282         { .irq = -1 }
4283 };
4284
4285 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4286         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4287         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4288         { .dma_req = -1 }
4289 };
4290
4291 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4292         {
4293                 .pa_start       = 0x48020000,
4294                 .pa_end         = 0x480200ff,
4295                 .flags          = ADDR_TYPE_RT
4296         },
4297         { }
4298 };
4299
4300 /* l4_per -> uart3 */
4301 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4302         .master         = &omap44xx_l4_per_hwmod,
4303         .slave          = &omap44xx_uart3_hwmod,
4304         .clk            = "l4_div_ck",
4305         .addr           = omap44xx_uart3_addrs,
4306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4307 };
4308
4309 static struct omap_hwmod omap44xx_uart3_hwmod = {
4310         .name           = "uart3",
4311         .class          = &omap44xx_uart_hwmod_class,
4312         .clkdm_name     = "l4_per_clkdm",
4313         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4314         .mpu_irqs       = omap44xx_uart3_irqs,
4315         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4316         .main_clk       = "uart3_fck",
4317         .prcm = {
4318                 .omap4 = {
4319                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
4320                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
4321                         .modulemode   = MODULEMODE_SWCTRL,
4322                 },
4323         },
4324 };
4325
4326 /* uart4 */
4327 static struct omap_hwmod omap44xx_uart4_hwmod;
4328 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4329         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4330         { .irq = -1 }
4331 };
4332
4333 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4334         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4335         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4336         { .dma_req = -1 }
4337 };
4338
4339 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4340         {
4341                 .pa_start       = 0x4806e000,
4342                 .pa_end         = 0x4806e0ff,
4343                 .flags          = ADDR_TYPE_RT
4344         },
4345         { }
4346 };
4347
4348 /* l4_per -> uart4 */
4349 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4350         .master         = &omap44xx_l4_per_hwmod,
4351         .slave          = &omap44xx_uart4_hwmod,
4352         .clk            = "l4_div_ck",
4353         .addr           = omap44xx_uart4_addrs,
4354         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4355 };
4356
4357 static struct omap_hwmod omap44xx_uart4_hwmod = {
4358         .name           = "uart4",
4359         .class          = &omap44xx_uart_hwmod_class,
4360         .clkdm_name     = "l4_per_clkdm",
4361         .mpu_irqs       = omap44xx_uart4_irqs,
4362         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4363         .main_clk       = "uart4_fck",
4364         .prcm = {
4365                 .omap4 = {
4366                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
4367                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
4368                         .modulemode   = MODULEMODE_SWCTRL,
4369                 },
4370         },
4371 };
4372
4373 /*
4374  * 'usb_otg_hs' class
4375  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4376  */
4377
4378 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4379         .rev_offs       = 0x0400,
4380         .sysc_offs      = 0x0404,
4381         .syss_offs      = 0x0408,
4382         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4383                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4384                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4385         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4386                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4387                            MSTANDBY_SMART),
4388         .sysc_fields    = &omap_hwmod_sysc_type1,
4389 };
4390
4391 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4392         .name   = "usb_otg_hs",
4393         .sysc   = &omap44xx_usb_otg_hs_sysc,
4394 };
4395
4396 /* usb_otg_hs */
4397 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4398         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4399         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4400         { .irq = -1 }
4401 };
4402
4403 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4404         {
4405                 .pa_start       = 0x4a0ab000,
4406                 .pa_end         = 0x4a0ab003,
4407                 .flags          = ADDR_TYPE_RT
4408         },
4409         { }
4410 };
4411
4412 /* l4_cfg -> usb_otg_hs */
4413 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4414         .master         = &omap44xx_l4_cfg_hwmod,
4415         .slave          = &omap44xx_usb_otg_hs_hwmod,
4416         .clk            = "l4_div_ck",
4417         .addr           = omap44xx_usb_otg_hs_addrs,
4418         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4419 };
4420
4421 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4422         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4423 };
4424
4425 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4426         .name           = "usb_otg_hs",
4427         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4428         .clkdm_name     = "l3_init_clkdm",
4429         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4430         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4431         .main_clk       = "usb_otg_hs_ick",
4432         .prcm = {
4433                 .omap4 = {
4434                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
4435                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
4436                         .modulemode   = MODULEMODE_HWCTRL,
4437                 },
4438         },
4439         .opt_clks       = usb_otg_hs_opt_clks,
4440         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
4441 };
4442
4443 /*
4444  * 'wd_timer' class
4445  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4446  * overflow condition
4447  */
4448
4449 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4450         .rev_offs       = 0x0000,
4451         .sysc_offs      = 0x0010,
4452         .syss_offs      = 0x0014,
4453         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4454                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4455         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4456                            SIDLE_SMART_WKUP),
4457         .sysc_fields    = &omap_hwmod_sysc_type1,
4458 };
4459
4460 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4461         .name           = "wd_timer",
4462         .sysc           = &omap44xx_wd_timer_sysc,
4463         .pre_shutdown   = &omap2_wd_timer_disable,
4464 };
4465
4466 /* wd_timer2 */
4467 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4468 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4469         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4470         { .irq = -1 }
4471 };
4472
4473 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4474         {
4475                 .pa_start       = 0x4a314000,
4476                 .pa_end         = 0x4a31407f,
4477                 .flags          = ADDR_TYPE_RT
4478         },
4479         { }
4480 };
4481
4482 /* l4_wkup -> wd_timer2 */
4483 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4484         .master         = &omap44xx_l4_wkup_hwmod,
4485         .slave          = &omap44xx_wd_timer2_hwmod,
4486         .clk            = "l4_wkup_clk_mux_ck",
4487         .addr           = omap44xx_wd_timer2_addrs,
4488         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4489 };
4490
4491 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4492         .name           = "wd_timer2",
4493         .class          = &omap44xx_wd_timer_hwmod_class,
4494         .clkdm_name     = "l4_wkup_clkdm",
4495         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4496         .main_clk       = "wd_timer2_fck",
4497         .prcm = {
4498                 .omap4 = {
4499                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
4500                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
4501                         .modulemode   = MODULEMODE_SWCTRL,
4502                 },
4503         },
4504 };
4505
4506 /* wd_timer3 */
4507 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4508 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4509         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4510         { .irq = -1 }
4511 };
4512
4513 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4514         {
4515                 .pa_start       = 0x40130000,
4516                 .pa_end         = 0x4013007f,
4517                 .flags          = ADDR_TYPE_RT
4518         },
4519         { }
4520 };
4521
4522 /* l4_abe -> wd_timer3 */
4523 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4524         .master         = &omap44xx_l4_abe_hwmod,
4525         .slave          = &omap44xx_wd_timer3_hwmod,
4526         .clk            = "ocp_abe_iclk",
4527         .addr           = omap44xx_wd_timer3_addrs,
4528         .user           = OCP_USER_MPU,
4529 };
4530
4531 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4532         {
4533                 .pa_start       = 0x49030000,
4534                 .pa_end         = 0x4903007f,
4535                 .flags          = ADDR_TYPE_RT
4536         },
4537         { }
4538 };
4539
4540 /* l4_abe -> wd_timer3 (dma) */
4541 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4542         .master         = &omap44xx_l4_abe_hwmod,
4543         .slave          = &omap44xx_wd_timer3_hwmod,
4544         .clk            = "ocp_abe_iclk",
4545         .addr           = omap44xx_wd_timer3_dma_addrs,
4546         .user           = OCP_USER_SDMA,
4547 };
4548
4549 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
4550         .name           = "wd_timer3",
4551         .class          = &omap44xx_wd_timer_hwmod_class,
4552         .clkdm_name     = "abe_clkdm",
4553         .mpu_irqs       = omap44xx_wd_timer3_irqs,
4554         .main_clk       = "wd_timer3_fck",
4555         .prcm = {
4556                 .omap4 = {
4557                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
4558                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
4559                         .modulemode   = MODULEMODE_SWCTRL,
4560                 },
4561         },
4562 };
4563
4564 /*
4565  * 'usb_host_hs' class
4566  * high-speed multi-port usb host controller
4567  */
4568 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
4569         .master         = &omap44xx_usb_host_hs_hwmod,
4570         .slave          = &omap44xx_l3_main_2_hwmod,
4571         .clk            = "l3_div_ck",
4572         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4573 };
4574
4575 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
4576         .rev_offs       = 0x0000,
4577         .sysc_offs      = 0x0010,
4578         .syss_offs      = 0x0014,
4579         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4580                            SYSC_HAS_SOFTRESET),
4581         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4582                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4583                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
4584         .sysc_fields    = &omap_hwmod_sysc_type2,
4585 };
4586
4587 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
4588         .name = "usb_host_hs",
4589         .sysc = &omap44xx_usb_host_hs_sysc,
4590 };
4591
4592 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
4593         {
4594                 .name           = "uhh",
4595                 .pa_start       = 0x4a064000,
4596                 .pa_end         = 0x4a0647ff,
4597                 .flags          = ADDR_TYPE_RT
4598         },
4599         {
4600                 .name           = "ohci",
4601                 .pa_start       = 0x4a064800,
4602                 .pa_end         = 0x4a064bff,
4603         },
4604         {
4605                 .name           = "ehci",
4606                 .pa_start       = 0x4a064c00,
4607                 .pa_end         = 0x4a064fff,
4608         },
4609         {}
4610 };
4611
4612 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
4613         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
4614         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
4615         { .irq = -1 }
4616 };
4617
4618 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4619         .master         = &omap44xx_l4_cfg_hwmod,
4620         .slave          = &omap44xx_usb_host_hs_hwmod,
4621         .clk            = "l4_div_ck",
4622         .addr           = omap44xx_usb_host_hs_addrs,
4623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4624 };
4625
4626 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
4627         .name           = "usb_host_hs",
4628         .class          = &omap44xx_usb_host_hs_hwmod_class,
4629         .clkdm_name     = "l3_init_clkdm",
4630         .main_clk       = "usb_host_hs_fck",
4631         .prcm = {
4632                 .omap4 = {
4633                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
4634                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
4635                         .modulemode   = MODULEMODE_SWCTRL,
4636                 },
4637         },
4638         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
4639
4640         /*
4641          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
4642          * id: i660
4643          *
4644          * Description:
4645          * In the following configuration :
4646          * - USBHOST module is set to smart-idle mode
4647          * - PRCM asserts idle_req to the USBHOST module ( This typically
4648          *   happens when the system is going to a low power mode : all ports
4649          *   have been suspended, the master part of the USBHOST module has
4650          *   entered the standby state, and SW has cut the functional clocks)
4651          * - an USBHOST interrupt occurs before the module is able to answer
4652          *   idle_ack, typically a remote wakeup IRQ.
4653          * Then the USB HOST module will enter a deadlock situation where it
4654          * is no more accessible nor functional.
4655          *
4656          * Workaround:
4657          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
4658          */
4659
4660         /*
4661          * Errata: USB host EHCI may stall when entering smart-standby mode
4662          * Id: i571
4663          *
4664          * Description:
4665          * When the USBHOST module is set to smart-standby mode, and when it is
4666          * ready to enter the standby state (i.e. all ports are suspended and
4667          * all attached devices are in suspend mode), then it can wrongly assert
4668          * the Mstandby signal too early while there are still some residual OCP
4669          * transactions ongoing. If this condition occurs, the internal state
4670          * machine may go to an undefined state and the USB link may be stuck
4671          * upon the next resume.
4672          *
4673          * Workaround:
4674          * Don't use smart standby; use only force standby,
4675          * hence HWMOD_SWSUP_MSTANDBY
4676          */
4677
4678         /*
4679          * During system boot; If the hwmod framework resets the module
4680          * the module will have smart idle settings; which can lead to deadlock
4681          * (above Errata Id:i660); so, dont reset the module during boot;
4682          * Use HWMOD_INIT_NO_RESET.
4683          */
4684
4685         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
4686                           HWMOD_INIT_NO_RESET,
4687 };
4688
4689 /*
4690  * 'usb_tll_hs' class
4691  * usb_tll_hs module is the adapter on the usb_host_hs ports
4692  */
4693 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
4694         .rev_offs       = 0x0000,
4695         .sysc_offs      = 0x0010,
4696         .syss_offs      = 0x0014,
4697         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
4698                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
4699                            SYSC_HAS_AUTOIDLE),
4700         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4701         .sysc_fields    = &omap_hwmod_sysc_type1,
4702 };
4703
4704 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
4705         .name = "usb_tll_hs",
4706         .sysc = &omap44xx_usb_tll_hs_sysc,
4707 };
4708
4709 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
4710         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
4711         { .irq = -1 }
4712 };
4713
4714 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
4715         {
4716                 .name           = "tll",
4717                 .pa_start       = 0x4a062000,
4718                 .pa_end         = 0x4a063fff,
4719                 .flags          = ADDR_TYPE_RT
4720         },
4721         {}
4722 };
4723
4724 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4725         .master         = &omap44xx_l4_cfg_hwmod,
4726         .slave          = &omap44xx_usb_tll_hs_hwmod,
4727         .clk            = "l4_div_ck",
4728         .addr           = omap44xx_usb_tll_hs_addrs,
4729         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4730 };
4731
4732 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
4733         .name           = "usb_tll_hs",
4734         .class          = &omap44xx_usb_tll_hs_hwmod_class,
4735         .clkdm_name     = "l3_init_clkdm",
4736         .main_clk       = "usb_tll_hs_ick",
4737         .prcm = {
4738                 .omap4 = {
4739                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
4740                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
4741                         .modulemode   = MODULEMODE_HWCTRL,
4742                 },
4743         },
4744         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
4745 };
4746
4747 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4748         &omap44xx_l3_main_1__dmm,
4749         &omap44xx_mpu__dmm,
4750         &omap44xx_dmm__emif_fw,
4751         &omap44xx_l4_cfg__emif_fw,
4752         &omap44xx_iva__l3_instr,
4753         &omap44xx_l3_main_3__l3_instr,
4754         &omap44xx_dsp__l3_main_1,
4755         &omap44xx_dss__l3_main_1,
4756         &omap44xx_l3_main_2__l3_main_1,
4757         &omap44xx_l4_cfg__l3_main_1,
4758         &omap44xx_mmc1__l3_main_1,
4759         &omap44xx_mmc2__l3_main_1,
4760         &omap44xx_mpu__l3_main_1,
4761         &omap44xx_dma_system__l3_main_2,
4762         &omap44xx_hsi__l3_main_2,
4763         &omap44xx_ipu__l3_main_2,
4764         &omap44xx_iss__l3_main_2,
4765         &omap44xx_iva__l3_main_2,
4766         &omap44xx_l3_main_1__l3_main_2,
4767         &omap44xx_l4_cfg__l3_main_2,
4768         &omap44xx_usb_host_hs__l3_main_2,
4769         &omap44xx_usb_otg_hs__l3_main_2,
4770         &omap44xx_l3_main_1__l3_main_3,
4771         &omap44xx_l3_main_2__l3_main_3,
4772         &omap44xx_l4_cfg__l3_main_3,
4773         &omap44xx_aess__l4_abe,
4774         &omap44xx_dsp__l4_abe,
4775         &omap44xx_l3_main_1__l4_abe,
4776         &omap44xx_mpu__l4_abe,
4777         &omap44xx_l3_main_1__l4_cfg,
4778         &omap44xx_l3_main_2__l4_per,
4779         &omap44xx_l4_cfg__l4_wkup,
4780         &omap44xx_mpu__mpu_private,
4781         &omap44xx_l4_abe__aess,
4782         &omap44xx_l4_abe__aess_dma,
4783         &omap44xx_l4_wkup__counter_32k,
4784         &omap44xx_l4_cfg__dma_system,
4785         &omap44xx_l4_abe__dmic,
4786         &omap44xx_l4_abe__dmic_dma,
4787         &omap44xx_dsp__iva,
4788         &omap44xx_l4_cfg__dsp,
4789         &omap44xx_l3_main_2__dss,
4790         &omap44xx_l4_per__dss,
4791         &omap44xx_l3_main_2__dss_dispc,
4792         &omap44xx_l4_per__dss_dispc,
4793         &omap44xx_l3_main_2__dss_dsi1,
4794         &omap44xx_l4_per__dss_dsi1,
4795         &omap44xx_l3_main_2__dss_dsi2,
4796         &omap44xx_l4_per__dss_dsi2,
4797         &omap44xx_l3_main_2__dss_hdmi,
4798         &omap44xx_l4_per__dss_hdmi,
4799         &omap44xx_l3_main_2__dss_rfbi,
4800         &omap44xx_l4_per__dss_rfbi,
4801         &omap44xx_l3_main_2__dss_venc,
4802         &omap44xx_l4_per__dss_venc,
4803         &omap44xx_l4_wkup__gpio1,
4804         &omap44xx_l4_per__gpio2,
4805         &omap44xx_l4_per__gpio3,
4806         &omap44xx_l4_per__gpio4,
4807         &omap44xx_l4_per__gpio5,
4808         &omap44xx_l4_per__gpio6,
4809         &omap44xx_l4_cfg__hsi,
4810         &omap44xx_l4_per__i2c1,
4811         &omap44xx_l4_per__i2c2,
4812         &omap44xx_l4_per__i2c3,
4813         &omap44xx_l4_per__i2c4,
4814         &omap44xx_l3_main_2__ipu,
4815         &omap44xx_l3_main_2__iss,
4816         &omap44xx_l3_main_2__iva,
4817         &omap44xx_l4_wkup__kbd,
4818         &omap44xx_l4_cfg__mailbox,
4819         &omap44xx_l4_abe__mcbsp1,
4820         &omap44xx_l4_abe__mcbsp1_dma,
4821         &omap44xx_l4_abe__mcbsp2,
4822         &omap44xx_l4_abe__mcbsp2_dma,
4823         &omap44xx_l4_abe__mcbsp3,
4824         &omap44xx_l4_abe__mcbsp3_dma,
4825         &omap44xx_l4_per__mcbsp4,
4826         &omap44xx_l4_abe__mcpdm,
4827         &omap44xx_l4_abe__mcpdm_dma,
4828         &omap44xx_l4_per__mcspi1,
4829         &omap44xx_l4_per__mcspi2,
4830         &omap44xx_l4_per__mcspi3,
4831         &omap44xx_l4_per__mcspi4,
4832         &omap44xx_l4_per__mmc1,
4833         &omap44xx_l4_per__mmc2,
4834         &omap44xx_l4_per__mmc3,
4835         &omap44xx_l4_per__mmc4,
4836         &omap44xx_l4_per__mmc5,
4837         &omap44xx_l4_cfg__smartreflex_core,
4838         &omap44xx_l4_cfg__smartreflex_iva,
4839         &omap44xx_l4_cfg__smartreflex_mpu,
4840         &omap44xx_l4_cfg__spinlock,
4841         &omap44xx_l4_wkup__timer1,
4842         &omap44xx_l4_per__timer2,
4843         &omap44xx_l4_per__timer3,
4844         &omap44xx_l4_per__timer4,
4845         &omap44xx_l4_abe__timer5,
4846         &omap44xx_l4_abe__timer5_dma,
4847         &omap44xx_l4_abe__timer6,
4848         &omap44xx_l4_abe__timer6_dma,
4849         &omap44xx_l4_abe__timer7,
4850         &omap44xx_l4_abe__timer7_dma,
4851         &omap44xx_l4_abe__timer8,
4852         &omap44xx_l4_abe__timer8_dma,
4853         &omap44xx_l4_per__timer9,
4854         &omap44xx_l4_per__timer10,
4855         &omap44xx_l4_per__timer11,
4856         &omap44xx_l4_per__uart1,
4857         &omap44xx_l4_per__uart2,
4858         &omap44xx_l4_per__uart3,
4859         &omap44xx_l4_per__uart4,
4860         &omap44xx_l4_cfg__usb_host_hs,
4861         &omap44xx_l4_cfg__usb_otg_hs,
4862         &omap44xx_l4_cfg__usb_tll_hs,
4863         &omap44xx_l4_wkup__wd_timer2,
4864         &omap44xx_l4_abe__wd_timer3,
4865         &omap44xx_l4_abe__wd_timer3_dma,
4866         NULL,
4867 };
4868
4869 int __init omap44xx_hwmod_init(void)
4870 {
4871         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4872 }
4873