arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/gpio.h>
  26 #include <plat/dma.h>
  27 #include <plat/mcspi.h>
  28 #include <plat/mcbsp.h>
  29 #include <plat/mmc.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "cm1_44xx.h"
  34 #include "cm2_44xx.h"
  35 #include "prm44xx.h"
  36 #include "prm-regbits-44xx.h"
  37 #include "wd_timer.h"
  38
  39 /* Base offset for all OMAP4 interrupts external to MPUSS */
  40 #define OMAP44XX_IRQ_GIC_START  32
  41
  42 /* Base offset for all OMAP4 dma requests */
  43 #define OMAP44XX_DMA_REQ_START  1
  44
  45 /* Backward references (IPs with Bus Master capability) */
  46 static struct omap_hwmod omap44xx_aess_hwmod;
  47 static struct omap_hwmod omap44xx_dma_system_hwmod;
  48 static struct omap_hwmod omap44xx_dmm_hwmod;
  49 static struct omap_hwmod omap44xx_dsp_hwmod;
  50 static struct omap_hwmod omap44xx_dss_hwmod;
  51 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  52 static struct omap_hwmod omap44xx_hsi_hwmod;
  53 static struct omap_hwmod omap44xx_ipu_hwmod;
  54 static struct omap_hwmod omap44xx_iss_hwmod;
  55 static struct omap_hwmod omap44xx_iva_hwmod;
  56 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  57 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  58 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  59 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  60 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  61 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  62 static struct omap_hwmod omap44xx_l4_per_hwmod;
  63 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  64 static struct omap_hwmod omap44xx_mmc1_hwmod;
  65 static struct omap_hwmod omap44xx_mmc2_hwmod;
  66 static struct omap_hwmod omap44xx_mpu_hwmod;
  67 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  68 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  69
  70 /*
  71  * Interconnects omap_hwmod structures
  72  * hwmods that compose the global OMAP interconnect
  73  */
  74
  75 /*
  76  * 'dmm' class
  77  * instance(s): dmm
  78  */
  79 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  80         .name   = "dmm",
  81 };
  82
  83 /* dmm */
  84 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  85         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  86         { .irq = -1 }
  87 };
  88
  89 /* l3_main_1 -> dmm */
  90 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  91         .master         = &omap44xx_l3_main_1_hwmod,
  92         .slave          = &omap44xx_dmm_hwmod,
  93         .clk            = "l3_div_ck",
  94         .user           = OCP_USER_SDMA,
  95 };
  96
  97 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
  98         {
  99                 .pa_start       = 0x4e000000,
 100                 .pa_end         = 0x4e0007ff,
 101                 .flags          = ADDR_TYPE_RT
 102         },
 103         { }
 104 };
 105
 106 /* mpu -> dmm */
 107 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 108         .master         = &omap44xx_mpu_hwmod,
 109         .slave          = &omap44xx_dmm_hwmod,
 110         .clk            = "l3_div_ck",
 111         .addr           = omap44xx_dmm_addrs,
 112         .user           = OCP_USER_MPU,
 113 };
 114
 115 /* dmm slave ports */
 116 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 117         &omap44xx_l3_main_1__dmm,
 118         &omap44xx_mpu__dmm,
 119 };
 120
 121 static struct omap_hwmod omap44xx_dmm_hwmod = {
 122         .name           = "dmm",
 123         .class          = &omap44xx_dmm_hwmod_class,
 124         .mpu_irqs       = omap44xx_dmm_irqs,
 125         .slaves         = omap44xx_dmm_slaves,
 126         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 127         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 128 };
 129
 130 /*
 131  * 'emif_fw' class
 132  * instance(s): emif_fw
 133  */
 134 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 135         .name   = "emif_fw",
 136 };
 137
 138 /* emif_fw */
 139 /* dmm -> emif_fw */
 140 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 141         .master         = &omap44xx_dmm_hwmod,
 142         .slave          = &omap44xx_emif_fw_hwmod,
 143         .clk            = "l3_div_ck",
 144         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 145 };
 146
 147 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 148         {
 149                 .pa_start       = 0x4a20c000,
 150                 .pa_end         = 0x4a20c0ff,
 151                 .flags          = ADDR_TYPE_RT
 152         },
 153         { }
 154 };
 155
 156 /* l4_cfg -> emif_fw */
 157 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 158         .master         = &omap44xx_l4_cfg_hwmod,
 159         .slave          = &omap44xx_emif_fw_hwmod,
 160         .clk            = "l4_div_ck",
 161         .addr           = omap44xx_emif_fw_addrs,
 162         .user           = OCP_USER_MPU,
 163 };
 164
 165 /* emif_fw slave ports */
 166 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 167         &omap44xx_dmm__emif_fw,
 168         &omap44xx_l4_cfg__emif_fw,
 169 };
 170
 171 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 172         .name           = "emif_fw",
 173         .class          = &omap44xx_emif_fw_hwmod_class,
 174         .slaves         = omap44xx_emif_fw_slaves,
 175         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 176         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 177 };
 178
 179 /*
 180  * 'l3' class
 181  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 182  */
 183 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 184         .name   = "l3",
 185 };
 186
 187 /* l3_instr */
 188 /* iva -> l3_instr */
 189 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 190         .master         = &omap44xx_iva_hwmod,
 191         .slave          = &omap44xx_l3_instr_hwmod,
 192         .clk            = "l3_div_ck",
 193         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 194 };
 195
 196 /* l3_main_3 -> l3_instr */
 197 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 198         .master         = &omap44xx_l3_main_3_hwmod,
 199         .slave          = &omap44xx_l3_instr_hwmod,
 200         .clk            = "l3_div_ck",
 201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 202 };
 203
 204 /* l3_instr slave ports */
 205 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 206         &omap44xx_iva__l3_instr,
 207         &omap44xx_l3_main_3__l3_instr,
 208 };
 209
 210 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 211         .name           = "l3_instr",
 212         .class          = &omap44xx_l3_hwmod_class,
 213         .slaves         = omap44xx_l3_instr_slaves,
 214         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 215         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 216 };
 217
 218 /* l3_main_1 */
 219 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 220         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 221         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 222         { .irq = -1 }
 223 };
 224
 225 /* dsp -> l3_main_1 */
 226 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 227         .master         = &omap44xx_dsp_hwmod,
 228         .slave          = &omap44xx_l3_main_1_hwmod,
 229         .clk            = "l3_div_ck",
 230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 231 };
 232
 233 /* dss -> l3_main_1 */
 234 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 235         .master         = &omap44xx_dss_hwmod,
 236         .slave          = &omap44xx_l3_main_1_hwmod,
 237         .clk            = "l3_div_ck",
 238         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 239 };
 240
 241 /* l3_main_2 -> l3_main_1 */
 242 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 243         .master         = &omap44xx_l3_main_2_hwmod,
 244         .slave          = &omap44xx_l3_main_1_hwmod,
 245         .clk            = "l3_div_ck",
 246         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 247 };
 248
 249 /* l4_cfg -> l3_main_1 */
 250 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 251         .master         = &omap44xx_l4_cfg_hwmod,
 252         .slave          = &omap44xx_l3_main_1_hwmod,
 253         .clk            = "l4_div_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 /* mmc1 -> l3_main_1 */
 258 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 259         .master         = &omap44xx_mmc1_hwmod,
 260         .slave          = &omap44xx_l3_main_1_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* mmc2 -> l3_main_1 */
 266 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 267         .master         = &omap44xx_mmc2_hwmod,
 268         .slave          = &omap44xx_l3_main_1_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 274         {
 275                 .pa_start       = 0x44000000,
 276                 .pa_end         = 0x44000fff,
 277                 .flags          = ADDR_TYPE_RT
 278         },
 279         { }
 280 };
 281
 282 /* mpu -> l3_main_1 */
 283 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 284         .master         = &omap44xx_mpu_hwmod,
 285         .slave          = &omap44xx_l3_main_1_hwmod,
 286         .clk            = "l3_div_ck",
 287         .addr           = omap44xx_l3_main_1_addrs,
 288         .user           = OCP_USER_MPU,
 289 };
 290
 291 /* l3_main_1 slave ports */
 292 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 293         &omap44xx_dsp__l3_main_1,
 294         &omap44xx_dss__l3_main_1,
 295         &omap44xx_l3_main_2__l3_main_1,
 296         &omap44xx_l4_cfg__l3_main_1,
 297         &omap44xx_mmc1__l3_main_1,
 298         &omap44xx_mmc2__l3_main_1,
 299         &omap44xx_mpu__l3_main_1,
 300 };
 301
 302 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 303         .name           = "l3_main_1",
 304         .class          = &omap44xx_l3_hwmod_class,
 305         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 306         .slaves         = omap44xx_l3_main_1_slaves,
 307         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 308         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 309 };
 310
 311 /* l3_main_2 */
 312 /* dma_system -> l3_main_2 */
 313 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 314         .master         = &omap44xx_dma_system_hwmod,
 315         .slave          = &omap44xx_l3_main_2_hwmod,
 316         .clk            = "l3_div_ck",
 317         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 318 };
 319
 320 /* hsi -> l3_main_2 */
 321 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 322         .master         = &omap44xx_hsi_hwmod,
 323         .slave          = &omap44xx_l3_main_2_hwmod,
 324         .clk            = "l3_div_ck",
 325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 326 };
 327
 328 /* ipu -> l3_main_2 */
 329 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 330         .master         = &omap44xx_ipu_hwmod,
 331         .slave          = &omap44xx_l3_main_2_hwmod,
 332         .clk            = "l3_div_ck",
 333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 334 };
 335
 336 /* iss -> l3_main_2 */
 337 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 338         .master         = &omap44xx_iss_hwmod,
 339         .slave          = &omap44xx_l3_main_2_hwmod,
 340         .clk            = "l3_div_ck",
 341         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 342 };
 343
 344 /* iva -> l3_main_2 */
 345 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 346         .master         = &omap44xx_iva_hwmod,
 347         .slave          = &omap44xx_l3_main_2_hwmod,
 348         .clk            = "l3_div_ck",
 349         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 350 };
 351
 352 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 353         {
 354                 .pa_start       = 0x44800000,
 355                 .pa_end         = 0x44801fff,
 356                 .flags          = ADDR_TYPE_RT
 357         },
 358         { }
 359 };
 360
 361 /* l3_main_1 -> l3_main_2 */
 362 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 363         .master         = &omap44xx_l3_main_1_hwmod,
 364         .slave          = &omap44xx_l3_main_2_hwmod,
 365         .clk            = "l3_div_ck",
 366         .addr           = omap44xx_l3_main_2_addrs,
 367         .user           = OCP_USER_MPU,
 368 };
 369
 370 /* l4_cfg -> l3_main_2 */
 371 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 372         .master         = &omap44xx_l4_cfg_hwmod,
 373         .slave          = &omap44xx_l3_main_2_hwmod,
 374         .clk            = "l4_div_ck",
 375         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 376 };
 377
 378 /* usb_otg_hs -> l3_main_2 */
 379 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 380         .master         = &omap44xx_usb_otg_hs_hwmod,
 381         .slave          = &omap44xx_l3_main_2_hwmod,
 382         .clk            = "l3_div_ck",
 383         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 384 };
 385
 386 /* l3_main_2 slave ports */
 387 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 388         &omap44xx_dma_system__l3_main_2,
 389         &omap44xx_hsi__l3_main_2,
 390         &omap44xx_ipu__l3_main_2,
 391         &omap44xx_iss__l3_main_2,
 392         &omap44xx_iva__l3_main_2,
 393         &omap44xx_l3_main_1__l3_main_2,
 394         &omap44xx_l4_cfg__l3_main_2,
 395         &omap44xx_usb_otg_hs__l3_main_2,
 396 };
 397
 398 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 399         .name           = "l3_main_2",
 400         .class          = &omap44xx_l3_hwmod_class,
 401         .slaves         = omap44xx_l3_main_2_slaves,
 402         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 403         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 404 };
 405
 406 /* l3_main_3 */
 407 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 408         {
 409                 .pa_start       = 0x45000000,
 410                 .pa_end         = 0x45000fff,
 411                 .flags          = ADDR_TYPE_RT
 412         },
 413         { }
 414 };
 415
 416 /* l3_main_1 -> l3_main_3 */
 417 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 418         .master         = &omap44xx_l3_main_1_hwmod,
 419         .slave          = &omap44xx_l3_main_3_hwmod,
 420         .clk            = "l3_div_ck",
 421         .addr           = omap44xx_l3_main_3_addrs,
 422         .user           = OCP_USER_MPU,
 423 };
 424
 425 /* l3_main_2 -> l3_main_3 */
 426 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 427         .master         = &omap44xx_l3_main_2_hwmod,
 428         .slave          = &omap44xx_l3_main_3_hwmod,
 429         .clk            = "l3_div_ck",
 430         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 431 };
 432
 433 /* l4_cfg -> l3_main_3 */
 434 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 435         .master         = &omap44xx_l4_cfg_hwmod,
 436         .slave          = &omap44xx_l3_main_3_hwmod,
 437         .clk            = "l4_div_ck",
 438         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 439 };
 440
 441 /* l3_main_3 slave ports */
 442 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 443         &omap44xx_l3_main_1__l3_main_3,
 444         &omap44xx_l3_main_2__l3_main_3,
 445         &omap44xx_l4_cfg__l3_main_3,
 446 };
 447
 448 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 449         .name           = "l3_main_3",
 450         .class          = &omap44xx_l3_hwmod_class,
 451         .slaves         = omap44xx_l3_main_3_slaves,
 452         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 453         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 454 };
 455
 456 /*
 457  * 'l4' class
 458  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 459  */
 460 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 461         .name   = "l4",
 462 };
 463
 464 /* l4_abe */
 465 /* aess -> l4_abe */
 466 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 467         .master         = &omap44xx_aess_hwmod,
 468         .slave          = &omap44xx_l4_abe_hwmod,
 469         .clk            = "ocp_abe_iclk",
 470         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 471 };
 472
 473 /* dsp -> l4_abe */
 474 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 475         .master         = &omap44xx_dsp_hwmod,
 476         .slave          = &omap44xx_l4_abe_hwmod,
 477         .clk            = "ocp_abe_iclk",
 478         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 479 };
 480
 481 /* l3_main_1 -> l4_abe */
 482 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 483         .master         = &omap44xx_l3_main_1_hwmod,
 484         .slave          = &omap44xx_l4_abe_hwmod,
 485         .clk            = "l3_div_ck",
 486         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 487 };
 488
 489 /* mpu -> l4_abe */
 490 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 491         .master         = &omap44xx_mpu_hwmod,
 492         .slave          = &omap44xx_l4_abe_hwmod,
 493         .clk            = "ocp_abe_iclk",
 494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 495 };
 496
 497 /* l4_abe slave ports */
 498 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 499         &omap44xx_aess__l4_abe,
 500         &omap44xx_dsp__l4_abe,
 501         &omap44xx_l3_main_1__l4_abe,
 502         &omap44xx_mpu__l4_abe,
 503 };
 504
 505 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 506         .name           = "l4_abe",
 507         .class          = &omap44xx_l4_hwmod_class,
 508         .slaves         = omap44xx_l4_abe_slaves,
 509         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 510         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 511 };
 512
 513 /* l4_cfg */
 514 /* l3_main_1 -> l4_cfg */
 515 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 516         .master         = &omap44xx_l3_main_1_hwmod,
 517         .slave          = &omap44xx_l4_cfg_hwmod,
 518         .clk            = "l3_div_ck",
 519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 520 };
 521
 522 /* l4_cfg slave ports */
 523 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 524         &omap44xx_l3_main_1__l4_cfg,
 525 };
 526
 527 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 528         .name           = "l4_cfg",
 529         .class          = &omap44xx_l4_hwmod_class,
 530         .slaves         = omap44xx_l4_cfg_slaves,
 531         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 532         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 533 };
 534
 535 /* l4_per */
 536 /* l3_main_2 -> l4_per */
 537 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 538         .master         = &omap44xx_l3_main_2_hwmod,
 539         .slave          = &omap44xx_l4_per_hwmod,
 540         .clk            = "l3_div_ck",
 541         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 542 };
 543
 544 /* l4_per slave ports */
 545 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 546         &omap44xx_l3_main_2__l4_per,
 547 };
 548
 549 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 550         .name           = "l4_per",
 551         .class          = &omap44xx_l4_hwmod_class,
 552         .slaves         = omap44xx_l4_per_slaves,
 553         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 554         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 555 };
 556
 557 /* l4_wkup */
 558 /* l4_cfg -> l4_wkup */
 559 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 560         .master         = &omap44xx_l4_cfg_hwmod,
 561         .slave          = &omap44xx_l4_wkup_hwmod,
 562         .clk            = "l4_div_ck",
 563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 564 };
 565
 566 /* l4_wkup slave ports */
 567 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 568         &omap44xx_l4_cfg__l4_wkup,
 569 };
 570
 571 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 572         .name           = "l4_wkup",
 573         .class          = &omap44xx_l4_hwmod_class,
 574         .slaves         = omap44xx_l4_wkup_slaves,
 575         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 576         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 577 };
 578
 579 /*
 580  * 'mpu_bus' class
 581  * instance(s): mpu_private
 582  */
 583 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 584         .name   = "mpu_bus",
 585 };
 586
 587 /* mpu_private */
 588 /* mpu -> mpu_private */
 589 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 590         .master         = &omap44xx_mpu_hwmod,
 591         .slave          = &omap44xx_mpu_private_hwmod,
 592         .clk            = "l3_div_ck",
 593         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 594 };
 595
 596 /* mpu_private slave ports */
 597 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 598         &omap44xx_mpu__mpu_private,
 599 };
 600
 601 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 602         .name           = "mpu_private",
 603         .class          = &omap44xx_mpu_bus_hwmod_class,
 604         .slaves         = omap44xx_mpu_private_slaves,
 605         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 606         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 607 };
 608
 609 /*
 610  * Modules omap_hwmod structures
 611  *
 612  * The following IPs are excluded for the moment because:
 613  * - They do not need an explicit SW control using omap_hwmod API.
 614  * - They still need to be validated with the driver
 615  *   properly adapted to omap_hwmod / omap_device
 616  *
 617  *  c2c
 618  *  c2c_target_fw
 619  *  cm_core
 620  *  cm_core_aon
 621  *  ctrl_module_core
 622  *  ctrl_module_pad_core
 623  *  ctrl_module_pad_wkup
 624  *  ctrl_module_wkup
 625  *  debugss
 626  *  efuse_ctrl_cust
 627  *  efuse_ctrl_std
 628  *  elm
 629  *  emif1
 630  *  emif2
 631  *  fdif
 632  *  gpmc
 633  *  gpu
 634  *  hdq1w
 635  *  mcasp
 636  *  mpu_c0
 637  *  mpu_c1
 638  *  ocmc_ram
 639  *  ocp2scp_usb_phy
 640  *  ocp_wp_noc
 641  *  prcm_mpu
 642  *  prm
 643  *  scrm
 644  *  sl2if
 645  *  slimbus1
 646  *  slimbus2
 647  *  usb_host_fs
 648  *  usb_host_hs
 649  *  usb_phy_cm
 650  *  usb_tll_hs
 651  *  usim
 652  */
 653
 654 /*
 655  * 'aess' class
 656  * audio engine sub system
 657  */
 658
 659 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 660         .rev_offs       = 0x0000,
 661         .sysc_offs      = 0x0010,
 662         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 663         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 664                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 665                            MSTANDBY_SMART_WKUP),
 666         .sysc_fields    = &omap_hwmod_sysc_type2,
 667 };
 668
 669 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 670         .name   = "aess",
 671         .sysc   = &omap44xx_aess_sysc,
 672 };
 673
 674 /* aess */
 675 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 676         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 677         { .irq = -1 }
 678 };
 679
 680 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 681         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 682         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 683         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 684         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 685         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 686         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 687         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 688         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 689         { .dma_req = -1 }
 690 };
 691
 692 /* aess master ports */
 693 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 694         &omap44xx_aess__l4_abe,
 695 };
 696
 697 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 698         {
 699                 .pa_start       = 0x401f1000,
 700                 .pa_end         = 0x401f13ff,
 701                 .flags          = ADDR_TYPE_RT
 702         },
 703         { }
 704 };
 705
 706 /* l4_abe -> aess */
 707 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 708         .master         = &omap44xx_l4_abe_hwmod,
 709         .slave          = &omap44xx_aess_hwmod,
 710         .clk            = "ocp_abe_iclk",
 711         .addr           = omap44xx_aess_addrs,
 712         .user           = OCP_USER_MPU,
 713 };
 714
 715 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 716         {
 717                 .pa_start       = 0x490f1000,
 718                 .pa_end         = 0x490f13ff,
 719                 .flags          = ADDR_TYPE_RT
 720         },
 721         { }
 722 };
 723
 724 /* l4_abe -> aess (dma) */
 725 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 726         .master         = &omap44xx_l4_abe_hwmod,
 727         .slave          = &omap44xx_aess_hwmod,
 728         .clk            = "ocp_abe_iclk",
 729         .addr           = omap44xx_aess_dma_addrs,
 730         .user           = OCP_USER_SDMA,
 731 };
 732
 733 /* aess slave ports */
 734 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 735         &omap44xx_l4_abe__aess,
 736         &omap44xx_l4_abe__aess_dma,
 737 };
 738
 739 static struct omap_hwmod omap44xx_aess_hwmod = {
 740         .name           = "aess",
 741         .class          = &omap44xx_aess_hwmod_class,
 742         .mpu_irqs       = omap44xx_aess_irqs,
 743         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 744         .main_clk       = "aess_fck",
 745         .prcm = {
 746                 .omap4 = {
 747                         .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
 748                 },
 749         },
 750         .slaves         = omap44xx_aess_slaves,
 751         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 752         .masters        = omap44xx_aess_masters,
 753         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 754         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 755 };
 756
 757 /*
 758  * 'bandgap' class
 759  * bangap reference for ldo regulators
 760  */
 761
 762 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 763         .name   = "bandgap",
 764 };
 765
 766 /* bandgap */
 767 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 768         { .role = "fclk", .clk = "bandgap_fclk" },
 769 };
 770
 771 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 772         .name           = "bandgap",
 773         .class          = &omap44xx_bandgap_hwmod_class,
 774         .prcm = {
 775                 .omap4 = {
 776                         .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
 777                 },
 778         },
 779         .opt_clks       = bandgap_opt_clks,
 780         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 781         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 782 };
 783
 784 /*
 785  * 'counter' class
 786  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 787  */
 788
 789 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 790         .rev_offs       = 0x0000,
 791         .sysc_offs      = 0x0004,
 792         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 793         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 794                            SIDLE_SMART_WKUP),
 795         .sysc_fields    = &omap_hwmod_sysc_type1,
 796 };
 797
 798 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 799         .name   = "counter",
 800         .sysc   = &omap44xx_counter_sysc,
 801 };
 802
 803 /* counter_32k */
 804 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 805 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 806         {
 807                 .pa_start       = 0x4a304000,
 808                 .pa_end         = 0x4a30401f,
 809                 .flags          = ADDR_TYPE_RT
 810         },
 811         { }
 812 };
 813
 814 /* l4_wkup -> counter_32k */
 815 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 816         .master         = &omap44xx_l4_wkup_hwmod,
 817         .slave          = &omap44xx_counter_32k_hwmod,
 818         .clk            = "l4_wkup_clk_mux_ck",
 819         .addr           = omap44xx_counter_32k_addrs,
 820         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 821 };
 822
 823 /* counter_32k slave ports */
 824 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 825         &omap44xx_l4_wkup__counter_32k,
 826 };
 827
 828 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 829         .name           = "counter_32k",
 830         .class          = &omap44xx_counter_hwmod_class,
 831         .flags          = HWMOD_SWSUP_SIDLE,
 832         .main_clk       = "sys_32k_ck",
 833         .prcm = {
 834                 .omap4 = {
 835                         .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
 836                 },
 837         },
 838         .slaves         = omap44xx_counter_32k_slaves,
 839         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 840         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 841 };
 842
 843 /*
 844  * 'dma' class
 845  * dma controller for data exchange between memory to memory (i.e. internal or
 846  * external memory) and gp peripherals to memory or memory to gp peripherals
 847  */
 848
 849 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 850         .rev_offs       = 0x0000,
 851         .sysc_offs      = 0x002c,
 852         .syss_offs      = 0x0028,
 853         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 854                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 855                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 856                            SYSS_HAS_RESET_STATUS),
 857         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 858                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 859         .sysc_fields    = &omap_hwmod_sysc_type1,
 860 };
 861
 862 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 863         .name   = "dma",
 864         .sysc   = &omap44xx_dma_sysc,
 865 };
 866
 867 /* dma dev_attr */
 868 static struct omap_dma_dev_attr dma_dev_attr = {
 869         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 870                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 871         .lch_count      = 32,
 872 };
 873
 874 /* dma_system */
 875 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 876         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 877         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 878         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 879         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 880         { .irq = -1 }
 881 };
 882
 883 /* dma_system master ports */
 884 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 885         &omap44xx_dma_system__l3_main_2,
 886 };
 887
 888 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 889         {
 890                 .pa_start       = 0x4a056000,
 891                 .pa_end         = 0x4a056fff,
 892                 .flags          = ADDR_TYPE_RT
 893         },
 894         { }
 895 };
 896
 897 /* l4_cfg -> dma_system */
 898 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 899         .master         = &omap44xx_l4_cfg_hwmod,
 900         .slave          = &omap44xx_dma_system_hwmod,
 901         .clk            = "l4_div_ck",
 902         .addr           = omap44xx_dma_system_addrs,
 903         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 904 };
 905
 906 /* dma_system slave ports */
 907 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 908         &omap44xx_l4_cfg__dma_system,
 909 };
 910
 911 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 912         .name           = "dma_system",
 913         .class          = &omap44xx_dma_hwmod_class,
 914         .mpu_irqs       = omap44xx_dma_system_irqs,
 915         .main_clk       = "l3_div_ck",
 916         .prcm = {
 917                 .omap4 = {
 918                         .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
 919                 },
 920         },
 921         .dev_attr       = &dma_dev_attr,
 922         .slaves         = omap44xx_dma_system_slaves,
 923         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 924         .masters        = omap44xx_dma_system_masters,
 925         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 926         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 927 };
 928
 929 /*
 930  * 'dmic' class
 931  * digital microphone controller
 932  */
 933
 934 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 935         .rev_offs       = 0x0000,
 936         .sysc_offs      = 0x0010,
 937         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 938                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 939         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 940                            SIDLE_SMART_WKUP),
 941         .sysc_fields    = &omap_hwmod_sysc_type2,
 942 };
 943
 944 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 945         .name   = "dmic",
 946         .sysc   = &omap44xx_dmic_sysc,
 947 };
 948
 949 /* dmic */
 950 static struct omap_hwmod omap44xx_dmic_hwmod;
 951 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
 952         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
 953         { .irq = -1 }
 954 };
 955
 956 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
 957         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
 958         { .dma_req = -1 }
 959 };
 960
 961 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
 962         {
 963                 .pa_start       = 0x4012e000,
 964                 .pa_end         = 0x4012e07f,
 965                 .flags          = ADDR_TYPE_RT
 966         },
 967         { }
 968 };
 969
 970 /* l4_abe -> dmic */
 971 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
 972         .master         = &omap44xx_l4_abe_hwmod,
 973         .slave          = &omap44xx_dmic_hwmod,
 974         .clk            = "ocp_abe_iclk",
 975         .addr           = omap44xx_dmic_addrs,
 976         .user           = OCP_USER_MPU,
 977 };
 978
 979 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
 980         {
 981                 .pa_start       = 0x4902e000,
 982                 .pa_end         = 0x4902e07f,
 983                 .flags          = ADDR_TYPE_RT
 984         },
 985         { }
 986 };
 987
 988 /* l4_abe -> dmic (dma) */
 989 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
 990         .master         = &omap44xx_l4_abe_hwmod,
 991         .slave          = &omap44xx_dmic_hwmod,
 992         .clk            = "ocp_abe_iclk",
 993         .addr           = omap44xx_dmic_dma_addrs,
 994         .user           = OCP_USER_SDMA,
 995 };
 996
 997 /* dmic slave ports */
 998 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
 999         &omap44xx_l4_abe__dmic,
1000         &omap44xx_l4_abe__dmic_dma,
1001 };
1002
1003 static struct omap_hwmod omap44xx_dmic_hwmod = {
1004         .name           = "dmic",
1005         .class          = &omap44xx_dmic_hwmod_class,
1006         .mpu_irqs       = omap44xx_dmic_irqs,
1007         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1008         .main_clk       = "dmic_fck",
1009         .prcm = {
1010                 .omap4 = {
1011                         .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1012                 },
1013         },
1014         .slaves         = omap44xx_dmic_slaves,
1015         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1016         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1017 };
1018
1019 /*
1020  * 'dsp' class
1021  * dsp sub-system
1022  */
1023
1024 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1025         .name   = "dsp",
1026 };
1027
1028 /* dsp */
1029 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1030         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1031         { .irq = -1 }
1032 };
1033
1034 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1035         { .name = "mmu_cache", .rst_shift = 1 },
1036 };
1037
1038 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1039         { .name = "dsp", .rst_shift = 0 },
1040 };
1041
1042 /* dsp -> iva */
1043 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1044         .master         = &omap44xx_dsp_hwmod,
1045         .slave          = &omap44xx_iva_hwmod,
1046         .clk            = "dpll_iva_m5x2_ck",
1047 };
1048
1049 /* dsp master ports */
1050 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1051         &omap44xx_dsp__l3_main_1,
1052         &omap44xx_dsp__l4_abe,
1053         &omap44xx_dsp__iva,
1054 };
1055
1056 /* l4_cfg -> dsp */
1057 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1058         .master         = &omap44xx_l4_cfg_hwmod,
1059         .slave          = &omap44xx_dsp_hwmod,
1060         .clk            = "l4_div_ck",
1061         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1062 };
1063
1064 /* dsp slave ports */
1065 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1066         &omap44xx_l4_cfg__dsp,
1067 };
1068
1069 /* Pseudo hwmod for reset control purpose only */
1070 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1071         .name           = "dsp_c0",
1072         .class          = &omap44xx_dsp_hwmod_class,
1073         .flags          = HWMOD_INIT_NO_RESET,
1074         .rst_lines      = omap44xx_dsp_c0_resets,
1075         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1076         .prcm = {
1077                 .omap4 = {
1078                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1079                 },
1080         },
1081         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1082 };
1083
1084 static struct omap_hwmod omap44xx_dsp_hwmod = {
1085         .name           = "dsp",
1086         .class          = &omap44xx_dsp_hwmod_class,
1087         .mpu_irqs       = omap44xx_dsp_irqs,
1088         .rst_lines      = omap44xx_dsp_resets,
1089         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1090         .main_clk       = "dsp_fck",
1091         .prcm = {
1092                 .omap4 = {
1093                         .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1094                         .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
1095                 },
1096         },
1097         .slaves         = omap44xx_dsp_slaves,
1098         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1099         .masters        = omap44xx_dsp_masters,
1100         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1101         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1102 };
1103
1104 /*
1105  * 'dss' class
1106  * display sub-system
1107  */
1108
1109 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1110         .rev_offs       = 0x0000,
1111         .syss_offs      = 0x0014,
1112         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1113 };
1114
1115 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1116         .name   = "dss",
1117         .sysc   = &omap44xx_dss_sysc,
1118 };
1119
1120 /* dss */
1121 /* dss master ports */
1122 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1123         &omap44xx_dss__l3_main_1,
1124 };
1125
1126 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1127         {
1128                 .pa_start       = 0x58000000,
1129                 .pa_end         = 0x5800007f,
1130                 .flags          = ADDR_TYPE_RT
1131         },
1132         { }
1133 };
1134
1135 /* l3_main_2 -> dss */
1136 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1137         .master         = &omap44xx_l3_main_2_hwmod,
1138         .slave          = &omap44xx_dss_hwmod,
1139         .clk            = "l3_div_ck",
1140         .addr           = omap44xx_dss_dma_addrs,
1141         .user           = OCP_USER_SDMA,
1142 };
1143
1144 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1145         {
1146                 .pa_start       = 0x48040000,
1147                 .pa_end         = 0x4804007f,
1148                 .flags          = ADDR_TYPE_RT
1149         },
1150         { }
1151 };
1152
1153 /* l4_per -> dss */
1154 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1155         .master         = &omap44xx_l4_per_hwmod,
1156         .slave          = &omap44xx_dss_hwmod,
1157         .clk            = "l4_div_ck",
1158         .addr           = omap44xx_dss_addrs,
1159         .user           = OCP_USER_MPU,
1160 };
1161
1162 /* dss slave ports */
1163 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1164         &omap44xx_l3_main_2__dss,
1165         &omap44xx_l4_per__dss,
1166 };
1167
1168 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1169         { .role = "sys_clk", .clk = "dss_sys_clk" },
1170         { .role = "tv_clk", .clk = "dss_tv_clk" },
1171         { .role = "dss_clk", .clk = "dss_dss_clk" },
1172         { .role = "video_clk", .clk = "dss_48mhz_clk" },
1173 };
1174
1175 static struct omap_hwmod omap44xx_dss_hwmod = {
1176         .name           = "dss_core",
1177         .class          = &omap44xx_dss_hwmod_class,
1178         .main_clk       = "dss_fck",
1179         .prcm = {
1180                 .omap4 = {
1181                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1182                 },
1183         },
1184         .opt_clks       = dss_opt_clks,
1185         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1186         .slaves         = omap44xx_dss_slaves,
1187         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1188         .masters        = omap44xx_dss_masters,
1189         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1190         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1191 };
1192
1193 /*
1194  * 'dispc' class
1195  * display controller
1196  */
1197
1198 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1199         .rev_offs       = 0x0000,
1200         .sysc_offs      = 0x0010,
1201         .syss_offs      = 0x0014,
1202         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1203                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1204                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1205                            SYSS_HAS_RESET_STATUS),
1206         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1208         .sysc_fields    = &omap_hwmod_sysc_type1,
1209 };
1210
1211 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1212         .name   = "dispc",
1213         .sysc   = &omap44xx_dispc_sysc,
1214 };
1215
1216 /* dss_dispc */
1217 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1218 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1219         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1220         { .irq = -1 }
1221 };
1222
1223 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1224         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1225         { .dma_req = -1 }
1226 };
1227
1228 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1229         {
1230                 .pa_start       = 0x58001000,
1231                 .pa_end         = 0x58001fff,
1232                 .flags          = ADDR_TYPE_RT
1233         },
1234         { }
1235 };
1236
1237 /* l3_main_2 -> dss_dispc */
1238 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1239         .master         = &omap44xx_l3_main_2_hwmod,
1240         .slave          = &omap44xx_dss_dispc_hwmod,
1241         .clk            = "l3_div_ck",
1242         .addr           = omap44xx_dss_dispc_dma_addrs,
1243         .user           = OCP_USER_SDMA,
1244 };
1245
1246 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1247         {
1248                 .pa_start       = 0x48041000,
1249                 .pa_end         = 0x48041fff,
1250                 .flags          = ADDR_TYPE_RT
1251         },
1252         { }
1253 };
1254
1255 /* l4_per -> dss_dispc */
1256 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1257         .master         = &omap44xx_l4_per_hwmod,
1258         .slave          = &omap44xx_dss_dispc_hwmod,
1259         .clk            = "l4_div_ck",
1260         .addr           = omap44xx_dss_dispc_addrs,
1261         .user           = OCP_USER_MPU,
1262 };
1263
1264 /* dss_dispc slave ports */
1265 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1266         &omap44xx_l3_main_2__dss_dispc,
1267         &omap44xx_l4_per__dss_dispc,
1268 };
1269
1270 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1271         .name           = "dss_dispc",
1272         .class          = &omap44xx_dispc_hwmod_class,
1273         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1274         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1275         .main_clk       = "dss_fck",
1276         .prcm = {
1277                 .omap4 = {
1278                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1279                 },
1280         },
1281         .slaves         = omap44xx_dss_dispc_slaves,
1282         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1283         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1284 };
1285
1286 /*
1287  * 'dsi' class
1288  * display serial interface controller
1289  */
1290
1291 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1292         .rev_offs       = 0x0000,
1293         .sysc_offs      = 0x0010,
1294         .syss_offs      = 0x0014,
1295         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1296                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1297                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1298         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1299         .sysc_fields    = &omap_hwmod_sysc_type1,
1300 };
1301
1302 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1303         .name   = "dsi",
1304         .sysc   = &omap44xx_dsi_sysc,
1305 };
1306
1307 /* dss_dsi1 */
1308 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1309 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1310         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1311         { .irq = -1 }
1312 };
1313
1314 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1315         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1316         { .dma_req = -1 }
1317 };
1318
1319 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1320         {
1321                 .pa_start       = 0x58004000,
1322                 .pa_end         = 0x580041ff,
1323                 .flags          = ADDR_TYPE_RT
1324         },
1325         { }
1326 };
1327
1328 /* l3_main_2 -> dss_dsi1 */
1329 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1330         .master         = &omap44xx_l3_main_2_hwmod,
1331         .slave          = &omap44xx_dss_dsi1_hwmod,
1332         .clk            = "l3_div_ck",
1333         .addr           = omap44xx_dss_dsi1_dma_addrs,
1334         .user           = OCP_USER_SDMA,
1335 };
1336
1337 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1338         {
1339                 .pa_start       = 0x48044000,
1340                 .pa_end         = 0x480441ff,
1341                 .flags          = ADDR_TYPE_RT
1342         },
1343         { }
1344 };
1345
1346 /* l4_per -> dss_dsi1 */
1347 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1348         .master         = &omap44xx_l4_per_hwmod,
1349         .slave          = &omap44xx_dss_dsi1_hwmod,
1350         .clk            = "l4_div_ck",
1351         .addr           = omap44xx_dss_dsi1_addrs,
1352         .user           = OCP_USER_MPU,
1353 };
1354
1355 /* dss_dsi1 slave ports */
1356 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1357         &omap44xx_l3_main_2__dss_dsi1,
1358         &omap44xx_l4_per__dss_dsi1,
1359 };
1360
1361 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1362         .name           = "dss_dsi1",
1363         .class          = &omap44xx_dsi_hwmod_class,
1364         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1365         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1366         .main_clk       = "dss_fck",
1367         .prcm = {
1368                 .omap4 = {
1369                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1370                 },
1371         },
1372         .slaves         = omap44xx_dss_dsi1_slaves,
1373         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1374         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1375 };
1376
1377 /* dss_dsi2 */
1378 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1379 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1380         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1381         { .irq = -1 }
1382 };
1383
1384 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1385         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1386         { .dma_req = -1 }
1387 };
1388
1389 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1390         {
1391                 .pa_start       = 0x58005000,
1392                 .pa_end         = 0x580051ff,
1393                 .flags          = ADDR_TYPE_RT
1394         },
1395         { }
1396 };
1397
1398 /* l3_main_2 -> dss_dsi2 */
1399 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1400         .master         = &omap44xx_l3_main_2_hwmod,
1401         .slave          = &omap44xx_dss_dsi2_hwmod,
1402         .clk            = "l3_div_ck",
1403         .addr           = omap44xx_dss_dsi2_dma_addrs,
1404         .user           = OCP_USER_SDMA,
1405 };
1406
1407 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1408         {
1409                 .pa_start       = 0x48045000,
1410                 .pa_end         = 0x480451ff,
1411                 .flags          = ADDR_TYPE_RT
1412         },
1413         { }
1414 };
1415
1416 /* l4_per -> dss_dsi2 */
1417 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1418         .master         = &omap44xx_l4_per_hwmod,
1419         .slave          = &omap44xx_dss_dsi2_hwmod,
1420         .clk            = "l4_div_ck",
1421         .addr           = omap44xx_dss_dsi2_addrs,
1422         .user           = OCP_USER_MPU,
1423 };
1424
1425 /* dss_dsi2 slave ports */
1426 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1427         &omap44xx_l3_main_2__dss_dsi2,
1428         &omap44xx_l4_per__dss_dsi2,
1429 };
1430
1431 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1432         .name           = "dss_dsi2",
1433         .class          = &omap44xx_dsi_hwmod_class,
1434         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1435         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1436         .main_clk       = "dss_fck",
1437         .prcm = {
1438                 .omap4 = {
1439                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1440                 },
1441         },
1442         .slaves         = omap44xx_dss_dsi2_slaves,
1443         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1444         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1445 };
1446
1447 /*
1448  * 'hdmi' class
1449  * hdmi controller
1450  */
1451
1452 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1453         .rev_offs       = 0x0000,
1454         .sysc_offs      = 0x0010,
1455         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1456                            SYSC_HAS_SOFTRESET),
1457         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1458                            SIDLE_SMART_WKUP),
1459         .sysc_fields    = &omap_hwmod_sysc_type2,
1460 };
1461
1462 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1463         .name   = "hdmi",
1464         .sysc   = &omap44xx_hdmi_sysc,
1465 };
1466
1467 /* dss_hdmi */
1468 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1469 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1470         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1471         { .irq = -1 }
1472 };
1473
1474 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1475         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1476         { .dma_req = -1 }
1477 };
1478
1479 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1480         {
1481                 .pa_start       = 0x58006000,
1482                 .pa_end         = 0x58006fff,
1483                 .flags          = ADDR_TYPE_RT
1484         },
1485         { }
1486 };
1487
1488 /* l3_main_2 -> dss_hdmi */
1489 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1490         .master         = &omap44xx_l3_main_2_hwmod,
1491         .slave          = &omap44xx_dss_hdmi_hwmod,
1492         .clk            = "l3_div_ck",
1493         .addr           = omap44xx_dss_hdmi_dma_addrs,
1494         .user           = OCP_USER_SDMA,
1495 };
1496
1497 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1498         {
1499                 .pa_start       = 0x48046000,
1500                 .pa_end         = 0x48046fff,
1501                 .flags          = ADDR_TYPE_RT
1502         },
1503         { }
1504 };
1505
1506 /* l4_per -> dss_hdmi */
1507 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1508         .master         = &omap44xx_l4_per_hwmod,
1509         .slave          = &omap44xx_dss_hdmi_hwmod,
1510         .clk            = "l4_div_ck",
1511         .addr           = omap44xx_dss_hdmi_addrs,
1512         .user           = OCP_USER_MPU,
1513 };
1514
1515 /* dss_hdmi slave ports */
1516 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1517         &omap44xx_l3_main_2__dss_hdmi,
1518         &omap44xx_l4_per__dss_hdmi,
1519 };
1520
1521 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1522         .name           = "dss_hdmi",
1523         .class          = &omap44xx_hdmi_hwmod_class,
1524         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1525         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1526         .main_clk       = "dss_fck",
1527         .prcm = {
1528                 .omap4 = {
1529                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1530                 },
1531         },
1532         .slaves         = omap44xx_dss_hdmi_slaves,
1533         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1534         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1535 };
1536
1537 /*
1538  * 'rfbi' class
1539  * remote frame buffer interface
1540  */
1541
1542 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1543         .rev_offs       = 0x0000,
1544         .sysc_offs      = 0x0010,
1545         .syss_offs      = 0x0014,
1546         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1547                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1548         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1549         .sysc_fields    = &omap_hwmod_sysc_type1,
1550 };
1551
1552 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1553         .name   = "rfbi",
1554         .sysc   = &omap44xx_rfbi_sysc,
1555 };
1556
1557 /* dss_rfbi */
1558 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1559 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1560         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1561         { .dma_req = -1 }
1562 };
1563
1564 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1565         {
1566                 .pa_start       = 0x58002000,
1567                 .pa_end         = 0x580020ff,
1568                 .flags          = ADDR_TYPE_RT
1569         },
1570         { }
1571 };
1572
1573 /* l3_main_2 -> dss_rfbi */
1574 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1575         .master         = &omap44xx_l3_main_2_hwmod,
1576         .slave          = &omap44xx_dss_rfbi_hwmod,
1577         .clk            = "l3_div_ck",
1578         .addr           = omap44xx_dss_rfbi_dma_addrs,
1579         .user           = OCP_USER_SDMA,
1580 };
1581
1582 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1583         {
1584                 .pa_start       = 0x48042000,
1585                 .pa_end         = 0x480420ff,
1586                 .flags          = ADDR_TYPE_RT
1587         },
1588         { }
1589 };
1590
1591 /* l4_per -> dss_rfbi */
1592 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1593         .master         = &omap44xx_l4_per_hwmod,
1594         .slave          = &omap44xx_dss_rfbi_hwmod,
1595         .clk            = "l4_div_ck",
1596         .addr           = omap44xx_dss_rfbi_addrs,
1597         .user           = OCP_USER_MPU,
1598 };
1599
1600 /* dss_rfbi slave ports */
1601 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1602         &omap44xx_l3_main_2__dss_rfbi,
1603         &omap44xx_l4_per__dss_rfbi,
1604 };
1605
1606 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1607         .name           = "dss_rfbi",
1608         .class          = &omap44xx_rfbi_hwmod_class,
1609         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1610         .main_clk       = "dss_fck",
1611         .prcm = {
1612                 .omap4 = {
1613                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1614                 },
1615         },
1616         .slaves         = omap44xx_dss_rfbi_slaves,
1617         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1618         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1619 };
1620
1621 /*
1622  * 'venc' class
1623  * video encoder
1624  */
1625
1626 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1627         .name   = "venc",
1628 };
1629
1630 /* dss_venc */
1631 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1632 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1633         {
1634                 .pa_start       = 0x58003000,
1635                 .pa_end         = 0x580030ff,
1636                 .flags          = ADDR_TYPE_RT
1637         },
1638         { }
1639 };
1640
1641 /* l3_main_2 -> dss_venc */
1642 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1643         .master         = &omap44xx_l3_main_2_hwmod,
1644         .slave          = &omap44xx_dss_venc_hwmod,
1645         .clk            = "l3_div_ck",
1646         .addr           = omap44xx_dss_venc_dma_addrs,
1647         .user           = OCP_USER_SDMA,
1648 };
1649
1650 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1651         {
1652                 .pa_start       = 0x48043000,
1653                 .pa_end         = 0x480430ff,
1654                 .flags          = ADDR_TYPE_RT
1655         },
1656         { }
1657 };
1658
1659 /* l4_per -> dss_venc */
1660 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1661         .master         = &omap44xx_l4_per_hwmod,
1662         .slave          = &omap44xx_dss_venc_hwmod,
1663         .clk            = "l4_div_ck",
1664         .addr           = omap44xx_dss_venc_addrs,
1665         .user           = OCP_USER_MPU,
1666 };
1667
1668 /* dss_venc slave ports */
1669 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1670         &omap44xx_l3_main_2__dss_venc,
1671         &omap44xx_l4_per__dss_venc,
1672 };
1673
1674 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1675         .name           = "dss_venc",
1676         .class          = &omap44xx_venc_hwmod_class,
1677         .main_clk       = "dss_fck",
1678         .prcm = {
1679                 .omap4 = {
1680                         .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1681                 },
1682         },
1683         .slaves         = omap44xx_dss_venc_slaves,
1684         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1685         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1686 };
1687
1688 /*
1689  * 'gpio' class
1690  * general purpose io module
1691  */
1692
1693 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1694         .rev_offs       = 0x0000,
1695         .sysc_offs      = 0x0010,
1696         .syss_offs      = 0x0114,
1697         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1698                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1699                            SYSS_HAS_RESET_STATUS),
1700         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1701                            SIDLE_SMART_WKUP),
1702         .sysc_fields    = &omap_hwmod_sysc_type1,
1703 };
1704
1705 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1706         .name   = "gpio",
1707         .sysc   = &omap44xx_gpio_sysc,
1708         .rev    = 2,
1709 };
1710
1711 /* gpio dev_attr */
1712 static struct omap_gpio_dev_attr gpio_dev_attr = {
1713         .bank_width     = 32,
1714         .dbck_flag      = true,
1715 };
1716
1717 /* gpio1 */
1718 static struct omap_hwmod omap44xx_gpio1_hwmod;
1719 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1720         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1721         { .irq = -1 }
1722 };
1723
1724 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1725         {
1726                 .pa_start       = 0x4a310000,
1727                 .pa_end         = 0x4a3101ff,
1728                 .flags          = ADDR_TYPE_RT
1729         },
1730         { }
1731 };
1732
1733 /* l4_wkup -> gpio1 */
1734 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1735         .master         = &omap44xx_l4_wkup_hwmod,
1736         .slave          = &omap44xx_gpio1_hwmod,
1737         .clk            = "l4_wkup_clk_mux_ck",
1738         .addr           = omap44xx_gpio1_addrs,
1739         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1740 };
1741
1742 /* gpio1 slave ports */
1743 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1744         &omap44xx_l4_wkup__gpio1,
1745 };
1746
1747 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1748         { .role = "dbclk", .clk = "gpio1_dbclk" },
1749 };
1750
1751 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1752         .name           = "gpio1",
1753         .class          = &omap44xx_gpio_hwmod_class,
1754         .mpu_irqs       = omap44xx_gpio1_irqs,
1755         .main_clk       = "gpio1_ick",
1756         .prcm = {
1757                 .omap4 = {
1758                         .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1759                 },
1760         },
1761         .opt_clks       = gpio1_opt_clks,
1762         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1763         .dev_attr       = &gpio_dev_attr,
1764         .slaves         = omap44xx_gpio1_slaves,
1765         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1766         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1767 };
1768
1769 /* gpio2 */
1770 static struct omap_hwmod omap44xx_gpio2_hwmod;
1771 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1772         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1773         { .irq = -1 }
1774 };
1775
1776 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1777         {
1778                 .pa_start       = 0x48055000,
1779                 .pa_end         = 0x480551ff,
1780                 .flags          = ADDR_TYPE_RT
1781         },
1782         { }
1783 };
1784
1785 /* l4_per -> gpio2 */
1786 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1787         .master         = &omap44xx_l4_per_hwmod,
1788         .slave          = &omap44xx_gpio2_hwmod,
1789         .clk            = "l4_div_ck",
1790         .addr           = omap44xx_gpio2_addrs,
1791         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1792 };
1793
1794 /* gpio2 slave ports */
1795 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1796         &omap44xx_l4_per__gpio2,
1797 };
1798
1799 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1800         { .role = "dbclk", .clk = "gpio2_dbclk" },
1801 };
1802
1803 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1804         .name           = "gpio2",
1805         .class          = &omap44xx_gpio_hwmod_class,
1806         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1807         .mpu_irqs       = omap44xx_gpio2_irqs,
1808         .main_clk       = "gpio2_ick",
1809         .prcm = {
1810                 .omap4 = {
1811                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1812                 },
1813         },
1814         .opt_clks       = gpio2_opt_clks,
1815         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1816         .dev_attr       = &gpio_dev_attr,
1817         .slaves         = omap44xx_gpio2_slaves,
1818         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1819         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1820 };
1821
1822 /* gpio3 */
1823 static struct omap_hwmod omap44xx_gpio3_hwmod;
1824 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1825         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1826         { .irq = -1 }
1827 };
1828
1829 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1830         {
1831                 .pa_start       = 0x48057000,
1832                 .pa_end         = 0x480571ff,
1833                 .flags          = ADDR_TYPE_RT
1834         },
1835         { }
1836 };
1837
1838 /* l4_per -> gpio3 */
1839 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1840         .master         = &omap44xx_l4_per_hwmod,
1841         .slave          = &omap44xx_gpio3_hwmod,
1842         .clk            = "l4_div_ck",
1843         .addr           = omap44xx_gpio3_addrs,
1844         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1845 };
1846
1847 /* gpio3 slave ports */
1848 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1849         &omap44xx_l4_per__gpio3,
1850 };
1851
1852 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1853         { .role = "dbclk", .clk = "gpio3_dbclk" },
1854 };
1855
1856 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1857         .name           = "gpio3",
1858         .class          = &omap44xx_gpio_hwmod_class,
1859         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1860         .mpu_irqs       = omap44xx_gpio3_irqs,
1861         .main_clk       = "gpio3_ick",
1862         .prcm = {
1863                 .omap4 = {
1864                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1865                 },
1866         },
1867         .opt_clks       = gpio3_opt_clks,
1868         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1869         .dev_attr       = &gpio_dev_attr,
1870         .slaves         = omap44xx_gpio3_slaves,
1871         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1872         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1873 };
1874
1875 /* gpio4 */
1876 static struct omap_hwmod omap44xx_gpio4_hwmod;
1877 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1878         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1879         { .irq = -1 }
1880 };
1881
1882 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1883         {
1884                 .pa_start       = 0x48059000,
1885                 .pa_end         = 0x480591ff,
1886                 .flags          = ADDR_TYPE_RT
1887         },
1888         { }
1889 };
1890
1891 /* l4_per -> gpio4 */
1892 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1893         .master         = &omap44xx_l4_per_hwmod,
1894         .slave          = &omap44xx_gpio4_hwmod,
1895         .clk            = "l4_div_ck",
1896         .addr           = omap44xx_gpio4_addrs,
1897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1898 };
1899
1900 /* gpio4 slave ports */
1901 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
1902         &omap44xx_l4_per__gpio4,
1903 };
1904
1905 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1906         { .role = "dbclk", .clk = "gpio4_dbclk" },
1907 };
1908
1909 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1910         .name           = "gpio4",
1911         .class          = &omap44xx_gpio_hwmod_class,
1912         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1913         .mpu_irqs       = omap44xx_gpio4_irqs,
1914         .main_clk       = "gpio4_ick",
1915         .prcm = {
1916                 .omap4 = {
1917                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1918                 },
1919         },
1920         .opt_clks       = gpio4_opt_clks,
1921         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
1922         .dev_attr       = &gpio_dev_attr,
1923         .slaves         = omap44xx_gpio4_slaves,
1924         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
1925         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1926 };
1927
1928 /* gpio5 */
1929 static struct omap_hwmod omap44xx_gpio5_hwmod;
1930 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
1931         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
1932         { .irq = -1 }
1933 };
1934
1935 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
1936         {
1937                 .pa_start       = 0x4805b000,
1938                 .pa_end         = 0x4805b1ff,
1939                 .flags          = ADDR_TYPE_RT
1940         },
1941         { }
1942 };
1943
1944 /* l4_per -> gpio5 */
1945 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
1946         .master         = &omap44xx_l4_per_hwmod,
1947         .slave          = &omap44xx_gpio5_hwmod,
1948         .clk            = "l4_div_ck",
1949         .addr           = omap44xx_gpio5_addrs,
1950         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1951 };
1952
1953 /* gpio5 slave ports */
1954 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
1955         &omap44xx_l4_per__gpio5,
1956 };
1957
1958 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1959         { .role = "dbclk", .clk = "gpio5_dbclk" },
1960 };
1961
1962 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1963         .name           = "gpio5",
1964         .class          = &omap44xx_gpio_hwmod_class,
1965         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1966         .mpu_irqs       = omap44xx_gpio5_irqs,
1967         .main_clk       = "gpio5_ick",
1968         .prcm = {
1969                 .omap4 = {
1970                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1971                 },
1972         },
1973         .opt_clks       = gpio5_opt_clks,
1974         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
1975         .dev_attr       = &gpio_dev_attr,
1976         .slaves         = omap44xx_gpio5_slaves,
1977         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
1978         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
1979 };
1980
1981 /* gpio6 */
1982 static struct omap_hwmod omap44xx_gpio6_hwmod;
1983 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
1984         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
1985         { .irq = -1 }
1986 };
1987
1988 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
1989         {
1990                 .pa_start       = 0x4805d000,
1991                 .pa_end         = 0x4805d1ff,
1992                 .flags          = ADDR_TYPE_RT
1993         },
1994         { }
1995 };
1996
1997 /* l4_per -> gpio6 */
1998 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
1999         .master         = &omap44xx_l4_per_hwmod,
2000         .slave          = &omap44xx_gpio6_hwmod,
2001         .clk            = "l4_div_ck",
2002         .addr           = omap44xx_gpio6_addrs,
2003         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2004 };
2005
2006 /* gpio6 slave ports */
2007 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2008         &omap44xx_l4_per__gpio6,
2009 };
2010
2011 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2012         { .role = "dbclk", .clk = "gpio6_dbclk" },
2013 };
2014
2015 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2016         .name           = "gpio6",
2017         .class          = &omap44xx_gpio_hwmod_class,
2018         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2019         .mpu_irqs       = omap44xx_gpio6_irqs,
2020         .main_clk       = "gpio6_ick",
2021         .prcm = {
2022                 .omap4 = {
2023                         .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
2024                 },
2025         },
2026         .opt_clks       = gpio6_opt_clks,
2027         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2028         .dev_attr       = &gpio_dev_attr,
2029         .slaves         = omap44xx_gpio6_slaves,
2030         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2031         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2032 };
2033
2034 /*
2035  * 'hsi' class
2036  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2037  * serial if)
2038  */
2039
2040 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2041         .rev_offs       = 0x0000,
2042         .sysc_offs      = 0x0010,
2043         .syss_offs      = 0x0014,
2044         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2045                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2046                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2047         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2048                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2049                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2050         .sysc_fields    = &omap_hwmod_sysc_type1,
2051 };
2052
2053 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2054         .name   = "hsi",
2055         .sysc   = &omap44xx_hsi_sysc,
2056 };
2057
2058 /* hsi */
2059 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2060         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2061         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2062         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2063         { .irq = -1 }
2064 };
2065
2066 /* hsi master ports */
2067 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2068         &omap44xx_hsi__l3_main_2,
2069 };
2070
2071 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2072         {
2073                 .pa_start       = 0x4a058000,
2074                 .pa_end         = 0x4a05bfff,
2075                 .flags          = ADDR_TYPE_RT
2076         },
2077         { }
2078 };
2079
2080 /* l4_cfg -> hsi */
2081 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2082         .master         = &omap44xx_l4_cfg_hwmod,
2083         .slave          = &omap44xx_hsi_hwmod,
2084         .clk            = "l4_div_ck",
2085         .addr           = omap44xx_hsi_addrs,
2086         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2087 };
2088
2089 /* hsi slave ports */
2090 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2091         &omap44xx_l4_cfg__hsi,
2092 };
2093
2094 static struct omap_hwmod omap44xx_hsi_hwmod = {
2095         .name           = "hsi",
2096         .class          = &omap44xx_hsi_hwmod_class,
2097         .mpu_irqs       = omap44xx_hsi_irqs,
2098         .main_clk       = "hsi_fck",
2099         .prcm = {
2100                 .omap4 = {
2101                         .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
2102                 },
2103         },
2104         .slaves         = omap44xx_hsi_slaves,
2105         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2106         .masters        = omap44xx_hsi_masters,
2107         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2108         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2109 };
2110
2111 /*
2112  * 'i2c' class
2113  * multimaster high-speed i2c controller
2114  */
2115
2116 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2117         .sysc_offs      = 0x0010,
2118         .syss_offs      = 0x0090,
2119         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2120                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2121                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2122         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2123                            SIDLE_SMART_WKUP),
2124         .sysc_fields    = &omap_hwmod_sysc_type1,
2125 };
2126
2127 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2128         .name   = "i2c",
2129         .sysc   = &omap44xx_i2c_sysc,
2130 };
2131
2132 /* i2c1 */
2133 static struct omap_hwmod omap44xx_i2c1_hwmod;
2134 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2135         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2136         { .irq = -1 }
2137 };
2138
2139 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2140         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2141         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2142         { .dma_req = -1 }
2143 };
2144
2145 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2146         {
2147                 .pa_start       = 0x48070000,
2148                 .pa_end         = 0x480700ff,
2149                 .flags          = ADDR_TYPE_RT
2150         },
2151         { }
2152 };
2153
2154 /* l4_per -> i2c1 */
2155 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2156         .master         = &omap44xx_l4_per_hwmod,
2157         .slave          = &omap44xx_i2c1_hwmod,
2158         .clk            = "l4_div_ck",
2159         .addr           = omap44xx_i2c1_addrs,
2160         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2161 };
2162
2163 /* i2c1 slave ports */
2164 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2165         &omap44xx_l4_per__i2c1,
2166 };
2167
2168 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2169         .name           = "i2c1",
2170         .class          = &omap44xx_i2c_hwmod_class,
2171         .flags          = HWMOD_INIT_NO_RESET,
2172         .mpu_irqs       = omap44xx_i2c1_irqs,
2173         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2174         .main_clk       = "i2c1_fck",
2175         .prcm = {
2176                 .omap4 = {
2177                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
2178                 },
2179         },
2180         .slaves         = omap44xx_i2c1_slaves,
2181         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2182         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2183 };
2184
2185 /* i2c2 */
2186 static struct omap_hwmod omap44xx_i2c2_hwmod;
2187 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2188         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2189         { .irq = -1 }
2190 };
2191
2192 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2193         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2194         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2195         { .dma_req = -1 }
2196 };
2197
2198 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2199         {
2200                 .pa_start       = 0x48072000,
2201                 .pa_end         = 0x480720ff,
2202                 .flags          = ADDR_TYPE_RT
2203         },
2204         { }
2205 };
2206
2207 /* l4_per -> i2c2 */
2208 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2209         .master         = &omap44xx_l4_per_hwmod,
2210         .slave          = &omap44xx_i2c2_hwmod,
2211         .clk            = "l4_div_ck",
2212         .addr           = omap44xx_i2c2_addrs,
2213         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2214 };
2215
2216 /* i2c2 slave ports */
2217 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2218         &omap44xx_l4_per__i2c2,
2219 };
2220
2221 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2222         .name           = "i2c2",
2223         .class          = &omap44xx_i2c_hwmod_class,
2224         .flags          = HWMOD_INIT_NO_RESET,
2225         .mpu_irqs       = omap44xx_i2c2_irqs,
2226         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2227         .main_clk       = "i2c2_fck",
2228         .prcm = {
2229                 .omap4 = {
2230                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
2231                 },
2232         },
2233         .slaves         = omap44xx_i2c2_slaves,
2234         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2235         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2236 };
2237
2238 /* i2c3 */
2239 static struct omap_hwmod omap44xx_i2c3_hwmod;
2240 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2241         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2242         { .irq = -1 }
2243 };
2244
2245 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2246         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2247         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2248         { .dma_req = -1 }
2249 };
2250
2251 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2252         {
2253                 .pa_start       = 0x48060000,
2254                 .pa_end         = 0x480600ff,
2255                 .flags          = ADDR_TYPE_RT
2256         },
2257         { }
2258 };
2259
2260 /* l4_per -> i2c3 */
2261 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2262         .master         = &omap44xx_l4_per_hwmod,
2263         .slave          = &omap44xx_i2c3_hwmod,
2264         .clk            = "l4_div_ck",
2265         .addr           = omap44xx_i2c3_addrs,
2266         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2267 };
2268
2269 /* i2c3 slave ports */
2270 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2271         &omap44xx_l4_per__i2c3,
2272 };
2273
2274 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2275         .name           = "i2c3",
2276         .class          = &omap44xx_i2c_hwmod_class,
2277         .flags          = HWMOD_INIT_NO_RESET,
2278         .mpu_irqs       = omap44xx_i2c3_irqs,
2279         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2280         .main_clk       = "i2c3_fck",
2281         .prcm = {
2282                 .omap4 = {
2283                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
2284                 },
2285         },
2286         .slaves         = omap44xx_i2c3_slaves,
2287         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2288         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2289 };
2290
2291 /* i2c4 */
2292 static struct omap_hwmod omap44xx_i2c4_hwmod;
2293 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2294         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2295         { .irq = -1 }
2296 };
2297
2298 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2299         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2300         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2301         { .dma_req = -1 }
2302 };
2303
2304 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2305         {
2306                 .pa_start       = 0x48350000,
2307                 .pa_end         = 0x483500ff,
2308                 .flags          = ADDR_TYPE_RT
2309         },
2310         { }
2311 };
2312
2313 /* l4_per -> i2c4 */
2314 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2315         .master         = &omap44xx_l4_per_hwmod,
2316         .slave          = &omap44xx_i2c4_hwmod,
2317         .clk            = "l4_div_ck",
2318         .addr           = omap44xx_i2c4_addrs,
2319         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2320 };
2321
2322 /* i2c4 slave ports */
2323 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2324         &omap44xx_l4_per__i2c4,
2325 };
2326
2327 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2328         .name           = "i2c4",
2329         .class          = &omap44xx_i2c_hwmod_class,
2330         .flags          = HWMOD_INIT_NO_RESET,
2331         .mpu_irqs       = omap44xx_i2c4_irqs,
2332         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2333         .main_clk       = "i2c4_fck",
2334         .prcm = {
2335                 .omap4 = {
2336                         .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
2337                 },
2338         },
2339         .slaves         = omap44xx_i2c4_slaves,
2340         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2341         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2342 };
2343
2344 /*
2345  * 'ipu' class
2346  * imaging processor unit
2347  */
2348
2349 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2350         .name   = "ipu",
2351 };
2352
2353 /* ipu */
2354 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2355         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2356         { .irq = -1 }
2357 };
2358
2359 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2360         { .name = "cpu0", .rst_shift = 0 },
2361 };
2362
2363 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2364         { .name = "cpu1", .rst_shift = 1 },
2365 };
2366
2367 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2368         { .name = "mmu_cache", .rst_shift = 2 },
2369 };
2370
2371 /* ipu master ports */
2372 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2373         &omap44xx_ipu__l3_main_2,
2374 };
2375
2376 /* l3_main_2 -> ipu */
2377 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2378         .master         = &omap44xx_l3_main_2_hwmod,
2379         .slave          = &omap44xx_ipu_hwmod,
2380         .clk            = "l3_div_ck",
2381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2382 };
2383
2384 /* ipu slave ports */
2385 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2386         &omap44xx_l3_main_2__ipu,
2387 };
2388
2389 /* Pseudo hwmod for reset control purpose only */
2390 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2391         .name           = "ipu_c0",
2392         .class          = &omap44xx_ipu_hwmod_class,
2393         .flags          = HWMOD_INIT_NO_RESET,
2394         .rst_lines      = omap44xx_ipu_c0_resets,
2395         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2396         .prcm = {
2397                 .omap4 = {
2398                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2399                 },
2400         },
2401         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2402 };
2403
2404 /* Pseudo hwmod for reset control purpose only */
2405 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2406         .name           = "ipu_c1",
2407         .class          = &omap44xx_ipu_hwmod_class,
2408         .flags          = HWMOD_INIT_NO_RESET,
2409         .rst_lines      = omap44xx_ipu_c1_resets,
2410         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2411         .prcm = {
2412                 .omap4 = {
2413                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2414                 },
2415         },
2416         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2417 };
2418
2419 static struct omap_hwmod omap44xx_ipu_hwmod = {
2420         .name           = "ipu",
2421         .class          = &omap44xx_ipu_hwmod_class,
2422         .mpu_irqs       = omap44xx_ipu_irqs,
2423         .rst_lines      = omap44xx_ipu_resets,
2424         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2425         .main_clk       = "ipu_fck",
2426         .prcm = {
2427                 .omap4 = {
2428                         .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
2429                         .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
2430                 },
2431         },
2432         .slaves         = omap44xx_ipu_slaves,
2433         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2434         .masters        = omap44xx_ipu_masters,
2435         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2436         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2437 };
2438
2439 /*
2440  * 'iss' class
2441  * external images sensor pixel data processor
2442  */
2443
2444 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2445         .rev_offs       = 0x0000,
2446         .sysc_offs      = 0x0010,
2447         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2448                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2449         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2450                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2451                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2452         .sysc_fields    = &omap_hwmod_sysc_type2,
2453 };
2454
2455 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2456         .name   = "iss",
2457         .sysc   = &omap44xx_iss_sysc,
2458 };
2459
2460 /* iss */
2461 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2462         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2463         { .irq = -1 }
2464 };
2465
2466 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2467         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2468         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2469         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2470         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2471         { .dma_req = -1 }
2472 };
2473
2474 /* iss master ports */
2475 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2476         &omap44xx_iss__l3_main_2,
2477 };
2478
2479 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2480         {
2481                 .pa_start       = 0x52000000,
2482                 .pa_end         = 0x520000ff,
2483                 .flags          = ADDR_TYPE_RT
2484         },
2485         { }
2486 };
2487
2488 /* l3_main_2 -> iss */
2489 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2490         .master         = &omap44xx_l3_main_2_hwmod,
2491         .slave          = &omap44xx_iss_hwmod,
2492         .clk            = "l3_div_ck",
2493         .addr           = omap44xx_iss_addrs,
2494         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2495 };
2496
2497 /* iss slave ports */
2498 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2499         &omap44xx_l3_main_2__iss,
2500 };
2501
2502 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2503         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2504 };
2505
2506 static struct omap_hwmod omap44xx_iss_hwmod = {
2507         .name           = "iss",
2508         .class          = &omap44xx_iss_hwmod_class,
2509         .mpu_irqs       = omap44xx_iss_irqs,
2510         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2511         .main_clk       = "iss_fck",
2512         .prcm = {
2513                 .omap4 = {
2514                         .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
2515                 },
2516         },
2517         .opt_clks       = iss_opt_clks,
2518         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2519         .slaves         = omap44xx_iss_slaves,
2520         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2521         .masters        = omap44xx_iss_masters,
2522         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2523         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2524 };
2525
2526 /*
2527  * 'iva' class
2528  * multi-standard video encoder/decoder hardware accelerator
2529  */
2530
2531 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2532         .name   = "iva",
2533 };
2534
2535 /* iva */
2536 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2537         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2538         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2539         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2540         { .irq = -1 }
2541 };
2542
2543 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2544         { .name = "logic", .rst_shift = 2 },
2545 };
2546
2547 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2548         { .name = "seq0", .rst_shift = 0 },
2549 };
2550
2551 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2552         { .name = "seq1", .rst_shift = 1 },
2553 };
2554
2555 /* iva master ports */
2556 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2557         &omap44xx_iva__l3_main_2,
2558         &omap44xx_iva__l3_instr,
2559 };
2560
2561 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2562         {
2563                 .pa_start       = 0x5a000000,
2564                 .pa_end         = 0x5a07ffff,
2565                 .flags          = ADDR_TYPE_RT
2566         },
2567         { }
2568 };
2569
2570 /* l3_main_2 -> iva */
2571 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2572         .master         = &omap44xx_l3_main_2_hwmod,
2573         .slave          = &omap44xx_iva_hwmod,
2574         .clk            = "l3_div_ck",
2575         .addr           = omap44xx_iva_addrs,
2576         .user           = OCP_USER_MPU,
2577 };
2578
2579 /* iva slave ports */
2580 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2581         &omap44xx_dsp__iva,
2582         &omap44xx_l3_main_2__iva,
2583 };
2584
2585 /* Pseudo hwmod for reset control purpose only */
2586 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2587         .name           = "iva_seq0",
2588         .class          = &omap44xx_iva_hwmod_class,
2589         .flags          = HWMOD_INIT_NO_RESET,
2590         .rst_lines      = omap44xx_iva_seq0_resets,
2591         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2592         .prcm = {
2593                 .omap4 = {
2594                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2595                 },
2596         },
2597         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2598 };
2599
2600 /* Pseudo hwmod for reset control purpose only */
2601 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2602         .name           = "iva_seq1",
2603         .class          = &omap44xx_iva_hwmod_class,
2604         .flags          = HWMOD_INIT_NO_RESET,
2605         .rst_lines      = omap44xx_iva_seq1_resets,
2606         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2607         .prcm = {
2608                 .omap4 = {
2609                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2610                 },
2611         },
2612         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2613 };
2614
2615 static struct omap_hwmod omap44xx_iva_hwmod = {
2616         .name           = "iva",
2617         .class          = &omap44xx_iva_hwmod_class,
2618         .mpu_irqs       = omap44xx_iva_irqs,
2619         .rst_lines      = omap44xx_iva_resets,
2620         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2621         .main_clk       = "iva_fck",
2622         .prcm = {
2623                 .omap4 = {
2624                         .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
2625                         .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
2626                 },
2627         },
2628         .slaves         = omap44xx_iva_slaves,
2629         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2630         .masters        = omap44xx_iva_masters,
2631         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2632         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2633 };
2634
2635 /*
2636  * 'kbd' class
2637  * keyboard controller
2638  */
2639
2640 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2641         .rev_offs       = 0x0000,
2642         .sysc_offs      = 0x0010,
2643         .syss_offs      = 0x0014,
2644         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2645                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2646                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2647                            SYSS_HAS_RESET_STATUS),
2648         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2649         .sysc_fields    = &omap_hwmod_sysc_type1,
2650 };
2651
2652 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2653         .name   = "kbd",
2654         .sysc   = &omap44xx_kbd_sysc,
2655 };
2656
2657 /* kbd */
2658 static struct omap_hwmod omap44xx_kbd_hwmod;
2659 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2660         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2661         { .irq = -1 }
2662 };
2663
2664 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2665         {
2666                 .pa_start       = 0x4a31c000,
2667                 .pa_end         = 0x4a31c07f,
2668                 .flags          = ADDR_TYPE_RT
2669         },
2670         { }
2671 };
2672
2673 /* l4_wkup -> kbd */
2674 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2675         .master         = &omap44xx_l4_wkup_hwmod,
2676         .slave          = &omap44xx_kbd_hwmod,
2677         .clk            = "l4_wkup_clk_mux_ck",
2678         .addr           = omap44xx_kbd_addrs,
2679         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2680 };
2681
2682 /* kbd slave ports */
2683 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2684         &omap44xx_l4_wkup__kbd,
2685 };
2686
2687 static struct omap_hwmod omap44xx_kbd_hwmod = {
2688         .name           = "kbd",
2689         .class          = &omap44xx_kbd_hwmod_class,
2690         .mpu_irqs       = omap44xx_kbd_irqs,
2691         .main_clk       = "kbd_fck",
2692         .prcm = {
2693                 .omap4 = {
2694                         .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
2695                 },
2696         },
2697         .slaves         = omap44xx_kbd_slaves,
2698         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2699         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2700 };
2701
2702 /*
2703  * 'mailbox' class
2704  * mailbox module allowing communication between the on-chip processors using a
2705  * queued mailbox-interrupt mechanism.
2706  */
2707
2708 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2709         .rev_offs       = 0x0000,
2710         .sysc_offs      = 0x0010,
2711         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2712                            SYSC_HAS_SOFTRESET),
2713         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2714         .sysc_fields    = &omap_hwmod_sysc_type2,
2715 };
2716
2717 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2718         .name   = "mailbox",
2719         .sysc   = &omap44xx_mailbox_sysc,
2720 };
2721
2722 /* mailbox */
2723 static struct omap_hwmod omap44xx_mailbox_hwmod;
2724 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2725         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2726         { .irq = -1 }
2727 };
2728
2729 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2730         {
2731                 .pa_start       = 0x4a0f4000,
2732                 .pa_end         = 0x4a0f41ff,
2733                 .flags          = ADDR_TYPE_RT
2734         },
2735         { }
2736 };
2737
2738 /* l4_cfg -> mailbox */
2739 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2740         .master         = &omap44xx_l4_cfg_hwmod,
2741         .slave          = &omap44xx_mailbox_hwmod,
2742         .clk            = "l4_div_ck",
2743         .addr           = omap44xx_mailbox_addrs,
2744         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2745 };
2746
2747 /* mailbox slave ports */
2748 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2749         &omap44xx_l4_cfg__mailbox,
2750 };
2751
2752 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2753         .name           = "mailbox",
2754         .class          = &omap44xx_mailbox_hwmod_class,
2755         .mpu_irqs       = omap44xx_mailbox_irqs,
2756         .prcm = {
2757                 .omap4 = {
2758                         .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
2759                 },
2760         },
2761         .slaves         = omap44xx_mailbox_slaves,
2762         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2763         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2764 };
2765
2766 /*
2767  * 'mcbsp' class
2768  * multi channel buffered serial port controller
2769  */
2770
2771 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2772         .sysc_offs      = 0x008c,
2773         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2774                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2775         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2776         .sysc_fields    = &omap_hwmod_sysc_type1,
2777 };
2778
2779 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2780         .name   = "mcbsp",
2781         .sysc   = &omap44xx_mcbsp_sysc,
2782         .rev    = MCBSP_CONFIG_TYPE4,
2783 };
2784
2785 /* mcbsp1 */
2786 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2787 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2788         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2789         { .irq = -1 }
2790 };
2791
2792 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2793         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2794         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2795         { .dma_req = -1 }
2796 };
2797
2798 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2799         {
2800                 .name           = "mpu",
2801                 .pa_start       = 0x40122000,
2802                 .pa_end         = 0x401220ff,
2803                 .flags          = ADDR_TYPE_RT
2804         },
2805         { }
2806 };
2807
2808 /* l4_abe -> mcbsp1 */
2809 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2810         .master         = &omap44xx_l4_abe_hwmod,
2811         .slave          = &omap44xx_mcbsp1_hwmod,
2812         .clk            = "ocp_abe_iclk",
2813         .addr           = omap44xx_mcbsp1_addrs,
2814         .user           = OCP_USER_MPU,
2815 };
2816
2817 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2818         {
2819                 .name           = "dma",
2820                 .pa_start       = 0x49022000,
2821                 .pa_end         = 0x490220ff,
2822                 .flags          = ADDR_TYPE_RT
2823         },
2824         { }
2825 };
2826
2827 /* l4_abe -> mcbsp1 (dma) */
2828 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2829         .master         = &omap44xx_l4_abe_hwmod,
2830         .slave          = &omap44xx_mcbsp1_hwmod,
2831         .clk            = "ocp_abe_iclk",
2832         .addr           = omap44xx_mcbsp1_dma_addrs,
2833         .user           = OCP_USER_SDMA,
2834 };
2835
2836 /* mcbsp1 slave ports */
2837 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2838         &omap44xx_l4_abe__mcbsp1,
2839         &omap44xx_l4_abe__mcbsp1_dma,
2840 };
2841
2842 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2843         .name           = "mcbsp1",
2844         .class          = &omap44xx_mcbsp_hwmod_class,
2845         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2846         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2847         .main_clk       = "mcbsp1_fck",
2848         .prcm = {
2849                 .omap4 = {
2850                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
2851                 },
2852         },
2853         .slaves         = omap44xx_mcbsp1_slaves,
2854         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2855         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2856 };
2857
2858 /* mcbsp2 */
2859 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2860 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2861         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2862         { .irq = -1 }
2863 };
2864
2865 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2866         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2867         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2868         { .dma_req = -1 }
2869 };
2870
2871 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2872         {
2873                 .name           = "mpu",
2874                 .pa_start       = 0x40124000,
2875                 .pa_end         = 0x401240ff,
2876                 .flags          = ADDR_TYPE_RT
2877         },
2878         { }
2879 };
2880
2881 /* l4_abe -> mcbsp2 */
2882 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2883         .master         = &omap44xx_l4_abe_hwmod,
2884         .slave          = &omap44xx_mcbsp2_hwmod,
2885         .clk            = "ocp_abe_iclk",
2886         .addr           = omap44xx_mcbsp2_addrs,
2887         .user           = OCP_USER_MPU,
2888 };
2889
2890 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2891         {
2892                 .name           = "dma",
2893                 .pa_start       = 0x49024000,
2894                 .pa_end         = 0x490240ff,
2895                 .flags          = ADDR_TYPE_RT
2896         },
2897         { }
2898 };
2899
2900 /* l4_abe -> mcbsp2 (dma) */
2901 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2902         .master         = &omap44xx_l4_abe_hwmod,
2903         .slave          = &omap44xx_mcbsp2_hwmod,
2904         .clk            = "ocp_abe_iclk",
2905         .addr           = omap44xx_mcbsp2_dma_addrs,
2906         .user           = OCP_USER_SDMA,
2907 };
2908
2909 /* mcbsp2 slave ports */
2910 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2911         &omap44xx_l4_abe__mcbsp2,
2912         &omap44xx_l4_abe__mcbsp2_dma,
2913 };
2914
2915 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
2916         .name           = "mcbsp2",
2917         .class          = &omap44xx_mcbsp_hwmod_class,
2918         .mpu_irqs       = omap44xx_mcbsp2_irqs,
2919         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
2920         .main_clk       = "mcbsp2_fck",
2921         .prcm = {
2922                 .omap4 = {
2923                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
2924                 },
2925         },
2926         .slaves         = omap44xx_mcbsp2_slaves,
2927         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
2928         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
2929 };
2930
2931 /* mcbsp3 */
2932 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
2933 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
2934         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
2935         { .irq = -1 }
2936 };
2937
2938 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2939         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
2940         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
2941         { .dma_req = -1 }
2942 };
2943
2944 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2945         {
2946                 .name           = "mpu",
2947                 .pa_start       = 0x40126000,
2948                 .pa_end         = 0x401260ff,
2949                 .flags          = ADDR_TYPE_RT
2950         },
2951         { }
2952 };
2953
2954 /* l4_abe -> mcbsp3 */
2955 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2956         .master         = &omap44xx_l4_abe_hwmod,
2957         .slave          = &omap44xx_mcbsp3_hwmod,
2958         .clk            = "ocp_abe_iclk",
2959         .addr           = omap44xx_mcbsp3_addrs,
2960         .user           = OCP_USER_MPU,
2961 };
2962
2963 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2964         {
2965                 .name           = "dma",
2966                 .pa_start       = 0x49026000,
2967                 .pa_end         = 0x490260ff,
2968                 .flags          = ADDR_TYPE_RT
2969         },
2970         { }
2971 };
2972
2973 /* l4_abe -> mcbsp3 (dma) */
2974 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
2975         .master         = &omap44xx_l4_abe_hwmod,
2976         .slave          = &omap44xx_mcbsp3_hwmod,
2977         .clk            = "ocp_abe_iclk",
2978         .addr           = omap44xx_mcbsp3_dma_addrs,
2979         .user           = OCP_USER_SDMA,
2980 };
2981
2982 /* mcbsp3 slave ports */
2983 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
2984         &omap44xx_l4_abe__mcbsp3,
2985         &omap44xx_l4_abe__mcbsp3_dma,
2986 };
2987
2988 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
2989         .name           = "mcbsp3",
2990         .class          = &omap44xx_mcbsp_hwmod_class,
2991         .mpu_irqs       = omap44xx_mcbsp3_irqs,
2992         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
2993         .main_clk       = "mcbsp3_fck",
2994         .prcm = {
2995                 .omap4 = {
2996                         .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
2997                 },
2998         },
2999         .slaves         = omap44xx_mcbsp3_slaves,
3000         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3001         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3002 };
3003
3004 /* mcbsp4 */
3005 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3006 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3007         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3008         { .irq = -1 }
3009 };
3010
3011 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3012         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3013         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3014         { .dma_req = -1 }
3015 };
3016
3017 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3018         {
3019                 .pa_start       = 0x48096000,
3020                 .pa_end         = 0x480960ff,
3021                 .flags          = ADDR_TYPE_RT
3022         },
3023         { }
3024 };
3025
3026 /* l4_per -> mcbsp4 */
3027 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3028         .master         = &omap44xx_l4_per_hwmod,
3029         .slave          = &omap44xx_mcbsp4_hwmod,
3030         .clk            = "l4_div_ck",
3031         .addr           = omap44xx_mcbsp4_addrs,
3032         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3033 };
3034
3035 /* mcbsp4 slave ports */
3036 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3037         &omap44xx_l4_per__mcbsp4,
3038 };
3039
3040 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3041         .name           = "mcbsp4",
3042         .class          = &omap44xx_mcbsp_hwmod_class,
3043         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3044         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3045         .main_clk       = "mcbsp4_fck",
3046         .prcm = {
3047                 .omap4 = {
3048                         .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
3049                 },
3050         },
3051         .slaves         = omap44xx_mcbsp4_slaves,
3052         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3053         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3054 };
3055
3056 /*
3057  * 'mcpdm' class
3058  * multi channel pdm controller (proprietary interface with phoenix power
3059  * ic)
3060  */
3061
3062 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3063         .rev_offs       = 0x0000,
3064         .sysc_offs      = 0x0010,
3065         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3066                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3067         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3068                            SIDLE_SMART_WKUP),
3069         .sysc_fields    = &omap_hwmod_sysc_type2,
3070 };
3071
3072 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3073         .name   = "mcpdm",
3074         .sysc   = &omap44xx_mcpdm_sysc,
3075 };
3076
3077 /* mcpdm */
3078 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3079 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3080         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3081         { .irq = -1 }
3082 };
3083
3084 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3085         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3086         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3087         { .dma_req = -1 }
3088 };
3089
3090 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3091         {
3092                 .pa_start       = 0x40132000,
3093                 .pa_end         = 0x4013207f,
3094                 .flags          = ADDR_TYPE_RT
3095         },
3096         { }
3097 };
3098
3099 /* l4_abe -> mcpdm */
3100 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3101         .master         = &omap44xx_l4_abe_hwmod,
3102         .slave          = &omap44xx_mcpdm_hwmod,
3103         .clk            = "ocp_abe_iclk",
3104         .addr           = omap44xx_mcpdm_addrs,
3105         .user           = OCP_USER_MPU,
3106 };
3107
3108 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3109         {
3110                 .pa_start       = 0x49032000,
3111                 .pa_end         = 0x4903207f,
3112                 .flags          = ADDR_TYPE_RT
3113         },
3114         { }
3115 };
3116
3117 /* l4_abe -> mcpdm (dma) */
3118 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3119         .master         = &omap44xx_l4_abe_hwmod,
3120         .slave          = &omap44xx_mcpdm_hwmod,
3121         .clk            = "ocp_abe_iclk",
3122         .addr           = omap44xx_mcpdm_dma_addrs,
3123         .user           = OCP_USER_SDMA,
3124 };
3125
3126 /* mcpdm slave ports */
3127 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3128         &omap44xx_l4_abe__mcpdm,
3129         &omap44xx_l4_abe__mcpdm_dma,
3130 };
3131
3132 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3133         .name           = "mcpdm",
3134         .class          = &omap44xx_mcpdm_hwmod_class,
3135         .mpu_irqs       = omap44xx_mcpdm_irqs,
3136         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3137         .main_clk       = "mcpdm_fck",
3138         .prcm = {
3139                 .omap4 = {
3140                         .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
3141                 },
3142         },
3143         .slaves         = omap44xx_mcpdm_slaves,
3144         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3145         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3146 };
3147
3148 /*
3149  * 'mcspi' class
3150  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3151  * bus
3152  */
3153
3154 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3155         .rev_offs       = 0x0000,
3156         .sysc_offs      = 0x0010,
3157         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3158                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3160                            SIDLE_SMART_WKUP),
3161         .sysc_fields    = &omap_hwmod_sysc_type2,
3162 };
3163
3164 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3165         .name   = "mcspi",
3166         .sysc   = &omap44xx_mcspi_sysc,
3167         .rev    = OMAP4_MCSPI_REV,
3168 };
3169
3170 /* mcspi1 */
3171 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3172 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3173         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3174         { .irq = -1 }
3175 };
3176
3177 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3178         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3179         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3180         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3181         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3182         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3183         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3184         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3185         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3186         { .dma_req = -1 }
3187 };
3188
3189 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3190         {
3191                 .pa_start       = 0x48098000,
3192                 .pa_end         = 0x480981ff,
3193                 .flags          = ADDR_TYPE_RT
3194         },
3195         { }
3196 };
3197
3198 /* l4_per -> mcspi1 */
3199 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3200         .master         = &omap44xx_l4_per_hwmod,
3201         .slave          = &omap44xx_mcspi1_hwmod,
3202         .clk            = "l4_div_ck",
3203         .addr           = omap44xx_mcspi1_addrs,
3204         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3205 };
3206
3207 /* mcspi1 slave ports */
3208 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3209         &omap44xx_l4_per__mcspi1,
3210 };
3211
3212 /* mcspi1 dev_attr */
3213 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3214         .num_chipselect = 4,
3215 };
3216
3217 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3218         .name           = "mcspi1",
3219         .class          = &omap44xx_mcspi_hwmod_class,
3220         .mpu_irqs       = omap44xx_mcspi1_irqs,
3221         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3222         .main_clk       = "mcspi1_fck",
3223         .prcm = {
3224                 .omap4 = {
3225                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
3226                 },
3227         },
3228         .dev_attr       = &mcspi1_dev_attr,
3229         .slaves         = omap44xx_mcspi1_slaves,
3230         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3231         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3232 };
3233
3234 /* mcspi2 */
3235 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3236 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3237         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3238         { .irq = -1 }
3239 };
3240
3241 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3242         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3243         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3244         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3245         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3246         { .dma_req = -1 }
3247 };
3248
3249 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3250         {
3251                 .pa_start       = 0x4809a000,
3252                 .pa_end         = 0x4809a1ff,
3253                 .flags          = ADDR_TYPE_RT
3254         },
3255         { }
3256 };
3257
3258 /* l4_per -> mcspi2 */
3259 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3260         .master         = &omap44xx_l4_per_hwmod,
3261         .slave          = &omap44xx_mcspi2_hwmod,
3262         .clk            = "l4_div_ck",
3263         .addr           = omap44xx_mcspi2_addrs,
3264         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3265 };
3266
3267 /* mcspi2 slave ports */
3268 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3269         &omap44xx_l4_per__mcspi2,
3270 };
3271
3272 /* mcspi2 dev_attr */
3273 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3274         .num_chipselect = 2,
3275 };
3276
3277 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3278         .name           = "mcspi2",
3279         .class          = &omap44xx_mcspi_hwmod_class,
3280         .mpu_irqs       = omap44xx_mcspi2_irqs,
3281         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3282         .main_clk       = "mcspi2_fck",
3283         .prcm = {
3284                 .omap4 = {
3285                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
3286                 },
3287         },
3288         .dev_attr       = &mcspi2_dev_attr,
3289         .slaves         = omap44xx_mcspi2_slaves,
3290         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3291         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3292 };
3293
3294 /* mcspi3 */
3295 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3296 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3297         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3298         { .irq = -1 }
3299 };
3300
3301 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3302         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3303         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3304         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3305         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3306         { .dma_req = -1 }
3307 };
3308
3309 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3310         {
3311                 .pa_start       = 0x480b8000,
3312                 .pa_end         = 0x480b81ff,
3313                 .flags          = ADDR_TYPE_RT
3314         },
3315         { }
3316 };
3317
3318 /* l4_per -> mcspi3 */
3319 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3320         .master         = &omap44xx_l4_per_hwmod,
3321         .slave          = &omap44xx_mcspi3_hwmod,
3322         .clk            = "l4_div_ck",
3323         .addr           = omap44xx_mcspi3_addrs,
3324         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3325 };
3326
3327 /* mcspi3 slave ports */
3328 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3329         &omap44xx_l4_per__mcspi3,
3330 };
3331
3332 /* mcspi3 dev_attr */
3333 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3334         .num_chipselect = 2,
3335 };
3336
3337 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3338         .name           = "mcspi3",
3339         .class          = &omap44xx_mcspi_hwmod_class,
3340         .mpu_irqs       = omap44xx_mcspi3_irqs,
3341         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3342         .main_clk       = "mcspi3_fck",
3343         .prcm = {
3344                 .omap4 = {
3345                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
3346                 },
3347         },
3348         .dev_attr       = &mcspi3_dev_attr,
3349         .slaves         = omap44xx_mcspi3_slaves,
3350         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3351         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3352 };
3353
3354 /* mcspi4 */
3355 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3356 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3357         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3358         { .irq = -1 }
3359 };
3360
3361 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3362         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3363         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3364         { .dma_req = -1 }
3365 };
3366
3367 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3368         {
3369                 .pa_start       = 0x480ba000,
3370                 .pa_end         = 0x480ba1ff,
3371                 .flags          = ADDR_TYPE_RT
3372         },
3373         { }
3374 };
3375
3376 /* l4_per -> mcspi4 */
3377 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3378         .master         = &omap44xx_l4_per_hwmod,
3379         .slave          = &omap44xx_mcspi4_hwmod,
3380         .clk            = "l4_div_ck",
3381         .addr           = omap44xx_mcspi4_addrs,
3382         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3383 };
3384
3385 /* mcspi4 slave ports */
3386 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3387         &omap44xx_l4_per__mcspi4,
3388 };
3389
3390 /* mcspi4 dev_attr */
3391 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3392         .num_chipselect = 1,
3393 };
3394
3395 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3396         .name           = "mcspi4",
3397         .class          = &omap44xx_mcspi_hwmod_class,
3398         .mpu_irqs       = omap44xx_mcspi4_irqs,
3399         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3400         .main_clk       = "mcspi4_fck",
3401         .prcm = {
3402                 .omap4 = {
3403                         .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
3404                 },
3405         },
3406         .dev_attr       = &mcspi4_dev_attr,
3407         .slaves         = omap44xx_mcspi4_slaves,
3408         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3409         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3410 };
3411
3412 /*
3413  * 'mmc' class
3414  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3415  */
3416
3417 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3418         .rev_offs       = 0x0000,
3419         .sysc_offs      = 0x0010,
3420         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3421                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3422                            SYSC_HAS_SOFTRESET),
3423         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3424                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3425                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3426         .sysc_fields    = &omap_hwmod_sysc_type2,
3427 };
3428
3429 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3430         .name   = "mmc",
3431         .sysc   = &omap44xx_mmc_sysc,
3432 };
3433
3434 /* mmc1 */
3435 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3436         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3437         { .irq = -1 }
3438 };
3439
3440 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3441         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3442         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3443         { .dma_req = -1 }
3444 };
3445
3446 /* mmc1 master ports */
3447 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3448         &omap44xx_mmc1__l3_main_1,
3449 };
3450
3451 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3452         {
3453                 .pa_start       = 0x4809c000,
3454                 .pa_end         = 0x4809c3ff,
3455                 .flags          = ADDR_TYPE_RT
3456         },
3457         { }
3458 };
3459
3460 /* l4_per -> mmc1 */
3461 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3462         .master         = &omap44xx_l4_per_hwmod,
3463         .slave          = &omap44xx_mmc1_hwmod,
3464         .clk            = "l4_div_ck",
3465         .addr           = omap44xx_mmc1_addrs,
3466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3467 };
3468
3469 /* mmc1 slave ports */
3470 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3471         &omap44xx_l4_per__mmc1,
3472 };
3473
3474 /* mmc1 dev_attr */
3475 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3476         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3477 };
3478
3479 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3480         .name           = "mmc1",
3481         .class          = &omap44xx_mmc_hwmod_class,
3482         .mpu_irqs       = omap44xx_mmc1_irqs,
3483         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3484         .main_clk       = "mmc1_fck",
3485         .prcm = {
3486                 .omap4 = {
3487                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3488                 },
3489         },
3490         .dev_attr       = &mmc1_dev_attr,
3491         .slaves         = omap44xx_mmc1_slaves,
3492         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3493         .masters        = omap44xx_mmc1_masters,
3494         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3495         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3496 };
3497
3498 /* mmc2 */
3499 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3500         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3501         { .irq = -1 }
3502 };
3503
3504 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3505         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3506         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3507         { .dma_req = -1 }
3508 };
3509
3510 /* mmc2 master ports */
3511 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3512         &omap44xx_mmc2__l3_main_1,
3513 };
3514
3515 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3516         {
3517                 .pa_start       = 0x480b4000,
3518                 .pa_end         = 0x480b43ff,
3519                 .flags          = ADDR_TYPE_RT
3520         },
3521         { }
3522 };
3523
3524 /* l4_per -> mmc2 */
3525 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3526         .master         = &omap44xx_l4_per_hwmod,
3527         .slave          = &omap44xx_mmc2_hwmod,
3528         .clk            = "l4_div_ck",
3529         .addr           = omap44xx_mmc2_addrs,
3530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3531 };
3532
3533 /* mmc2 slave ports */
3534 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3535         &omap44xx_l4_per__mmc2,
3536 };
3537
3538 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3539         .name           = "mmc2",
3540         .class          = &omap44xx_mmc_hwmod_class,
3541         .mpu_irqs       = omap44xx_mmc2_irqs,
3542         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3543         .main_clk       = "mmc2_fck",
3544         .prcm = {
3545                 .omap4 = {
3546                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
3547                 },
3548         },
3549         .slaves         = omap44xx_mmc2_slaves,
3550         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3551         .masters        = omap44xx_mmc2_masters,
3552         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3553         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3554 };
3555
3556 /* mmc3 */
3557 static struct omap_hwmod omap44xx_mmc3_hwmod;
3558 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3559         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3560         { .irq = -1 }
3561 };
3562
3563 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3564         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3565         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3566         { .dma_req = -1 }
3567 };
3568
3569 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3570         {
3571                 .pa_start       = 0x480ad000,
3572                 .pa_end         = 0x480ad3ff,
3573                 .flags          = ADDR_TYPE_RT
3574         },
3575         { }
3576 };
3577
3578 /* l4_per -> mmc3 */
3579 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3580         .master         = &omap44xx_l4_per_hwmod,
3581         .slave          = &omap44xx_mmc3_hwmod,
3582         .clk            = "l4_div_ck",
3583         .addr           = omap44xx_mmc3_addrs,
3584         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3585 };
3586
3587 /* mmc3 slave ports */
3588 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3589         &omap44xx_l4_per__mmc3,
3590 };
3591
3592 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3593         .name           = "mmc3",
3594         .class          = &omap44xx_mmc_hwmod_class,
3595         .mpu_irqs       = omap44xx_mmc3_irqs,
3596         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3597         .main_clk       = "mmc3_fck",
3598         .prcm = {
3599                 .omap4 = {
3600                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
3601                 },
3602         },
3603         .slaves         = omap44xx_mmc3_slaves,
3604         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3605         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3606 };
3607
3608 /* mmc4 */
3609 static struct omap_hwmod omap44xx_mmc4_hwmod;
3610 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3611         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3612         { .irq = -1 }
3613 };
3614
3615 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3616         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3617         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3618         { .dma_req = -1 }
3619 };
3620
3621 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3622         {
3623                 .pa_start       = 0x480d1000,
3624                 .pa_end         = 0x480d13ff,
3625                 .flags          = ADDR_TYPE_RT
3626         },
3627         { }
3628 };
3629
3630 /* l4_per -> mmc4 */
3631 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3632         .master         = &omap44xx_l4_per_hwmod,
3633         .slave          = &omap44xx_mmc4_hwmod,
3634         .clk            = "l4_div_ck",
3635         .addr           = omap44xx_mmc4_addrs,
3636         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3637 };
3638
3639 /* mmc4 slave ports */
3640 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3641         &omap44xx_l4_per__mmc4,
3642 };
3643
3644 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3645         .name           = "mmc4",
3646         .class          = &omap44xx_mmc_hwmod_class,
3647         .mpu_irqs       = omap44xx_mmc4_irqs,
3648
3649         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3650         .main_clk       = "mmc4_fck",
3651         .prcm = {
3652                 .omap4 = {
3653                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
3654                 },
3655         },
3656         .slaves         = omap44xx_mmc4_slaves,
3657         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3658         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3659 };
3660
3661 /* mmc5 */
3662 static struct omap_hwmod omap44xx_mmc5_hwmod;
3663 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3664         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3665         { .irq = -1 }
3666 };
3667
3668 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3669         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3670         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3671         { .dma_req = -1 }
3672 };
3673
3674 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3675         {
3676                 .pa_start       = 0x480d5000,
3677                 .pa_end         = 0x480d53ff,
3678                 .flags          = ADDR_TYPE_RT
3679         },
3680         { }
3681 };
3682
3683 /* l4_per -> mmc5 */
3684 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3685         .master         = &omap44xx_l4_per_hwmod,
3686         .slave          = &omap44xx_mmc5_hwmod,
3687         .clk            = "l4_div_ck",
3688         .addr           = omap44xx_mmc5_addrs,
3689         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3690 };
3691
3692 /* mmc5 slave ports */
3693 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3694         &omap44xx_l4_per__mmc5,
3695 };
3696
3697 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3698         .name           = "mmc5",
3699         .class          = &omap44xx_mmc_hwmod_class,
3700         .mpu_irqs       = omap44xx_mmc5_irqs,
3701         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3702         .main_clk       = "mmc5_fck",
3703         .prcm = {
3704                 .omap4 = {
3705                         .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
3706                 },
3707         },
3708         .slaves         = omap44xx_mmc5_slaves,
3709         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3710         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3711 };
3712
3713 /*
3714  * 'mpu' class
3715  * mpu sub-system
3716  */
3717
3718 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3719         .name   = "mpu",
3720 };
3721
3722 /* mpu */
3723 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3724         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3725         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3726         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3727         { .irq = -1 }
3728 };
3729
3730 /* mpu master ports */
3731 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3732         &omap44xx_mpu__l3_main_1,
3733         &omap44xx_mpu__l4_abe,
3734         &omap44xx_mpu__dmm,
3735 };
3736
3737 static struct omap_hwmod omap44xx_mpu_hwmod = {
3738         .name           = "mpu",
3739         .class          = &omap44xx_mpu_hwmod_class,
3740         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3741         .mpu_irqs       = omap44xx_mpu_irqs,
3742         .main_clk       = "dpll_mpu_m2_ck",
3743         .prcm = {
3744                 .omap4 = {
3745                         .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
3746                 },
3747         },
3748         .masters        = omap44xx_mpu_masters,
3749         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3750         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3751 };
3752
3753 /*
3754  * 'smartreflex' class
3755  * smartreflex module (monitor silicon performance and outputs a measure of
3756  * performance error)
3757  */
3758
3759 /* The IP is not compliant to type1 / type2 scheme */
3760 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3761         .sidle_shift    = 24,
3762         .enwkup_shift   = 26,
3763 };
3764
3765 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3766         .sysc_offs      = 0x0038,
3767         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3768         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3769                            SIDLE_SMART_WKUP),
3770         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3771 };
3772
3773 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3774         .name   = "smartreflex",
3775         .sysc   = &omap44xx_smartreflex_sysc,
3776         .rev    = 2,
3777 };
3778
3779 /* smartreflex_core */
3780 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3781 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3782         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3783         { .irq = -1 }
3784 };
3785
3786 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3787         {
3788                 .pa_start       = 0x4a0dd000,
3789                 .pa_end         = 0x4a0dd03f,
3790                 .flags          = ADDR_TYPE_RT
3791         },
3792         { }
3793 };
3794
3795 /* l4_cfg -> smartreflex_core */
3796 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3797         .master         = &omap44xx_l4_cfg_hwmod,
3798         .slave          = &omap44xx_smartreflex_core_hwmod,
3799         .clk            = "l4_div_ck",
3800         .addr           = omap44xx_smartreflex_core_addrs,
3801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3802 };
3803
3804 /* smartreflex_core slave ports */
3805 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3806         &omap44xx_l4_cfg__smartreflex_core,
3807 };
3808
3809 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3810         .name           = "smartreflex_core",
3811         .class          = &omap44xx_smartreflex_hwmod_class,
3812         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3813
3814         .main_clk       = "smartreflex_core_fck",
3815         .vdd_name       = "core",
3816         .prcm = {
3817                 .omap4 = {
3818                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
3819                 },
3820         },
3821         .slaves         = omap44xx_smartreflex_core_slaves,
3822         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3823         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3824 };
3825
3826 /* smartreflex_iva */
3827 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3828 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3829         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3830         { .irq = -1 }
3831 };
3832
3833 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3834         {
3835                 .pa_start       = 0x4a0db000,
3836                 .pa_end         = 0x4a0db03f,
3837                 .flags          = ADDR_TYPE_RT
3838         },
3839         { }
3840 };
3841
3842 /* l4_cfg -> smartreflex_iva */
3843 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3844         .master         = &omap44xx_l4_cfg_hwmod,
3845         .slave          = &omap44xx_smartreflex_iva_hwmod,
3846         .clk            = "l4_div_ck",
3847         .addr           = omap44xx_smartreflex_iva_addrs,
3848         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3849 };
3850
3851 /* smartreflex_iva slave ports */
3852 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3853         &omap44xx_l4_cfg__smartreflex_iva,
3854 };
3855
3856 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
3857         .name           = "smartreflex_iva",
3858         .class          = &omap44xx_smartreflex_hwmod_class,
3859         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
3860         .main_clk       = "smartreflex_iva_fck",
3861         .vdd_name       = "iva",
3862         .prcm = {
3863                 .omap4 = {
3864                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
3865                 },
3866         },
3867         .slaves         = omap44xx_smartreflex_iva_slaves,
3868         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
3869         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3870 };
3871
3872 /* smartreflex_mpu */
3873 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
3874 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
3875         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
3876         { .irq = -1 }
3877 };
3878
3879 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
3880         {
3881                 .pa_start       = 0x4a0d9000,
3882                 .pa_end         = 0x4a0d903f,
3883                 .flags          = ADDR_TYPE_RT
3884         },
3885         { }
3886 };
3887
3888 /* l4_cfg -> smartreflex_mpu */
3889 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3890         .master         = &omap44xx_l4_cfg_hwmod,
3891         .slave          = &omap44xx_smartreflex_mpu_hwmod,
3892         .clk            = "l4_div_ck",
3893         .addr           = omap44xx_smartreflex_mpu_addrs,
3894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3895 };
3896
3897 /* smartreflex_mpu slave ports */
3898 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
3899         &omap44xx_l4_cfg__smartreflex_mpu,
3900 };
3901
3902 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
3903         .name           = "smartreflex_mpu",
3904         .class          = &omap44xx_smartreflex_hwmod_class,
3905         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
3906         .main_clk       = "smartreflex_mpu_fck",
3907         .vdd_name       = "mpu",
3908         .prcm = {
3909                 .omap4 = {
3910                         .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
3911                 },
3912         },
3913         .slaves         = omap44xx_smartreflex_mpu_slaves,
3914         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
3915         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3916 };
3917
3918 /*
3919  * 'spinlock' class
3920  * spinlock provides hardware assistance for synchronizing the processes
3921  * running on multiple processors
3922  */
3923
3924 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
3925         .rev_offs       = 0x0000,
3926         .sysc_offs      = 0x0010,
3927         .syss_offs      = 0x0014,
3928         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3929                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
3930                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3931         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3932                            SIDLE_SMART_WKUP),
3933         .sysc_fields    = &omap_hwmod_sysc_type1,
3934 };
3935
3936 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
3937         .name   = "spinlock",
3938         .sysc   = &omap44xx_spinlock_sysc,
3939 };
3940
3941 /* spinlock */
3942 static struct omap_hwmod omap44xx_spinlock_hwmod;
3943 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
3944         {
3945                 .pa_start       = 0x4a0f6000,
3946                 .pa_end         = 0x4a0f6fff,
3947                 .flags          = ADDR_TYPE_RT
3948         },
3949         { }
3950 };
3951
3952 /* l4_cfg -> spinlock */
3953 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3954         .master         = &omap44xx_l4_cfg_hwmod,
3955         .slave          = &omap44xx_spinlock_hwmod,
3956         .clk            = "l4_div_ck",
3957         .addr           = omap44xx_spinlock_addrs,
3958         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3959 };
3960
3961 /* spinlock slave ports */
3962 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
3963         &omap44xx_l4_cfg__spinlock,
3964 };
3965
3966 static struct omap_hwmod omap44xx_spinlock_hwmod = {
3967         .name           = "spinlock",
3968         .class          = &omap44xx_spinlock_hwmod_class,
3969         .prcm = {
3970                 .omap4 = {
3971                         .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
3972                 },
3973         },
3974         .slaves         = omap44xx_spinlock_slaves,
3975         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
3976         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
3977 };
3978
3979 /*
3980  * 'timer' class
3981  * general purpose timer module with accurate 1ms tick
3982  * This class contains several variants: ['timer_1ms', 'timer']
3983  */
3984
3985 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3986         .rev_offs       = 0x0000,
3987         .sysc_offs      = 0x0010,
3988         .syss_offs      = 0x0014,
3989         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
3990                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
3991                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3992                            SYSS_HAS_RESET_STATUS),
3993         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3994         .sysc_fields    = &omap_hwmod_sysc_type1,
3995 };
3996
3997 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
3998         .name   = "timer",
3999         .sysc   = &omap44xx_timer_1ms_sysc,
4000 };
4001
4002 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4003         .rev_offs       = 0x0000,
4004         .sysc_offs      = 0x0010,
4005         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4006                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4007         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4008                            SIDLE_SMART_WKUP),
4009         .sysc_fields    = &omap_hwmod_sysc_type2,
4010 };
4011
4012 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4013         .name   = "timer",
4014         .sysc   = &omap44xx_timer_sysc,
4015 };
4016
4017 /* timer1 */
4018 static struct omap_hwmod omap44xx_timer1_hwmod;
4019 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4020         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4021         { .irq = -1 }
4022 };
4023
4024 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4025         {
4026                 .pa_start       = 0x4a318000,
4027                 .pa_end         = 0x4a31807f,
4028                 .flags          = ADDR_TYPE_RT
4029         },
4030         { }
4031 };
4032
4033 /* l4_wkup -> timer1 */
4034 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4035         .master         = &omap44xx_l4_wkup_hwmod,
4036         .slave          = &omap44xx_timer1_hwmod,
4037         .clk            = "l4_wkup_clk_mux_ck",
4038         .addr           = omap44xx_timer1_addrs,
4039         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4040 };
4041
4042 /* timer1 slave ports */
4043 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4044         &omap44xx_l4_wkup__timer1,
4045 };
4046
4047 static struct omap_hwmod omap44xx_timer1_hwmod = {
4048         .name           = "timer1",
4049         .class          = &omap44xx_timer_1ms_hwmod_class,
4050         .mpu_irqs       = omap44xx_timer1_irqs,
4051         .main_clk       = "timer1_fck",
4052         .prcm = {
4053                 .omap4 = {
4054                         .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
4055                 },
4056         },
4057         .slaves         = omap44xx_timer1_slaves,
4058         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4059         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4060 };
4061
4062 /* timer2 */
4063 static struct omap_hwmod omap44xx_timer2_hwmod;
4064 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4065         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4066         { .irq = -1 }
4067 };
4068
4069 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4070         {
4071                 .pa_start       = 0x48032000,
4072                 .pa_end         = 0x4803207f,
4073                 .flags          = ADDR_TYPE_RT
4074         },
4075         { }
4076 };
4077
4078 /* l4_per -> timer2 */
4079 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4080         .master         = &omap44xx_l4_per_hwmod,
4081         .slave          = &omap44xx_timer2_hwmod,
4082         .clk            = "l4_div_ck",
4083         .addr           = omap44xx_timer2_addrs,
4084         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4085 };
4086
4087 /* timer2 slave ports */
4088 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4089         &omap44xx_l4_per__timer2,
4090 };
4091
4092 static struct omap_hwmod omap44xx_timer2_hwmod = {
4093         .name           = "timer2",
4094         .class          = &omap44xx_timer_1ms_hwmod_class,
4095         .mpu_irqs       = omap44xx_timer2_irqs,
4096         .main_clk       = "timer2_fck",
4097         .prcm = {
4098                 .omap4 = {
4099                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
4100                 },
4101         },
4102         .slaves         = omap44xx_timer2_slaves,
4103         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4104         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4105 };
4106
4107 /* timer3 */
4108 static struct omap_hwmod omap44xx_timer3_hwmod;
4109 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4110         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4111         { .irq = -1 }
4112 };
4113
4114 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4115         {
4116                 .pa_start       = 0x48034000,
4117                 .pa_end         = 0x4803407f,
4118                 .flags          = ADDR_TYPE_RT
4119         },
4120         { }
4121 };
4122
4123 /* l4_per -> timer3 */
4124 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4125         .master         = &omap44xx_l4_per_hwmod,
4126         .slave          = &omap44xx_timer3_hwmod,
4127         .clk            = "l4_div_ck",
4128         .addr           = omap44xx_timer3_addrs,
4129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4130 };
4131
4132 /* timer3 slave ports */
4133 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4134         &omap44xx_l4_per__timer3,
4135 };
4136
4137 static struct omap_hwmod omap44xx_timer3_hwmod = {
4138         .name           = "timer3",
4139         .class          = &omap44xx_timer_hwmod_class,
4140         .mpu_irqs       = omap44xx_timer3_irqs,
4141         .main_clk       = "timer3_fck",
4142         .prcm = {
4143                 .omap4 = {
4144                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
4145                 },
4146         },
4147         .slaves         = omap44xx_timer3_slaves,
4148         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4149         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4150 };
4151
4152 /* timer4 */
4153 static struct omap_hwmod omap44xx_timer4_hwmod;
4154 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4155         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4156         { .irq = -1 }
4157 };
4158
4159 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4160         {
4161                 .pa_start       = 0x48036000,
4162                 .pa_end         = 0x4803607f,
4163                 .flags          = ADDR_TYPE_RT
4164         },
4165         { }
4166 };
4167
4168 /* l4_per -> timer4 */
4169 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4170         .master         = &omap44xx_l4_per_hwmod,
4171         .slave          = &omap44xx_timer4_hwmod,
4172         .clk            = "l4_div_ck",
4173         .addr           = omap44xx_timer4_addrs,
4174         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4175 };
4176
4177 /* timer4 slave ports */
4178 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4179         &omap44xx_l4_per__timer4,
4180 };
4181
4182 static struct omap_hwmod omap44xx_timer4_hwmod = {
4183         .name           = "timer4",
4184         .class          = &omap44xx_timer_hwmod_class,
4185         .mpu_irqs       = omap44xx_timer4_irqs,
4186         .main_clk       = "timer4_fck",
4187         .prcm = {
4188                 .omap4 = {
4189                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
4190                 },
4191         },
4192         .slaves         = omap44xx_timer4_slaves,
4193         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4194         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4195 };
4196
4197 /* timer5 */
4198 static struct omap_hwmod omap44xx_timer5_hwmod;
4199 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4200         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4201         { .irq = -1 }
4202 };
4203
4204 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4205         {
4206                 .pa_start       = 0x40138000,
4207                 .pa_end         = 0x4013807f,
4208                 .flags          = ADDR_TYPE_RT
4209         },
4210         { }
4211 };
4212
4213 /* l4_abe -> timer5 */
4214 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4215         .master         = &omap44xx_l4_abe_hwmod,
4216         .slave          = &omap44xx_timer5_hwmod,
4217         .clk            = "ocp_abe_iclk",
4218         .addr           = omap44xx_timer5_addrs,
4219         .user           = OCP_USER_MPU,
4220 };
4221
4222 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4223         {
4224                 .pa_start       = 0x49038000,
4225                 .pa_end         = 0x4903807f,
4226                 .flags          = ADDR_TYPE_RT
4227         },
4228         { }
4229 };
4230
4231 /* l4_abe -> timer5 (dma) */
4232 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4233         .master         = &omap44xx_l4_abe_hwmod,
4234         .slave          = &omap44xx_timer5_hwmod,
4235         .clk            = "ocp_abe_iclk",
4236         .addr           = omap44xx_timer5_dma_addrs,
4237         .user           = OCP_USER_SDMA,
4238 };
4239
4240 /* timer5 slave ports */
4241 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4242         &omap44xx_l4_abe__timer5,
4243         &omap44xx_l4_abe__timer5_dma,
4244 };
4245
4246 static struct omap_hwmod omap44xx_timer5_hwmod = {
4247         .name           = "timer5",
4248         .class          = &omap44xx_timer_hwmod_class,
4249         .mpu_irqs       = omap44xx_timer5_irqs,
4250         .main_clk       = "timer5_fck",
4251         .prcm = {
4252                 .omap4 = {
4253                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
4254                 },
4255         },
4256         .slaves         = omap44xx_timer5_slaves,
4257         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4258         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4259 };
4260
4261 /* timer6 */
4262 static struct omap_hwmod omap44xx_timer6_hwmod;
4263 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4264         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4265         { .irq = -1 }
4266 };
4267
4268 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4269         {
4270                 .pa_start       = 0x4013a000,
4271                 .pa_end         = 0x4013a07f,
4272                 .flags          = ADDR_TYPE_RT
4273         },
4274         { }
4275 };
4276
4277 /* l4_abe -> timer6 */
4278 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4279         .master         = &omap44xx_l4_abe_hwmod,
4280         .slave          = &omap44xx_timer6_hwmod,
4281         .clk            = "ocp_abe_iclk",
4282         .addr           = omap44xx_timer6_addrs,
4283         .user           = OCP_USER_MPU,
4284 };
4285
4286 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4287         {
4288                 .pa_start       = 0x4903a000,
4289                 .pa_end         = 0x4903a07f,
4290                 .flags          = ADDR_TYPE_RT
4291         },
4292         { }
4293 };
4294
4295 /* l4_abe -> timer6 (dma) */
4296 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4297         .master         = &omap44xx_l4_abe_hwmod,
4298         .slave          = &omap44xx_timer6_hwmod,
4299         .clk            = "ocp_abe_iclk",
4300         .addr           = omap44xx_timer6_dma_addrs,
4301         .user           = OCP_USER_SDMA,
4302 };
4303
4304 /* timer6 slave ports */
4305 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4306         &omap44xx_l4_abe__timer6,
4307         &omap44xx_l4_abe__timer6_dma,
4308 };
4309
4310 static struct omap_hwmod omap44xx_timer6_hwmod = {
4311         .name           = "timer6",
4312         .class          = &omap44xx_timer_hwmod_class,
4313         .mpu_irqs       = omap44xx_timer6_irqs,
4314
4315         .main_clk       = "timer6_fck",
4316         .prcm = {
4317                 .omap4 = {
4318                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
4319                 },
4320         },
4321         .slaves         = omap44xx_timer6_slaves,
4322         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4323         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4324 };
4325
4326 /* timer7 */
4327 static struct omap_hwmod omap44xx_timer7_hwmod;
4328 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4329         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4330         { .irq = -1 }
4331 };
4332
4333 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4334         {
4335                 .pa_start       = 0x4013c000,
4336                 .pa_end         = 0x4013c07f,
4337                 .flags          = ADDR_TYPE_RT
4338         },
4339         { }
4340 };
4341
4342 /* l4_abe -> timer7 */
4343 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4344         .master         = &omap44xx_l4_abe_hwmod,
4345         .slave          = &omap44xx_timer7_hwmod,
4346         .clk            = "ocp_abe_iclk",
4347         .addr           = omap44xx_timer7_addrs,
4348         .user           = OCP_USER_MPU,
4349 };
4350
4351 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4352         {
4353                 .pa_start       = 0x4903c000,
4354                 .pa_end         = 0x4903c07f,
4355                 .flags          = ADDR_TYPE_RT
4356         },
4357         { }
4358 };
4359
4360 /* l4_abe -> timer7 (dma) */
4361 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4362         .master         = &omap44xx_l4_abe_hwmod,
4363         .slave          = &omap44xx_timer7_hwmod,
4364         .clk            = "ocp_abe_iclk",
4365         .addr           = omap44xx_timer7_dma_addrs,
4366         .user           = OCP_USER_SDMA,
4367 };
4368
4369 /* timer7 slave ports */
4370 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4371         &omap44xx_l4_abe__timer7,
4372         &omap44xx_l4_abe__timer7_dma,
4373 };
4374
4375 static struct omap_hwmod omap44xx_timer7_hwmod = {
4376         .name           = "timer7",
4377         .class          = &omap44xx_timer_hwmod_class,
4378         .mpu_irqs       = omap44xx_timer7_irqs,
4379         .main_clk       = "timer7_fck",
4380         .prcm = {
4381                 .omap4 = {
4382                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
4383                 },
4384         },
4385         .slaves         = omap44xx_timer7_slaves,
4386         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4387         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4388 };
4389
4390 /* timer8 */
4391 static struct omap_hwmod omap44xx_timer8_hwmod;
4392 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4393         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4394         { .irq = -1 }
4395 };
4396
4397 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4398         {
4399                 .pa_start       = 0x4013e000,
4400                 .pa_end         = 0x4013e07f,
4401                 .flags          = ADDR_TYPE_RT
4402         },
4403         { }
4404 };
4405
4406 /* l4_abe -> timer8 */
4407 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4408         .master         = &omap44xx_l4_abe_hwmod,
4409         .slave          = &omap44xx_timer8_hwmod,
4410         .clk            = "ocp_abe_iclk",
4411         .addr           = omap44xx_timer8_addrs,
4412         .user           = OCP_USER_MPU,
4413 };
4414
4415 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4416         {
4417                 .pa_start       = 0x4903e000,
4418                 .pa_end         = 0x4903e07f,
4419                 .flags          = ADDR_TYPE_RT
4420         },
4421         { }
4422 };
4423
4424 /* l4_abe -> timer8 (dma) */
4425 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4426         .master         = &omap44xx_l4_abe_hwmod,
4427         .slave          = &omap44xx_timer8_hwmod,
4428         .clk            = "ocp_abe_iclk",
4429         .addr           = omap44xx_timer8_dma_addrs,
4430         .user           = OCP_USER_SDMA,
4431 };
4432
4433 /* timer8 slave ports */
4434 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4435         &omap44xx_l4_abe__timer8,
4436         &omap44xx_l4_abe__timer8_dma,
4437 };
4438
4439 static struct omap_hwmod omap44xx_timer8_hwmod = {
4440         .name           = "timer8",
4441         .class          = &omap44xx_timer_hwmod_class,
4442         .mpu_irqs       = omap44xx_timer8_irqs,
4443         .main_clk       = "timer8_fck",
4444         .prcm = {
4445                 .omap4 = {
4446                         .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
4447                 },
4448         },
4449         .slaves         = omap44xx_timer8_slaves,
4450         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4451         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4452 };
4453
4454 /* timer9 */
4455 static struct omap_hwmod omap44xx_timer9_hwmod;
4456 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4457         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4458         { .irq = -1 }
4459 };
4460
4461 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4462         {
4463                 .pa_start       = 0x4803e000,
4464                 .pa_end         = 0x4803e07f,
4465                 .flags          = ADDR_TYPE_RT
4466         },
4467         { }
4468 };
4469
4470 /* l4_per -> timer9 */
4471 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4472         .master         = &omap44xx_l4_per_hwmod,
4473         .slave          = &omap44xx_timer9_hwmod,
4474         .clk            = "l4_div_ck",
4475         .addr           = omap44xx_timer9_addrs,
4476         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4477 };
4478
4479 /* timer9 slave ports */
4480 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4481         &omap44xx_l4_per__timer9,
4482 };
4483
4484 static struct omap_hwmod omap44xx_timer9_hwmod = {
4485         .name           = "timer9",
4486         .class          = &omap44xx_timer_hwmod_class,
4487         .mpu_irqs       = omap44xx_timer9_irqs,
4488         .main_clk       = "timer9_fck",
4489         .prcm = {
4490                 .omap4 = {
4491                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
4492                 },
4493         },
4494         .slaves         = omap44xx_timer9_slaves,
4495         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4496         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4497 };
4498
4499 /* timer10 */
4500 static struct omap_hwmod omap44xx_timer10_hwmod;
4501 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4502         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4503         { .irq = -1 }
4504 };
4505
4506 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4507         {
4508                 .pa_start       = 0x48086000,
4509                 .pa_end         = 0x4808607f,
4510                 .flags          = ADDR_TYPE_RT
4511         },
4512         { }
4513 };
4514
4515 /* l4_per -> timer10 */
4516 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4517         .master         = &omap44xx_l4_per_hwmod,
4518         .slave          = &omap44xx_timer10_hwmod,
4519         .clk            = "l4_div_ck",
4520         .addr           = omap44xx_timer10_addrs,
4521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4522 };
4523
4524 /* timer10 slave ports */
4525 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4526         &omap44xx_l4_per__timer10,
4527 };
4528
4529 static struct omap_hwmod omap44xx_timer10_hwmod = {
4530         .name           = "timer10",
4531         .class          = &omap44xx_timer_1ms_hwmod_class,
4532         .mpu_irqs       = omap44xx_timer10_irqs,
4533         .main_clk       = "timer10_fck",
4534         .prcm = {
4535                 .omap4 = {
4536                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
4537                 },
4538         },
4539         .slaves         = omap44xx_timer10_slaves,
4540         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4541         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4542 };
4543
4544 /* timer11 */
4545 static struct omap_hwmod omap44xx_timer11_hwmod;
4546 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4547         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4548         { .irq = -1 }
4549 };
4550
4551 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4552         {
4553                 .pa_start       = 0x48088000,
4554                 .pa_end         = 0x4808807f,
4555                 .flags          = ADDR_TYPE_RT
4556         },
4557         { }
4558 };
4559
4560 /* l4_per -> timer11 */
4561 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4562         .master         = &omap44xx_l4_per_hwmod,
4563         .slave          = &omap44xx_timer11_hwmod,
4564         .clk            = "l4_div_ck",
4565         .addr           = omap44xx_timer11_addrs,
4566         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4567 };
4568
4569 /* timer11 slave ports */
4570 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4571         &omap44xx_l4_per__timer11,
4572 };
4573
4574 static struct omap_hwmod omap44xx_timer11_hwmod = {
4575         .name           = "timer11",
4576         .class          = &omap44xx_timer_hwmod_class,
4577         .mpu_irqs       = omap44xx_timer11_irqs,
4578         .main_clk       = "timer11_fck",
4579         .prcm = {
4580                 .omap4 = {
4581                         .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
4582                 },
4583         },
4584         .slaves         = omap44xx_timer11_slaves,
4585         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4586         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4587 };
4588
4589 /*
4590  * 'uart' class
4591  * universal asynchronous receiver/transmitter (uart)
4592  */
4593
4594 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4595         .rev_offs       = 0x0050,
4596         .sysc_offs      = 0x0054,
4597         .syss_offs      = 0x0058,
4598         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4599                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4600                            SYSS_HAS_RESET_STATUS),
4601         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4602                            SIDLE_SMART_WKUP),
4603         .sysc_fields    = &omap_hwmod_sysc_type1,
4604 };
4605
4606 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4607         .name   = "uart",
4608         .sysc   = &omap44xx_uart_sysc,
4609 };
4610
4611 /* uart1 */
4612 static struct omap_hwmod omap44xx_uart1_hwmod;
4613 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4614         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4615         { .irq = -1 }
4616 };
4617
4618 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4619         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4620         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4621         { .dma_req = -1 }
4622 };
4623
4624 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4625         {
4626                 .pa_start       = 0x4806a000,
4627                 .pa_end         = 0x4806a0ff,
4628                 .flags          = ADDR_TYPE_RT
4629         },
4630         { }
4631 };
4632
4633 /* l4_per -> uart1 */
4634 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4635         .master         = &omap44xx_l4_per_hwmod,
4636         .slave          = &omap44xx_uart1_hwmod,
4637         .clk            = "l4_div_ck",
4638         .addr           = omap44xx_uart1_addrs,
4639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4640 };
4641
4642 /* uart1 slave ports */
4643 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4644         &omap44xx_l4_per__uart1,
4645 };
4646
4647 static struct omap_hwmod omap44xx_uart1_hwmod = {
4648         .name           = "uart1",
4649         .class          = &omap44xx_uart_hwmod_class,
4650         .mpu_irqs       = omap44xx_uart1_irqs,
4651         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4652         .main_clk       = "uart1_fck",
4653         .prcm = {
4654                 .omap4 = {
4655                         .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
4656                 },
4657         },
4658         .slaves         = omap44xx_uart1_slaves,
4659         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4660         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4661 };
4662
4663 /* uart2 */
4664 static struct omap_hwmod omap44xx_uart2_hwmod;
4665 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4666         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4667         { .irq = -1 }
4668 };
4669
4670 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4671         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4672         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4673         { .dma_req = -1 }
4674 };
4675
4676 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4677         {
4678                 .pa_start       = 0x4806c000,
4679                 .pa_end         = 0x4806c0ff,
4680                 .flags          = ADDR_TYPE_RT
4681         },
4682         { }
4683 };
4684
4685 /* l4_per -> uart2 */
4686 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4687         .master         = &omap44xx_l4_per_hwmod,
4688         .slave          = &omap44xx_uart2_hwmod,
4689         .clk            = "l4_div_ck",
4690         .addr           = omap44xx_uart2_addrs,
4691         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4692 };
4693
4694 /* uart2 slave ports */
4695 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4696         &omap44xx_l4_per__uart2,
4697 };
4698
4699 static struct omap_hwmod omap44xx_uart2_hwmod = {
4700         .name           = "uart2",
4701         .class          = &omap44xx_uart_hwmod_class,
4702         .mpu_irqs       = omap44xx_uart2_irqs,
4703         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4704         .main_clk       = "uart2_fck",
4705         .prcm = {
4706                 .omap4 = {
4707                         .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
4708                 },
4709         },
4710         .slaves         = omap44xx_uart2_slaves,
4711         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4712         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4713 };
4714
4715 /* uart3 */
4716 static struct omap_hwmod omap44xx_uart3_hwmod;
4717 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4718         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4719         { .irq = -1 }
4720 };
4721
4722 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4723         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4724         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4725         { .dma_req = -1 }
4726 };
4727
4728 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4729         {
4730                 .pa_start       = 0x48020000,
4731                 .pa_end         = 0x480200ff,
4732                 .flags          = ADDR_TYPE_RT
4733         },
4734         { }
4735 };
4736
4737 /* l4_per -> uart3 */
4738 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4739         .master         = &omap44xx_l4_per_hwmod,
4740         .slave          = &omap44xx_uart3_hwmod,
4741         .clk            = "l4_div_ck",
4742         .addr           = omap44xx_uart3_addrs,
4743         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4744 };
4745
4746 /* uart3 slave ports */
4747 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4748         &omap44xx_l4_per__uart3,
4749 };
4750
4751 static struct omap_hwmod omap44xx_uart3_hwmod = {
4752         .name           = "uart3",
4753         .class          = &omap44xx_uart_hwmod_class,
4754         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4755         .mpu_irqs       = omap44xx_uart3_irqs,
4756         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4757         .main_clk       = "uart3_fck",
4758         .prcm = {
4759                 .omap4 = {
4760                         .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
4761                 },
4762         },
4763         .slaves         = omap44xx_uart3_slaves,
4764         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4765         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4766 };
4767
4768 /* uart4 */
4769 static struct omap_hwmod omap44xx_uart4_hwmod;
4770 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4771         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4772         { .irq = -1 }
4773 };
4774
4775 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4776         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4777         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4778         { .dma_req = -1 }
4779 };
4780
4781 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4782         {
4783                 .pa_start       = 0x4806e000,
4784                 .pa_end         = 0x4806e0ff,
4785                 .flags          = ADDR_TYPE_RT
4786         },
4787         { }
4788 };
4789
4790 /* l4_per -> uart4 */
4791 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4792         .master         = &omap44xx_l4_per_hwmod,
4793         .slave          = &omap44xx_uart4_hwmod,
4794         .clk            = "l4_div_ck",
4795         .addr           = omap44xx_uart4_addrs,
4796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4797 };
4798
4799 /* uart4 slave ports */
4800 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
4801         &omap44xx_l4_per__uart4,
4802 };
4803
4804 static struct omap_hwmod omap44xx_uart4_hwmod = {
4805         .name           = "uart4",
4806         .class          = &omap44xx_uart_hwmod_class,
4807         .mpu_irqs       = omap44xx_uart4_irqs,
4808         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
4809         .main_clk       = "uart4_fck",
4810         .prcm = {
4811                 .omap4 = {
4812                         .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
4813                 },
4814         },
4815         .slaves         = omap44xx_uart4_slaves,
4816         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
4817         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4818 };
4819
4820 /*
4821  * 'usb_otg_hs' class
4822  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
4823  */
4824
4825 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
4826         .rev_offs       = 0x0400,
4827         .sysc_offs      = 0x0404,
4828         .syss_offs      = 0x0408,
4829         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4830                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
4831                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4832         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4833                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
4834                            MSTANDBY_SMART),
4835         .sysc_fields    = &omap_hwmod_sysc_type1,
4836 };
4837
4838 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
4839         .name   = "usb_otg_hs",
4840         .sysc   = &omap44xx_usb_otg_hs_sysc,
4841 };
4842
4843 /* usb_otg_hs */
4844 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
4845         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
4846         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
4847         { .irq = -1 }
4848 };
4849
4850 /* usb_otg_hs master ports */
4851 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
4852         &omap44xx_usb_otg_hs__l3_main_2,
4853 };
4854
4855 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
4856         {
4857                 .pa_start       = 0x4a0ab000,
4858                 .pa_end         = 0x4a0ab003,
4859                 .flags          = ADDR_TYPE_RT
4860         },
4861         { }
4862 };
4863
4864 /* l4_cfg -> usb_otg_hs */
4865 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4866         .master         = &omap44xx_l4_cfg_hwmod,
4867         .slave          = &omap44xx_usb_otg_hs_hwmod,
4868         .clk            = "l4_div_ck",
4869         .addr           = omap44xx_usb_otg_hs_addrs,
4870         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4871 };
4872
4873 /* usb_otg_hs slave ports */
4874 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
4875         &omap44xx_l4_cfg__usb_otg_hs,
4876 };
4877
4878 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
4879         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
4880 };
4881
4882 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
4883         .name           = "usb_otg_hs",
4884         .class          = &omap44xx_usb_otg_hs_hwmod_class,
4885         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
4886         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
4887         .main_clk       = "usb_otg_hs_ick",
4888         .prcm = {
4889                 .omap4 = {
4890                         .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
4891                 },
4892         },
4893         .opt_clks       = usb_otg_hs_opt_clks,
4894         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
4895         .slaves         = omap44xx_usb_otg_hs_slaves,
4896         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
4897         .masters        = omap44xx_usb_otg_hs_masters,
4898         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
4899         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4900 };
4901
4902 /*
4903  * 'wd_timer' class
4904  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
4905  * overflow condition
4906  */
4907
4908 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
4909         .rev_offs       = 0x0000,
4910         .sysc_offs      = 0x0010,
4911         .syss_offs      = 0x0014,
4912         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
4913                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4914         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4915                            SIDLE_SMART_WKUP),
4916         .sysc_fields    = &omap_hwmod_sysc_type1,
4917 };
4918
4919 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
4920         .name           = "wd_timer",
4921         .sysc           = &omap44xx_wd_timer_sysc,
4922         .pre_shutdown   = &omap2_wd_timer_disable,
4923 };
4924
4925 /* wd_timer2 */
4926 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
4927 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
4928         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
4929         { .irq = -1 }
4930 };
4931
4932 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
4933         {
4934                 .pa_start       = 0x4a314000,
4935                 .pa_end         = 0x4a31407f,
4936                 .flags          = ADDR_TYPE_RT
4937         },
4938         { }
4939 };
4940
4941 /* l4_wkup -> wd_timer2 */
4942 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4943         .master         = &omap44xx_l4_wkup_hwmod,
4944         .slave          = &omap44xx_wd_timer2_hwmod,
4945         .clk            = "l4_wkup_clk_mux_ck",
4946         .addr           = omap44xx_wd_timer2_addrs,
4947         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4948 };
4949
4950 /* wd_timer2 slave ports */
4951 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
4952         &omap44xx_l4_wkup__wd_timer2,
4953 };
4954
4955 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
4956         .name           = "wd_timer2",
4957         .class          = &omap44xx_wd_timer_hwmod_class,
4958         .mpu_irqs       = omap44xx_wd_timer2_irqs,
4959         .main_clk       = "wd_timer2_fck",
4960         .prcm = {
4961                 .omap4 = {
4962                         .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
4963                 },
4964         },
4965         .slaves         = omap44xx_wd_timer2_slaves,
4966         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
4967         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
4968 };
4969
4970 /* wd_timer3 */
4971 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
4972 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
4973         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
4974         { .irq = -1 }
4975 };
4976
4977 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4978         {
4979                 .pa_start       = 0x40130000,
4980                 .pa_end         = 0x4013007f,
4981                 .flags          = ADDR_TYPE_RT
4982         },
4983         { }
4984 };
4985
4986 /* l4_abe -> wd_timer3 */
4987 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4988         .master         = &omap44xx_l4_abe_hwmod,
4989         .slave          = &omap44xx_wd_timer3_hwmod,
4990         .clk            = "ocp_abe_iclk",
4991         .addr           = omap44xx_wd_timer3_addrs,
4992         .user           = OCP_USER_MPU,
4993 };
4994
4995 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4996         {
4997                 .pa_start       = 0x49030000,
4998                 .pa_end         = 0x4903007f,
4999                 .flags          = ADDR_TYPE_RT
5000         },
5001         { }
5002 };
5003
5004 /* l4_abe -> wd_timer3 (dma) */
5005 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5006         .master         = &omap44xx_l4_abe_hwmod,
5007         .slave          = &omap44xx_wd_timer3_hwmod,
5008         .clk            = "ocp_abe_iclk",
5009         .addr           = omap44xx_wd_timer3_dma_addrs,
5010         .user           = OCP_USER_SDMA,
5011 };
5012
5013 /* wd_timer3 slave ports */
5014 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5015         &omap44xx_l4_abe__wd_timer3,
5016         &omap44xx_l4_abe__wd_timer3_dma,
5017 };
5018
5019 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5020         .name           = "wd_timer3",
5021         .class          = &omap44xx_wd_timer_hwmod_class,
5022         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5023         .main_clk       = "wd_timer3_fck",
5024         .prcm = {
5025                 .omap4 = {
5026                         .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
5027                 },
5028         },
5029         .slaves         = omap44xx_wd_timer3_slaves,
5030         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5031         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
5032 };
5033
5034 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5035
5036         /* dmm class */
5037         &omap44xx_dmm_hwmod,
5038
5039         /* emif_fw class */
5040         &omap44xx_emif_fw_hwmod,
5041
5042         /* l3 class */
5043         &omap44xx_l3_instr_hwmod,
5044         &omap44xx_l3_main_1_hwmod,
5045         &omap44xx_l3_main_2_hwmod,
5046         &omap44xx_l3_main_3_hwmod,
5047
5048         /* l4 class */
5049         &omap44xx_l4_abe_hwmod,
5050         &omap44xx_l4_cfg_hwmod,
5051         &omap44xx_l4_per_hwmod,
5052         &omap44xx_l4_wkup_hwmod,
5053
5054         /* mpu_bus class */
5055         &omap44xx_mpu_private_hwmod,
5056
5057         /* aess class */
5058 /*      &omap44xx_aess_hwmod, */
5059
5060         /* bandgap class */
5061         &omap44xx_bandgap_hwmod,
5062
5063         /* counter class */
5064 /*      &omap44xx_counter_32k_hwmod, */
5065
5066         /* dma class */
5067         &omap44xx_dma_system_hwmod,
5068
5069         /* dmic class */
5070         &omap44xx_dmic_hwmod,
5071
5072         /* dsp class */
5073         &omap44xx_dsp_hwmod,
5074         &omap44xx_dsp_c0_hwmod,
5075
5076         /* dss class */
5077         &omap44xx_dss_hwmod,
5078         &omap44xx_dss_dispc_hwmod,
5079         &omap44xx_dss_dsi1_hwmod,
5080         &omap44xx_dss_dsi2_hwmod,
5081         &omap44xx_dss_hdmi_hwmod,
5082         &omap44xx_dss_rfbi_hwmod,
5083         &omap44xx_dss_venc_hwmod,
5084
5085         /* gpio class */
5086         &omap44xx_gpio1_hwmod,
5087         &omap44xx_gpio2_hwmod,
5088         &omap44xx_gpio3_hwmod,
5089         &omap44xx_gpio4_hwmod,
5090         &omap44xx_gpio5_hwmod,
5091         &omap44xx_gpio6_hwmod,
5092
5093         /* hsi class */
5094 /*      &omap44xx_hsi_hwmod, */
5095
5096         /* i2c class */
5097         &omap44xx_i2c1_hwmod,
5098         &omap44xx_i2c2_hwmod,
5099         &omap44xx_i2c3_hwmod,
5100         &omap44xx_i2c4_hwmod,
5101
5102         /* ipu class */
5103         &omap44xx_ipu_hwmod,
5104         &omap44xx_ipu_c0_hwmod,
5105         &omap44xx_ipu_c1_hwmod,
5106
5107         /* iss class */
5108 /*      &omap44xx_iss_hwmod, */
5109
5110         /* iva class */
5111         &omap44xx_iva_hwmod,
5112         &omap44xx_iva_seq0_hwmod,
5113         &omap44xx_iva_seq1_hwmod,
5114
5115         /* kbd class */
5116         &omap44xx_kbd_hwmod,
5117
5118         /* mailbox class */
5119         &omap44xx_mailbox_hwmod,
5120
5121         /* mcbsp class */
5122         &omap44xx_mcbsp1_hwmod,
5123         &omap44xx_mcbsp2_hwmod,
5124         &omap44xx_mcbsp3_hwmod,
5125         &omap44xx_mcbsp4_hwmod,
5126
5127         /* mcpdm class */
5128 /*      &omap44xx_mcpdm_hwmod, */
5129
5130         /* mcspi class */
5131         &omap44xx_mcspi1_hwmod,
5132         &omap44xx_mcspi2_hwmod,
5133         &omap44xx_mcspi3_hwmod,
5134         &omap44xx_mcspi4_hwmod,
5135
5136         /* mmc class */
5137         &omap44xx_mmc1_hwmod,
5138         &omap44xx_mmc2_hwmod,
5139         &omap44xx_mmc3_hwmod,
5140         &omap44xx_mmc4_hwmod,
5141         &omap44xx_mmc5_hwmod,
5142
5143         /* mpu class */
5144         &omap44xx_mpu_hwmod,
5145
5146         /* smartreflex class */
5147         &omap44xx_smartreflex_core_hwmod,
5148         &omap44xx_smartreflex_iva_hwmod,
5149         &omap44xx_smartreflex_mpu_hwmod,
5150
5151         /* spinlock class */
5152         &omap44xx_spinlock_hwmod,
5153
5154         /* timer class */
5155         &omap44xx_timer1_hwmod,
5156         &omap44xx_timer2_hwmod,
5157         &omap44xx_timer3_hwmod,
5158         &omap44xx_timer4_hwmod,
5159         &omap44xx_timer5_hwmod,
5160         &omap44xx_timer6_hwmod,
5161         &omap44xx_timer7_hwmod,
5162         &omap44xx_timer8_hwmod,
5163         &omap44xx_timer9_hwmod,
5164         &omap44xx_timer10_hwmod,
5165         &omap44xx_timer11_hwmod,
5166
5167         /* uart class */
5168         &omap44xx_uart1_hwmod,
5169         &omap44xx_uart2_hwmod,
5170         &omap44xx_uart3_hwmod,
5171         &omap44xx_uart4_hwmod,
5172
5173         /* usb_otg_hs class */
5174         &omap44xx_usb_otg_hs_hwmod,
5175
5176         /* wd_timer class */
5177         &omap44xx_wd_timer2_hwmod,
5178         &omap44xx_wd_timer3_hwmod,
5179
5180         NULL,
5181 };
5182
5183 int __init omap44xx_hwmod_init(void)
5184 {
5185         return omap_hwmod_register(omap44xx_hwmods);
5186 }
5187