arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/dmtimer.h>
  32 #include <plat/common.h>
  33
  34 #include "omap_hwmod_common_data.h"
  35
  36 #include "smartreflex.h"
  37 #include "cm1_44xx.h"
  38 #include "cm2_44xx.h"
  39 #include "prm44xx.h"
  40 #include "prm-regbits-44xx.h"
  41 #include "wd_timer.h"
  42
  43 /* Base offset for all OMAP4 interrupts external to MPUSS */
  44 #define OMAP44XX_IRQ_GIC_START  32
  45
  46 /* Base offset for all OMAP4 dma requests */
  47 #define OMAP44XX_DMA_REQ_START  1
  48
  49 /* Backward references (IPs with Bus Master capability) */
  50 static struct omap_hwmod omap44xx_aess_hwmod;
  51 static struct omap_hwmod omap44xx_dma_system_hwmod;
  52 static struct omap_hwmod omap44xx_dmm_hwmod;
  53 static struct omap_hwmod omap44xx_dsp_hwmod;
  54 static struct omap_hwmod omap44xx_dss_hwmod;
  55 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  56 static struct omap_hwmod omap44xx_hsi_hwmod;
  57 static struct omap_hwmod omap44xx_ipu_hwmod;
  58 static struct omap_hwmod omap44xx_iss_hwmod;
  59 static struct omap_hwmod omap44xx_iva_hwmod;
  60 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  61 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  62 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  63 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  64 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  65 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  66 static struct omap_hwmod omap44xx_l4_per_hwmod;
  67 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  68 static struct omap_hwmod omap44xx_mmc1_hwmod;
  69 static struct omap_hwmod omap44xx_mmc2_hwmod;
  70 static struct omap_hwmod omap44xx_mpu_hwmod;
  71 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  72 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  73 static struct omap_hwmod omap44xx_usb_host_hs_hwmod;
  74 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod;
  75
  76 /*
  77  * Interconnects omap_hwmod structures
  78  * hwmods that compose the global OMAP interconnect
  79  */
  80
  81 /*
  82  * 'dmm' class
  83  * instance(s): dmm
  84  */
  85 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  86         .name   = "dmm",
  87 };
  88
  89 /* dmm */
  90 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  91         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  92         { .irq = -1 }
  93 };
  94
  95 /* l3_main_1 -> dmm */
  96 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  97         .master         = &omap44xx_l3_main_1_hwmod,
  98         .slave          = &omap44xx_dmm_hwmod,
  99         .clk            = "l3_div_ck",
 100         .user           = OCP_USER_SDMA,
 101 };
 102
 103 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 104         {
 105                 .pa_start       = 0x4e000000,
 106                 .pa_end         = 0x4e0007ff,
 107                 .flags          = ADDR_TYPE_RT
 108         },
 109         { }
 110 };
 111
 112 /* mpu -> dmm */
 113 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 114         .master         = &omap44xx_mpu_hwmod,
 115         .slave          = &omap44xx_dmm_hwmod,
 116         .clk            = "l3_div_ck",
 117         .addr           = omap44xx_dmm_addrs,
 118         .user           = OCP_USER_MPU,
 119 };
 120
 121 /* dmm slave ports */
 122 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 123         &omap44xx_l3_main_1__dmm,
 124         &omap44xx_mpu__dmm,
 125 };
 126
 127 static struct omap_hwmod omap44xx_dmm_hwmod = {
 128         .name           = "dmm",
 129         .class          = &omap44xx_dmm_hwmod_class,
 130         .clkdm_name     = "l3_emif_clkdm",
 131         .prcm = {
 132                 .omap4 = {
 133                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 134                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 135                 },
 136         },
 137         .slaves         = omap44xx_dmm_slaves,
 138         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 139         .mpu_irqs       = omap44xx_dmm_irqs,
 140 };
 141
 142 /*
 143  * 'emif_fw' class
 144  * instance(s): emif_fw
 145  */
 146 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 147         .name   = "emif_fw",
 148 };
 149
 150 /* emif_fw */
 151 /* dmm -> emif_fw */
 152 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 153         .master         = &omap44xx_dmm_hwmod,
 154         .slave          = &omap44xx_emif_fw_hwmod,
 155         .clk            = "l3_div_ck",
 156         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 157 };
 158
 159 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 160         {
 161                 .pa_start       = 0x4a20c000,
 162                 .pa_end         = 0x4a20c0ff,
 163                 .flags          = ADDR_TYPE_RT
 164         },
 165         { }
 166 };
 167
 168 /* l4_cfg -> emif_fw */
 169 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 170         .master         = &omap44xx_l4_cfg_hwmod,
 171         .slave          = &omap44xx_emif_fw_hwmod,
 172         .clk            = "l4_div_ck",
 173         .addr           = omap44xx_emif_fw_addrs,
 174         .user           = OCP_USER_MPU,
 175 };
 176
 177 /* emif_fw slave ports */
 178 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 179         &omap44xx_dmm__emif_fw,
 180         &omap44xx_l4_cfg__emif_fw,
 181 };
 182
 183 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 184         .name           = "emif_fw",
 185         .class          = &omap44xx_emif_fw_hwmod_class,
 186         .clkdm_name     = "l3_emif_clkdm",
 187         .prcm = {
 188                 .omap4 = {
 189                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 190                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 191                 },
 192         },
 193         .slaves         = omap44xx_emif_fw_slaves,
 194         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 195 };
 196
 197 /*
 198  * 'l3' class
 199  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 200  */
 201 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 202         .name   = "l3",
 203 };
 204
 205 /* l3_instr */
 206 /* iva -> l3_instr */
 207 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 208         .master         = &omap44xx_iva_hwmod,
 209         .slave          = &omap44xx_l3_instr_hwmod,
 210         .clk            = "l3_div_ck",
 211         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 212 };
 213
 214 /* l3_main_3 -> l3_instr */
 215 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 216         .master         = &omap44xx_l3_main_3_hwmod,
 217         .slave          = &omap44xx_l3_instr_hwmod,
 218         .clk            = "l3_div_ck",
 219         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 220 };
 221
 222 /* l3_instr slave ports */
 223 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 224         &omap44xx_iva__l3_instr,
 225         &omap44xx_l3_main_3__l3_instr,
 226 };
 227
 228 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 229         .name           = "l3_instr",
 230         .class          = &omap44xx_l3_hwmod_class,
 231         .clkdm_name     = "l3_instr_clkdm",
 232         .prcm = {
 233                 .omap4 = {
 234                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 235                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 236                         .modulemode   = MODULEMODE_HWCTRL,
 237                 },
 238         },
 239         .slaves         = omap44xx_l3_instr_slaves,
 240         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 241 };
 242
 243 /* l3_main_1 */
 244 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 245         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 246         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 247         { .irq = -1 }
 248 };
 249
 250 /* dsp -> l3_main_1 */
 251 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 252         .master         = &omap44xx_dsp_hwmod,
 253         .slave          = &omap44xx_l3_main_1_hwmod,
 254         .clk            = "l3_div_ck",
 255         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 256 };
 257
 258 /* dss -> l3_main_1 */
 259 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 260         .master         = &omap44xx_dss_hwmod,
 261         .slave          = &omap44xx_l3_main_1_hwmod,
 262         .clk            = "l3_div_ck",
 263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 264 };
 265
 266 /* l3_main_2 -> l3_main_1 */
 267 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 268         .master         = &omap44xx_l3_main_2_hwmod,
 269         .slave          = &omap44xx_l3_main_1_hwmod,
 270         .clk            = "l3_div_ck",
 271         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 272 };
 273
 274 /* l4_cfg -> l3_main_1 */
 275 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 276         .master         = &omap44xx_l4_cfg_hwmod,
 277         .slave          = &omap44xx_l3_main_1_hwmod,
 278         .clk            = "l4_div_ck",
 279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 280 };
 281
 282 /* mmc1 -> l3_main_1 */
 283 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 284         .master         = &omap44xx_mmc1_hwmod,
 285         .slave          = &omap44xx_l3_main_1_hwmod,
 286         .clk            = "l3_div_ck",
 287         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 288 };
 289
 290 /* mmc2 -> l3_main_1 */
 291 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 292         .master         = &omap44xx_mmc2_hwmod,
 293         .slave          = &omap44xx_l3_main_1_hwmod,
 294         .clk            = "l3_div_ck",
 295         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 296 };
 297
 298 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 299         {
 300                 .pa_start       = 0x44000000,
 301                 .pa_end         = 0x44000fff,
 302                 .flags          = ADDR_TYPE_RT
 303         },
 304         { }
 305 };
 306
 307 /* mpu -> l3_main_1 */
 308 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 309         .master         = &omap44xx_mpu_hwmod,
 310         .slave          = &omap44xx_l3_main_1_hwmod,
 311         .clk            = "l3_div_ck",
 312         .addr           = omap44xx_l3_main_1_addrs,
 313         .user           = OCP_USER_MPU,
 314 };
 315
 316 /* l3_main_1 slave ports */
 317 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 318         &omap44xx_dsp__l3_main_1,
 319         &omap44xx_dss__l3_main_1,
 320         &omap44xx_l3_main_2__l3_main_1,
 321         &omap44xx_l4_cfg__l3_main_1,
 322         &omap44xx_mmc1__l3_main_1,
 323         &omap44xx_mmc2__l3_main_1,
 324         &omap44xx_mpu__l3_main_1,
 325 };
 326
 327 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 328         .name           = "l3_main_1",
 329         .class          = &omap44xx_l3_hwmod_class,
 330         .clkdm_name     = "l3_1_clkdm",
 331         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 332         .prcm = {
 333                 .omap4 = {
 334                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 335                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 336                 },
 337         },
 338         .slaves         = omap44xx_l3_main_1_slaves,
 339         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 340 };
 341
 342 /* l3_main_2 */
 343 /* dma_system -> l3_main_2 */
 344 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 345         .master         = &omap44xx_dma_system_hwmod,
 346         .slave          = &omap44xx_l3_main_2_hwmod,
 347         .clk            = "l3_div_ck",
 348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 349 };
 350
 351 /* hsi -> l3_main_2 */
 352 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 353         .master         = &omap44xx_hsi_hwmod,
 354         .slave          = &omap44xx_l3_main_2_hwmod,
 355         .clk            = "l3_div_ck",
 356         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 357 };
 358
 359 /* ipu -> l3_main_2 */
 360 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 361         .master         = &omap44xx_ipu_hwmod,
 362         .slave          = &omap44xx_l3_main_2_hwmod,
 363         .clk            = "l3_div_ck",
 364         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 365 };
 366
 367 /* iss -> l3_main_2 */
 368 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 369         .master         = &omap44xx_iss_hwmod,
 370         .slave          = &omap44xx_l3_main_2_hwmod,
 371         .clk            = "l3_div_ck",
 372         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 373 };
 374
 375 /* iva -> l3_main_2 */
 376 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 377         .master         = &omap44xx_iva_hwmod,
 378         .slave          = &omap44xx_l3_main_2_hwmod,
 379         .clk            = "l3_div_ck",
 380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 381 };
 382
 383 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 384         {
 385                 .pa_start       = 0x44800000,
 386                 .pa_end         = 0x44801fff,
 387                 .flags          = ADDR_TYPE_RT
 388         },
 389         { }
 390 };
 391
 392 /* l3_main_1 -> l3_main_2 */
 393 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 394         .master         = &omap44xx_l3_main_1_hwmod,
 395         .slave          = &omap44xx_l3_main_2_hwmod,
 396         .clk            = "l3_div_ck",
 397         .addr           = omap44xx_l3_main_2_addrs,
 398         .user           = OCP_USER_MPU,
 399 };
 400
 401 /* l4_cfg -> l3_main_2 */
 402 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 403         .master         = &omap44xx_l4_cfg_hwmod,
 404         .slave          = &omap44xx_l3_main_2_hwmod,
 405         .clk            = "l4_div_ck",
 406         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 407 };
 408
 409 /* usb_otg_hs -> l3_main_2 */
 410 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 411         .master         = &omap44xx_usb_otg_hs_hwmod,
 412         .slave          = &omap44xx_l3_main_2_hwmod,
 413         .clk            = "l3_div_ck",
 414         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 415 };
 416
 417 /* l3_main_2 slave ports */
 418 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 419         &omap44xx_dma_system__l3_main_2,
 420         &omap44xx_hsi__l3_main_2,
 421         &omap44xx_ipu__l3_main_2,
 422         &omap44xx_iss__l3_main_2,
 423         &omap44xx_iva__l3_main_2,
 424         &omap44xx_l3_main_1__l3_main_2,
 425         &omap44xx_l4_cfg__l3_main_2,
 426         &omap44xx_usb_otg_hs__l3_main_2,
 427 };
 428
 429 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 430         .name           = "l3_main_2",
 431         .class          = &omap44xx_l3_hwmod_class,
 432         .clkdm_name     = "l3_2_clkdm",
 433         .prcm = {
 434                 .omap4 = {
 435                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 436                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 437                 },
 438         },
 439         .slaves         = omap44xx_l3_main_2_slaves,
 440         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 441 };
 442
 443 /* l3_main_3 */
 444 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 445         {
 446                 .pa_start       = 0x45000000,
 447                 .pa_end         = 0x45000fff,
 448                 .flags          = ADDR_TYPE_RT
 449         },
 450         { }
 451 };
 452
 453 /* l3_main_1 -> l3_main_3 */
 454 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 455         .master         = &omap44xx_l3_main_1_hwmod,
 456         .slave          = &omap44xx_l3_main_3_hwmod,
 457         .clk            = "l3_div_ck",
 458         .addr           = omap44xx_l3_main_3_addrs,
 459         .user           = OCP_USER_MPU,
 460 };
 461
 462 /* l3_main_2 -> l3_main_3 */
 463 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 464         .master         = &omap44xx_l3_main_2_hwmod,
 465         .slave          = &omap44xx_l3_main_3_hwmod,
 466         .clk            = "l3_div_ck",
 467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 468 };
 469
 470 /* l4_cfg -> l3_main_3 */
 471 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 472         .master         = &omap44xx_l4_cfg_hwmod,
 473         .slave          = &omap44xx_l3_main_3_hwmod,
 474         .clk            = "l4_div_ck",
 475         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 476 };
 477
 478 /* l3_main_3 slave ports */
 479 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 480         &omap44xx_l3_main_1__l3_main_3,
 481         &omap44xx_l3_main_2__l3_main_3,
 482         &omap44xx_l4_cfg__l3_main_3,
 483 };
 484
 485 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 486         .name           = "l3_main_3",
 487         .class          = &omap44xx_l3_hwmod_class,
 488         .clkdm_name     = "l3_instr_clkdm",
 489         .prcm = {
 490                 .omap4 = {
 491                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 492                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 493                         .modulemode   = MODULEMODE_HWCTRL,
 494                 },
 495         },
 496         .slaves         = omap44xx_l3_main_3_slaves,
 497         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 498 };
 499
 500 /*
 501  * 'l4' class
 502  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 503  */
 504 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 505         .name   = "l4",
 506 };
 507
 508 /* l4_abe */
 509 /* aess -> l4_abe */
 510 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 511         .master         = &omap44xx_aess_hwmod,
 512         .slave          = &omap44xx_l4_abe_hwmod,
 513         .clk            = "ocp_abe_iclk",
 514         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 515 };
 516
 517 /* dsp -> l4_abe */
 518 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 519         .master         = &omap44xx_dsp_hwmod,
 520         .slave          = &omap44xx_l4_abe_hwmod,
 521         .clk            = "ocp_abe_iclk",
 522         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 523 };
 524
 525 /* l3_main_1 -> l4_abe */
 526 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 527         .master         = &omap44xx_l3_main_1_hwmod,
 528         .slave          = &omap44xx_l4_abe_hwmod,
 529         .clk            = "l3_div_ck",
 530         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 531 };
 532
 533 /* mpu -> l4_abe */
 534 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 535         .master         = &omap44xx_mpu_hwmod,
 536         .slave          = &omap44xx_l4_abe_hwmod,
 537         .clk            = "ocp_abe_iclk",
 538         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 539 };
 540
 541 /* l4_abe slave ports */
 542 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 543         &omap44xx_aess__l4_abe,
 544         &omap44xx_dsp__l4_abe,
 545         &omap44xx_l3_main_1__l4_abe,
 546         &omap44xx_mpu__l4_abe,
 547 };
 548
 549 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 550         .name           = "l4_abe",
 551         .class          = &omap44xx_l4_hwmod_class,
 552         .clkdm_name     = "abe_clkdm",
 553         .prcm = {
 554                 .omap4 = {
 555                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 556                 },
 557         },
 558         .slaves         = omap44xx_l4_abe_slaves,
 559         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 560 };
 561
 562 /* l4_cfg */
 563 /* l3_main_1 -> l4_cfg */
 564 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 565         .master         = &omap44xx_l3_main_1_hwmod,
 566         .slave          = &omap44xx_l4_cfg_hwmod,
 567         .clk            = "l3_div_ck",
 568         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 569 };
 570
 571 /* l4_cfg slave ports */
 572 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 573         &omap44xx_l3_main_1__l4_cfg,
 574 };
 575
 576 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 577         .name           = "l4_cfg",
 578         .class          = &omap44xx_l4_hwmod_class,
 579         .clkdm_name     = "l4_cfg_clkdm",
 580         .prcm = {
 581                 .omap4 = {
 582                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 583                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 584                 },
 585         },
 586         .slaves         = omap44xx_l4_cfg_slaves,
 587         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 588 };
 589
 590 /* l4_per */
 591 /* l3_main_2 -> l4_per */
 592 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 593         .master         = &omap44xx_l3_main_2_hwmod,
 594         .slave          = &omap44xx_l4_per_hwmod,
 595         .clk            = "l3_div_ck",
 596         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 597 };
 598
 599 /* l4_per slave ports */
 600 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 601         &omap44xx_l3_main_2__l4_per,
 602 };
 603
 604 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 605         .name           = "l4_per",
 606         .class          = &omap44xx_l4_hwmod_class,
 607         .clkdm_name     = "l4_per_clkdm",
 608         .prcm = {
 609                 .omap4 = {
 610                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 611                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 612                 },
 613         },
 614         .slaves         = omap44xx_l4_per_slaves,
 615         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 616 };
 617
 618 /* l4_wkup */
 619 /* l4_cfg -> l4_wkup */
 620 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 621         .master         = &omap44xx_l4_cfg_hwmod,
 622         .slave          = &omap44xx_l4_wkup_hwmod,
 623         .clk            = "l4_div_ck",
 624         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 625 };
 626
 627 /* l4_wkup slave ports */
 628 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 629         &omap44xx_l4_cfg__l4_wkup,
 630 };
 631
 632 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 633         .name           = "l4_wkup",
 634         .class          = &omap44xx_l4_hwmod_class,
 635         .clkdm_name     = "l4_wkup_clkdm",
 636         .prcm = {
 637                 .omap4 = {
 638                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 639                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 640                 },
 641         },
 642         .slaves         = omap44xx_l4_wkup_slaves,
 643         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 644 };
 645
 646 /*
 647  * 'mpu_bus' class
 648  * instance(s): mpu_private
 649  */
 650 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 651         .name   = "mpu_bus",
 652 };
 653
 654 /* mpu_private */
 655 /* mpu -> mpu_private */
 656 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 657         .master         = &omap44xx_mpu_hwmod,
 658         .slave          = &omap44xx_mpu_private_hwmod,
 659         .clk            = "l3_div_ck",
 660         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 661 };
 662
 663 /* mpu_private slave ports */
 664 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 665         &omap44xx_mpu__mpu_private,
 666 };
 667
 668 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 669         .name           = "mpu_private",
 670         .class          = &omap44xx_mpu_bus_hwmod_class,
 671         .clkdm_name     = "mpuss_clkdm",
 672         .slaves         = omap44xx_mpu_private_slaves,
 673         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 674 };
 675
 676 /*
 677  * Modules omap_hwmod structures
 678  *
 679  * The following IPs are excluded for the moment because:
 680  * - They do not need an explicit SW control using omap_hwmod API.
 681  * - They still need to be validated with the driver
 682  *   properly adapted to omap_hwmod / omap_device
 683  *
 684  *  c2c
 685  *  c2c_target_fw
 686  *  cm_core
 687  *  cm_core_aon
 688  *  ctrl_module_core
 689  *  ctrl_module_pad_core
 690  *  ctrl_module_pad_wkup
 691  *  ctrl_module_wkup
 692  *  debugss
 693  *  efuse_ctrl_cust
 694  *  efuse_ctrl_std
 695  *  elm
 696  *  emif1
 697  *  emif2
 698  *  fdif
 699  *  gpmc
 700  *  gpu
 701  *  hdq1w
 702  *  mcasp
 703  *  mpu_c0
 704  *  mpu_c1
 705  *  ocmc_ram
 706  *  ocp2scp_usb_phy
 707  *  ocp_wp_noc
 708  *  prcm_mpu
 709  *  prm
 710  *  scrm
 711  *  sl2if
 712  *  slimbus1
 713  *  slimbus2
 714  *  usb_host_fs
 715  *  usb_host_hs
 716  *  usb_phy_cm
 717  *  usb_tll_hs
 718  *  usim
 719  */
 720
 721 /*
 722  * 'aess' class
 723  * audio engine sub system
 724  */
 725
 726 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 727         .rev_offs       = 0x0000,
 728         .sysc_offs      = 0x0010,
 729         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 730         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 731                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 732                            MSTANDBY_SMART_WKUP),
 733         .sysc_fields    = &omap_hwmod_sysc_type2,
 734 };
 735
 736 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 737         .name   = "aess",
 738         .sysc   = &omap44xx_aess_sysc,
 739 };
 740
 741 /* aess */
 742 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 743         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 744         { .irq = -1 }
 745 };
 746
 747 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 748         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 749         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 750         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 751         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 752         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 753         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 754         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 755         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 756         { .dma_req = -1 }
 757 };
 758
 759 /* aess master ports */
 760 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 761         &omap44xx_aess__l4_abe,
 762 };
 763
 764 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 765         {
 766                 .pa_start       = 0x401f1000,
 767                 .pa_end         = 0x401f13ff,
 768                 .flags          = ADDR_TYPE_RT
 769         },
 770         { }
 771 };
 772
 773 /* l4_abe -> aess */
 774 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 775         .master         = &omap44xx_l4_abe_hwmod,
 776         .slave          = &omap44xx_aess_hwmod,
 777         .clk            = "ocp_abe_iclk",
 778         .addr           = omap44xx_aess_addrs,
 779         .user           = OCP_USER_MPU,
 780 };
 781
 782 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 783         {
 784                 .pa_start       = 0x490f1000,
 785                 .pa_end         = 0x490f13ff,
 786                 .flags          = ADDR_TYPE_RT
 787         },
 788         { }
 789 };
 790
 791 /* l4_abe -> aess (dma) */
 792 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 793         .master         = &omap44xx_l4_abe_hwmod,
 794         .slave          = &omap44xx_aess_hwmod,
 795         .clk            = "ocp_abe_iclk",
 796         .addr           = omap44xx_aess_dma_addrs,
 797         .user           = OCP_USER_SDMA,
 798 };
 799
 800 /* aess slave ports */
 801 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 802         &omap44xx_l4_abe__aess,
 803         &omap44xx_l4_abe__aess_dma,
 804 };
 805
 806 static struct omap_hwmod omap44xx_aess_hwmod = {
 807         .name           = "aess",
 808         .class          = &omap44xx_aess_hwmod_class,
 809         .clkdm_name     = "abe_clkdm",
 810         .mpu_irqs       = omap44xx_aess_irqs,
 811         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 812         .main_clk       = "aess_fck",
 813         .prcm = {
 814                 .omap4 = {
 815                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 816                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 817                         .modulemode   = MODULEMODE_SWCTRL,
 818                 },
 819         },
 820         .slaves         = omap44xx_aess_slaves,
 821         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 822         .masters        = omap44xx_aess_masters,
 823         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 824 };
 825
 826 /*
 827  * 'bandgap' class
 828  * bangap reference for ldo regulators
 829  */
 830
 831 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 832         .name   = "bandgap",
 833 };
 834
 835 /* bandgap */
 836 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 837         { .role = "fclk", .clk = "bandgap_fclk" },
 838 };
 839
 840 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 841         .name           = "bandgap",
 842         .class          = &omap44xx_bandgap_hwmod_class,
 843         .clkdm_name     = "l4_wkup_clkdm",
 844         .prcm = {
 845                 .omap4 = {
 846                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 847                 },
 848         },
 849         .opt_clks       = bandgap_opt_clks,
 850         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 851 };
 852
 853 /*
 854  * 'counter' class
 855  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 856  */
 857
 858 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 859         .rev_offs       = 0x0000,
 860         .sysc_offs      = 0x0004,
 861         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 862         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 863                            SIDLE_SMART_WKUP),
 864         .sysc_fields    = &omap_hwmod_sysc_type1,
 865 };
 866
 867 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 868         .name   = "counter",
 869         .sysc   = &omap44xx_counter_sysc,
 870 };
 871
 872 /* counter_32k */
 873 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 874 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 875         {
 876                 .pa_start       = 0x4a304000,
 877                 .pa_end         = 0x4a30401f,
 878                 .flags          = ADDR_TYPE_RT
 879         },
 880         { }
 881 };
 882
 883 /* l4_wkup -> counter_32k */
 884 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 885         .master         = &omap44xx_l4_wkup_hwmod,
 886         .slave          = &omap44xx_counter_32k_hwmod,
 887         .clk            = "l4_wkup_clk_mux_ck",
 888         .addr           = omap44xx_counter_32k_addrs,
 889         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 890 };
 891
 892 /* counter_32k slave ports */
 893 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 894         &omap44xx_l4_wkup__counter_32k,
 895 };
 896
 897 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 898         .name           = "counter_32k",
 899         .class          = &omap44xx_counter_hwmod_class,
 900         .clkdm_name     = "l4_wkup_clkdm",
 901         .flags          = HWMOD_SWSUP_SIDLE,
 902         .main_clk       = "sys_32k_ck",
 903         .prcm = {
 904                 .omap4 = {
 905                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 906                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 907                 },
 908         },
 909         .slaves         = omap44xx_counter_32k_slaves,
 910         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 911 };
 912
 913 /*
 914  * 'dma' class
 915  * dma controller for data exchange between memory to memory (i.e. internal or
 916  * external memory) and gp peripherals to memory or memory to gp peripherals
 917  */
 918
 919 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 920         .rev_offs       = 0x0000,
 921         .sysc_offs      = 0x002c,
 922         .syss_offs      = 0x0028,
 923         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 924                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 925                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 926                            SYSS_HAS_RESET_STATUS),
 927         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 928                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 929         .sysc_fields    = &omap_hwmod_sysc_type1,
 930 };
 931
 932 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 933         .name   = "dma",
 934         .sysc   = &omap44xx_dma_sysc,
 935 };
 936
 937 /* dma dev_attr */
 938 static struct omap_dma_dev_attr dma_dev_attr = {
 939         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 940                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 941         .lch_count      = 32,
 942 };
 943
 944 /* dma_system */
 945 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 946         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 947         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 948         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 949         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 950         { .irq = -1 }
 951 };
 952
 953 /* dma_system master ports */
 954 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 955         &omap44xx_dma_system__l3_main_2,
 956 };
 957
 958 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 959         {
 960                 .pa_start       = 0x4a056000,
 961                 .pa_end         = 0x4a056fff,
 962                 .flags          = ADDR_TYPE_RT
 963         },
 964         { }
 965 };
 966
 967 /* l4_cfg -> dma_system */
 968 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 969         .master         = &omap44xx_l4_cfg_hwmod,
 970         .slave          = &omap44xx_dma_system_hwmod,
 971         .clk            = "l4_div_ck",
 972         .addr           = omap44xx_dma_system_addrs,
 973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 974 };
 975
 976 /* dma_system slave ports */
 977 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 978         &omap44xx_l4_cfg__dma_system,
 979 };
 980
 981 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 982         .name           = "dma_system",
 983         .class          = &omap44xx_dma_hwmod_class,
 984         .clkdm_name     = "l3_dma_clkdm",
 985         .mpu_irqs       = omap44xx_dma_system_irqs,
 986         .main_clk       = "l3_div_ck",
 987         .prcm = {
 988                 .omap4 = {
 989                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 990                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 991                 },
 992         },
 993         .dev_attr       = &dma_dev_attr,
 994         .slaves         = omap44xx_dma_system_slaves,
 995         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 996         .masters        = omap44xx_dma_system_masters,
 997         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 998 };
 999
1000 /*
1001  * 'dmic' class
1002  * digital microphone controller
1003  */
1004
1005 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1006         .rev_offs       = 0x0000,
1007         .sysc_offs      = 0x0010,
1008         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1009                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1010         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1011                            SIDLE_SMART_WKUP),
1012         .sysc_fields    = &omap_hwmod_sysc_type2,
1013 };
1014
1015 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1016         .name   = "dmic",
1017         .sysc   = &omap44xx_dmic_sysc,
1018 };
1019
1020 /* dmic */
1021 static struct omap_hwmod omap44xx_dmic_hwmod;
1022 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1023         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1024         { .irq = -1 }
1025 };
1026
1027 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1028         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1029         { .dma_req = -1 }
1030 };
1031
1032 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033         {
1034                 .name           = "mpu",
1035                 .pa_start       = 0x4012e000,
1036                 .pa_end         = 0x4012e07f,
1037                 .flags          = ADDR_TYPE_RT
1038         },
1039         { }
1040 };
1041
1042 /* l4_abe -> dmic */
1043 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1044         .master         = &omap44xx_l4_abe_hwmod,
1045         .slave          = &omap44xx_dmic_hwmod,
1046         .clk            = "ocp_abe_iclk",
1047         .addr           = omap44xx_dmic_addrs,
1048         .user           = OCP_USER_MPU,
1049 };
1050
1051 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1052         {
1053                 .name           = "dma",
1054                 .pa_start       = 0x4902e000,
1055                 .pa_end         = 0x4902e07f,
1056                 .flags          = ADDR_TYPE_RT
1057         },
1058         { }
1059 };
1060
1061 /* l4_abe -> dmic (dma) */
1062 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1063         .master         = &omap44xx_l4_abe_hwmod,
1064         .slave          = &omap44xx_dmic_hwmod,
1065         .clk            = "ocp_abe_iclk",
1066         .addr           = omap44xx_dmic_dma_addrs,
1067         .user           = OCP_USER_SDMA,
1068 };
1069
1070 /* dmic slave ports */
1071 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1072         &omap44xx_l4_abe__dmic,
1073         &omap44xx_l4_abe__dmic_dma,
1074 };
1075
1076 static struct omap_hwmod omap44xx_dmic_hwmod = {
1077         .name           = "dmic",
1078         .class          = &omap44xx_dmic_hwmod_class,
1079         .clkdm_name     = "abe_clkdm",
1080         .mpu_irqs       = omap44xx_dmic_irqs,
1081         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1082         .main_clk       = "dmic_fck",
1083         .prcm = {
1084                 .omap4 = {
1085                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1086                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1087                         .modulemode   = MODULEMODE_SWCTRL,
1088                 },
1089         },
1090         .slaves         = omap44xx_dmic_slaves,
1091         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1092 };
1093
1094 /*
1095  * 'dsp' class
1096  * dsp sub-system
1097  */
1098
1099 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1100         .name   = "dsp",
1101 };
1102
1103 /* dsp */
1104 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1105         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1106         { .irq = -1 }
1107 };
1108
1109 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1110         { .name = "dsp", .rst_shift = 0 },
1111         { .name = "mmu_cache", .rst_shift = 1 },
1112 };
1113
1114 /* dsp -> iva */
1115 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1116         .master         = &omap44xx_dsp_hwmod,
1117         .slave          = &omap44xx_iva_hwmod,
1118         .clk            = "dpll_iva_m5x2_ck",
1119 };
1120
1121 /* dsp master ports */
1122 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1123         &omap44xx_dsp__l3_main_1,
1124         &omap44xx_dsp__l4_abe,
1125         &omap44xx_dsp__iva,
1126 };
1127
1128 /* l4_cfg -> dsp */
1129 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1130         .master         = &omap44xx_l4_cfg_hwmod,
1131         .slave          = &omap44xx_dsp_hwmod,
1132         .clk            = "l4_div_ck",
1133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1134 };
1135
1136 /* dsp slave ports */
1137 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1138         &omap44xx_l4_cfg__dsp,
1139 };
1140
1141 static struct omap_hwmod omap44xx_dsp_hwmod = {
1142         .name           = "dsp",
1143         .class          = &omap44xx_dsp_hwmod_class,
1144         .clkdm_name     = "tesla_clkdm",
1145         .mpu_irqs       = omap44xx_dsp_irqs,
1146         .rst_lines      = omap44xx_dsp_resets,
1147         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1148         .main_clk       = "dsp_fck",
1149         .prcm = {
1150                 .omap4 = {
1151                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1152                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1153                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1154                         .modulemode   = MODULEMODE_HWCTRL,
1155                 },
1156         },
1157         .slaves         = omap44xx_dsp_slaves,
1158         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1159         .masters        = omap44xx_dsp_masters,
1160         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1161 };
1162
1163 /*
1164  * 'dss' class
1165  * display sub-system
1166  */
1167
1168 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1169         .rev_offs       = 0x0000,
1170         .syss_offs      = 0x0014,
1171         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1172 };
1173
1174 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1175         .name   = "dss",
1176         .sysc   = &omap44xx_dss_sysc,
1177         .reset  = omap_dss_reset,
1178 };
1179
1180 /* dss */
1181 /* dss master ports */
1182 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1183         &omap44xx_dss__l3_main_1,
1184 };
1185
1186 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1187         {
1188                 .pa_start       = 0x58000000,
1189                 .pa_end         = 0x5800007f,
1190                 .flags          = ADDR_TYPE_RT
1191         },
1192         { }
1193 };
1194
1195 /* l3_main_2 -> dss */
1196 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1197         .master         = &omap44xx_l3_main_2_hwmod,
1198         .slave          = &omap44xx_dss_hwmod,
1199         .clk            = "dss_fck",
1200         .addr           = omap44xx_dss_dma_addrs,
1201         .user           = OCP_USER_SDMA,
1202 };
1203
1204 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1205         {
1206                 .pa_start       = 0x48040000,
1207                 .pa_end         = 0x4804007f,
1208                 .flags          = ADDR_TYPE_RT
1209         },
1210         { }
1211 };
1212
1213 /* l4_per -> dss */
1214 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1215         .master         = &omap44xx_l4_per_hwmod,
1216         .slave          = &omap44xx_dss_hwmod,
1217         .clk            = "l4_div_ck",
1218         .addr           = omap44xx_dss_addrs,
1219         .user           = OCP_USER_MPU,
1220 };
1221
1222 /* dss slave ports */
1223 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1224         &omap44xx_l3_main_2__dss,
1225         &omap44xx_l4_per__dss,
1226 };
1227
1228 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1229         { .role = "sys_clk", .clk = "dss_sys_clk" },
1230         { .role = "tv_clk", .clk = "dss_tv_clk" },
1231         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1232 };
1233
1234 static struct omap_hwmod omap44xx_dss_hwmod = {
1235         .name           = "dss_core",
1236         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1237         .class          = &omap44xx_dss_hwmod_class,
1238         .clkdm_name     = "l3_dss_clkdm",
1239         .main_clk       = "dss_dss_clk",
1240         .prcm = {
1241                 .omap4 = {
1242                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1243                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1244                 },
1245         },
1246         .opt_clks       = dss_opt_clks,
1247         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1248         .slaves         = omap44xx_dss_slaves,
1249         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1250         .masters        = omap44xx_dss_masters,
1251         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1252 };
1253
1254 /*
1255  * 'dispc' class
1256  * display controller
1257  */
1258
1259 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1260         .rev_offs       = 0x0000,
1261         .sysc_offs      = 0x0010,
1262         .syss_offs      = 0x0014,
1263         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1264                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1265                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1266                            SYSS_HAS_RESET_STATUS),
1267         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1268                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1269         .sysc_fields    = &omap_hwmod_sysc_type1,
1270 };
1271
1272 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1273         .name   = "dispc",
1274         .sysc   = &omap44xx_dispc_sysc,
1275 };
1276
1277 /* dss_dispc */
1278 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1279 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1280         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1281         { .irq = -1 }
1282 };
1283
1284 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1285         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1286         { .dma_req = -1 }
1287 };
1288
1289 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1290         {
1291                 .pa_start       = 0x58001000,
1292                 .pa_end         = 0x58001fff,
1293                 .flags          = ADDR_TYPE_RT
1294         },
1295         { }
1296 };
1297
1298 /* l3_main_2 -> dss_dispc */
1299 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1300         .master         = &omap44xx_l3_main_2_hwmod,
1301         .slave          = &omap44xx_dss_dispc_hwmod,
1302         .clk            = "dss_fck",
1303         .addr           = omap44xx_dss_dispc_dma_addrs,
1304         .user           = OCP_USER_SDMA,
1305 };
1306
1307 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1308         {
1309                 .pa_start       = 0x48041000,
1310                 .pa_end         = 0x48041fff,
1311                 .flags          = ADDR_TYPE_RT
1312         },
1313         { }
1314 };
1315
1316 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1317         .manager_count          = 3,
1318         .has_framedonetv_irq    = 1
1319 };
1320
1321 /* l4_per -> dss_dispc */
1322 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1323         .master         = &omap44xx_l4_per_hwmod,
1324         .slave          = &omap44xx_dss_dispc_hwmod,
1325         .clk            = "l4_div_ck",
1326         .addr           = omap44xx_dss_dispc_addrs,
1327         .user           = OCP_USER_MPU,
1328 };
1329
1330 /* dss_dispc slave ports */
1331 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1332         &omap44xx_l3_main_2__dss_dispc,
1333         &omap44xx_l4_per__dss_dispc,
1334 };
1335
1336 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1337         .name           = "dss_dispc",
1338         .class          = &omap44xx_dispc_hwmod_class,
1339         .clkdm_name     = "l3_dss_clkdm",
1340         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1341         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1342         .main_clk       = "dss_dss_clk",
1343         .prcm = {
1344                 .omap4 = {
1345                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1346                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1347                 },
1348         },
1349         .slaves         = omap44xx_dss_dispc_slaves,
1350         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1351         .dev_attr       = &omap44xx_dss_dispc_dev_attr
1352 };
1353
1354 /*
1355  * 'dsi' class
1356  * display serial interface controller
1357  */
1358
1359 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1360         .rev_offs       = 0x0000,
1361         .sysc_offs      = 0x0010,
1362         .syss_offs      = 0x0014,
1363         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1364                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1365                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1366         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1367         .sysc_fields    = &omap_hwmod_sysc_type1,
1368 };
1369
1370 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1371         .name   = "dsi",
1372         .sysc   = &omap44xx_dsi_sysc,
1373 };
1374
1375 /* dss_dsi1 */
1376 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1377 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1378         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1379         { .irq = -1 }
1380 };
1381
1382 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1383         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1384         { .dma_req = -1 }
1385 };
1386
1387 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1388         {
1389                 .pa_start       = 0x58004000,
1390                 .pa_end         = 0x580041ff,
1391                 .flags          = ADDR_TYPE_RT
1392         },
1393         { }
1394 };
1395
1396 /* l3_main_2 -> dss_dsi1 */
1397 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1398         .master         = &omap44xx_l3_main_2_hwmod,
1399         .slave          = &omap44xx_dss_dsi1_hwmod,
1400         .clk            = "dss_fck",
1401         .addr           = omap44xx_dss_dsi1_dma_addrs,
1402         .user           = OCP_USER_SDMA,
1403 };
1404
1405 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1406         {
1407                 .pa_start       = 0x48044000,
1408                 .pa_end         = 0x480441ff,
1409                 .flags          = ADDR_TYPE_RT
1410         },
1411         { }
1412 };
1413
1414 /* l4_per -> dss_dsi1 */
1415 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1416         .master         = &omap44xx_l4_per_hwmod,
1417         .slave          = &omap44xx_dss_dsi1_hwmod,
1418         .clk            = "l4_div_ck",
1419         .addr           = omap44xx_dss_dsi1_addrs,
1420         .user           = OCP_USER_MPU,
1421 };
1422
1423 /* dss_dsi1 slave ports */
1424 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1425         &omap44xx_l3_main_2__dss_dsi1,
1426         &omap44xx_l4_per__dss_dsi1,
1427 };
1428
1429 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1430         { .role = "sys_clk", .clk = "dss_sys_clk" },
1431 };
1432
1433 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1434         .name           = "dss_dsi1",
1435         .class          = &omap44xx_dsi_hwmod_class,
1436         .clkdm_name     = "l3_dss_clkdm",
1437         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1438         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1439         .main_clk       = "dss_dss_clk",
1440         .prcm = {
1441                 .omap4 = {
1442                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1443                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1444                 },
1445         },
1446         .opt_clks       = dss_dsi1_opt_clks,
1447         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1448         .slaves         = omap44xx_dss_dsi1_slaves,
1449         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1450 };
1451
1452 /* dss_dsi2 */
1453 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1454 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1455         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1456         { .irq = -1 }
1457 };
1458
1459 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1460         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1461         { .dma_req = -1 }
1462 };
1463
1464 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1465         {
1466                 .pa_start       = 0x58005000,
1467                 .pa_end         = 0x580051ff,
1468                 .flags          = ADDR_TYPE_RT
1469         },
1470         { }
1471 };
1472
1473 /* l3_main_2 -> dss_dsi2 */
1474 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1475         .master         = &omap44xx_l3_main_2_hwmod,
1476         .slave          = &omap44xx_dss_dsi2_hwmod,
1477         .clk            = "dss_fck",
1478         .addr           = omap44xx_dss_dsi2_dma_addrs,
1479         .user           = OCP_USER_SDMA,
1480 };
1481
1482 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1483         {
1484                 .pa_start       = 0x48045000,
1485                 .pa_end         = 0x480451ff,
1486                 .flags          = ADDR_TYPE_RT
1487         },
1488         { }
1489 };
1490
1491 /* l4_per -> dss_dsi2 */
1492 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1493         .master         = &omap44xx_l4_per_hwmod,
1494         .slave          = &omap44xx_dss_dsi2_hwmod,
1495         .clk            = "l4_div_ck",
1496         .addr           = omap44xx_dss_dsi2_addrs,
1497         .user           = OCP_USER_MPU,
1498 };
1499
1500 /* dss_dsi2 slave ports */
1501 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1502         &omap44xx_l3_main_2__dss_dsi2,
1503         &omap44xx_l4_per__dss_dsi2,
1504 };
1505
1506 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1507         { .role = "sys_clk", .clk = "dss_sys_clk" },
1508 };
1509
1510 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1511         .name           = "dss_dsi2",
1512         .class          = &omap44xx_dsi_hwmod_class,
1513         .clkdm_name     = "l3_dss_clkdm",
1514         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1515         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1516         .main_clk       = "dss_dss_clk",
1517         .prcm = {
1518                 .omap4 = {
1519                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1520                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1521                 },
1522         },
1523         .opt_clks       = dss_dsi2_opt_clks,
1524         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1525         .slaves         = omap44xx_dss_dsi2_slaves,
1526         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1527 };
1528
1529 /*
1530  * 'hdmi' class
1531  * hdmi controller
1532  */
1533
1534 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1535         .rev_offs       = 0x0000,
1536         .sysc_offs      = 0x0010,
1537         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1538                            SYSC_HAS_SOFTRESET),
1539         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1540                            SIDLE_SMART_WKUP),
1541         .sysc_fields    = &omap_hwmod_sysc_type2,
1542 };
1543
1544 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1545         .name   = "hdmi",
1546         .sysc   = &omap44xx_hdmi_sysc,
1547 };
1548
1549 /* dss_hdmi */
1550 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1551 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1552         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1553         { .irq = -1 }
1554 };
1555
1556 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1557         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1558         { .dma_req = -1 }
1559 };
1560
1561 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1562         {
1563                 .pa_start       = 0x58006000,
1564                 .pa_end         = 0x58006fff,
1565                 .flags          = ADDR_TYPE_RT
1566         },
1567         { }
1568 };
1569
1570 /* l3_main_2 -> dss_hdmi */
1571 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1572         .master         = &omap44xx_l3_main_2_hwmod,
1573         .slave          = &omap44xx_dss_hdmi_hwmod,
1574         .clk            = "dss_fck",
1575         .addr           = omap44xx_dss_hdmi_dma_addrs,
1576         .user           = OCP_USER_SDMA,
1577 };
1578
1579 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1580         {
1581                 .pa_start       = 0x48046000,
1582                 .pa_end         = 0x48046fff,
1583                 .flags          = ADDR_TYPE_RT
1584         },
1585         { }
1586 };
1587
1588 /* l4_per -> dss_hdmi */
1589 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1590         .master         = &omap44xx_l4_per_hwmod,
1591         .slave          = &omap44xx_dss_hdmi_hwmod,
1592         .clk            = "l4_div_ck",
1593         .addr           = omap44xx_dss_hdmi_addrs,
1594         .user           = OCP_USER_MPU,
1595 };
1596
1597 /* dss_hdmi slave ports */
1598 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1599         &omap44xx_l3_main_2__dss_hdmi,
1600         &omap44xx_l4_per__dss_hdmi,
1601 };
1602
1603 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1604         { .role = "sys_clk", .clk = "dss_sys_clk" },
1605 };
1606
1607 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1608         .name           = "dss_hdmi",
1609         .class          = &omap44xx_hdmi_hwmod_class,
1610         .clkdm_name     = "l3_dss_clkdm",
1611         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1612         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1613         .main_clk       = "dss_48mhz_clk",
1614         .prcm = {
1615                 .omap4 = {
1616                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1617                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1618                 },
1619         },
1620         .opt_clks       = dss_hdmi_opt_clks,
1621         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1622         .slaves         = omap44xx_dss_hdmi_slaves,
1623         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1624 };
1625
1626 /*
1627  * 'rfbi' class
1628  * remote frame buffer interface
1629  */
1630
1631 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1632         .rev_offs       = 0x0000,
1633         .sysc_offs      = 0x0010,
1634         .syss_offs      = 0x0014,
1635         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1636                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1637         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1638         .sysc_fields    = &omap_hwmod_sysc_type1,
1639 };
1640
1641 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1642         .name   = "rfbi",
1643         .sysc   = &omap44xx_rfbi_sysc,
1644 };
1645
1646 /* dss_rfbi */
1647 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1648 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1649         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1650         { .dma_req = -1 }
1651 };
1652
1653 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1654         {
1655                 .pa_start       = 0x58002000,
1656                 .pa_end         = 0x580020ff,
1657                 .flags          = ADDR_TYPE_RT
1658         },
1659         { }
1660 };
1661
1662 /* l3_main_2 -> dss_rfbi */
1663 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1664         .master         = &omap44xx_l3_main_2_hwmod,
1665         .slave          = &omap44xx_dss_rfbi_hwmod,
1666         .clk            = "dss_fck",
1667         .addr           = omap44xx_dss_rfbi_dma_addrs,
1668         .user           = OCP_USER_SDMA,
1669 };
1670
1671 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1672         {
1673                 .pa_start       = 0x48042000,
1674                 .pa_end         = 0x480420ff,
1675                 .flags          = ADDR_TYPE_RT
1676         },
1677         { }
1678 };
1679
1680 /* l4_per -> dss_rfbi */
1681 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1682         .master         = &omap44xx_l4_per_hwmod,
1683         .slave          = &omap44xx_dss_rfbi_hwmod,
1684         .clk            = "l4_div_ck",
1685         .addr           = omap44xx_dss_rfbi_addrs,
1686         .user           = OCP_USER_MPU,
1687 };
1688
1689 /* dss_rfbi slave ports */
1690 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1691         &omap44xx_l3_main_2__dss_rfbi,
1692         &omap44xx_l4_per__dss_rfbi,
1693 };
1694
1695 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1696         { .role = "ick", .clk = "dss_fck" },
1697 };
1698
1699 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1700         .name           = "dss_rfbi",
1701         .class          = &omap44xx_rfbi_hwmod_class,
1702         .clkdm_name     = "l3_dss_clkdm",
1703         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1704         .main_clk       = "dss_dss_clk",
1705         .prcm = {
1706                 .omap4 = {
1707                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1708                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1709                 },
1710         },
1711         .opt_clks       = dss_rfbi_opt_clks,
1712         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1713         .slaves         = omap44xx_dss_rfbi_slaves,
1714         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1715 };
1716
1717 /*
1718  * 'venc' class
1719  * video encoder
1720  */
1721
1722 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1723         .name   = "venc",
1724 };
1725
1726 /* dss_venc */
1727 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1728 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1729         {
1730                 .pa_start       = 0x58003000,
1731                 .pa_end         = 0x580030ff,
1732                 .flags          = ADDR_TYPE_RT
1733         },
1734         { }
1735 };
1736
1737 /* l3_main_2 -> dss_venc */
1738 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1739         .master         = &omap44xx_l3_main_2_hwmod,
1740         .slave          = &omap44xx_dss_venc_hwmod,
1741         .clk            = "dss_fck",
1742         .addr           = omap44xx_dss_venc_dma_addrs,
1743         .user           = OCP_USER_SDMA,
1744 };
1745
1746 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1747         {
1748                 .pa_start       = 0x48043000,
1749                 .pa_end         = 0x480430ff,
1750                 .flags          = ADDR_TYPE_RT
1751         },
1752         { }
1753 };
1754
1755 /* l4_per -> dss_venc */
1756 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1757         .master         = &omap44xx_l4_per_hwmod,
1758         .slave          = &omap44xx_dss_venc_hwmod,
1759         .clk            = "l4_div_ck",
1760         .addr           = omap44xx_dss_venc_addrs,
1761         .user           = OCP_USER_MPU,
1762 };
1763
1764 /* dss_venc slave ports */
1765 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1766         &omap44xx_l3_main_2__dss_venc,
1767         &omap44xx_l4_per__dss_venc,
1768 };
1769
1770 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1771         .name           = "dss_venc",
1772         .class          = &omap44xx_venc_hwmod_class,
1773         .clkdm_name     = "l3_dss_clkdm",
1774         .main_clk       = "dss_tv_clk",
1775         .prcm = {
1776                 .omap4 = {
1777                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1778                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1779                 },
1780         },
1781         .slaves         = omap44xx_dss_venc_slaves,
1782         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1783 };
1784
1785 /*
1786  * 'gpio' class
1787  * general purpose io module
1788  */
1789
1790 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1791         .rev_offs       = 0x0000,
1792         .sysc_offs      = 0x0010,
1793         .syss_offs      = 0x0114,
1794         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1795                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1796                            SYSS_HAS_RESET_STATUS),
1797         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1798                            SIDLE_SMART_WKUP),
1799         .sysc_fields    = &omap_hwmod_sysc_type1,
1800 };
1801
1802 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1803         .name   = "gpio",
1804         .sysc   = &omap44xx_gpio_sysc,
1805         .rev    = 2,
1806 };
1807
1808 /* gpio dev_attr */
1809 static struct omap_gpio_dev_attr gpio_dev_attr = {
1810         .bank_width     = 32,
1811         .dbck_flag      = true,
1812 };
1813
1814 /* gpio1 */
1815 static struct omap_hwmod omap44xx_gpio1_hwmod;
1816 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1817         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1818         { .irq = -1 }
1819 };
1820
1821 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1822         {
1823                 .pa_start       = 0x4a310000,
1824                 .pa_end         = 0x4a3101ff,
1825                 .flags          = ADDR_TYPE_RT
1826         },
1827         { }
1828 };
1829
1830 /* l4_wkup -> gpio1 */
1831 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1832         .master         = &omap44xx_l4_wkup_hwmod,
1833         .slave          = &omap44xx_gpio1_hwmod,
1834         .clk            = "l4_wkup_clk_mux_ck",
1835         .addr           = omap44xx_gpio1_addrs,
1836         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1837 };
1838
1839 /* gpio1 slave ports */
1840 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1841         &omap44xx_l4_wkup__gpio1,
1842 };
1843
1844 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1845         { .role = "dbclk", .clk = "gpio1_dbclk" },
1846 };
1847
1848 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1849         .name           = "gpio1",
1850         .class          = &omap44xx_gpio_hwmod_class,
1851         .clkdm_name     = "l4_wkup_clkdm",
1852         .mpu_irqs       = omap44xx_gpio1_irqs,
1853         .main_clk       = "gpio1_ick",
1854         .prcm = {
1855                 .omap4 = {
1856                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1857                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1858                         .modulemode   = MODULEMODE_HWCTRL,
1859                 },
1860         },
1861         .opt_clks       = gpio1_opt_clks,
1862         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1863         .dev_attr       = &gpio_dev_attr,
1864         .slaves         = omap44xx_gpio1_slaves,
1865         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1866 };
1867
1868 /* gpio2 */
1869 static struct omap_hwmod omap44xx_gpio2_hwmod;
1870 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1871         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1872         { .irq = -1 }
1873 };
1874
1875 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1876         {
1877                 .pa_start       = 0x48055000,
1878                 .pa_end         = 0x480551ff,
1879                 .flags          = ADDR_TYPE_RT
1880         },
1881         { }
1882 };
1883
1884 /* l4_per -> gpio2 */
1885 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1886         .master         = &omap44xx_l4_per_hwmod,
1887         .slave          = &omap44xx_gpio2_hwmod,
1888         .clk            = "l4_div_ck",
1889         .addr           = omap44xx_gpio2_addrs,
1890         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1891 };
1892
1893 /* gpio2 slave ports */
1894 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1895         &omap44xx_l4_per__gpio2,
1896 };
1897
1898 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1899         { .role = "dbclk", .clk = "gpio2_dbclk" },
1900 };
1901
1902 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1903         .name           = "gpio2",
1904         .class          = &omap44xx_gpio_hwmod_class,
1905         .clkdm_name     = "l4_per_clkdm",
1906         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1907         .mpu_irqs       = omap44xx_gpio2_irqs,
1908         .main_clk       = "gpio2_ick",
1909         .prcm = {
1910                 .omap4 = {
1911                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1912                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1913                         .modulemode   = MODULEMODE_HWCTRL,
1914                 },
1915         },
1916         .opt_clks       = gpio2_opt_clks,
1917         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1918         .dev_attr       = &gpio_dev_attr,
1919         .slaves         = omap44xx_gpio2_slaves,
1920         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1921 };
1922
1923 /* gpio3 */
1924 static struct omap_hwmod omap44xx_gpio3_hwmod;
1925 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1926         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1927         { .irq = -1 }
1928 };
1929
1930 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1931         {
1932                 .pa_start       = 0x48057000,
1933                 .pa_end         = 0x480571ff,
1934                 .flags          = ADDR_TYPE_RT
1935         },
1936         { }
1937 };
1938
1939 /* l4_per -> gpio3 */
1940 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1941         .master         = &omap44xx_l4_per_hwmod,
1942         .slave          = &omap44xx_gpio3_hwmod,
1943         .clk            = "l4_div_ck",
1944         .addr           = omap44xx_gpio3_addrs,
1945         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1946 };
1947
1948 /* gpio3 slave ports */
1949 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1950         &omap44xx_l4_per__gpio3,
1951 };
1952
1953 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1954         { .role = "dbclk", .clk = "gpio3_dbclk" },
1955 };
1956
1957 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1958         .name           = "gpio3",
1959         .class          = &omap44xx_gpio_hwmod_class,
1960         .clkdm_name     = "l4_per_clkdm",
1961         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1962         .mpu_irqs       = omap44xx_gpio3_irqs,
1963         .main_clk       = "gpio3_ick",
1964         .prcm = {
1965                 .omap4 = {
1966                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1967                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1968                         .modulemode   = MODULEMODE_HWCTRL,
1969                 },
1970         },
1971         .opt_clks       = gpio3_opt_clks,
1972         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1973         .dev_attr       = &gpio_dev_attr,
1974         .slaves         = omap44xx_gpio3_slaves,
1975         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1976 };
1977
1978 /* gpio4 */
1979 static struct omap_hwmod omap44xx_gpio4_hwmod;
1980 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1981         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1982         { .irq = -1 }
1983 };
1984
1985 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
1986         {
1987                 .pa_start       = 0x48059000,
1988                 .pa_end         = 0x480591ff,
1989                 .flags          = ADDR_TYPE_RT
1990         },
1991         { }
1992 };
1993
1994 /* l4_per -> gpio4 */
1995 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
1996         .master         = &omap44xx_l4_per_hwmod,
1997         .slave          = &omap44xx_gpio4_hwmod,
1998         .clk            = "l4_div_ck",
1999         .addr           = omap44xx_gpio4_addrs,
2000         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2001 };
2002
2003 /* gpio4 slave ports */
2004 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2005         &omap44xx_l4_per__gpio4,
2006 };
2007
2008 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2009         { .role = "dbclk", .clk = "gpio4_dbclk" },
2010 };
2011
2012 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2013         .name           = "gpio4",
2014         .class          = &omap44xx_gpio_hwmod_class,
2015         .clkdm_name     = "l4_per_clkdm",
2016         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2017         .mpu_irqs       = omap44xx_gpio4_irqs,
2018         .main_clk       = "gpio4_ick",
2019         .prcm = {
2020                 .omap4 = {
2021                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2022                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2023                         .modulemode   = MODULEMODE_HWCTRL,
2024                 },
2025         },
2026         .opt_clks       = gpio4_opt_clks,
2027         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2028         .dev_attr       = &gpio_dev_attr,
2029         .slaves         = omap44xx_gpio4_slaves,
2030         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2031 };
2032
2033 /* gpio5 */
2034 static struct omap_hwmod omap44xx_gpio5_hwmod;
2035 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2036         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2037         { .irq = -1 }
2038 };
2039
2040 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2041         {
2042                 .pa_start       = 0x4805b000,
2043                 .pa_end         = 0x4805b1ff,
2044                 .flags          = ADDR_TYPE_RT
2045         },
2046         { }
2047 };
2048
2049 /* l4_per -> gpio5 */
2050 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2051         .master         = &omap44xx_l4_per_hwmod,
2052         .slave          = &omap44xx_gpio5_hwmod,
2053         .clk            = "l4_div_ck",
2054         .addr           = omap44xx_gpio5_addrs,
2055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2056 };
2057
2058 /* gpio5 slave ports */
2059 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2060         &omap44xx_l4_per__gpio5,
2061 };
2062
2063 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2064         { .role = "dbclk", .clk = "gpio5_dbclk" },
2065 };
2066
2067 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2068         .name           = "gpio5",
2069         .class          = &omap44xx_gpio_hwmod_class,
2070         .clkdm_name     = "l4_per_clkdm",
2071         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2072         .mpu_irqs       = omap44xx_gpio5_irqs,
2073         .main_clk       = "gpio5_ick",
2074         .prcm = {
2075                 .omap4 = {
2076                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2077                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2078                         .modulemode   = MODULEMODE_HWCTRL,
2079                 },
2080         },
2081         .opt_clks       = gpio5_opt_clks,
2082         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2083         .dev_attr       = &gpio_dev_attr,
2084         .slaves         = omap44xx_gpio5_slaves,
2085         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2086 };
2087
2088 /* gpio6 */
2089 static struct omap_hwmod omap44xx_gpio6_hwmod;
2090 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2091         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2092         { .irq = -1 }
2093 };
2094
2095 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2096         {
2097                 .pa_start       = 0x4805d000,
2098                 .pa_end         = 0x4805d1ff,
2099                 .flags          = ADDR_TYPE_RT
2100         },
2101         { }
2102 };
2103
2104 /* l4_per -> gpio6 */
2105 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2106         .master         = &omap44xx_l4_per_hwmod,
2107         .slave          = &omap44xx_gpio6_hwmod,
2108         .clk            = "l4_div_ck",
2109         .addr           = omap44xx_gpio6_addrs,
2110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2111 };
2112
2113 /* gpio6 slave ports */
2114 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2115         &omap44xx_l4_per__gpio6,
2116 };
2117
2118 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2119         { .role = "dbclk", .clk = "gpio6_dbclk" },
2120 };
2121
2122 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2123         .name           = "gpio6",
2124         .class          = &omap44xx_gpio_hwmod_class,
2125         .clkdm_name     = "l4_per_clkdm",
2126         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2127         .mpu_irqs       = omap44xx_gpio6_irqs,
2128         .main_clk       = "gpio6_ick",
2129         .prcm = {
2130                 .omap4 = {
2131                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2132                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2133                         .modulemode   = MODULEMODE_HWCTRL,
2134                 },
2135         },
2136         .opt_clks       = gpio6_opt_clks,
2137         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2138         .dev_attr       = &gpio_dev_attr,
2139         .slaves         = omap44xx_gpio6_slaves,
2140         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2141 };
2142
2143 /*
2144  * 'hsi' class
2145  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2146  * serial if)
2147  */
2148
2149 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2150         .rev_offs       = 0x0000,
2151         .sysc_offs      = 0x0010,
2152         .syss_offs      = 0x0014,
2153         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2154                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2155                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2156         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2157                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2158                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2159         .sysc_fields    = &omap_hwmod_sysc_type1,
2160 };
2161
2162 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2163         .name   = "hsi",
2164         .sysc   = &omap44xx_hsi_sysc,
2165 };
2166
2167 /* hsi */
2168 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2169         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2170         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2171         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2172         { .irq = -1 }
2173 };
2174
2175 /* hsi master ports */
2176 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2177         &omap44xx_hsi__l3_main_2,
2178 };
2179
2180 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2181         {
2182                 .pa_start       = 0x4a058000,
2183                 .pa_end         = 0x4a05bfff,
2184                 .flags          = ADDR_TYPE_RT
2185         },
2186         { }
2187 };
2188
2189 /* l4_cfg -> hsi */
2190 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2191         .master         = &omap44xx_l4_cfg_hwmod,
2192         .slave          = &omap44xx_hsi_hwmod,
2193         .clk            = "l4_div_ck",
2194         .addr           = omap44xx_hsi_addrs,
2195         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2196 };
2197
2198 /* hsi slave ports */
2199 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2200         &omap44xx_l4_cfg__hsi,
2201 };
2202
2203 static struct omap_hwmod omap44xx_hsi_hwmod = {
2204         .name           = "hsi",
2205         .class          = &omap44xx_hsi_hwmod_class,
2206         .clkdm_name     = "l3_init_clkdm",
2207         .mpu_irqs       = omap44xx_hsi_irqs,
2208         .main_clk       = "hsi_fck",
2209         .prcm = {
2210                 .omap4 = {
2211                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2212                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2213                         .modulemode   = MODULEMODE_HWCTRL,
2214                 },
2215         },
2216         .slaves         = omap44xx_hsi_slaves,
2217         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2218         .masters        = omap44xx_hsi_masters,
2219         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2220 };
2221
2222 /*
2223  * 'i2c' class
2224  * multimaster high-speed i2c controller
2225  */
2226
2227 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2228         .sysc_offs      = 0x0010,
2229         .syss_offs      = 0x0090,
2230         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2231                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2232                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2233         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2234                            SIDLE_SMART_WKUP),
2235         .clockact       = CLOCKACT_TEST_ICLK,
2236         .sysc_fields    = &omap_hwmod_sysc_type1,
2237 };
2238
2239 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2240         .name   = "i2c",
2241         .sysc   = &omap44xx_i2c_sysc,
2242         .rev    = OMAP_I2C_IP_VERSION_2,
2243         .reset  = &omap_i2c_reset,
2244 };
2245
2246 static struct omap_i2c_dev_attr i2c_dev_attr = {
2247         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2248 };
2249
2250 /* i2c1 */
2251 static struct omap_hwmod omap44xx_i2c1_hwmod;
2252 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2253         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2254         { .irq = -1 }
2255 };
2256
2257 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2258         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2259         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2260         { .dma_req = -1 }
2261 };
2262
2263 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2264         {
2265                 .pa_start       = 0x48070000,
2266                 .pa_end         = 0x480700ff,
2267                 .flags          = ADDR_TYPE_RT
2268         },
2269         { }
2270 };
2271
2272 /* l4_per -> i2c1 */
2273 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2274         .master         = &omap44xx_l4_per_hwmod,
2275         .slave          = &omap44xx_i2c1_hwmod,
2276         .clk            = "l4_div_ck",
2277         .addr           = omap44xx_i2c1_addrs,
2278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2279 };
2280
2281 /* i2c1 slave ports */
2282 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2283         &omap44xx_l4_per__i2c1,
2284 };
2285
2286 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2287         .name           = "i2c1",
2288         .class          = &omap44xx_i2c_hwmod_class,
2289         .clkdm_name     = "l4_per_clkdm",
2290         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2291         .mpu_irqs       = omap44xx_i2c1_irqs,
2292         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2293         .main_clk       = "i2c1_fck",
2294         .prcm = {
2295                 .omap4 = {
2296                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2297                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2298                         .modulemode   = MODULEMODE_SWCTRL,
2299                 },
2300         },
2301         .slaves         = omap44xx_i2c1_slaves,
2302         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2303         .dev_attr       = &i2c_dev_attr,
2304 };
2305
2306 /* i2c2 */
2307 static struct omap_hwmod omap44xx_i2c2_hwmod;
2308 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2309         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2310         { .irq = -1 }
2311 };
2312
2313 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2314         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2315         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2316         { .dma_req = -1 }
2317 };
2318
2319 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2320         {
2321                 .pa_start       = 0x48072000,
2322                 .pa_end         = 0x480720ff,
2323                 .flags          = ADDR_TYPE_RT
2324         },
2325         { }
2326 };
2327
2328 /* l4_per -> i2c2 */
2329 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2330         .master         = &omap44xx_l4_per_hwmod,
2331         .slave          = &omap44xx_i2c2_hwmod,
2332         .clk            = "l4_div_ck",
2333         .addr           = omap44xx_i2c2_addrs,
2334         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2335 };
2336
2337 /* i2c2 slave ports */
2338 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2339         &omap44xx_l4_per__i2c2,
2340 };
2341
2342 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2343         .name           = "i2c2",
2344         .class          = &omap44xx_i2c_hwmod_class,
2345         .clkdm_name     = "l4_per_clkdm",
2346         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2347         .mpu_irqs       = omap44xx_i2c2_irqs,
2348         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2349         .main_clk       = "i2c2_fck",
2350         .prcm = {
2351                 .omap4 = {
2352                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2353                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2354                         .modulemode   = MODULEMODE_SWCTRL,
2355                 },
2356         },
2357         .slaves         = omap44xx_i2c2_slaves,
2358         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2359         .dev_attr       = &i2c_dev_attr,
2360 };
2361
2362 /* i2c3 */
2363 static struct omap_hwmod omap44xx_i2c3_hwmod;
2364 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2365         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2366         { .irq = -1 }
2367 };
2368
2369 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2370         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2371         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2372         { .dma_req = -1 }
2373 };
2374
2375 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2376         {
2377                 .pa_start       = 0x48060000,
2378                 .pa_end         = 0x480600ff,
2379                 .flags          = ADDR_TYPE_RT
2380         },
2381         { }
2382 };
2383
2384 /* l4_per -> i2c3 */
2385 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2386         .master         = &omap44xx_l4_per_hwmod,
2387         .slave          = &omap44xx_i2c3_hwmod,
2388         .clk            = "l4_div_ck",
2389         .addr           = omap44xx_i2c3_addrs,
2390         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2391 };
2392
2393 /* i2c3 slave ports */
2394 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2395         &omap44xx_l4_per__i2c3,
2396 };
2397
2398 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2399         .name           = "i2c3",
2400         .class          = &omap44xx_i2c_hwmod_class,
2401         .clkdm_name     = "l4_per_clkdm",
2402         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2403         .mpu_irqs       = omap44xx_i2c3_irqs,
2404         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2405         .main_clk       = "i2c3_fck",
2406         .prcm = {
2407                 .omap4 = {
2408                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2409                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2410                         .modulemode   = MODULEMODE_SWCTRL,
2411                 },
2412         },
2413         .slaves         = omap44xx_i2c3_slaves,
2414         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2415         .dev_attr       = &i2c_dev_attr,
2416 };
2417
2418 /* i2c4 */
2419 static struct omap_hwmod omap44xx_i2c4_hwmod;
2420 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2421         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2422         { .irq = -1 }
2423 };
2424
2425 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2426         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2427         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2428         { .dma_req = -1 }
2429 };
2430
2431 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2432         {
2433                 .pa_start       = 0x48350000,
2434                 .pa_end         = 0x483500ff,
2435                 .flags          = ADDR_TYPE_RT
2436         },
2437         { }
2438 };
2439
2440 /* l4_per -> i2c4 */
2441 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2442         .master         = &omap44xx_l4_per_hwmod,
2443         .slave          = &omap44xx_i2c4_hwmod,
2444         .clk            = "l4_div_ck",
2445         .addr           = omap44xx_i2c4_addrs,
2446         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2447 };
2448
2449 /* i2c4 slave ports */
2450 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2451         &omap44xx_l4_per__i2c4,
2452 };
2453
2454 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2455         .name           = "i2c4",
2456         .class          = &omap44xx_i2c_hwmod_class,
2457         .clkdm_name     = "l4_per_clkdm",
2458         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
2459         .mpu_irqs       = omap44xx_i2c4_irqs,
2460         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2461         .main_clk       = "i2c4_fck",
2462         .prcm = {
2463                 .omap4 = {
2464                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2465                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2466                         .modulemode   = MODULEMODE_SWCTRL,
2467                 },
2468         },
2469         .slaves         = omap44xx_i2c4_slaves,
2470         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2471         .dev_attr       = &i2c_dev_attr,
2472 };
2473
2474 /*
2475  * 'ipu' class
2476  * imaging processor unit
2477  */
2478
2479 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2480         .name   = "ipu",
2481 };
2482
2483 /* ipu */
2484 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2485         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2486         { .irq = -1 }
2487 };
2488
2489 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2490         { .name = "cpu0", .rst_shift = 0 },
2491         { .name = "cpu1", .rst_shift = 1 },
2492         { .name = "mmu_cache", .rst_shift = 2 },
2493 };
2494
2495 /* ipu master ports */
2496 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2497         &omap44xx_ipu__l3_main_2,
2498 };
2499
2500 /* l3_main_2 -> ipu */
2501 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2502         .master         = &omap44xx_l3_main_2_hwmod,
2503         .slave          = &omap44xx_ipu_hwmod,
2504         .clk            = "l3_div_ck",
2505         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2506 };
2507
2508 /* ipu slave ports */
2509 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2510         &omap44xx_l3_main_2__ipu,
2511 };
2512
2513 static struct omap_hwmod omap44xx_ipu_hwmod = {
2514         .name           = "ipu",
2515         .class          = &omap44xx_ipu_hwmod_class,
2516         .clkdm_name     = "ducati_clkdm",
2517         .mpu_irqs       = omap44xx_ipu_irqs,
2518         .rst_lines      = omap44xx_ipu_resets,
2519         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2520         .main_clk       = "ipu_fck",
2521         .prcm = {
2522                 .omap4 = {
2523                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2524                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2525                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2526                         .modulemode   = MODULEMODE_HWCTRL,
2527                 },
2528         },
2529         .slaves         = omap44xx_ipu_slaves,
2530         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2531         .masters        = omap44xx_ipu_masters,
2532         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2533 };
2534
2535 /*
2536  * 'iss' class
2537  * external images sensor pixel data processor
2538  */
2539
2540 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2541         .rev_offs       = 0x0000,
2542         .sysc_offs      = 0x0010,
2543         /*
2544          * ISS needs 100 OCP clk cycles delay after a softreset before
2545          * accessing sysconfig again.
2546          * The lowest frequency at the moment for L3 bus is 100 MHz, so
2547          * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
2548          *
2549          * TODO: Indicate errata when available.
2550          */
2551         .srst_udelay    = 2,
2552         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2553                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2554         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2555                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2556                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2557         .sysc_fields    = &omap_hwmod_sysc_type2,
2558 };
2559
2560 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2561         .name   = "iss",
2562         .sysc   = &omap44xx_iss_sysc,
2563 };
2564
2565 /* iss */
2566 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2567         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2568         { .irq = -1 }
2569 };
2570
2571 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2572         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2573         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2574         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2575         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2576         { .dma_req = -1 }
2577 };
2578
2579 /* iss master ports */
2580 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2581         &omap44xx_iss__l3_main_2,
2582 };
2583
2584 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2585         {
2586                 .pa_start       = 0x52000000,
2587                 .pa_end         = 0x520000ff,
2588                 .flags          = ADDR_TYPE_RT
2589         },
2590         { }
2591 };
2592
2593 /* l3_main_2 -> iss */
2594 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2595         .master         = &omap44xx_l3_main_2_hwmod,
2596         .slave          = &omap44xx_iss_hwmod,
2597         .clk            = "l3_div_ck",
2598         .addr           = omap44xx_iss_addrs,
2599         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2600 };
2601
2602 /* iss slave ports */
2603 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2604         &omap44xx_l3_main_2__iss,
2605 };
2606
2607 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2608         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2609 };
2610
2611 static struct omap_hwmod omap44xx_iss_hwmod = {
2612         .name           = "iss",
2613         .class          = &omap44xx_iss_hwmod_class,
2614         .clkdm_name     = "iss_clkdm",
2615         .mpu_irqs       = omap44xx_iss_irqs,
2616         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2617         .main_clk       = "iss_fck",
2618         .prcm = {
2619                 .omap4 = {
2620                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2621                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2622                         .modulemode   = MODULEMODE_SWCTRL,
2623                 },
2624         },
2625         .opt_clks       = iss_opt_clks,
2626         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2627         .slaves         = omap44xx_iss_slaves,
2628         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2629         .masters        = omap44xx_iss_masters,
2630         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2631 };
2632
2633 /*
2634  * 'iva' class
2635  * multi-standard video encoder/decoder hardware accelerator
2636  */
2637
2638 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2639         .name   = "iva",
2640 };
2641
2642 /* iva */
2643 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2644         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2645         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2646         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2647         { .irq = -1 }
2648 };
2649
2650 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2651         { .name = "seq0", .rst_shift = 0 },
2652         { .name = "seq1", .rst_shift = 1 },
2653         { .name = "logic", .rst_shift = 2 },
2654 };
2655
2656 /* iva master ports */
2657 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2658         &omap44xx_iva__l3_main_2,
2659         &omap44xx_iva__l3_instr,
2660 };
2661
2662 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2663         {
2664                 .pa_start       = 0x5a000000,
2665                 .pa_end         = 0x5a07ffff,
2666                 .flags          = ADDR_TYPE_RT
2667         },
2668         { }
2669 };
2670
2671 /* l3_main_2 -> iva */
2672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2673         .master         = &omap44xx_l3_main_2_hwmod,
2674         .slave          = &omap44xx_iva_hwmod,
2675         .clk            = "l3_div_ck",
2676         .addr           = omap44xx_iva_addrs,
2677         .user           = OCP_USER_MPU,
2678 };
2679
2680 /* iva slave ports */
2681 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2682         &omap44xx_dsp__iva,
2683         &omap44xx_l3_main_2__iva,
2684 };
2685
2686 static struct omap_hwmod omap44xx_iva_hwmod = {
2687         .name           = "iva",
2688         .class          = &omap44xx_iva_hwmod_class,
2689         .clkdm_name     = "ivahd_clkdm",
2690         .mpu_irqs       = omap44xx_iva_irqs,
2691         .rst_lines      = omap44xx_iva_resets,
2692         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2693         .main_clk       = "iva_fck",
2694         .prcm = {
2695                 .omap4 = {
2696                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2697                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2698                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2699                         .modulemode   = MODULEMODE_HWCTRL,
2700                 },
2701         },
2702         .slaves         = omap44xx_iva_slaves,
2703         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2704         .masters        = omap44xx_iva_masters,
2705         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2706 };
2707
2708 /*
2709  * 'kbd' class
2710  * keyboard controller
2711  */
2712
2713 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2714         .rev_offs       = 0x0000,
2715         .sysc_offs      = 0x0010,
2716         .syss_offs      = 0x0014,
2717         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2718                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2719                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2720                            SYSS_HAS_RESET_STATUS),
2721         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2722         .sysc_fields    = &omap_hwmod_sysc_type1,
2723 };
2724
2725 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2726         .name   = "kbd",
2727         .sysc   = &omap44xx_kbd_sysc,
2728 };
2729
2730 /* kbd */
2731 static struct omap_hwmod omap44xx_kbd_hwmod;
2732 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2733         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2734         { .irq = -1 }
2735 };
2736
2737 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2738         {
2739                 .pa_start       = 0x4a31c000,
2740                 .pa_end         = 0x4a31c07f,
2741                 .flags          = ADDR_TYPE_RT
2742         },
2743         { }
2744 };
2745
2746 /* l4_wkup -> kbd */
2747 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2748         .master         = &omap44xx_l4_wkup_hwmod,
2749         .slave          = &omap44xx_kbd_hwmod,
2750         .clk            = "l4_wkup_clk_mux_ck",
2751         .addr           = omap44xx_kbd_addrs,
2752         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2753 };
2754
2755 /* kbd slave ports */
2756 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2757         &omap44xx_l4_wkup__kbd,
2758 };
2759
2760 static struct omap_hwmod omap44xx_kbd_hwmod = {
2761         .name           = "kbd",
2762         .class          = &omap44xx_kbd_hwmod_class,
2763         .clkdm_name     = "l4_wkup_clkdm",
2764         .mpu_irqs       = omap44xx_kbd_irqs,
2765         .main_clk       = "kbd_fck",
2766         .prcm = {
2767                 .omap4 = {
2768                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2769                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2770                         .modulemode   = MODULEMODE_SWCTRL,
2771                 },
2772         },
2773         .slaves         = omap44xx_kbd_slaves,
2774         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2775 };
2776
2777 /*
2778  * 'mailbox' class
2779  * mailbox module allowing communication between the on-chip processors using a
2780  * queued mailbox-interrupt mechanism.
2781  */
2782
2783 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2784         .rev_offs       = 0x0000,
2785         .sysc_offs      = 0x0010,
2786         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2787                            SYSC_HAS_SOFTRESET),
2788         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2789         .sysc_fields    = &omap_hwmod_sysc_type2,
2790 };
2791
2792 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2793         .name   = "mailbox",
2794         .sysc   = &omap44xx_mailbox_sysc,
2795 };
2796
2797 /* mailbox */
2798 static struct omap_hwmod omap44xx_mailbox_hwmod;
2799 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2800         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2801         { .irq = -1 }
2802 };
2803
2804 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2805         {
2806                 .pa_start       = 0x4a0f4000,
2807                 .pa_end         = 0x4a0f41ff,
2808                 .flags          = ADDR_TYPE_RT
2809         },
2810         { }
2811 };
2812
2813 /* l4_cfg -> mailbox */
2814 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2815         .master         = &omap44xx_l4_cfg_hwmod,
2816         .slave          = &omap44xx_mailbox_hwmod,
2817         .clk            = "l4_div_ck",
2818         .addr           = omap44xx_mailbox_addrs,
2819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2820 };
2821
2822 /* mailbox slave ports */
2823 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2824         &omap44xx_l4_cfg__mailbox,
2825 };
2826
2827 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2828         .name           = "mailbox",
2829         .class          = &omap44xx_mailbox_hwmod_class,
2830         .clkdm_name     = "l4_cfg_clkdm",
2831         .mpu_irqs       = omap44xx_mailbox_irqs,
2832         .prcm = {
2833                 .omap4 = {
2834                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2835                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2836                 },
2837         },
2838         .slaves         = omap44xx_mailbox_slaves,
2839         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2840 };
2841
2842 /*
2843  * 'mcbsp' class
2844  * multi channel buffered serial port controller
2845  */
2846
2847 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2848         .sysc_offs      = 0x008c,
2849         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2850                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2851         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2852         .sysc_fields    = &omap_hwmod_sysc_type1,
2853 };
2854
2855 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2856         .name   = "mcbsp",
2857         .sysc   = &omap44xx_mcbsp_sysc,
2858         .rev    = MCBSP_CONFIG_TYPE4,
2859 };
2860
2861 /* mcbsp1 */
2862 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2863 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2864         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2865         { .irq = -1 }
2866 };
2867
2868 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2869         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2870         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2871         { .dma_req = -1 }
2872 };
2873
2874 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2875         {
2876                 .name           = "mpu",
2877                 .pa_start       = 0x40122000,
2878                 .pa_end         = 0x401220ff,
2879                 .flags          = ADDR_TYPE_RT
2880         },
2881         { }
2882 };
2883
2884 /* l4_abe -> mcbsp1 */
2885 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2886         .master         = &omap44xx_l4_abe_hwmod,
2887         .slave          = &omap44xx_mcbsp1_hwmod,
2888         .clk            = "ocp_abe_iclk",
2889         .addr           = omap44xx_mcbsp1_addrs,
2890         .user           = OCP_USER_MPU,
2891 };
2892
2893 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2894         {
2895                 .name           = "dma",
2896                 .pa_start       = 0x49022000,
2897                 .pa_end         = 0x490220ff,
2898                 .flags          = ADDR_TYPE_RT
2899         },
2900         { }
2901 };
2902
2903 /* l4_abe -> mcbsp1 (dma) */
2904 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2905         .master         = &omap44xx_l4_abe_hwmod,
2906         .slave          = &omap44xx_mcbsp1_hwmod,
2907         .clk            = "ocp_abe_iclk",
2908         .addr           = omap44xx_mcbsp1_dma_addrs,
2909         .user           = OCP_USER_SDMA,
2910 };
2911
2912 /* mcbsp1 slave ports */
2913 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2914         &omap44xx_l4_abe__mcbsp1,
2915         &omap44xx_l4_abe__mcbsp1_dma,
2916 };
2917
2918 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
2919         { .role = "pad_fck", .clk = "pad_clks_ck" },
2920         { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" },
2921 };
2922
2923 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2924         .name           = "mcbsp1",
2925         .class          = &omap44xx_mcbsp_hwmod_class,
2926         .clkdm_name     = "abe_clkdm",
2927         .mpu_irqs       = omap44xx_mcbsp1_irqs,
2928         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
2929         .main_clk       = "mcbsp1_fck",
2930         .prcm = {
2931                 .omap4 = {
2932                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
2933                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
2934                         .modulemode   = MODULEMODE_SWCTRL,
2935                 },
2936         },
2937         .slaves         = omap44xx_mcbsp1_slaves,
2938         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
2939         .opt_clks       = mcbsp1_opt_clks,
2940         .opt_clks_cnt   = ARRAY_SIZE(mcbsp1_opt_clks),
2941 };
2942
2943 /* mcbsp2 */
2944 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
2945 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
2946         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
2947         { .irq = -1 }
2948 };
2949
2950 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2951         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
2952         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
2953         { .dma_req = -1 }
2954 };
2955
2956 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2957         {
2958                 .name           = "mpu",
2959                 .pa_start       = 0x40124000,
2960                 .pa_end         = 0x401240ff,
2961                 .flags          = ADDR_TYPE_RT
2962         },
2963         { }
2964 };
2965
2966 /* l4_abe -> mcbsp2 */
2967 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2968         .master         = &omap44xx_l4_abe_hwmod,
2969         .slave          = &omap44xx_mcbsp2_hwmod,
2970         .clk            = "ocp_abe_iclk",
2971         .addr           = omap44xx_mcbsp2_addrs,
2972         .user           = OCP_USER_MPU,
2973 };
2974
2975 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2976         {
2977                 .name           = "dma",
2978                 .pa_start       = 0x49024000,
2979                 .pa_end         = 0x490240ff,
2980                 .flags          = ADDR_TYPE_RT
2981         },
2982         { }
2983 };
2984
2985 /* l4_abe -> mcbsp2 (dma) */
2986 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
2987         .master         = &omap44xx_l4_abe_hwmod,
2988         .slave          = &omap44xx_mcbsp2_hwmod,
2989         .clk            = "ocp_abe_iclk",
2990         .addr           = omap44xx_mcbsp2_dma_addrs,
2991         .user           = OCP_USER_SDMA,
2992 };
2993
2994 /* mcbsp2 slave ports */
2995 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
2996         &omap44xx_l4_abe__mcbsp2,
2997         &omap44xx_l4_abe__mcbsp2_dma,
2998 };
2999
3000 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
3001         { .role = "pad_fck", .clk = "pad_clks_ck" },
3002         { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" },
3003 };
3004
3005 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3006         .name           = "mcbsp2",
3007         .class          = &omap44xx_mcbsp_hwmod_class,
3008         .clkdm_name     = "abe_clkdm",
3009         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3010         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3011         .main_clk       = "mcbsp2_fck",
3012         .prcm = {
3013                 .omap4 = {
3014                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3015                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3016                         .modulemode   = MODULEMODE_SWCTRL,
3017                 },
3018         },
3019         .slaves         = omap44xx_mcbsp2_slaves,
3020         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3021         .opt_clks       = mcbsp2_opt_clks,
3022         .opt_clks_cnt   = ARRAY_SIZE(mcbsp2_opt_clks),
3023 };
3024
3025 /* mcbsp3 */
3026 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3027 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3028         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3029         { .irq = -1 }
3030 };
3031
3032 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3033         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3034         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3035         { .dma_req = -1 }
3036 };
3037
3038 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3039         {
3040                 .name           = "mpu",
3041                 .pa_start       = 0x40126000,
3042                 .pa_end         = 0x401260ff,
3043                 .flags          = ADDR_TYPE_RT
3044         },
3045         { }
3046 };
3047
3048 /* l4_abe -> mcbsp3 */
3049 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3050         .master         = &omap44xx_l4_abe_hwmod,
3051         .slave          = &omap44xx_mcbsp3_hwmod,
3052         .clk            = "ocp_abe_iclk",
3053         .addr           = omap44xx_mcbsp3_addrs,
3054         .user           = OCP_USER_MPU,
3055 };
3056
3057 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3058         {
3059                 .name           = "dma",
3060                 .pa_start       = 0x49026000,
3061                 .pa_end         = 0x490260ff,
3062                 .flags          = ADDR_TYPE_RT
3063         },
3064         { }
3065 };
3066
3067 /* l4_abe -> mcbsp3 (dma) */
3068 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3069         .master         = &omap44xx_l4_abe_hwmod,
3070         .slave          = &omap44xx_mcbsp3_hwmod,
3071         .clk            = "ocp_abe_iclk",
3072         .addr           = omap44xx_mcbsp3_dma_addrs,
3073         .user           = OCP_USER_SDMA,
3074 };
3075
3076 /* mcbsp3 slave ports */
3077 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3078         &omap44xx_l4_abe__mcbsp3,
3079         &omap44xx_l4_abe__mcbsp3_dma,
3080 };
3081
3082 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
3083         { .role = "pad_fck", .clk = "pad_clks_ck" },
3084         { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" },
3085 };
3086
3087 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3088         .name           = "mcbsp3",
3089         .class          = &omap44xx_mcbsp_hwmod_class,
3090         .clkdm_name     = "abe_clkdm",
3091         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3092         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3093         .main_clk       = "mcbsp3_fck",
3094         .prcm = {
3095                 .omap4 = {
3096                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3097                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3098                         .modulemode   = MODULEMODE_SWCTRL,
3099                 },
3100         },
3101         .slaves         = omap44xx_mcbsp3_slaves,
3102         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3103         .opt_clks       = mcbsp3_opt_clks,
3104         .opt_clks_cnt   = ARRAY_SIZE(mcbsp3_opt_clks),
3105 };
3106
3107 /* mcbsp4 */
3108 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3109 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3110         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3111         { .irq = -1 }
3112 };
3113
3114 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3115         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3116         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3117         { .dma_req = -1 }
3118 };
3119
3120 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3121         {
3122                 .pa_start       = 0x48096000,
3123                 .pa_end         = 0x480960ff,
3124                 .flags          = ADDR_TYPE_RT
3125         },
3126         { }
3127 };
3128
3129 /* l4_per -> mcbsp4 */
3130 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3131         .master         = &omap44xx_l4_per_hwmod,
3132         .slave          = &omap44xx_mcbsp4_hwmod,
3133         .clk            = "l4_div_ck",
3134         .addr           = omap44xx_mcbsp4_addrs,
3135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3136 };
3137
3138 /* mcbsp4 slave ports */
3139 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3140         &omap44xx_l4_per__mcbsp4,
3141 };
3142
3143 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
3144         { .role = "pad_fck", .clk = "pad_clks_ck" },
3145         { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" },
3146 };
3147
3148 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3149         .name           = "mcbsp4",
3150         .class          = &omap44xx_mcbsp_hwmod_class,
3151         .clkdm_name     = "l4_per_clkdm",
3152         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3153         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3154         .main_clk       = "mcbsp4_fck",
3155         .prcm = {
3156                 .omap4 = {
3157                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3158                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3159                         .modulemode   = MODULEMODE_SWCTRL,
3160                 },
3161         },
3162         .slaves         = omap44xx_mcbsp4_slaves,
3163         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3164         .opt_clks       = mcbsp4_opt_clks,
3165         .opt_clks_cnt   = ARRAY_SIZE(mcbsp4_opt_clks),
3166 };
3167
3168 /*
3169  * 'mcpdm' class
3170  * multi channel pdm controller (proprietary interface with phoenix power
3171  * ic)
3172  */
3173
3174 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3175         .rev_offs       = 0x0000,
3176         .sysc_offs      = 0x0010,
3177         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3178                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3179         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3180                            SIDLE_SMART_WKUP),
3181         .sysc_fields    = &omap_hwmod_sysc_type2,
3182 };
3183
3184 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3185         .name   = "mcpdm",
3186         .sysc   = &omap44xx_mcpdm_sysc,
3187 };
3188
3189 /* mcpdm */
3190 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3191 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3192         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3193         { .irq = -1 }
3194 };
3195
3196 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3197         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3198         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3199         { .dma_req = -1 }
3200 };
3201
3202 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3203         {
3204                 .pa_start       = 0x40132000,
3205                 .pa_end         = 0x4013207f,
3206                 .flags          = ADDR_TYPE_RT
3207         },
3208         { }
3209 };
3210
3211 /* l4_abe -> mcpdm */
3212 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3213         .master         = &omap44xx_l4_abe_hwmod,
3214         .slave          = &omap44xx_mcpdm_hwmod,
3215         .clk            = "ocp_abe_iclk",
3216         .addr           = omap44xx_mcpdm_addrs,
3217         .user           = OCP_USER_MPU,
3218 };
3219
3220 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3221         {
3222                 .pa_start       = 0x49032000,
3223                 .pa_end         = 0x4903207f,
3224                 .flags          = ADDR_TYPE_RT
3225         },
3226         { }
3227 };
3228
3229 /* l4_abe -> mcpdm (dma) */
3230 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3231         .master         = &omap44xx_l4_abe_hwmod,
3232         .slave          = &omap44xx_mcpdm_hwmod,
3233         .clk            = "ocp_abe_iclk",
3234         .addr           = omap44xx_mcpdm_dma_addrs,
3235         .user           = OCP_USER_SDMA,
3236 };
3237
3238 /* mcpdm slave ports */
3239 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3240         &omap44xx_l4_abe__mcpdm,
3241         &omap44xx_l4_abe__mcpdm_dma,
3242 };
3243
3244 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3245         .name           = "mcpdm",
3246         .class          = &omap44xx_mcpdm_hwmod_class,
3247         .clkdm_name     = "abe_clkdm",
3248         .mpu_irqs       = omap44xx_mcpdm_irqs,
3249         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3250         .main_clk       = "mcpdm_fck",
3251         .prcm = {
3252                 .omap4 = {
3253                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3254                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3255                         .modulemode   = MODULEMODE_SWCTRL,
3256                 },
3257         },
3258         .slaves         = omap44xx_mcpdm_slaves,
3259         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3260 };
3261
3262 /*
3263  * 'mcspi' class
3264  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3265  * bus
3266  */
3267
3268 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3269         .rev_offs       = 0x0000,
3270         .sysc_offs      = 0x0010,
3271         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3272                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3273         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3274                            SIDLE_SMART_WKUP),
3275         .sysc_fields    = &omap_hwmod_sysc_type2,
3276 };
3277
3278 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3279         .name   = "mcspi",
3280         .sysc   = &omap44xx_mcspi_sysc,
3281         .rev    = OMAP4_MCSPI_REV,
3282 };
3283
3284 /* mcspi1 */
3285 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3286 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3287         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3288         { .irq = -1 }
3289 };
3290
3291 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3292         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3293         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3294         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3295         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3296         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3297         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3298         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3299         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3300         { .dma_req = -1 }
3301 };
3302
3303 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3304         {
3305                 .pa_start       = 0x48098000,
3306                 .pa_end         = 0x480981ff,
3307                 .flags          = ADDR_TYPE_RT
3308         },
3309         { }
3310 };
3311
3312 /* l4_per -> mcspi1 */
3313 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3314         .master         = &omap44xx_l4_per_hwmod,
3315         .slave          = &omap44xx_mcspi1_hwmod,
3316         .clk            = "l4_div_ck",
3317         .addr           = omap44xx_mcspi1_addrs,
3318         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3319 };
3320
3321 /* mcspi1 slave ports */
3322 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3323         &omap44xx_l4_per__mcspi1,
3324 };
3325
3326 /* mcspi1 dev_attr */
3327 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3328         .num_chipselect = 4,
3329 };
3330
3331 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3332         .name           = "mcspi1",
3333         .class          = &omap44xx_mcspi_hwmod_class,
3334         .clkdm_name     = "l4_per_clkdm",
3335         .mpu_irqs       = omap44xx_mcspi1_irqs,
3336         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3337         .main_clk       = "mcspi1_fck",
3338         .prcm = {
3339                 .omap4 = {
3340                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3341                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3342                         .modulemode   = MODULEMODE_SWCTRL,
3343                 },
3344         },
3345         .dev_attr       = &mcspi1_dev_attr,
3346         .slaves         = omap44xx_mcspi1_slaves,
3347         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3348 };
3349
3350 /* mcspi2 */
3351 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3352 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3353         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3354         { .irq = -1 }
3355 };
3356
3357 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3358         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3359         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3360         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3361         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3362         { .dma_req = -1 }
3363 };
3364
3365 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3366         {
3367                 .pa_start       = 0x4809a000,
3368                 .pa_end         = 0x4809a1ff,
3369                 .flags          = ADDR_TYPE_RT
3370         },
3371         { }
3372 };
3373
3374 /* l4_per -> mcspi2 */
3375 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3376         .master         = &omap44xx_l4_per_hwmod,
3377         .slave          = &omap44xx_mcspi2_hwmod,
3378         .clk            = "l4_div_ck",
3379         .addr           = omap44xx_mcspi2_addrs,
3380         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3381 };
3382
3383 /* mcspi2 slave ports */
3384 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3385         &omap44xx_l4_per__mcspi2,
3386 };
3387
3388 /* mcspi2 dev_attr */
3389 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3390         .num_chipselect = 2,
3391 };
3392
3393 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3394         .name           = "mcspi2",
3395         .class          = &omap44xx_mcspi_hwmod_class,
3396         .clkdm_name     = "l4_per_clkdm",
3397         .mpu_irqs       = omap44xx_mcspi2_irqs,
3398         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3399         .main_clk       = "mcspi2_fck",
3400         .prcm = {
3401                 .omap4 = {
3402                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3403                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3404                         .modulemode   = MODULEMODE_SWCTRL,
3405                 },
3406         },
3407         .dev_attr       = &mcspi2_dev_attr,
3408         .slaves         = omap44xx_mcspi2_slaves,
3409         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3410 };
3411
3412 /* mcspi3 */
3413 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3414 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3415         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3416         { .irq = -1 }
3417 };
3418
3419 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3420         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3421         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3422         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3423         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3424         { .dma_req = -1 }
3425 };
3426
3427 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3428         {
3429                 .pa_start       = 0x480b8000,
3430                 .pa_end         = 0x480b81ff,
3431                 .flags          = ADDR_TYPE_RT
3432         },
3433         { }
3434 };
3435
3436 /* l4_per -> mcspi3 */
3437 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3438         .master         = &omap44xx_l4_per_hwmod,
3439         .slave          = &omap44xx_mcspi3_hwmod,
3440         .clk            = "l4_div_ck",
3441         .addr           = omap44xx_mcspi3_addrs,
3442         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3443 };
3444
3445 /* mcspi3 slave ports */
3446 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3447         &omap44xx_l4_per__mcspi3,
3448 };
3449
3450 /* mcspi3 dev_attr */
3451 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3452         .num_chipselect = 2,
3453 };
3454
3455 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3456         .name           = "mcspi3",
3457         .class          = &omap44xx_mcspi_hwmod_class,
3458         .clkdm_name     = "l4_per_clkdm",
3459         .mpu_irqs       = omap44xx_mcspi3_irqs,
3460         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3461         .main_clk       = "mcspi3_fck",
3462         .prcm = {
3463                 .omap4 = {
3464                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3465                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3466                         .modulemode   = MODULEMODE_SWCTRL,
3467                 },
3468         },
3469         .dev_attr       = &mcspi3_dev_attr,
3470         .slaves         = omap44xx_mcspi3_slaves,
3471         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3472 };
3473
3474 /* mcspi4 */
3475 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3476 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3477         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3478         { .irq = -1 }
3479 };
3480
3481 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3482         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3483         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3484         { .dma_req = -1 }
3485 };
3486
3487 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3488         {
3489                 .pa_start       = 0x480ba000,
3490                 .pa_end         = 0x480ba1ff,
3491                 .flags          = ADDR_TYPE_RT
3492         },
3493         { }
3494 };
3495
3496 /* l4_per -> mcspi4 */
3497 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3498         .master         = &omap44xx_l4_per_hwmod,
3499         .slave          = &omap44xx_mcspi4_hwmod,
3500         .clk            = "l4_div_ck",
3501         .addr           = omap44xx_mcspi4_addrs,
3502         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3503 };
3504
3505 /* mcspi4 slave ports */
3506 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3507         &omap44xx_l4_per__mcspi4,
3508 };
3509
3510 /* mcspi4 dev_attr */
3511 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3512         .num_chipselect = 1,
3513 };
3514
3515 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3516         .name           = "mcspi4",
3517         .class          = &omap44xx_mcspi_hwmod_class,
3518         .clkdm_name     = "l4_per_clkdm",
3519         .mpu_irqs       = omap44xx_mcspi4_irqs,
3520         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3521         .main_clk       = "mcspi4_fck",
3522         .prcm = {
3523                 .omap4 = {
3524                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3525                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3526                         .modulemode   = MODULEMODE_SWCTRL,
3527                 },
3528         },
3529         .dev_attr       = &mcspi4_dev_attr,
3530         .slaves         = omap44xx_mcspi4_slaves,
3531         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3532 };
3533
3534 /*
3535  * 'mmc' class
3536  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3537  */
3538
3539 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3540         .rev_offs       = 0x0000,
3541         .sysc_offs      = 0x0010,
3542         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3543                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3544                            SYSC_HAS_SOFTRESET),
3545         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3546                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3547                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3548         .sysc_fields    = &omap_hwmod_sysc_type2,
3549 };
3550
3551 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3552         .name   = "mmc",
3553         .sysc   = &omap44xx_mmc_sysc,
3554 };
3555
3556 /* mmc1 */
3557 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3558         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3559         { .irq = -1 }
3560 };
3561
3562 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3563         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3564         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3565         { .dma_req = -1 }
3566 };
3567
3568 /* mmc1 master ports */
3569 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3570         &omap44xx_mmc1__l3_main_1,
3571 };
3572
3573 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3574         {
3575                 .pa_start       = 0x4809c000,
3576                 .pa_end         = 0x4809c3ff,
3577                 .flags          = ADDR_TYPE_RT
3578         },
3579         { }
3580 };
3581
3582 /* l4_per -> mmc1 */
3583 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3584         .master         = &omap44xx_l4_per_hwmod,
3585         .slave          = &omap44xx_mmc1_hwmod,
3586         .clk            = "l4_div_ck",
3587         .addr           = omap44xx_mmc1_addrs,
3588         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3589 };
3590
3591 /* mmc1 slave ports */
3592 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3593         &omap44xx_l4_per__mmc1,
3594 };
3595
3596 /* mmc1 dev_attr */
3597 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3598         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3599 };
3600
3601 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3602         .name           = "mmc1",
3603         .class          = &omap44xx_mmc_hwmod_class,
3604         .clkdm_name     = "l3_init_clkdm",
3605         .mpu_irqs       = omap44xx_mmc1_irqs,
3606         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3607         .main_clk       = "mmc1_fck",
3608         .prcm = {
3609                 .omap4 = {
3610                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3611                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3612                         .modulemode   = MODULEMODE_SWCTRL,
3613                 },
3614         },
3615         .dev_attr       = &mmc1_dev_attr,
3616         .slaves         = omap44xx_mmc1_slaves,
3617         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3618         .masters        = omap44xx_mmc1_masters,
3619         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3620 };
3621
3622 /* mmc2 */
3623 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3624         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3625         { .irq = -1 }
3626 };
3627
3628 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3629         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3630         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3631         { .dma_req = -1 }
3632 };
3633
3634 /* mmc2 master ports */
3635 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3636         &omap44xx_mmc2__l3_main_1,
3637 };
3638
3639 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3640         {
3641                 .pa_start       = 0x480b4000,
3642                 .pa_end         = 0x480b43ff,
3643                 .flags          = ADDR_TYPE_RT
3644         },
3645         { }
3646 };
3647
3648 /* l4_per -> mmc2 */
3649 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3650         .master         = &omap44xx_l4_per_hwmod,
3651         .slave          = &omap44xx_mmc2_hwmod,
3652         .clk            = "l4_div_ck",
3653         .addr           = omap44xx_mmc2_addrs,
3654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3655 };
3656
3657 /* mmc2 slave ports */
3658 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3659         &omap44xx_l4_per__mmc2,
3660 };
3661
3662 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3663         .name           = "mmc2",
3664         .class          = &omap44xx_mmc_hwmod_class,
3665         .clkdm_name     = "l3_init_clkdm",
3666         .mpu_irqs       = omap44xx_mmc2_irqs,
3667         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3668         .main_clk       = "mmc2_fck",
3669         .prcm = {
3670                 .omap4 = {
3671                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3672                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3673                         .modulemode   = MODULEMODE_SWCTRL,
3674                 },
3675         },
3676         .slaves         = omap44xx_mmc2_slaves,
3677         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3678         .masters        = omap44xx_mmc2_masters,
3679         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3680 };
3681
3682 /* mmc3 */
3683 static struct omap_hwmod omap44xx_mmc3_hwmod;
3684 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3685         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3686         { .irq = -1 }
3687 };
3688
3689 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3690         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3691         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3692         { .dma_req = -1 }
3693 };
3694
3695 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3696         {
3697                 .pa_start       = 0x480ad000,
3698                 .pa_end         = 0x480ad3ff,
3699                 .flags          = ADDR_TYPE_RT
3700         },
3701         { }
3702 };
3703
3704 /* l4_per -> mmc3 */
3705 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3706         .master         = &omap44xx_l4_per_hwmod,
3707         .slave          = &omap44xx_mmc3_hwmod,
3708         .clk            = "l4_div_ck",
3709         .addr           = omap44xx_mmc3_addrs,
3710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3711 };
3712
3713 /* mmc3 slave ports */
3714 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3715         &omap44xx_l4_per__mmc3,
3716 };
3717
3718 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3719         .name           = "mmc3",
3720         .class          = &omap44xx_mmc_hwmod_class,
3721         .clkdm_name     = "l4_per_clkdm",
3722         .mpu_irqs       = omap44xx_mmc3_irqs,
3723         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3724         .main_clk       = "mmc3_fck",
3725         .prcm = {
3726                 .omap4 = {
3727                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3728                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3729                         .modulemode   = MODULEMODE_SWCTRL,
3730                 },
3731         },
3732         .slaves         = omap44xx_mmc3_slaves,
3733         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3734 };
3735
3736 /* mmc4 */
3737 static struct omap_hwmod omap44xx_mmc4_hwmod;
3738 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3739         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3740         { .irq = -1 }
3741 };
3742
3743 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3744         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3745         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3746         { .dma_req = -1 }
3747 };
3748
3749 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3750         {
3751                 .pa_start       = 0x480d1000,
3752                 .pa_end         = 0x480d13ff,
3753                 .flags          = ADDR_TYPE_RT
3754         },
3755         { }
3756 };
3757
3758 /* l4_per -> mmc4 */
3759 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3760         .master         = &omap44xx_l4_per_hwmod,
3761         .slave          = &omap44xx_mmc4_hwmod,
3762         .clk            = "l4_div_ck",
3763         .addr           = omap44xx_mmc4_addrs,
3764         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3765 };
3766
3767 /* mmc4 slave ports */
3768 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3769         &omap44xx_l4_per__mmc4,
3770 };
3771
3772 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3773         .name           = "mmc4",
3774         .class          = &omap44xx_mmc_hwmod_class,
3775         .clkdm_name     = "l4_per_clkdm",
3776         .mpu_irqs       = omap44xx_mmc4_irqs,
3777
3778         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3779         .main_clk       = "mmc4_fck",
3780         .prcm = {
3781                 .omap4 = {
3782                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3783                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3784                         .modulemode   = MODULEMODE_SWCTRL,
3785                 },
3786         },
3787         .slaves         = omap44xx_mmc4_slaves,
3788         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3789 };
3790
3791 /* mmc5 */
3792 static struct omap_hwmod omap44xx_mmc5_hwmod;
3793 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3794         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3795         { .irq = -1 }
3796 };
3797
3798 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3799         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3800         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3801         { .dma_req = -1 }
3802 };
3803
3804 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3805         {
3806                 .pa_start       = 0x480d5000,
3807                 .pa_end         = 0x480d53ff,
3808                 .flags          = ADDR_TYPE_RT
3809         },
3810         { }
3811 };
3812
3813 /* l4_per -> mmc5 */
3814 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3815         .master         = &omap44xx_l4_per_hwmod,
3816         .slave          = &omap44xx_mmc5_hwmod,
3817         .clk            = "l4_div_ck",
3818         .addr           = omap44xx_mmc5_addrs,
3819         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3820 };
3821
3822 /* mmc5 slave ports */
3823 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3824         &omap44xx_l4_per__mmc5,
3825 };
3826
3827 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3828         .name           = "mmc5",
3829         .class          = &omap44xx_mmc_hwmod_class,
3830         .clkdm_name     = "l4_per_clkdm",
3831         .mpu_irqs       = omap44xx_mmc5_irqs,
3832         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3833         .main_clk       = "mmc5_fck",
3834         .prcm = {
3835                 .omap4 = {
3836                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3837                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3838                         .modulemode   = MODULEMODE_SWCTRL,
3839                 },
3840         },
3841         .slaves         = omap44xx_mmc5_slaves,
3842         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3843 };
3844
3845 /*
3846  * 'mpu' class
3847  * mpu sub-system
3848  */
3849
3850 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3851         .name   = "mpu",
3852 };
3853
3854 /* mpu */
3855 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3856         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3857         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3858         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3859         { .irq = -1 }
3860 };
3861
3862 /* mpu master ports */
3863 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3864         &omap44xx_mpu__l3_main_1,
3865         &omap44xx_mpu__l4_abe,
3866         &omap44xx_mpu__dmm,
3867 };
3868
3869 static struct omap_hwmod omap44xx_mpu_hwmod = {
3870         .name           = "mpu",
3871         .class          = &omap44xx_mpu_hwmod_class,
3872         .clkdm_name     = "mpuss_clkdm",
3873         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3874         .mpu_irqs       = omap44xx_mpu_irqs,
3875         .main_clk       = "dpll_mpu_m2_ck",
3876         .prcm = {
3877                 .omap4 = {
3878                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3879                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3880                 },
3881         },
3882         .masters        = omap44xx_mpu_masters,
3883         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3884 };
3885
3886 /*
3887  * 'smartreflex' class
3888  * smartreflex module (monitor silicon performance and outputs a measure of
3889  * performance error)
3890  */
3891
3892 /* The IP is not compliant to type1 / type2 scheme */
3893 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3894         .sidle_shift    = 24,
3895         .enwkup_shift   = 26,
3896 };
3897
3898 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3899         .sysc_offs      = 0x0038,
3900         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3901         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3902                            SIDLE_SMART_WKUP),
3903         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3904 };
3905
3906 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3907         .name   = "smartreflex",
3908         .sysc   = &omap44xx_smartreflex_sysc,
3909         .rev    = 2,
3910 };
3911
3912 /* smartreflex_core */
3913 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
3914         .sensor_voltdm_name   = "core",
3915 };
3916
3917 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3918 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3919         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3920         { .irq = -1 }
3921 };
3922
3923 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3924         {
3925                 .pa_start       = 0x4a0dd000,
3926                 .pa_end         = 0x4a0dd03f,
3927                 .flags          = ADDR_TYPE_RT
3928         },
3929         { }
3930 };
3931
3932 /* l4_cfg -> smartreflex_core */
3933 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3934         .master         = &omap44xx_l4_cfg_hwmod,
3935         .slave          = &omap44xx_smartreflex_core_hwmod,
3936         .clk            = "l4_div_ck",
3937         .addr           = omap44xx_smartreflex_core_addrs,
3938         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3939 };
3940
3941 /* smartreflex_core slave ports */
3942 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3943         &omap44xx_l4_cfg__smartreflex_core,
3944 };
3945
3946 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3947         .name           = "smartreflex_core",
3948         .class          = &omap44xx_smartreflex_hwmod_class,
3949         .clkdm_name     = "l4_ao_clkdm",
3950         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
3951
3952         .main_clk       = "smartreflex_core_fck",
3953         .prcm = {
3954                 .omap4 = {
3955                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
3956                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
3957                         .modulemode   = MODULEMODE_SWCTRL,
3958                 },
3959         },
3960         .slaves         = omap44xx_smartreflex_core_slaves,
3961         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
3962         .dev_attr       = &smartreflex_core_dev_attr,
3963 };
3964
3965 /* smartreflex_iva */
3966 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
3967         .sensor_voltdm_name     = "iva",
3968 };
3969
3970 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
3971 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
3972         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
3973         { .irq = -1 }
3974 };
3975
3976 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
3977         {
3978                 .pa_start       = 0x4a0db000,
3979                 .pa_end         = 0x4a0db03f,
3980                 .flags          = ADDR_TYPE_RT
3981         },
3982         { }
3983 };
3984
3985 /* l4_cfg -> smartreflex_iva */
3986 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3987         .master         = &omap44xx_l4_cfg_hwmod,
3988         .slave          = &omap44xx_smartreflex_iva_hwmod,
3989         .clk            = "l4_div_ck",
3990         .addr           = omap44xx_smartreflex_iva_addrs,
3991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3993
3994 /* smartreflex_iva slave ports */
3995 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
3996         &omap44xx_l4_cfg__smartreflex_iva,
3997 };
3998
3999 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4000         .name           = "smartreflex_iva",
4001         .class          = &omap44xx_smartreflex_hwmod_class,
4002         .clkdm_name     = "l4_ao_clkdm",
4003         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4004         .main_clk       = "smartreflex_iva_fck",
4005         .prcm = {
4006                 .omap4 = {
4007                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4008                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4009                         .modulemode   = MODULEMODE_SWCTRL,
4010                 },
4011         },
4012         .slaves         = omap44xx_smartreflex_iva_slaves,
4013         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4014         .dev_attr       = &smartreflex_iva_dev_attr,
4015 };
4016
4017 /* smartreflex_mpu */
4018 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4019         .sensor_voltdm_name     = "mpu",
4020 };
4021
4022 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4023 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4024         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4025         { .irq = -1 }
4026 };
4027
4028 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4029         {
4030                 .pa_start       = 0x4a0d9000,
4031                 .pa_end         = 0x4a0d903f,
4032                 .flags          = ADDR_TYPE_RT
4033         },
4034         { }
4035 };
4036
4037 /* l4_cfg -> smartreflex_mpu */
4038 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4039         .master         = &omap44xx_l4_cfg_hwmod,
4040         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4041         .clk            = "l4_div_ck",
4042         .addr           = omap44xx_smartreflex_mpu_addrs,
4043         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4044 };
4045
4046 /* smartreflex_mpu slave ports */
4047 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4048         &omap44xx_l4_cfg__smartreflex_mpu,
4049 };
4050
4051 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4052         .name           = "smartreflex_mpu",
4053         .class          = &omap44xx_smartreflex_hwmod_class,
4054         .clkdm_name     = "l4_ao_clkdm",
4055         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4056         .main_clk       = "smartreflex_mpu_fck",
4057         .prcm = {
4058                 .omap4 = {
4059                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4060                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4061                         .modulemode   = MODULEMODE_SWCTRL,
4062                 },
4063         },
4064         .slaves         = omap44xx_smartreflex_mpu_slaves,
4065         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4066         .dev_attr       = &smartreflex_mpu_dev_attr,
4067 };
4068
4069 /*
4070  * 'spinlock' class
4071  * spinlock provides hardware assistance for synchronizing the processes
4072  * running on multiple processors
4073  */
4074
4075 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4076         .rev_offs       = 0x0000,
4077         .sysc_offs      = 0x0010,
4078         .syss_offs      = 0x0014,
4079         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4080                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4081                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4082         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4083                            SIDLE_SMART_WKUP),
4084         .sysc_fields    = &omap_hwmod_sysc_type1,
4085 };
4086
4087 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4088         .name   = "spinlock",
4089         .sysc   = &omap44xx_spinlock_sysc,
4090 };
4091
4092 /* spinlock */
4093 static struct omap_hwmod omap44xx_spinlock_hwmod;
4094 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4095         {
4096                 .pa_start       = 0x4a0f6000,
4097                 .pa_end         = 0x4a0f6fff,
4098                 .flags          = ADDR_TYPE_RT
4099         },
4100         { }
4101 };
4102
4103 /* l4_cfg -> spinlock */
4104 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4105         .master         = &omap44xx_l4_cfg_hwmod,
4106         .slave          = &omap44xx_spinlock_hwmod,
4107         .clk            = "l4_div_ck",
4108         .addr           = omap44xx_spinlock_addrs,
4109         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4110 };
4111
4112 /* spinlock slave ports */
4113 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4114         &omap44xx_l4_cfg__spinlock,
4115 };
4116
4117 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4118         .name           = "spinlock",
4119         .class          = &omap44xx_spinlock_hwmod_class,
4120         .clkdm_name     = "l4_cfg_clkdm",
4121         .prcm = {
4122                 .omap4 = {
4123                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4124                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4125                 },
4126         },
4127         .slaves         = omap44xx_spinlock_slaves,
4128         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4129 };
4130
4131 /*
4132  * 'timer' class
4133  * general purpose timer module with accurate 1ms tick
4134  * This class contains several variants: ['timer_1ms', 'timer']
4135  */
4136
4137 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4138         .rev_offs       = 0x0000,
4139         .sysc_offs      = 0x0010,
4140         .syss_offs      = 0x0014,
4141         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4142                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4143                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4144                            SYSS_HAS_RESET_STATUS),
4145         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4146         .sysc_fields    = &omap_hwmod_sysc_type1,
4147 };
4148
4149 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4150         .name   = "timer",
4151         .sysc   = &omap44xx_timer_1ms_sysc,
4152 };
4153
4154 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4155         .rev_offs       = 0x0000,
4156         .sysc_offs      = 0x0010,
4157         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4158                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4159         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4160                            SIDLE_SMART_WKUP),
4161         .sysc_fields    = &omap_hwmod_sysc_type2,
4162 };
4163
4164 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4165         .name   = "timer",
4166         .sysc   = &omap44xx_timer_sysc,
4167 };
4168
4169 /* always-on timers dev attribute */
4170 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4171         .timer_capability       = OMAP_TIMER_ALWON,
4172 };
4173
4174 /* pwm timers dev attribute */
4175 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4176         .timer_capability       = OMAP_TIMER_HAS_PWM,
4177 };
4178
4179 /* timer1 */
4180 static struct omap_hwmod omap44xx_timer1_hwmod;
4181 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4182         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4183         { .irq = -1 }
4184 };
4185
4186 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4187         {
4188                 .pa_start       = 0x4a318000,
4189                 .pa_end         = 0x4a31807f,
4190                 .flags          = ADDR_TYPE_RT
4191         },
4192         { }
4193 };
4194
4195 /* l4_wkup -> timer1 */
4196 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4197         .master         = &omap44xx_l4_wkup_hwmod,
4198         .slave          = &omap44xx_timer1_hwmod,
4199         .clk            = "l4_wkup_clk_mux_ck",
4200         .addr           = omap44xx_timer1_addrs,
4201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4202 };
4203
4204 /* timer1 slave ports */
4205 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4206         &omap44xx_l4_wkup__timer1,
4207 };
4208
4209 static struct omap_hwmod omap44xx_timer1_hwmod = {
4210         .name           = "timer1",
4211         .class          = &omap44xx_timer_1ms_hwmod_class,
4212         .clkdm_name     = "l4_wkup_clkdm",
4213         .mpu_irqs       = omap44xx_timer1_irqs,
4214         .main_clk       = "timer1_fck",
4215         .prcm = {
4216                 .omap4 = {
4217                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4218                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4219                         .modulemode   = MODULEMODE_SWCTRL,
4220                 },
4221         },
4222         .dev_attr       = &capability_alwon_dev_attr,
4223         .slaves         = omap44xx_timer1_slaves,
4224         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4225 };
4226
4227 /* timer2 */
4228 static struct omap_hwmod omap44xx_timer2_hwmod;
4229 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4230         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4231         { .irq = -1 }
4232 };
4233
4234 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4235         {
4236                 .pa_start       = 0x48032000,
4237                 .pa_end         = 0x4803207f,
4238                 .flags          = ADDR_TYPE_RT
4239         },
4240         { }
4241 };
4242
4243 /* l4_per -> timer2 */
4244 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4245         .master         = &omap44xx_l4_per_hwmod,
4246         .slave          = &omap44xx_timer2_hwmod,
4247         .clk            = "l4_div_ck",
4248         .addr           = omap44xx_timer2_addrs,
4249         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4250 };
4251
4252 /* timer2 slave ports */
4253 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4254         &omap44xx_l4_per__timer2,
4255 };
4256
4257 static struct omap_hwmod omap44xx_timer2_hwmod = {
4258         .name           = "timer2",
4259         .class          = &omap44xx_timer_1ms_hwmod_class,
4260         .clkdm_name     = "l4_per_clkdm",
4261         .mpu_irqs       = omap44xx_timer2_irqs,
4262         .main_clk       = "timer2_fck",
4263         .prcm = {
4264                 .omap4 = {
4265                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4266                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4267                         .modulemode   = MODULEMODE_SWCTRL,
4268                 },
4269         },
4270         .dev_attr       = &capability_alwon_dev_attr,
4271         .slaves         = omap44xx_timer2_slaves,
4272         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4273 };
4274
4275 /* timer3 */
4276 static struct omap_hwmod omap44xx_timer3_hwmod;
4277 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4278         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4279         { .irq = -1 }
4280 };
4281
4282 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4283         {
4284                 .pa_start       = 0x48034000,
4285                 .pa_end         = 0x4803407f,
4286                 .flags          = ADDR_TYPE_RT
4287         },
4288         { }
4289 };
4290
4291 /* l4_per -> timer3 */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4293         .master         = &omap44xx_l4_per_hwmod,
4294         .slave          = &omap44xx_timer3_hwmod,
4295         .clk            = "l4_div_ck",
4296         .addr           = omap44xx_timer3_addrs,
4297         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4298 };
4299
4300 /* timer3 slave ports */
4301 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4302         &omap44xx_l4_per__timer3,
4303 };
4304
4305 static struct omap_hwmod omap44xx_timer3_hwmod = {
4306         .name           = "timer3",
4307         .class          = &omap44xx_timer_hwmod_class,
4308         .clkdm_name     = "l4_per_clkdm",
4309         .mpu_irqs       = omap44xx_timer3_irqs,
4310         .main_clk       = "timer3_fck",
4311         .prcm = {
4312                 .omap4 = {
4313                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4314                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4315                         .modulemode   = MODULEMODE_SWCTRL,
4316                 },
4317         },
4318         .dev_attr       = &capability_alwon_dev_attr,
4319         .slaves         = omap44xx_timer3_slaves,
4320         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4321 };
4322
4323 /* timer4 */
4324 static struct omap_hwmod omap44xx_timer4_hwmod;
4325 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4326         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4327         { .irq = -1 }
4328 };
4329
4330 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4331         {
4332                 .pa_start       = 0x48036000,
4333                 .pa_end         = 0x4803607f,
4334                 .flags          = ADDR_TYPE_RT
4335         },
4336         { }
4337 };
4338
4339 /* l4_per -> timer4 */
4340 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4341         .master         = &omap44xx_l4_per_hwmod,
4342         .slave          = &omap44xx_timer4_hwmod,
4343         .clk            = "l4_div_ck",
4344         .addr           = omap44xx_timer4_addrs,
4345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4346 };
4347
4348 /* timer4 slave ports */
4349 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4350         &omap44xx_l4_per__timer4,
4351 };
4352
4353 static struct omap_hwmod omap44xx_timer4_hwmod = {
4354         .name           = "timer4",
4355         .class          = &omap44xx_timer_hwmod_class,
4356         .clkdm_name     = "l4_per_clkdm",
4357         .mpu_irqs       = omap44xx_timer4_irqs,
4358         .main_clk       = "timer4_fck",
4359         .prcm = {
4360                 .omap4 = {
4361                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4362                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4363                         .modulemode   = MODULEMODE_SWCTRL,
4364                 },
4365         },
4366         .dev_attr       = &capability_alwon_dev_attr,
4367         .slaves         = omap44xx_timer4_slaves,
4368         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4369 };
4370
4371 /* timer5 */
4372 static struct omap_hwmod omap44xx_timer5_hwmod;
4373 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4374         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4375         { .irq = -1 }
4376 };
4377
4378 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4379         {
4380                 .pa_start       = 0x40138000,
4381                 .pa_end         = 0x4013807f,
4382                 .flags          = ADDR_TYPE_RT
4383         },
4384         { }
4385 };
4386
4387 /* l4_abe -> timer5 */
4388 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4389         .master         = &omap44xx_l4_abe_hwmod,
4390         .slave          = &omap44xx_timer5_hwmod,
4391         .clk            = "ocp_abe_iclk",
4392         .addr           = omap44xx_timer5_addrs,
4393         .user           = OCP_USER_MPU,
4394 };
4395
4396 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4397         {
4398                 .pa_start       = 0x49038000,
4399                 .pa_end         = 0x4903807f,
4400                 .flags          = ADDR_TYPE_RT
4401         },
4402         { }
4403 };
4404
4405 /* l4_abe -> timer5 (dma) */
4406 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4407         .master         = &omap44xx_l4_abe_hwmod,
4408         .slave          = &omap44xx_timer5_hwmod,
4409         .clk            = "ocp_abe_iclk",
4410         .addr           = omap44xx_timer5_dma_addrs,
4411         .user           = OCP_USER_SDMA,
4412 };
4413
4414 /* timer5 slave ports */
4415 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4416         &omap44xx_l4_abe__timer5,
4417         &omap44xx_l4_abe__timer5_dma,
4418 };
4419
4420 static struct omap_hwmod omap44xx_timer5_hwmod = {
4421         .name           = "timer5",
4422         .class          = &omap44xx_timer_hwmod_class,
4423         .clkdm_name     = "abe_clkdm",
4424         .mpu_irqs       = omap44xx_timer5_irqs,
4425         .main_clk       = "timer5_fck",
4426         .prcm = {
4427                 .omap4 = {
4428                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4429                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4430                         .modulemode   = MODULEMODE_SWCTRL,
4431                 },
4432         },
4433         .dev_attr       = &capability_alwon_dev_attr,
4434         .slaves         = omap44xx_timer5_slaves,
4435         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4436 };
4437
4438 /* timer6 */
4439 static struct omap_hwmod omap44xx_timer6_hwmod;
4440 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4441         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4442         { .irq = -1 }
4443 };
4444
4445 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4446         {
4447                 .pa_start       = 0x4013a000,
4448                 .pa_end         = 0x4013a07f,
4449                 .flags          = ADDR_TYPE_RT
4450         },
4451         { }
4452 };
4453
4454 /* l4_abe -> timer6 */
4455 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4456         .master         = &omap44xx_l4_abe_hwmod,
4457         .slave          = &omap44xx_timer6_hwmod,
4458         .clk            = "ocp_abe_iclk",
4459         .addr           = omap44xx_timer6_addrs,
4460         .user           = OCP_USER_MPU,
4461 };
4462
4463 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4464         {
4465                 .pa_start       = 0x4903a000,
4466                 .pa_end         = 0x4903a07f,
4467                 .flags          = ADDR_TYPE_RT
4468         },
4469         { }
4470 };
4471
4472 /* l4_abe -> timer6 (dma) */
4473 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4474         .master         = &omap44xx_l4_abe_hwmod,
4475         .slave          = &omap44xx_timer6_hwmod,
4476         .clk            = "ocp_abe_iclk",
4477         .addr           = omap44xx_timer6_dma_addrs,
4478         .user           = OCP_USER_SDMA,
4479 };
4480
4481 /* timer6 slave ports */
4482 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4483         &omap44xx_l4_abe__timer6,
4484         &omap44xx_l4_abe__timer6_dma,
4485 };
4486
4487 static struct omap_hwmod omap44xx_timer6_hwmod = {
4488         .name           = "timer6",
4489         .class          = &omap44xx_timer_hwmod_class,
4490         .clkdm_name     = "abe_clkdm",
4491         .mpu_irqs       = omap44xx_timer6_irqs,
4492
4493         .main_clk       = "timer6_fck",
4494         .prcm = {
4495                 .omap4 = {
4496                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4497                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4498                         .modulemode   = MODULEMODE_SWCTRL,
4499                 },
4500         },
4501         .dev_attr       = &capability_alwon_dev_attr,
4502         .slaves         = omap44xx_timer6_slaves,
4503         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4504 };
4505
4506 /* timer7 */
4507 static struct omap_hwmod omap44xx_timer7_hwmod;
4508 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4509         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4510         { .irq = -1 }
4511 };
4512
4513 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4514         {
4515                 .pa_start       = 0x4013c000,
4516                 .pa_end         = 0x4013c07f,
4517                 .flags          = ADDR_TYPE_RT
4518         },
4519         { }
4520 };
4521
4522 /* l4_abe -> timer7 */
4523 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4524         .master         = &omap44xx_l4_abe_hwmod,
4525         .slave          = &omap44xx_timer7_hwmod,
4526         .clk            = "ocp_abe_iclk",
4527         .addr           = omap44xx_timer7_addrs,
4528         .user           = OCP_USER_MPU,
4529 };
4530
4531 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4532         {
4533                 .pa_start       = 0x4903c000,
4534                 .pa_end         = 0x4903c07f,
4535                 .flags          = ADDR_TYPE_RT
4536         },
4537         { }
4538 };
4539
4540 /* l4_abe -> timer7 (dma) */
4541 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4542         .master         = &omap44xx_l4_abe_hwmod,
4543         .slave          = &omap44xx_timer7_hwmod,
4544         .clk            = "ocp_abe_iclk",
4545         .addr           = omap44xx_timer7_dma_addrs,
4546         .user           = OCP_USER_SDMA,
4547 };
4548
4549 /* timer7 slave ports */
4550 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4551         &omap44xx_l4_abe__timer7,
4552         &omap44xx_l4_abe__timer7_dma,
4553 };
4554
4555 static struct omap_hwmod omap44xx_timer7_hwmod = {
4556         .name           = "timer7",
4557         .class          = &omap44xx_timer_hwmod_class,
4558         .clkdm_name     = "abe_clkdm",
4559         .mpu_irqs       = omap44xx_timer7_irqs,
4560         .main_clk       = "timer7_fck",
4561         .prcm = {
4562                 .omap4 = {
4563                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4564                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4565                         .modulemode   = MODULEMODE_SWCTRL,
4566                 },
4567         },
4568         .dev_attr       = &capability_alwon_dev_attr,
4569         .slaves         = omap44xx_timer7_slaves,
4570         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4571 };
4572
4573 /* timer8 */
4574 static struct omap_hwmod omap44xx_timer8_hwmod;
4575 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4576         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4577         { .irq = -1 }
4578 };
4579
4580 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4581         {
4582                 .pa_start       = 0x4013e000,
4583                 .pa_end         = 0x4013e07f,
4584                 .flags          = ADDR_TYPE_RT
4585         },
4586         { }
4587 };
4588
4589 /* l4_abe -> timer8 */
4590 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4591         .master         = &omap44xx_l4_abe_hwmod,
4592         .slave          = &omap44xx_timer8_hwmod,
4593         .clk            = "ocp_abe_iclk",
4594         .addr           = omap44xx_timer8_addrs,
4595         .user           = OCP_USER_MPU,
4596 };
4597
4598 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4599         {
4600                 .pa_start       = 0x4903e000,
4601                 .pa_end         = 0x4903e07f,
4602                 .flags          = ADDR_TYPE_RT
4603         },
4604         { }
4605 };
4606
4607 /* l4_abe -> timer8 (dma) */
4608 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4609         .master         = &omap44xx_l4_abe_hwmod,
4610         .slave          = &omap44xx_timer8_hwmod,
4611         .clk            = "ocp_abe_iclk",
4612         .addr           = omap44xx_timer8_dma_addrs,
4613         .user           = OCP_USER_SDMA,
4614 };
4615
4616 /* timer8 slave ports */
4617 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4618         &omap44xx_l4_abe__timer8,
4619         &omap44xx_l4_abe__timer8_dma,
4620 };
4621
4622 static struct omap_hwmod omap44xx_timer8_hwmod = {
4623         .name           = "timer8",
4624         .class          = &omap44xx_timer_hwmod_class,
4625         .clkdm_name     = "abe_clkdm",
4626         .mpu_irqs       = omap44xx_timer8_irqs,
4627         .main_clk       = "timer8_fck",
4628         .prcm = {
4629                 .omap4 = {
4630                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4631                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4632                         .modulemode   = MODULEMODE_SWCTRL,
4633                 },
4634         },
4635         .dev_attr       = &capability_pwm_dev_attr,
4636         .slaves         = omap44xx_timer8_slaves,
4637         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4638 };
4639
4640 /* timer9 */
4641 static struct omap_hwmod omap44xx_timer9_hwmod;
4642 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4643         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4644         { .irq = -1 }
4645 };
4646
4647 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4648         {
4649                 .pa_start       = 0x4803e000,
4650                 .pa_end         = 0x4803e07f,
4651                 .flags          = ADDR_TYPE_RT
4652         },
4653         { }
4654 };
4655
4656 /* l4_per -> timer9 */
4657 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4658         .master         = &omap44xx_l4_per_hwmod,
4659         .slave          = &omap44xx_timer9_hwmod,
4660         .clk            = "l4_div_ck",
4661         .addr           = omap44xx_timer9_addrs,
4662         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4663 };
4664
4665 /* timer9 slave ports */
4666 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4667         &omap44xx_l4_per__timer9,
4668 };
4669
4670 static struct omap_hwmod omap44xx_timer9_hwmod = {
4671         .name           = "timer9",
4672         .class          = &omap44xx_timer_hwmod_class,
4673         .clkdm_name     = "l4_per_clkdm",
4674         .mpu_irqs       = omap44xx_timer9_irqs,
4675         .main_clk       = "timer9_fck",
4676         .prcm = {
4677                 .omap4 = {
4678                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4679                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4680                         .modulemode   = MODULEMODE_SWCTRL,
4681                 },
4682         },
4683         .dev_attr       = &capability_pwm_dev_attr,
4684         .slaves         = omap44xx_timer9_slaves,
4685         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4686 };
4687
4688 /* timer10 */
4689 static struct omap_hwmod omap44xx_timer10_hwmod;
4690 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4691         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4692         { .irq = -1 }
4693 };
4694
4695 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4696         {
4697                 .pa_start       = 0x48086000,
4698                 .pa_end         = 0x4808607f,
4699                 .flags          = ADDR_TYPE_RT
4700         },
4701         { }
4702 };
4703
4704 /* l4_per -> timer10 */
4705 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4706         .master         = &omap44xx_l4_per_hwmod,
4707         .slave          = &omap44xx_timer10_hwmod,
4708         .clk            = "l4_div_ck",
4709         .addr           = omap44xx_timer10_addrs,
4710         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4711 };
4712
4713 /* timer10 slave ports */
4714 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4715         &omap44xx_l4_per__timer10,
4716 };
4717
4718 static struct omap_hwmod omap44xx_timer10_hwmod = {
4719         .name           = "timer10",
4720         .class          = &omap44xx_timer_1ms_hwmod_class,
4721         .clkdm_name     = "l4_per_clkdm",
4722         .mpu_irqs       = omap44xx_timer10_irqs,
4723         .main_clk       = "timer10_fck",
4724         .prcm = {
4725                 .omap4 = {
4726                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4727                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4728                         .modulemode   = MODULEMODE_SWCTRL,
4729                 },
4730         },
4731         .dev_attr       = &capability_pwm_dev_attr,
4732         .slaves         = omap44xx_timer10_slaves,
4733         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4734 };
4735
4736 /* timer11 */
4737 static struct omap_hwmod omap44xx_timer11_hwmod;
4738 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4739         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4740         { .irq = -1 }
4741 };
4742
4743 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4744         {
4745                 .pa_start       = 0x48088000,
4746                 .pa_end         = 0x4808807f,
4747                 .flags          = ADDR_TYPE_RT
4748         },
4749         { }
4750 };
4751
4752 /* l4_per -> timer11 */
4753 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4754         .master         = &omap44xx_l4_per_hwmod,
4755         .slave          = &omap44xx_timer11_hwmod,
4756         .clk            = "l4_div_ck",
4757         .addr           = omap44xx_timer11_addrs,
4758         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4759 };
4760
4761 /* timer11 slave ports */
4762 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4763         &omap44xx_l4_per__timer11,
4764 };
4765
4766 static struct omap_hwmod omap44xx_timer11_hwmod = {
4767         .name           = "timer11",
4768         .class          = &omap44xx_timer_hwmod_class,
4769         .clkdm_name     = "l4_per_clkdm",
4770         .mpu_irqs       = omap44xx_timer11_irqs,
4771         .main_clk       = "timer11_fck",
4772         .prcm = {
4773                 .omap4 = {
4774                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4775                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4776                         .modulemode   = MODULEMODE_SWCTRL,
4777                 },
4778         },
4779         .dev_attr       = &capability_pwm_dev_attr,
4780         .slaves         = omap44xx_timer11_slaves,
4781         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4782 };
4783
4784 /*
4785  * 'uart' class
4786  * universal asynchronous receiver/transmitter (uart)
4787  */
4788
4789 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4790         .rev_offs       = 0x0050,
4791         .sysc_offs      = 0x0054,
4792         .syss_offs      = 0x0058,
4793         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4794                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4795                            SYSS_HAS_RESET_STATUS),
4796         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4797                            SIDLE_SMART_WKUP),
4798         .sysc_fields    = &omap_hwmod_sysc_type1,
4799 };
4800
4801 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4802         .name   = "uart",
4803         .sysc   = &omap44xx_uart_sysc,
4804 };
4805
4806 /* uart1 */
4807 static struct omap_hwmod omap44xx_uart1_hwmod;
4808 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4809         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4810         { .irq = -1 }
4811 };
4812
4813 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4814         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4815         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4816         { .dma_req = -1 }
4817 };
4818
4819 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4820         {
4821                 .pa_start       = 0x4806a000,
4822                 .pa_end         = 0x4806a0ff,
4823                 .flags          = ADDR_TYPE_RT
4824         },
4825         { }
4826 };
4827
4828 /* l4_per -> uart1 */
4829 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4830         .master         = &omap44xx_l4_per_hwmod,
4831         .slave          = &omap44xx_uart1_hwmod,
4832         .clk            = "l4_div_ck",
4833         .addr           = omap44xx_uart1_addrs,
4834         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4835 };
4836
4837 /* uart1 slave ports */
4838 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4839         &omap44xx_l4_per__uart1,
4840 };
4841
4842 static struct omap_hwmod omap44xx_uart1_hwmod = {
4843         .name           = "uart1",
4844         .class          = &omap44xx_uart_hwmod_class,
4845         .clkdm_name     = "l4_per_clkdm",
4846         .mpu_irqs       = omap44xx_uart1_irqs,
4847         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4848         .main_clk       = "uart1_fck",
4849         .prcm = {
4850                 .omap4 = {
4851                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4852                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4853                         .modulemode   = MODULEMODE_SWCTRL,
4854                 },
4855         },
4856         .slaves         = omap44xx_uart1_slaves,
4857         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4858 };
4859
4860 /* uart2 */
4861 static struct omap_hwmod omap44xx_uart2_hwmod;
4862 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4863         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4864         { .irq = -1 }
4865 };
4866
4867 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4868         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4869         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4870         { .dma_req = -1 }
4871 };
4872
4873 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4874         {
4875                 .pa_start       = 0x4806c000,
4876                 .pa_end         = 0x4806c0ff,
4877                 .flags          = ADDR_TYPE_RT
4878         },
4879         { }
4880 };
4881
4882 /* l4_per -> uart2 */
4883 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4884         .master         = &omap44xx_l4_per_hwmod,
4885         .slave          = &omap44xx_uart2_hwmod,
4886         .clk            = "l4_div_ck",
4887         .addr           = omap44xx_uart2_addrs,
4888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4889 };
4890
4891 /* uart2 slave ports */
4892 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4893         &omap44xx_l4_per__uart2,
4894 };
4895
4896 static struct omap_hwmod omap44xx_uart2_hwmod = {
4897         .name           = "uart2",
4898         .class          = &omap44xx_uart_hwmod_class,
4899         .clkdm_name     = "l4_per_clkdm",
4900         .mpu_irqs       = omap44xx_uart2_irqs,
4901         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4902         .main_clk       = "uart2_fck",
4903         .prcm = {
4904                 .omap4 = {
4905                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4906                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4907                         .modulemode   = MODULEMODE_SWCTRL,
4908                 },
4909         },
4910         .slaves         = omap44xx_uart2_slaves,
4911         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4912 };
4913
4914 /* uart3 */
4915 static struct omap_hwmod omap44xx_uart3_hwmod;
4916 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4917         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4918         { .irq = -1 }
4919 };
4920
4921 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4922         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4923         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4924         { .dma_req = -1 }
4925 };
4926
4927 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4928         {
4929                 .pa_start       = 0x48020000,
4930                 .pa_end         = 0x480200ff,
4931                 .flags          = ADDR_TYPE_RT
4932         },
4933         { }
4934 };
4935
4936 /* l4_per -> uart3 */
4937 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4938         .master         = &omap44xx_l4_per_hwmod,
4939         .slave          = &omap44xx_uart3_hwmod,
4940         .clk            = "l4_div_ck",
4941         .addr           = omap44xx_uart3_addrs,
4942         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4943 };
4944
4945 /* uart3 slave ports */
4946 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4947         &omap44xx_l4_per__uart3,
4948 };
4949
4950 static struct omap_hwmod omap44xx_uart3_hwmod = {
4951         .name           = "uart3",
4952         .class          = &omap44xx_uart_hwmod_class,
4953         .clkdm_name     = "l4_per_clkdm",
4954         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
4955         .mpu_irqs       = omap44xx_uart3_irqs,
4956         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
4957         .main_clk       = "uart3_fck",
4958         .prcm = {
4959                 .omap4 = {
4960                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
4961                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
4962                         .modulemode   = MODULEMODE_SWCTRL,
4963                 },
4964         },
4965         .slaves         = omap44xx_uart3_slaves,
4966         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
4967 };
4968
4969 /* uart4 */
4970 static struct omap_hwmod omap44xx_uart4_hwmod;
4971 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
4972         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
4973         { .irq = -1 }
4974 };
4975
4976 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
4977         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
4978         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
4979         { .dma_req = -1 }
4980 };
4981
4982 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
4983         {
4984                 .pa_start       = 0x4806e000,
4985                 .pa_end         = 0x4806e0ff,
4986                 .flags          = ADDR_TYPE_RT
4987         },
4988         { }
4989 };
4990
4991 /* l4_per -> uart4 */
4992 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4993         .master         = &omap44xx_l4_per_hwmod,
4994         .slave          = &omap44xx_uart4_hwmod,
4995         .clk            = "l4_div_ck",
4996         .addr           = omap44xx_uart4_addrs,
4997         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4998 };
4999
5000 /* uart4 slave ports */
5001 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5002         &omap44xx_l4_per__uart4,
5003 };
5004
5005 static struct omap_hwmod omap44xx_uart4_hwmod = {
5006         .name           = "uart4",
5007         .class          = &omap44xx_uart_hwmod_class,
5008         .clkdm_name     = "l4_per_clkdm",
5009         .mpu_irqs       = omap44xx_uart4_irqs,
5010         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5011         .main_clk       = "uart4_fck",
5012         .prcm = {
5013                 .omap4 = {
5014                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5015                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5016                         .modulemode   = MODULEMODE_SWCTRL,
5017                 },
5018         },
5019         .slaves         = omap44xx_uart4_slaves,
5020         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5021 };
5022
5023 /*
5024  * 'usb_otg_hs' class
5025  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5026  */
5027
5028 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5029         .rev_offs       = 0x0400,
5030         .sysc_offs      = 0x0404,
5031         .syss_offs      = 0x0408,
5032         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5033                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5034                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5035         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5036                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5037                            MSTANDBY_SMART),
5038         .sysc_fields    = &omap_hwmod_sysc_type1,
5039 };
5040
5041 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5042         .name   = "usb_otg_hs",
5043         .sysc   = &omap44xx_usb_otg_hs_sysc,
5044 };
5045
5046 /* usb_otg_hs */
5047 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5048         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5049         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5050         { .irq = -1 }
5051 };
5052
5053 /* usb_otg_hs master ports */
5054 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5055         &omap44xx_usb_otg_hs__l3_main_2,
5056 };
5057
5058 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5059         {
5060                 .pa_start       = 0x4a0ab000,
5061                 .pa_end         = 0x4a0ab003,
5062                 .flags          = ADDR_TYPE_RT
5063         },
5064         { }
5065 };
5066
5067 /* l4_cfg -> usb_otg_hs */
5068 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5069         .master         = &omap44xx_l4_cfg_hwmod,
5070         .slave          = &omap44xx_usb_otg_hs_hwmod,
5071         .clk            = "l4_div_ck",
5072         .addr           = omap44xx_usb_otg_hs_addrs,
5073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5074 };
5075
5076 /* usb_otg_hs slave ports */
5077 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5078         &omap44xx_l4_cfg__usb_otg_hs,
5079 };
5080
5081 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5082         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5083 };
5084
5085 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5086         .name           = "usb_otg_hs",
5087         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5088         .clkdm_name     = "l3_init_clkdm",
5089         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5090         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5091         .main_clk       = "usb_otg_hs_ick",
5092         .prcm = {
5093                 .omap4 = {
5094                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5095                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5096                         .modulemode   = MODULEMODE_HWCTRL,
5097                 },
5098         },
5099         .opt_clks       = usb_otg_hs_opt_clks,
5100         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5101         .slaves         = omap44xx_usb_otg_hs_slaves,
5102         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5103         .masters        = omap44xx_usb_otg_hs_masters,
5104         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5105 };
5106
5107 /*
5108  * 'wd_timer' class
5109  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5110  * overflow condition
5111  */
5112
5113 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5114         .rev_offs       = 0x0000,
5115         .sysc_offs      = 0x0010,
5116         .syss_offs      = 0x0014,
5117         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5118                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5119         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5120                            SIDLE_SMART_WKUP),
5121         .sysc_fields    = &omap_hwmod_sysc_type1,
5122 };
5123
5124 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5125         .name           = "wd_timer",
5126         .sysc           = &omap44xx_wd_timer_sysc,
5127         .pre_shutdown   = &omap2_wd_timer_disable,
5128 };
5129
5130 /* wd_timer2 */
5131 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5132 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5133         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5134         { .irq = -1 }
5135 };
5136
5137 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5138         {
5139                 .pa_start       = 0x4a314000,
5140                 .pa_end         = 0x4a31407f,
5141                 .flags          = ADDR_TYPE_RT
5142         },
5143         { }
5144 };
5145
5146 /* l4_wkup -> wd_timer2 */
5147 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5148         .master         = &omap44xx_l4_wkup_hwmod,
5149         .slave          = &omap44xx_wd_timer2_hwmod,
5150         .clk            = "l4_wkup_clk_mux_ck",
5151         .addr           = omap44xx_wd_timer2_addrs,
5152         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5153 };
5154
5155 /* wd_timer2 slave ports */
5156 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5157         &omap44xx_l4_wkup__wd_timer2,
5158 };
5159
5160 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5161         .name           = "wd_timer2",
5162         .class          = &omap44xx_wd_timer_hwmod_class,
5163         .clkdm_name     = "l4_wkup_clkdm",
5164         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5165         .main_clk       = "wd_timer2_fck",
5166         .prcm = {
5167                 .omap4 = {
5168                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5169                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5170                         .modulemode   = MODULEMODE_SWCTRL,
5171                 },
5172         },
5173         .slaves         = omap44xx_wd_timer2_slaves,
5174         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5175 };
5176
5177 /* wd_timer3 */
5178 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5179 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5180         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5181         { .irq = -1 }
5182 };
5183
5184 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5185         {
5186                 .pa_start       = 0x40130000,
5187                 .pa_end         = 0x4013007f,
5188                 .flags          = ADDR_TYPE_RT
5189         },
5190         { }
5191 };
5192
5193 /* l4_abe -> wd_timer3 */
5194 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5195         .master         = &omap44xx_l4_abe_hwmod,
5196         .slave          = &omap44xx_wd_timer3_hwmod,
5197         .clk            = "ocp_abe_iclk",
5198         .addr           = omap44xx_wd_timer3_addrs,
5199         .user           = OCP_USER_MPU,
5200 };
5201
5202 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5203         {
5204                 .pa_start       = 0x49030000,
5205                 .pa_end         = 0x4903007f,
5206                 .flags          = ADDR_TYPE_RT
5207         },
5208         { }
5209 };
5210
5211 /* l4_abe -> wd_timer3 (dma) */
5212 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5213         .master         = &omap44xx_l4_abe_hwmod,
5214         .slave          = &omap44xx_wd_timer3_hwmod,
5215         .clk            = "ocp_abe_iclk",
5216         .addr           = omap44xx_wd_timer3_dma_addrs,
5217         .user           = OCP_USER_SDMA,
5218 };
5219
5220 /* wd_timer3 slave ports */
5221 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5222         &omap44xx_l4_abe__wd_timer3,
5223         &omap44xx_l4_abe__wd_timer3_dma,
5224 };
5225
5226 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5227         .name           = "wd_timer3",
5228         .class          = &omap44xx_wd_timer_hwmod_class,
5229         .clkdm_name     = "abe_clkdm",
5230         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5231         .main_clk       = "wd_timer3_fck",
5232         .prcm = {
5233                 .omap4 = {
5234                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5235                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5236                         .modulemode   = MODULEMODE_SWCTRL,
5237                 },
5238         },
5239         .slaves         = omap44xx_wd_timer3_slaves,
5240         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5241 };
5242
5243 /*
5244  * 'usb_host_hs' class
5245  * high-speed multi-port usb host controller
5246  */
5247 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
5248         .master         = &omap44xx_usb_host_hs_hwmod,
5249         .slave          = &omap44xx_l3_main_2_hwmod,
5250         .clk            = "l3_div_ck",
5251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5252 };
5253
5254 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
5255         .rev_offs       = 0x0000,
5256         .sysc_offs      = 0x0010,
5257         .syss_offs      = 0x0014,
5258         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5259                            SYSC_HAS_SOFTRESET),
5260         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5261                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5262                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
5263         .sysc_fields    = &omap_hwmod_sysc_type2,
5264 };
5265
5266 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
5267         .name = "usb_host_hs",
5268         .sysc = &omap44xx_usb_host_hs_sysc,
5269 };
5270
5271 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_masters[] = {
5272         &omap44xx_usb_host_hs__l3_main_2,
5273 };
5274
5275 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = {
5276         {
5277                 .name           = "uhh",
5278                 .pa_start       = 0x4a064000,
5279                 .pa_end         = 0x4a0647ff,
5280                 .flags          = ADDR_TYPE_RT
5281         },
5282         {
5283                 .name           = "ohci",
5284                 .pa_start       = 0x4a064800,
5285                 .pa_end         = 0x4a064bff,
5286         },
5287         {
5288                 .name           = "ehci",
5289                 .pa_start       = 0x4a064c00,
5290                 .pa_end         = 0x4a064fff,
5291         },
5292         {}
5293 };
5294
5295 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = {
5296         { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START },
5297         { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START },
5298         { .irq = -1 }
5299 };
5300
5301 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
5302         .master         = &omap44xx_l4_cfg_hwmod,
5303         .slave          = &omap44xx_usb_host_hs_hwmod,
5304         .clk            = "l4_div_ck",
5305         .addr           = omap44xx_usb_host_hs_addrs,
5306         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5307 };
5308
5309 static struct omap_hwmod_ocp_if *omap44xx_usb_host_hs_slaves[] = {
5310         &omap44xx_l4_cfg__usb_host_hs,
5311 };
5312
5313 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
5314         .name           = "usb_host_hs",
5315         .class          = &omap44xx_usb_host_hs_hwmod_class,
5316         .clkdm_name     = "l3_init_clkdm",
5317         .main_clk       = "usb_host_hs_fck",
5318         .prcm = {
5319                 .omap4 = {
5320                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
5321                         .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
5322                         .modulemode   = MODULEMODE_SWCTRL,
5323                 },
5324         },
5325         .mpu_irqs       = omap44xx_usb_host_hs_irqs,
5326         .slaves         = omap44xx_usb_host_hs_slaves,
5327         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_host_hs_slaves),
5328         .masters        = omap44xx_usb_host_hs_masters,
5329         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_host_hs_masters),
5330
5331         /*
5332          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
5333          * id: i660
5334          *
5335          * Description:
5336          * In the following configuration :
5337          * - USBHOST module is set to smart-idle mode
5338          * - PRCM asserts idle_req to the USBHOST module ( This typically
5339          *   happens when the system is going to a low power mode : all ports
5340          *   have been suspended, the master part of the USBHOST module has
5341          *   entered the standby state, and SW has cut the functional clocks)
5342          * - an USBHOST interrupt occurs before the module is able to answer
5343          *   idle_ack, typically a remote wakeup IRQ.
5344          * Then the USB HOST module will enter a deadlock situation where it
5345          * is no more accessible nor functional.
5346          *
5347          * Workaround:
5348          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
5349          */
5350
5351         /*
5352          * Errata: USB host EHCI may stall when entering smart-standby mode
5353          * Id: i571
5354          *
5355          * Description:
5356          * When the USBHOST module is set to smart-standby mode, and when it is
5357          * ready to enter the standby state (i.e. all ports are suspended and
5358          * all attached devices are in suspend mode), then it can wrongly assert
5359          * the Mstandby signal too early while there are still some residual OCP
5360          * transactions ongoing. If this condition occurs, the internal state
5361          * machine may go to an undefined state and the USB link may be stuck
5362          * upon the next resume.
5363          *
5364          * Workaround:
5365          * Don't use smart standby; use only force standby,
5366          * hence HWMOD_SWSUP_MSTANDBY
5367          */
5368
5369         /*
5370          * During system boot; If the hwmod framework resets the module
5371          * the module will have smart idle settings; which can lead to deadlock
5372          * (above Errata Id:i660); so, dont reset the module during boot;
5373          * Use HWMOD_INIT_NO_RESET.
5374          */
5375
5376         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
5377                           HWMOD_INIT_NO_RESET,
5378 };
5379
5380 /*
5381  * 'usb_tll_hs' class
5382  * usb_tll_hs module is the adapter on the usb_host_hs ports
5383  */
5384 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
5385         .rev_offs       = 0x0000,
5386         .sysc_offs      = 0x0010,
5387         .syss_offs      = 0x0014,
5388         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
5389                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
5390                            SYSC_HAS_AUTOIDLE),
5391         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
5392         .sysc_fields    = &omap_hwmod_sysc_type1,
5393 };
5394
5395 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
5396         .name = "usb_tll_hs",
5397         .sysc = &omap44xx_usb_tll_hs_sysc,
5398 };
5399
5400 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = {
5401         { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START },
5402         { .irq = -1 }
5403 };
5404
5405 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = {
5406         {
5407                 .name           = "tll",
5408                 .pa_start       = 0x4a062000,
5409                 .pa_end         = 0x4a063fff,
5410                 .flags          = ADDR_TYPE_RT
5411         },
5412         {}
5413 };
5414
5415 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
5416         .master         = &omap44xx_l4_cfg_hwmod,
5417         .slave          = &omap44xx_usb_tll_hs_hwmod,
5418         .clk            = "l4_div_ck",
5419         .addr           = omap44xx_usb_tll_hs_addrs,
5420         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5421 };
5422
5423 static struct omap_hwmod_ocp_if *omap44xx_usb_tll_hs_slaves[] = {
5424         &omap44xx_l4_cfg__usb_tll_hs,
5425 };
5426
5427 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
5428         .name           = "usb_tll_hs",
5429         .class          = &omap44xx_usb_tll_hs_hwmod_class,
5430         .clkdm_name     = "l3_init_clkdm",
5431         .main_clk       = "usb_tll_hs_ick",
5432         .prcm = {
5433                 .omap4 = {
5434                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
5435                         .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
5436                         .modulemode   = MODULEMODE_HWCTRL,
5437                 },
5438         },
5439         .mpu_irqs       = omap44xx_usb_tll_hs_irqs,
5440         .slaves         = omap44xx_usb_tll_hs_slaves,
5441         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_tll_hs_slaves),
5442 };
5443
5444 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5445
5446         /* dmm class */
5447         &omap44xx_dmm_hwmod,
5448
5449         /* emif_fw class */
5450         &omap44xx_emif_fw_hwmod,
5451
5452         /* l3 class */
5453         &omap44xx_l3_instr_hwmod,
5454         &omap44xx_l3_main_1_hwmod,
5455         &omap44xx_l3_main_2_hwmod,
5456         &omap44xx_l3_main_3_hwmod,
5457
5458         /* l4 class */
5459         &omap44xx_l4_abe_hwmod,
5460         &omap44xx_l4_cfg_hwmod,
5461         &omap44xx_l4_per_hwmod,
5462         &omap44xx_l4_wkup_hwmod,
5463
5464         /* mpu_bus class */
5465         &omap44xx_mpu_private_hwmod,
5466
5467         /* aess class */
5468 /*      &omap44xx_aess_hwmod, */
5469
5470         /* bandgap class */
5471         &omap44xx_bandgap_hwmod,
5472
5473         /* counter class */
5474 /*      &omap44xx_counter_32k_hwmod, */
5475
5476         /* dma class */
5477         &omap44xx_dma_system_hwmod,
5478
5479         /* dmic class */
5480         &omap44xx_dmic_hwmod,
5481
5482         /* dsp class */
5483         &omap44xx_dsp_hwmod,
5484
5485         /* dss class */
5486         &omap44xx_dss_hwmod,
5487         &omap44xx_dss_dispc_hwmod,
5488         &omap44xx_dss_dsi1_hwmod,
5489         &omap44xx_dss_dsi2_hwmod,
5490         &omap44xx_dss_hdmi_hwmod,
5491         &omap44xx_dss_rfbi_hwmod,
5492         &omap44xx_dss_venc_hwmod,
5493
5494         /* gpio class */
5495         &omap44xx_gpio1_hwmod,
5496         &omap44xx_gpio2_hwmod,
5497         &omap44xx_gpio3_hwmod,
5498         &omap44xx_gpio4_hwmod,
5499         &omap44xx_gpio5_hwmod,
5500         &omap44xx_gpio6_hwmod,
5501
5502         /* hsi class */
5503 /*      &omap44xx_hsi_hwmod, */
5504
5505         /* i2c class */
5506         &omap44xx_i2c1_hwmod,
5507         &omap44xx_i2c2_hwmod,
5508         &omap44xx_i2c3_hwmod,
5509         &omap44xx_i2c4_hwmod,
5510
5511         /* ipu class */
5512         &omap44xx_ipu_hwmod,
5513
5514         /* iss class */
5515 /*      &omap44xx_iss_hwmod, */
5516
5517         /* iva class */
5518         &omap44xx_iva_hwmod,
5519
5520         /* kbd class */
5521         &omap44xx_kbd_hwmod,
5522
5523         /* mailbox class */
5524         &omap44xx_mailbox_hwmod,
5525
5526         /* mcbsp class */
5527         &omap44xx_mcbsp1_hwmod,
5528         &omap44xx_mcbsp2_hwmod,
5529         &omap44xx_mcbsp3_hwmod,
5530         &omap44xx_mcbsp4_hwmod,
5531
5532         /* mcpdm class */
5533         &omap44xx_mcpdm_hwmod,
5534
5535         /* mcspi class */
5536         &omap44xx_mcspi1_hwmod,
5537         &omap44xx_mcspi2_hwmod,
5538         &omap44xx_mcspi3_hwmod,
5539         &omap44xx_mcspi4_hwmod,
5540
5541         /* mmc class */
5542         &omap44xx_mmc1_hwmod,
5543         &omap44xx_mmc2_hwmod,
5544         &omap44xx_mmc3_hwmod,
5545         &omap44xx_mmc4_hwmod,
5546         &omap44xx_mmc5_hwmod,
5547
5548         /* mpu class */
5549         &omap44xx_mpu_hwmod,
5550
5551         /* smartreflex class */
5552         &omap44xx_smartreflex_core_hwmod,
5553         &omap44xx_smartreflex_iva_hwmod,
5554         &omap44xx_smartreflex_mpu_hwmod,
5555
5556         /* spinlock class */
5557         &omap44xx_spinlock_hwmod,
5558
5559         /* timer class */
5560         &omap44xx_timer1_hwmod,
5561         &omap44xx_timer2_hwmod,
5562         &omap44xx_timer3_hwmod,
5563         &omap44xx_timer4_hwmod,
5564         &omap44xx_timer5_hwmod,
5565         &omap44xx_timer6_hwmod,
5566         &omap44xx_timer7_hwmod,
5567         &omap44xx_timer8_hwmod,
5568         &omap44xx_timer9_hwmod,
5569         &omap44xx_timer10_hwmod,
5570         &omap44xx_timer11_hwmod,
5571
5572         /* uart class */
5573         &omap44xx_uart1_hwmod,
5574         &omap44xx_uart2_hwmod,
5575         &omap44xx_uart3_hwmod,
5576         &omap44xx_uart4_hwmod,
5577
5578         /* usb host class */
5579         &omap44xx_usb_host_hs_hwmod,
5580         &omap44xx_usb_tll_hs_hwmod,
5581
5582         /* usb_otg_hs class */
5583         &omap44xx_usb_otg_hs_hwmod,
5584
5585         /* wd_timer class */
5586         &omap44xx_wd_timer2_hwmod,
5587         &omap44xx_wd_timer3_hwmod,
5588         NULL,
5589 };
5590
5591 int __init omap44xx_hwmod_init(void)
5592 {
5593         return omap_hwmod_register(omap44xx_hwmods);
5594 }
5595