arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 /*
   2  * Hardware modules present on the OMAP44xx chips
   3  *
   4  * Copyright (C) 2009-2011 Texas Instruments, Inc.
   5  * Copyright (C) 2009-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/io.h>
  22
  23 #include <plat/omap_hwmod.h>
  24 #include <plat/cpu.h>
  25 #include <plat/i2c.h>
  26 #include <plat/gpio.h>
  27 #include <plat/dma.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/mmc.h>
  31 #include <plat/i2c.h>
  32 #include <plat/dmtimer.h>
  33 #include <plat/common.h>
  34
  35 #include "omap_hwmod_common_data.h"
  36
  37 #include "smartreflex.h"
  38 #include "cm1_44xx.h"
  39 #include "cm2_44xx.h"
  40 #include "prm44xx.h"
  41 #include "prm-regbits-44xx.h"
  42 #include "wd_timer.h"
  43
  44 /* Base offset for all OMAP4 interrupts external to MPUSS */
  45 #define OMAP44XX_IRQ_GIC_START  32
  46
  47 /* Base offset for all OMAP4 dma requests */
  48 #define OMAP44XX_DMA_REQ_START  1
  49
  50 /* Backward references (IPs with Bus Master capability) */
  51 static struct omap_hwmod omap44xx_aess_hwmod;
  52 static struct omap_hwmod omap44xx_dma_system_hwmod;
  53 static struct omap_hwmod omap44xx_dmm_hwmod;
  54 static struct omap_hwmod omap44xx_dsp_hwmod;
  55 static struct omap_hwmod omap44xx_dss_hwmod;
  56 static struct omap_hwmod omap44xx_emif_fw_hwmod;
  57 static struct omap_hwmod omap44xx_hsi_hwmod;
  58 static struct omap_hwmod omap44xx_ipu_hwmod;
  59 static struct omap_hwmod omap44xx_iss_hwmod;
  60 static struct omap_hwmod omap44xx_iva_hwmod;
  61 static struct omap_hwmod omap44xx_l3_instr_hwmod;
  62 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
  63 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
  64 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
  65 static struct omap_hwmod omap44xx_l4_abe_hwmod;
  66 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
  67 static struct omap_hwmod omap44xx_l4_per_hwmod;
  68 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
  69 static struct omap_hwmod omap44xx_mmc1_hwmod;
  70 static struct omap_hwmod omap44xx_mmc2_hwmod;
  71 static struct omap_hwmod omap44xx_mpu_hwmod;
  72 static struct omap_hwmod omap44xx_mpu_private_hwmod;
  73 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
  74
  75 /*
  76  * Interconnects omap_hwmod structures
  77  * hwmods that compose the global OMAP interconnect
  78  */
  79
  80 /*
  81  * 'dmm' class
  82  * instance(s): dmm
  83  */
  84 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  85         .name   = "dmm",
  86 };
  87
  88 /* dmm */
  89 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
  90         { .irq = 113 + OMAP44XX_IRQ_GIC_START },
  91         { .irq = -1 }
  92 };
  93
  94 /* l3_main_1 -> dmm */
  95 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
  96         .master         = &omap44xx_l3_main_1_hwmod,
  97         .slave          = &omap44xx_dmm_hwmod,
  98         .clk            = "l3_div_ck",
  99         .user           = OCP_USER_SDMA,
 100 };
 101
 102 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
 103         {
 104                 .pa_start       = 0x4e000000,
 105                 .pa_end         = 0x4e0007ff,
 106                 .flags          = ADDR_TYPE_RT
 107         },
 108         { }
 109 };
 110
 111 /* mpu -> dmm */
 112 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
 113         .master         = &omap44xx_mpu_hwmod,
 114         .slave          = &omap44xx_dmm_hwmod,
 115         .clk            = "l3_div_ck",
 116         .addr           = omap44xx_dmm_addrs,
 117         .user           = OCP_USER_MPU,
 118 };
 119
 120 /* dmm slave ports */
 121 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
 122         &omap44xx_l3_main_1__dmm,
 123         &omap44xx_mpu__dmm,
 124 };
 125
 126 static struct omap_hwmod omap44xx_dmm_hwmod = {
 127         .name           = "dmm",
 128         .class          = &omap44xx_dmm_hwmod_class,
 129         .clkdm_name     = "l3_emif_clkdm",
 130         .prcm = {
 131                 .omap4 = {
 132                         .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
 133                         .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
 134                 },
 135         },
 136         .slaves         = omap44xx_dmm_slaves,
 137         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmm_slaves),
 138         .mpu_irqs       = omap44xx_dmm_irqs,
 139 };
 140
 141 /*
 142  * 'emif_fw' class
 143  * instance(s): emif_fw
 144  */
 145 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
 146         .name   = "emif_fw",
 147 };
 148
 149 /* emif_fw */
 150 /* dmm -> emif_fw */
 151 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
 152         .master         = &omap44xx_dmm_hwmod,
 153         .slave          = &omap44xx_emif_fw_hwmod,
 154         .clk            = "l3_div_ck",
 155         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 156 };
 157
 158 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
 159         {
 160                 .pa_start       = 0x4a20c000,
 161                 .pa_end         = 0x4a20c0ff,
 162                 .flags          = ADDR_TYPE_RT
 163         },
 164         { }
 165 };
 166
 167 /* l4_cfg -> emif_fw */
 168 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
 169         .master         = &omap44xx_l4_cfg_hwmod,
 170         .slave          = &omap44xx_emif_fw_hwmod,
 171         .clk            = "l4_div_ck",
 172         .addr           = omap44xx_emif_fw_addrs,
 173         .user           = OCP_USER_MPU,
 174 };
 175
 176 /* emif_fw slave ports */
 177 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
 178         &omap44xx_dmm__emif_fw,
 179         &omap44xx_l4_cfg__emif_fw,
 180 };
 181
 182 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
 183         .name           = "emif_fw",
 184         .class          = &omap44xx_emif_fw_hwmod_class,
 185         .clkdm_name     = "l3_emif_clkdm",
 186         .prcm = {
 187                 .omap4 = {
 188                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
 189                         .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
 190                 },
 191         },
 192         .slaves         = omap44xx_emif_fw_slaves,
 193         .slaves_cnt     = ARRAY_SIZE(omap44xx_emif_fw_slaves),
 194 };
 195
 196 /*
 197  * 'l3' class
 198  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
 199  */
 200 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
 201         .name   = "l3",
 202 };
 203
 204 /* l3_instr */
 205 /* iva -> l3_instr */
 206 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
 207         .master         = &omap44xx_iva_hwmod,
 208         .slave          = &omap44xx_l3_instr_hwmod,
 209         .clk            = "l3_div_ck",
 210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 211 };
 212
 213 /* l3_main_3 -> l3_instr */
 214 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 215         .master         = &omap44xx_l3_main_3_hwmod,
 216         .slave          = &omap44xx_l3_instr_hwmod,
 217         .clk            = "l3_div_ck",
 218         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 219 };
 220
 221 /* l3_instr slave ports */
 222 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
 223         &omap44xx_iva__l3_instr,
 224         &omap44xx_l3_main_3__l3_instr,
 225 };
 226
 227 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
 228         .name           = "l3_instr",
 229         .class          = &omap44xx_l3_hwmod_class,
 230         .clkdm_name     = "l3_instr_clkdm",
 231         .prcm = {
 232                 .omap4 = {
 233                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
 234                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
 235                         .modulemode   = MODULEMODE_HWCTRL,
 236                 },
 237         },
 238         .slaves         = omap44xx_l3_instr_slaves,
 239         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_instr_slaves),
 240 };
 241
 242 /* l3_main_1 */
 243 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
 244         { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
 245         { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
 246         { .irq = -1 }
 247 };
 248
 249 /* dsp -> l3_main_1 */
 250 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
 251         .master         = &omap44xx_dsp_hwmod,
 252         .slave          = &omap44xx_l3_main_1_hwmod,
 253         .clk            = "l3_div_ck",
 254         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 255 };
 256
 257 /* dss -> l3_main_1 */
 258 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
 259         .master         = &omap44xx_dss_hwmod,
 260         .slave          = &omap44xx_l3_main_1_hwmod,
 261         .clk            = "l3_div_ck",
 262         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 263 };
 264
 265 /* l3_main_2 -> l3_main_1 */
 266 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 267         .master         = &omap44xx_l3_main_2_hwmod,
 268         .slave          = &omap44xx_l3_main_1_hwmod,
 269         .clk            = "l3_div_ck",
 270         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 271 };
 272
 273 /* l4_cfg -> l3_main_1 */
 274 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 275         .master         = &omap44xx_l4_cfg_hwmod,
 276         .slave          = &omap44xx_l3_main_1_hwmod,
 277         .clk            = "l4_div_ck",
 278         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 279 };
 280
 281 /* mmc1 -> l3_main_1 */
 282 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
 283         .master         = &omap44xx_mmc1_hwmod,
 284         .slave          = &omap44xx_l3_main_1_hwmod,
 285         .clk            = "l3_div_ck",
 286         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 287 };
 288
 289 /* mmc2 -> l3_main_1 */
 290 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
 291         .master         = &omap44xx_mmc2_hwmod,
 292         .slave          = &omap44xx_l3_main_1_hwmod,
 293         .clk            = "l3_div_ck",
 294         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 295 };
 296
 297 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
 298         {
 299                 .pa_start       = 0x44000000,
 300                 .pa_end         = 0x44000fff,
 301                 .flags          = ADDR_TYPE_RT
 302         },
 303         { }
 304 };
 305
 306 /* mpu -> l3_main_1 */
 307 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 308         .master         = &omap44xx_mpu_hwmod,
 309         .slave          = &omap44xx_l3_main_1_hwmod,
 310         .clk            = "l3_div_ck",
 311         .addr           = omap44xx_l3_main_1_addrs,
 312         .user           = OCP_USER_MPU,
 313 };
 314
 315 /* l3_main_1 slave ports */
 316 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 317         &omap44xx_dsp__l3_main_1,
 318         &omap44xx_dss__l3_main_1,
 319         &omap44xx_l3_main_2__l3_main_1,
 320         &omap44xx_l4_cfg__l3_main_1,
 321         &omap44xx_mmc1__l3_main_1,
 322         &omap44xx_mmc2__l3_main_1,
 323         &omap44xx_mpu__l3_main_1,
 324 };
 325
 326 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
 327         .name           = "l3_main_1",
 328         .class          = &omap44xx_l3_hwmod_class,
 329         .clkdm_name     = "l3_1_clkdm",
 330         .mpu_irqs       = omap44xx_l3_main_1_irqs,
 331         .prcm = {
 332                 .omap4 = {
 333                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 334                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 335                 },
 336         },
 337         .slaves         = omap44xx_l3_main_1_slaves,
 338         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
 339 };
 340
 341 /* l3_main_2 */
 342 /* dma_system -> l3_main_2 */
 343 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
 344         .master         = &omap44xx_dma_system_hwmod,
 345         .slave          = &omap44xx_l3_main_2_hwmod,
 346         .clk            = "l3_div_ck",
 347         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 348 };
 349
 350 /* hsi -> l3_main_2 */
 351 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
 352         .master         = &omap44xx_hsi_hwmod,
 353         .slave          = &omap44xx_l3_main_2_hwmod,
 354         .clk            = "l3_div_ck",
 355         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 356 };
 357
 358 /* ipu -> l3_main_2 */
 359 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
 360         .master         = &omap44xx_ipu_hwmod,
 361         .slave          = &omap44xx_l3_main_2_hwmod,
 362         .clk            = "l3_div_ck",
 363         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 364 };
 365
 366 /* iss -> l3_main_2 */
 367 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
 368         .master         = &omap44xx_iss_hwmod,
 369         .slave          = &omap44xx_l3_main_2_hwmod,
 370         .clk            = "l3_div_ck",
 371         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 372 };
 373
 374 /* iva -> l3_main_2 */
 375 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
 376         .master         = &omap44xx_iva_hwmod,
 377         .slave          = &omap44xx_l3_main_2_hwmod,
 378         .clk            = "l3_div_ck",
 379         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 380 };
 381
 382 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
 383         {
 384                 .pa_start       = 0x44800000,
 385                 .pa_end         = 0x44801fff,
 386                 .flags          = ADDR_TYPE_RT
 387         },
 388         { }
 389 };
 390
 391 /* l3_main_1 -> l3_main_2 */
 392 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 393         .master         = &omap44xx_l3_main_1_hwmod,
 394         .slave          = &omap44xx_l3_main_2_hwmod,
 395         .clk            = "l3_div_ck",
 396         .addr           = omap44xx_l3_main_2_addrs,
 397         .user           = OCP_USER_MPU,
 398 };
 399
 400 /* l4_cfg -> l3_main_2 */
 401 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 402         .master         = &omap44xx_l4_cfg_hwmod,
 403         .slave          = &omap44xx_l3_main_2_hwmod,
 404         .clk            = "l4_div_ck",
 405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 406 };
 407
 408 /* usb_otg_hs -> l3_main_2 */
 409 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
 410         .master         = &omap44xx_usb_otg_hs_hwmod,
 411         .slave          = &omap44xx_l3_main_2_hwmod,
 412         .clk            = "l3_div_ck",
 413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 414 };
 415
 416 /* l3_main_2 slave ports */
 417 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
 418         &omap44xx_dma_system__l3_main_2,
 419         &omap44xx_hsi__l3_main_2,
 420         &omap44xx_ipu__l3_main_2,
 421         &omap44xx_iss__l3_main_2,
 422         &omap44xx_iva__l3_main_2,
 423         &omap44xx_l3_main_1__l3_main_2,
 424         &omap44xx_l4_cfg__l3_main_2,
 425         &omap44xx_usb_otg_hs__l3_main_2,
 426 };
 427
 428 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 429         .name           = "l3_main_2",
 430         .class          = &omap44xx_l3_hwmod_class,
 431         .clkdm_name     = "l3_2_clkdm",
 432         .prcm = {
 433                 .omap4 = {
 434                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 435                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 436                 },
 437         },
 438         .slaves         = omap44xx_l3_main_2_slaves,
 439         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
 440 };
 441
 442 /* l3_main_3 */
 443 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
 444         {
 445                 .pa_start       = 0x45000000,
 446                 .pa_end         = 0x45000fff,
 447                 .flags          = ADDR_TYPE_RT
 448         },
 449         { }
 450 };
 451
 452 /* l3_main_1 -> l3_main_3 */
 453 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 454         .master         = &omap44xx_l3_main_1_hwmod,
 455         .slave          = &omap44xx_l3_main_3_hwmod,
 456         .clk            = "l3_div_ck",
 457         .addr           = omap44xx_l3_main_3_addrs,
 458         .user           = OCP_USER_MPU,
 459 };
 460
 461 /* l3_main_2 -> l3_main_3 */
 462 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 463         .master         = &omap44xx_l3_main_2_hwmod,
 464         .slave          = &omap44xx_l3_main_3_hwmod,
 465         .clk            = "l3_div_ck",
 466         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 467 };
 468
 469 /* l4_cfg -> l3_main_3 */
 470 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 471         .master         = &omap44xx_l4_cfg_hwmod,
 472         .slave          = &omap44xx_l3_main_3_hwmod,
 473         .clk            = "l4_div_ck",
 474         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 475 };
 476
 477 /* l3_main_3 slave ports */
 478 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
 479         &omap44xx_l3_main_1__l3_main_3,
 480         &omap44xx_l3_main_2__l3_main_3,
 481         &omap44xx_l4_cfg__l3_main_3,
 482 };
 483
 484 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 485         .name           = "l3_main_3",
 486         .class          = &omap44xx_l3_hwmod_class,
 487         .clkdm_name     = "l3_instr_clkdm",
 488         .prcm = {
 489                 .omap4 = {
 490                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 491                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 492                         .modulemode   = MODULEMODE_HWCTRL,
 493                 },
 494         },
 495         .slaves         = omap44xx_l3_main_3_slaves,
 496         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
 497 };
 498
 499 /*
 500  * 'l4' class
 501  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 502  */
 503 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 504         .name   = "l4",
 505 };
 506
 507 /* l4_abe */
 508 /* aess -> l4_abe */
 509 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
 510         .master         = &omap44xx_aess_hwmod,
 511         .slave          = &omap44xx_l4_abe_hwmod,
 512         .clk            = "ocp_abe_iclk",
 513         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 514 };
 515
 516 /* dsp -> l4_abe */
 517 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
 518         .master         = &omap44xx_dsp_hwmod,
 519         .slave          = &omap44xx_l4_abe_hwmod,
 520         .clk            = "ocp_abe_iclk",
 521         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 522 };
 523
 524 /* l3_main_1 -> l4_abe */
 525 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
 526         .master         = &omap44xx_l3_main_1_hwmod,
 527         .slave          = &omap44xx_l4_abe_hwmod,
 528         .clk            = "l3_div_ck",
 529         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 530 };
 531
 532 /* mpu -> l4_abe */
 533 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
 534         .master         = &omap44xx_mpu_hwmod,
 535         .slave          = &omap44xx_l4_abe_hwmod,
 536         .clk            = "ocp_abe_iclk",
 537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 538 };
 539
 540 /* l4_abe slave ports */
 541 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
 542         &omap44xx_aess__l4_abe,
 543         &omap44xx_dsp__l4_abe,
 544         &omap44xx_l3_main_1__l4_abe,
 545         &omap44xx_mpu__l4_abe,
 546 };
 547
 548 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 549         .name           = "l4_abe",
 550         .class          = &omap44xx_l4_hwmod_class,
 551         .clkdm_name     = "abe_clkdm",
 552         .prcm = {
 553                 .omap4 = {
 554                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 555                 },
 556         },
 557         .slaves         = omap44xx_l4_abe_slaves,
 558         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_abe_slaves),
 559 };
 560
 561 /* l4_cfg */
 562 /* l3_main_1 -> l4_cfg */
 563 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 564         .master         = &omap44xx_l3_main_1_hwmod,
 565         .slave          = &omap44xx_l4_cfg_hwmod,
 566         .clk            = "l3_div_ck",
 567         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 568 };
 569
 570 /* l4_cfg slave ports */
 571 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
 572         &omap44xx_l3_main_1__l4_cfg,
 573 };
 574
 575 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 576         .name           = "l4_cfg",
 577         .class          = &omap44xx_l4_hwmod_class,
 578         .clkdm_name     = "l4_cfg_clkdm",
 579         .prcm = {
 580                 .omap4 = {
 581                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 582                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 583                 },
 584         },
 585         .slaves         = omap44xx_l4_cfg_slaves,
 586         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
 587 };
 588
 589 /* l4_per */
 590 /* l3_main_2 -> l4_per */
 591 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 592         .master         = &omap44xx_l3_main_2_hwmod,
 593         .slave          = &omap44xx_l4_per_hwmod,
 594         .clk            = "l3_div_ck",
 595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 596 };
 597
 598 /* l4_per slave ports */
 599 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
 600         &omap44xx_l3_main_2__l4_per,
 601 };
 602
 603 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 604         .name           = "l4_per",
 605         .class          = &omap44xx_l4_hwmod_class,
 606         .clkdm_name     = "l4_per_clkdm",
 607         .prcm = {
 608                 .omap4 = {
 609                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 610                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 611                 },
 612         },
 613         .slaves         = omap44xx_l4_per_slaves,
 614         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_per_slaves),
 615 };
 616
 617 /* l4_wkup */
 618 /* l4_cfg -> l4_wkup */
 619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 620         .master         = &omap44xx_l4_cfg_hwmod,
 621         .slave          = &omap44xx_l4_wkup_hwmod,
 622         .clk            = "l4_div_ck",
 623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 624 };
 625
 626 /* l4_wkup slave ports */
 627 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
 628         &omap44xx_l4_cfg__l4_wkup,
 629 };
 630
 631 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 632         .name           = "l4_wkup",
 633         .class          = &omap44xx_l4_hwmod_class,
 634         .clkdm_name     = "l4_wkup_clkdm",
 635         .prcm = {
 636                 .omap4 = {
 637                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 638                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 639                 },
 640         },
 641         .slaves         = omap44xx_l4_wkup_slaves,
 642         .slaves_cnt     = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
 643 };
 644
 645 /*
 646  * 'mpu_bus' class
 647  * instance(s): mpu_private
 648  */
 649 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 650         .name   = "mpu_bus",
 651 };
 652
 653 /* mpu_private */
 654 /* mpu -> mpu_private */
 655 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 656         .master         = &omap44xx_mpu_hwmod,
 657         .slave          = &omap44xx_mpu_private_hwmod,
 658         .clk            = "l3_div_ck",
 659         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 660 };
 661
 662 /* mpu_private slave ports */
 663 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
 664         &omap44xx_mpu__mpu_private,
 665 };
 666
 667 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 668         .name           = "mpu_private",
 669         .class          = &omap44xx_mpu_bus_hwmod_class,
 670         .clkdm_name     = "mpuss_clkdm",
 671         .slaves         = omap44xx_mpu_private_slaves,
 672         .slaves_cnt     = ARRAY_SIZE(omap44xx_mpu_private_slaves),
 673 };
 674
 675 /*
 676  * Modules omap_hwmod structures
 677  *
 678  * The following IPs are excluded for the moment because:
 679  * - They do not need an explicit SW control using omap_hwmod API.
 680  * - They still need to be validated with the driver
 681  *   properly adapted to omap_hwmod / omap_device
 682  *
 683  *  c2c
 684  *  c2c_target_fw
 685  *  cm_core
 686  *  cm_core_aon
 687  *  ctrl_module_core
 688  *  ctrl_module_pad_core
 689  *  ctrl_module_pad_wkup
 690  *  ctrl_module_wkup
 691  *  debugss
 692  *  efuse_ctrl_cust
 693  *  efuse_ctrl_std
 694  *  elm
 695  *  emif1
 696  *  emif2
 697  *  fdif
 698  *  gpmc
 699  *  gpu
 700  *  hdq1w
 701  *  mcasp
 702  *  mpu_c0
 703  *  mpu_c1
 704  *  ocmc_ram
 705  *  ocp2scp_usb_phy
 706  *  ocp_wp_noc
 707  *  prcm_mpu
 708  *  prm
 709  *  scrm
 710  *  sl2if
 711  *  slimbus1
 712  *  slimbus2
 713  *  usb_host_fs
 714  *  usb_host_hs
 715  *  usb_phy_cm
 716  *  usb_tll_hs
 717  *  usim
 718  */
 719
 720 /*
 721  * 'aess' class
 722  * audio engine sub system
 723  */
 724
 725 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 726         .rev_offs       = 0x0000,
 727         .sysc_offs      = 0x0010,
 728         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 729         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 730                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 731                            MSTANDBY_SMART_WKUP),
 732         .sysc_fields    = &omap_hwmod_sysc_type2,
 733 };
 734
 735 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 736         .name   = "aess",
 737         .sysc   = &omap44xx_aess_sysc,
 738 };
 739
 740 /* aess */
 741 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
 742         { .irq = 99 + OMAP44XX_IRQ_GIC_START },
 743         { .irq = -1 }
 744 };
 745
 746 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
 747         { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
 748         { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
 749         { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
 750         { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
 751         { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
 752         { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
 753         { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
 754         { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
 755         { .dma_req = -1 }
 756 };
 757
 758 /* aess master ports */
 759 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
 760         &omap44xx_aess__l4_abe,
 761 };
 762
 763 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
 764         {
 765                 .pa_start       = 0x401f1000,
 766                 .pa_end         = 0x401f13ff,
 767                 .flags          = ADDR_TYPE_RT
 768         },
 769         { }
 770 };
 771
 772 /* l4_abe -> aess */
 773 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
 774         .master         = &omap44xx_l4_abe_hwmod,
 775         .slave          = &omap44xx_aess_hwmod,
 776         .clk            = "ocp_abe_iclk",
 777         .addr           = omap44xx_aess_addrs,
 778         .user           = OCP_USER_MPU,
 779 };
 780
 781 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
 782         {
 783                 .pa_start       = 0x490f1000,
 784                 .pa_end         = 0x490f13ff,
 785                 .flags          = ADDR_TYPE_RT
 786         },
 787         { }
 788 };
 789
 790 /* l4_abe -> aess (dma) */
 791 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
 792         .master         = &omap44xx_l4_abe_hwmod,
 793         .slave          = &omap44xx_aess_hwmod,
 794         .clk            = "ocp_abe_iclk",
 795         .addr           = omap44xx_aess_dma_addrs,
 796         .user           = OCP_USER_SDMA,
 797 };
 798
 799 /* aess slave ports */
 800 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
 801         &omap44xx_l4_abe__aess,
 802         &omap44xx_l4_abe__aess_dma,
 803 };
 804
 805 static struct omap_hwmod omap44xx_aess_hwmod = {
 806         .name           = "aess",
 807         .class          = &omap44xx_aess_hwmod_class,
 808         .clkdm_name     = "abe_clkdm",
 809         .mpu_irqs       = omap44xx_aess_irqs,
 810         .sdma_reqs      = omap44xx_aess_sdma_reqs,
 811         .main_clk       = "aess_fck",
 812         .prcm = {
 813                 .omap4 = {
 814                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 815                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 816                         .modulemode   = MODULEMODE_SWCTRL,
 817                 },
 818         },
 819         .slaves         = omap44xx_aess_slaves,
 820         .slaves_cnt     = ARRAY_SIZE(omap44xx_aess_slaves),
 821         .masters        = omap44xx_aess_masters,
 822         .masters_cnt    = ARRAY_SIZE(omap44xx_aess_masters),
 823 };
 824
 825 /*
 826  * 'bandgap' class
 827  * bangap reference for ldo regulators
 828  */
 829
 830 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
 831         .name   = "bandgap",
 832 };
 833
 834 /* bandgap */
 835 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
 836         { .role = "fclk", .clk = "bandgap_fclk" },
 837 };
 838
 839 static struct omap_hwmod omap44xx_bandgap_hwmod = {
 840         .name           = "bandgap",
 841         .class          = &omap44xx_bandgap_hwmod_class,
 842         .clkdm_name     = "l4_wkup_clkdm",
 843         .prcm = {
 844                 .omap4 = {
 845                         .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
 846                 },
 847         },
 848         .opt_clks       = bandgap_opt_clks,
 849         .opt_clks_cnt   = ARRAY_SIZE(bandgap_opt_clks),
 850 };
 851
 852 /*
 853  * 'counter' class
 854  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 855  */
 856
 857 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 858         .rev_offs       = 0x0000,
 859         .sysc_offs      = 0x0004,
 860         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 861         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 862                            SIDLE_SMART_WKUP),
 863         .sysc_fields    = &omap_hwmod_sysc_type1,
 864 };
 865
 866 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 867         .name   = "counter",
 868         .sysc   = &omap44xx_counter_sysc,
 869 };
 870
 871 /* counter_32k */
 872 static struct omap_hwmod omap44xx_counter_32k_hwmod;
 873 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
 874         {
 875                 .pa_start       = 0x4a304000,
 876                 .pa_end         = 0x4a30401f,
 877                 .flags          = ADDR_TYPE_RT
 878         },
 879         { }
 880 };
 881
 882 /* l4_wkup -> counter_32k */
 883 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
 884         .master         = &omap44xx_l4_wkup_hwmod,
 885         .slave          = &omap44xx_counter_32k_hwmod,
 886         .clk            = "l4_wkup_clk_mux_ck",
 887         .addr           = omap44xx_counter_32k_addrs,
 888         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 889 };
 890
 891 /* counter_32k slave ports */
 892 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
 893         &omap44xx_l4_wkup__counter_32k,
 894 };
 895
 896 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 897         .name           = "counter_32k",
 898         .class          = &omap44xx_counter_hwmod_class,
 899         .clkdm_name     = "l4_wkup_clkdm",
 900         .flags          = HWMOD_SWSUP_SIDLE,
 901         .main_clk       = "sys_32k_ck",
 902         .prcm = {
 903                 .omap4 = {
 904                         .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 905                         .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 906                 },
 907         },
 908         .slaves         = omap44xx_counter_32k_slaves,
 909         .slaves_cnt     = ARRAY_SIZE(omap44xx_counter_32k_slaves),
 910 };
 911
 912 /*
 913  * 'dma' class
 914  * dma controller for data exchange between memory to memory (i.e. internal or
 915  * external memory) and gp peripherals to memory or memory to gp peripherals
 916  */
 917
 918 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 919         .rev_offs       = 0x0000,
 920         .sysc_offs      = 0x002c,
 921         .syss_offs      = 0x0028,
 922         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 923                            SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 924                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 925                            SYSS_HAS_RESET_STATUS),
 926         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 927                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 928         .sysc_fields    = &omap_hwmod_sysc_type1,
 929 };
 930
 931 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 932         .name   = "dma",
 933         .sysc   = &omap44xx_dma_sysc,
 934 };
 935
 936 /* dma dev_attr */
 937 static struct omap_dma_dev_attr dma_dev_attr = {
 938         .dev_caps       = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 939                           IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 940         .lch_count      = 32,
 941 };
 942
 943 /* dma_system */
 944 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
 945         { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
 946         { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
 947         { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
 948         { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
 949         { .irq = -1 }
 950 };
 951
 952 /* dma_system master ports */
 953 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
 954         &omap44xx_dma_system__l3_main_2,
 955 };
 956
 957 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
 958         {
 959                 .pa_start       = 0x4a056000,
 960                 .pa_end         = 0x4a056fff,
 961                 .flags          = ADDR_TYPE_RT
 962         },
 963         { }
 964 };
 965
 966 /* l4_cfg -> dma_system */
 967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
 968         .master         = &omap44xx_l4_cfg_hwmod,
 969         .slave          = &omap44xx_dma_system_hwmod,
 970         .clk            = "l4_div_ck",
 971         .addr           = omap44xx_dma_system_addrs,
 972         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 973 };
 974
 975 /* dma_system slave ports */
 976 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
 977         &omap44xx_l4_cfg__dma_system,
 978 };
 979
 980 static struct omap_hwmod omap44xx_dma_system_hwmod = {
 981         .name           = "dma_system",
 982         .class          = &omap44xx_dma_hwmod_class,
 983         .clkdm_name     = "l3_dma_clkdm",
 984         .mpu_irqs       = omap44xx_dma_system_irqs,
 985         .main_clk       = "l3_div_ck",
 986         .prcm = {
 987                 .omap4 = {
 988                         .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 989                         .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 990                 },
 991         },
 992         .dev_attr       = &dma_dev_attr,
 993         .slaves         = omap44xx_dma_system_slaves,
 994         .slaves_cnt     = ARRAY_SIZE(omap44xx_dma_system_slaves),
 995         .masters        = omap44xx_dma_system_masters,
 996         .masters_cnt    = ARRAY_SIZE(omap44xx_dma_system_masters),
 997 };
 998
 999 /*
1000  * 'dmic' class
1001  * digital microphone controller
1002  */
1003
1004 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1005         .rev_offs       = 0x0000,
1006         .sysc_offs      = 0x0010,
1007         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1008                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1009         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1010                            SIDLE_SMART_WKUP),
1011         .sysc_fields    = &omap_hwmod_sysc_type2,
1012 };
1013
1014 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1015         .name   = "dmic",
1016         .sysc   = &omap44xx_dmic_sysc,
1017 };
1018
1019 /* dmic */
1020 static struct omap_hwmod omap44xx_dmic_hwmod;
1021 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1022         { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1023         { .irq = -1 }
1024 };
1025
1026 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1027         { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1028         { .dma_req = -1 }
1029 };
1030
1031 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1032         {
1033                 .pa_start       = 0x4012e000,
1034                 .pa_end         = 0x4012e07f,
1035                 .flags          = ADDR_TYPE_RT
1036         },
1037         { }
1038 };
1039
1040 /* l4_abe -> dmic */
1041 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1042         .master         = &omap44xx_l4_abe_hwmod,
1043         .slave          = &omap44xx_dmic_hwmod,
1044         .clk            = "ocp_abe_iclk",
1045         .addr           = omap44xx_dmic_addrs,
1046         .user           = OCP_USER_MPU,
1047 };
1048
1049 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1050         {
1051                 .pa_start       = 0x4902e000,
1052                 .pa_end         = 0x4902e07f,
1053                 .flags          = ADDR_TYPE_RT
1054         },
1055         { }
1056 };
1057
1058 /* l4_abe -> dmic (dma) */
1059 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1060         .master         = &omap44xx_l4_abe_hwmod,
1061         .slave          = &omap44xx_dmic_hwmod,
1062         .clk            = "ocp_abe_iclk",
1063         .addr           = omap44xx_dmic_dma_addrs,
1064         .user           = OCP_USER_SDMA,
1065 };
1066
1067 /* dmic slave ports */
1068 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1069         &omap44xx_l4_abe__dmic,
1070         &omap44xx_l4_abe__dmic_dma,
1071 };
1072
1073 static struct omap_hwmod omap44xx_dmic_hwmod = {
1074         .name           = "dmic",
1075         .class          = &omap44xx_dmic_hwmod_class,
1076         .clkdm_name     = "abe_clkdm",
1077         .mpu_irqs       = omap44xx_dmic_irqs,
1078         .sdma_reqs      = omap44xx_dmic_sdma_reqs,
1079         .main_clk       = "dmic_fck",
1080         .prcm = {
1081                 .omap4 = {
1082                         .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1083                         .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1084                         .modulemode   = MODULEMODE_SWCTRL,
1085                 },
1086         },
1087         .slaves         = omap44xx_dmic_slaves,
1088         .slaves_cnt     = ARRAY_SIZE(omap44xx_dmic_slaves),
1089 };
1090
1091 /*
1092  * 'dsp' class
1093  * dsp sub-system
1094  */
1095
1096 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1097         .name   = "dsp",
1098 };
1099
1100 /* dsp */
1101 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1102         { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1103         { .irq = -1 }
1104 };
1105
1106 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1107         { .name = "mmu_cache", .rst_shift = 1 },
1108 };
1109
1110 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1111         { .name = "dsp", .rst_shift = 0 },
1112 };
1113
1114 /* dsp -> iva */
1115 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1116         .master         = &omap44xx_dsp_hwmod,
1117         .slave          = &omap44xx_iva_hwmod,
1118         .clk            = "dpll_iva_m5x2_ck",
1119 };
1120
1121 /* dsp master ports */
1122 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1123         &omap44xx_dsp__l3_main_1,
1124         &omap44xx_dsp__l4_abe,
1125         &omap44xx_dsp__iva,
1126 };
1127
1128 /* l4_cfg -> dsp */
1129 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1130         .master         = &omap44xx_l4_cfg_hwmod,
1131         .slave          = &omap44xx_dsp_hwmod,
1132         .clk            = "l4_div_ck",
1133         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1134 };
1135
1136 /* dsp slave ports */
1137 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1138         &omap44xx_l4_cfg__dsp,
1139 };
1140
1141 /* Pseudo hwmod for reset control purpose only */
1142 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1143         .name           = "dsp_c0",
1144         .class          = &omap44xx_dsp_hwmod_class,
1145         .clkdm_name     = "tesla_clkdm",
1146         .flags          = HWMOD_INIT_NO_RESET,
1147         .rst_lines      = omap44xx_dsp_c0_resets,
1148         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1149         .prcm = {
1150                 .omap4 = {
1151                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1152                 },
1153         },
1154 };
1155
1156 static struct omap_hwmod omap44xx_dsp_hwmod = {
1157         .name           = "dsp",
1158         .class          = &omap44xx_dsp_hwmod_class,
1159         .clkdm_name     = "tesla_clkdm",
1160         .mpu_irqs       = omap44xx_dsp_irqs,
1161         .rst_lines      = omap44xx_dsp_resets,
1162         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_dsp_resets),
1163         .main_clk       = "dsp_fck",
1164         .prcm = {
1165                 .omap4 = {
1166                         .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1167                         .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1168                         .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1169                         .modulemode   = MODULEMODE_HWCTRL,
1170                 },
1171         },
1172         .slaves         = omap44xx_dsp_slaves,
1173         .slaves_cnt     = ARRAY_SIZE(omap44xx_dsp_slaves),
1174         .masters        = omap44xx_dsp_masters,
1175         .masters_cnt    = ARRAY_SIZE(omap44xx_dsp_masters),
1176 };
1177
1178 /*
1179  * 'dss' class
1180  * display sub-system
1181  */
1182
1183 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1184         .rev_offs       = 0x0000,
1185         .syss_offs      = 0x0014,
1186         .sysc_flags     = SYSS_HAS_RESET_STATUS,
1187 };
1188
1189 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1190         .name   = "dss",
1191         .sysc   = &omap44xx_dss_sysc,
1192         .reset  = omap_dss_reset,
1193 };
1194
1195 /* dss */
1196 /* dss master ports */
1197 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1198         &omap44xx_dss__l3_main_1,
1199 };
1200
1201 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1202         {
1203                 .pa_start       = 0x58000000,
1204                 .pa_end         = 0x5800007f,
1205                 .flags          = ADDR_TYPE_RT
1206         },
1207         { }
1208 };
1209
1210 /* l3_main_2 -> dss */
1211 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1212         .master         = &omap44xx_l3_main_2_hwmod,
1213         .slave          = &omap44xx_dss_hwmod,
1214         .clk            = "dss_fck",
1215         .addr           = omap44xx_dss_dma_addrs,
1216         .user           = OCP_USER_SDMA,
1217 };
1218
1219 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1220         {
1221                 .pa_start       = 0x48040000,
1222                 .pa_end         = 0x4804007f,
1223                 .flags          = ADDR_TYPE_RT
1224         },
1225         { }
1226 };
1227
1228 /* l4_per -> dss */
1229 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1230         .master         = &omap44xx_l4_per_hwmod,
1231         .slave          = &omap44xx_dss_hwmod,
1232         .clk            = "l4_div_ck",
1233         .addr           = omap44xx_dss_addrs,
1234         .user           = OCP_USER_MPU,
1235 };
1236
1237 /* dss slave ports */
1238 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1239         &omap44xx_l3_main_2__dss,
1240         &omap44xx_l4_per__dss,
1241 };
1242
1243 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1244         { .role = "sys_clk", .clk = "dss_sys_clk" },
1245         { .role = "tv_clk", .clk = "dss_tv_clk" },
1246         { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1247 };
1248
1249 static struct omap_hwmod omap44xx_dss_hwmod = {
1250         .name           = "dss_core",
1251         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1252         .class          = &omap44xx_dss_hwmod_class,
1253         .clkdm_name     = "l3_dss_clkdm",
1254         .main_clk       = "dss_dss_clk",
1255         .prcm = {
1256                 .omap4 = {
1257                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1258                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1259                 },
1260         },
1261         .opt_clks       = dss_opt_clks,
1262         .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
1263         .slaves         = omap44xx_dss_slaves,
1264         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_slaves),
1265         .masters        = omap44xx_dss_masters,
1266         .masters_cnt    = ARRAY_SIZE(omap44xx_dss_masters),
1267 };
1268
1269 /*
1270  * 'dispc' class
1271  * display controller
1272  */
1273
1274 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1275         .rev_offs       = 0x0000,
1276         .sysc_offs      = 0x0010,
1277         .syss_offs      = 0x0014,
1278         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1279                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1280                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1281                            SYSS_HAS_RESET_STATUS),
1282         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1283                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1284         .sysc_fields    = &omap_hwmod_sysc_type1,
1285 };
1286
1287 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1288         .name   = "dispc",
1289         .sysc   = &omap44xx_dispc_sysc,
1290 };
1291
1292 /* dss_dispc */
1293 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1294 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1295         { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1296         { .irq = -1 }
1297 };
1298
1299 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1300         { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1301         { .dma_req = -1 }
1302 };
1303
1304 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1305         {
1306                 .pa_start       = 0x58001000,
1307                 .pa_end         = 0x58001fff,
1308                 .flags          = ADDR_TYPE_RT
1309         },
1310         { }
1311 };
1312
1313 /* l3_main_2 -> dss_dispc */
1314 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1315         .master         = &omap44xx_l3_main_2_hwmod,
1316         .slave          = &omap44xx_dss_dispc_hwmod,
1317         .clk            = "dss_fck",
1318         .addr           = omap44xx_dss_dispc_dma_addrs,
1319         .user           = OCP_USER_SDMA,
1320 };
1321
1322 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1323         {
1324                 .pa_start       = 0x48041000,
1325                 .pa_end         = 0x48041fff,
1326                 .flags          = ADDR_TYPE_RT
1327         },
1328         { }
1329 };
1330
1331 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1332         .manager_count          = 3,
1333         .has_framedonetv_irq    = 1
1334 };
1335
1336 /* l4_per -> dss_dispc */
1337 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1338         .master         = &omap44xx_l4_per_hwmod,
1339         .slave          = &omap44xx_dss_dispc_hwmod,
1340         .clk            = "l4_div_ck",
1341         .addr           = omap44xx_dss_dispc_addrs,
1342         .user           = OCP_USER_MPU,
1343 };
1344
1345 /* dss_dispc slave ports */
1346 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1347         &omap44xx_l3_main_2__dss_dispc,
1348         &omap44xx_l4_per__dss_dispc,
1349 };
1350
1351 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1352         .name           = "dss_dispc",
1353         .class          = &omap44xx_dispc_hwmod_class,
1354         .clkdm_name     = "l3_dss_clkdm",
1355         .mpu_irqs       = omap44xx_dss_dispc_irqs,
1356         .sdma_reqs      = omap44xx_dss_dispc_sdma_reqs,
1357         .main_clk       = "dss_dss_clk",
1358         .prcm = {
1359                 .omap4 = {
1360                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1361                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1362                 },
1363         },
1364         .slaves         = omap44xx_dss_dispc_slaves,
1365         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1366         .dev_attr       = &omap44xx_dss_dispc_dev_attr
1367 };
1368
1369 /*
1370  * 'dsi' class
1371  * display serial interface controller
1372  */
1373
1374 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1375         .rev_offs       = 0x0000,
1376         .sysc_offs      = 0x0010,
1377         .syss_offs      = 0x0014,
1378         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1379                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1380                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1381         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1382         .sysc_fields    = &omap_hwmod_sysc_type1,
1383 };
1384
1385 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1386         .name   = "dsi",
1387         .sysc   = &omap44xx_dsi_sysc,
1388 };
1389
1390 /* dss_dsi1 */
1391 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1392 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1393         { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1394         { .irq = -1 }
1395 };
1396
1397 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1398         { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1399         { .dma_req = -1 }
1400 };
1401
1402 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1403         {
1404                 .pa_start       = 0x58004000,
1405                 .pa_end         = 0x580041ff,
1406                 .flags          = ADDR_TYPE_RT
1407         },
1408         { }
1409 };
1410
1411 /* l3_main_2 -> dss_dsi1 */
1412 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1413         .master         = &omap44xx_l3_main_2_hwmod,
1414         .slave          = &omap44xx_dss_dsi1_hwmod,
1415         .clk            = "dss_fck",
1416         .addr           = omap44xx_dss_dsi1_dma_addrs,
1417         .user           = OCP_USER_SDMA,
1418 };
1419
1420 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1421         {
1422                 .pa_start       = 0x48044000,
1423                 .pa_end         = 0x480441ff,
1424                 .flags          = ADDR_TYPE_RT
1425         },
1426         { }
1427 };
1428
1429 /* l4_per -> dss_dsi1 */
1430 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1431         .master         = &omap44xx_l4_per_hwmod,
1432         .slave          = &omap44xx_dss_dsi1_hwmod,
1433         .clk            = "l4_div_ck",
1434         .addr           = omap44xx_dss_dsi1_addrs,
1435         .user           = OCP_USER_MPU,
1436 };
1437
1438 /* dss_dsi1 slave ports */
1439 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1440         &omap44xx_l3_main_2__dss_dsi1,
1441         &omap44xx_l4_per__dss_dsi1,
1442 };
1443
1444 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1445         { .role = "sys_clk", .clk = "dss_sys_clk" },
1446 };
1447
1448 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1449         .name           = "dss_dsi1",
1450         .class          = &omap44xx_dsi_hwmod_class,
1451         .clkdm_name     = "l3_dss_clkdm",
1452         .mpu_irqs       = omap44xx_dss_dsi1_irqs,
1453         .sdma_reqs      = omap44xx_dss_dsi1_sdma_reqs,
1454         .main_clk       = "dss_dss_clk",
1455         .prcm = {
1456                 .omap4 = {
1457                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1458                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1459                 },
1460         },
1461         .opt_clks       = dss_dsi1_opt_clks,
1462         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
1463         .slaves         = omap44xx_dss_dsi1_slaves,
1464         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1465 };
1466
1467 /* dss_dsi2 */
1468 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1469 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1470         { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1471         { .irq = -1 }
1472 };
1473
1474 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1475         { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1476         { .dma_req = -1 }
1477 };
1478
1479 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1480         {
1481                 .pa_start       = 0x58005000,
1482                 .pa_end         = 0x580051ff,
1483                 .flags          = ADDR_TYPE_RT
1484         },
1485         { }
1486 };
1487
1488 /* l3_main_2 -> dss_dsi2 */
1489 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1490         .master         = &omap44xx_l3_main_2_hwmod,
1491         .slave          = &omap44xx_dss_dsi2_hwmod,
1492         .clk            = "dss_fck",
1493         .addr           = omap44xx_dss_dsi2_dma_addrs,
1494         .user           = OCP_USER_SDMA,
1495 };
1496
1497 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1498         {
1499                 .pa_start       = 0x48045000,
1500                 .pa_end         = 0x480451ff,
1501                 .flags          = ADDR_TYPE_RT
1502         },
1503         { }
1504 };
1505
1506 /* l4_per -> dss_dsi2 */
1507 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1508         .master         = &omap44xx_l4_per_hwmod,
1509         .slave          = &omap44xx_dss_dsi2_hwmod,
1510         .clk            = "l4_div_ck",
1511         .addr           = omap44xx_dss_dsi2_addrs,
1512         .user           = OCP_USER_MPU,
1513 };
1514
1515 /* dss_dsi2 slave ports */
1516 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1517         &omap44xx_l3_main_2__dss_dsi2,
1518         &omap44xx_l4_per__dss_dsi2,
1519 };
1520
1521 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1522         { .role = "sys_clk", .clk = "dss_sys_clk" },
1523 };
1524
1525 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1526         .name           = "dss_dsi2",
1527         .class          = &omap44xx_dsi_hwmod_class,
1528         .clkdm_name     = "l3_dss_clkdm",
1529         .mpu_irqs       = omap44xx_dss_dsi2_irqs,
1530         .sdma_reqs      = omap44xx_dss_dsi2_sdma_reqs,
1531         .main_clk       = "dss_dss_clk",
1532         .prcm = {
1533                 .omap4 = {
1534                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1535                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1536                 },
1537         },
1538         .opt_clks       = dss_dsi2_opt_clks,
1539         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi2_opt_clks),
1540         .slaves         = omap44xx_dss_dsi2_slaves,
1541         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1542 };
1543
1544 /*
1545  * 'hdmi' class
1546  * hdmi controller
1547  */
1548
1549 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1550         .rev_offs       = 0x0000,
1551         .sysc_offs      = 0x0010,
1552         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1553                            SYSC_HAS_SOFTRESET),
1554         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1555                            SIDLE_SMART_WKUP),
1556         .sysc_fields    = &omap_hwmod_sysc_type2,
1557 };
1558
1559 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1560         .name   = "hdmi",
1561         .sysc   = &omap44xx_hdmi_sysc,
1562 };
1563
1564 /* dss_hdmi */
1565 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1566 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1567         { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1568         { .irq = -1 }
1569 };
1570
1571 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1572         { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1573         { .dma_req = -1 }
1574 };
1575
1576 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1577         {
1578                 .pa_start       = 0x58006000,
1579                 .pa_end         = 0x58006fff,
1580                 .flags          = ADDR_TYPE_RT
1581         },
1582         { }
1583 };
1584
1585 /* l3_main_2 -> dss_hdmi */
1586 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1587         .master         = &omap44xx_l3_main_2_hwmod,
1588         .slave          = &omap44xx_dss_hdmi_hwmod,
1589         .clk            = "dss_fck",
1590         .addr           = omap44xx_dss_hdmi_dma_addrs,
1591         .user           = OCP_USER_SDMA,
1592 };
1593
1594 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1595         {
1596                 .pa_start       = 0x48046000,
1597                 .pa_end         = 0x48046fff,
1598                 .flags          = ADDR_TYPE_RT
1599         },
1600         { }
1601 };
1602
1603 /* l4_per -> dss_hdmi */
1604 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1605         .master         = &omap44xx_l4_per_hwmod,
1606         .slave          = &omap44xx_dss_hdmi_hwmod,
1607         .clk            = "l4_div_ck",
1608         .addr           = omap44xx_dss_hdmi_addrs,
1609         .user           = OCP_USER_MPU,
1610 };
1611
1612 /* dss_hdmi slave ports */
1613 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1614         &omap44xx_l3_main_2__dss_hdmi,
1615         &omap44xx_l4_per__dss_hdmi,
1616 };
1617
1618 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1619         { .role = "sys_clk", .clk = "dss_sys_clk" },
1620 };
1621
1622 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1623         .name           = "dss_hdmi",
1624         .class          = &omap44xx_hdmi_hwmod_class,
1625         .clkdm_name     = "l3_dss_clkdm",
1626         .mpu_irqs       = omap44xx_dss_hdmi_irqs,
1627         .sdma_reqs      = omap44xx_dss_hdmi_sdma_reqs,
1628         .main_clk       = "dss_48mhz_clk",
1629         .prcm = {
1630                 .omap4 = {
1631                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1632                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1633                 },
1634         },
1635         .opt_clks       = dss_hdmi_opt_clks,
1636         .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
1637         .slaves         = omap44xx_dss_hdmi_slaves,
1638         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1639 };
1640
1641 /*
1642  * 'rfbi' class
1643  * remote frame buffer interface
1644  */
1645
1646 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1647         .rev_offs       = 0x0000,
1648         .sysc_offs      = 0x0010,
1649         .syss_offs      = 0x0014,
1650         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1651                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1652         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1653         .sysc_fields    = &omap_hwmod_sysc_type1,
1654 };
1655
1656 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1657         .name   = "rfbi",
1658         .sysc   = &omap44xx_rfbi_sysc,
1659 };
1660
1661 /* dss_rfbi */
1662 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1663 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1664         { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1665         { .dma_req = -1 }
1666 };
1667
1668 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1669         {
1670                 .pa_start       = 0x58002000,
1671                 .pa_end         = 0x580020ff,
1672                 .flags          = ADDR_TYPE_RT
1673         },
1674         { }
1675 };
1676
1677 /* l3_main_2 -> dss_rfbi */
1678 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1679         .master         = &omap44xx_l3_main_2_hwmod,
1680         .slave          = &omap44xx_dss_rfbi_hwmod,
1681         .clk            = "dss_fck",
1682         .addr           = omap44xx_dss_rfbi_dma_addrs,
1683         .user           = OCP_USER_SDMA,
1684 };
1685
1686 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1687         {
1688                 .pa_start       = 0x48042000,
1689                 .pa_end         = 0x480420ff,
1690                 .flags          = ADDR_TYPE_RT
1691         },
1692         { }
1693 };
1694
1695 /* l4_per -> dss_rfbi */
1696 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1697         .master         = &omap44xx_l4_per_hwmod,
1698         .slave          = &omap44xx_dss_rfbi_hwmod,
1699         .clk            = "l4_div_ck",
1700         .addr           = omap44xx_dss_rfbi_addrs,
1701         .user           = OCP_USER_MPU,
1702 };
1703
1704 /* dss_rfbi slave ports */
1705 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1706         &omap44xx_l3_main_2__dss_rfbi,
1707         &omap44xx_l4_per__dss_rfbi,
1708 };
1709
1710 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1711         { .role = "ick", .clk = "dss_fck" },
1712 };
1713
1714 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1715         .name           = "dss_rfbi",
1716         .class          = &omap44xx_rfbi_hwmod_class,
1717         .clkdm_name     = "l3_dss_clkdm",
1718         .sdma_reqs      = omap44xx_dss_rfbi_sdma_reqs,
1719         .main_clk       = "dss_dss_clk",
1720         .prcm = {
1721                 .omap4 = {
1722                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1723                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1724                 },
1725         },
1726         .opt_clks       = dss_rfbi_opt_clks,
1727         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
1728         .slaves         = omap44xx_dss_rfbi_slaves,
1729         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1730 };
1731
1732 /*
1733  * 'venc' class
1734  * video encoder
1735  */
1736
1737 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1738         .name   = "venc",
1739 };
1740
1741 /* dss_venc */
1742 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1743 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1744         {
1745                 .pa_start       = 0x58003000,
1746                 .pa_end         = 0x580030ff,
1747                 .flags          = ADDR_TYPE_RT
1748         },
1749         { }
1750 };
1751
1752 /* l3_main_2 -> dss_venc */
1753 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1754         .master         = &omap44xx_l3_main_2_hwmod,
1755         .slave          = &omap44xx_dss_venc_hwmod,
1756         .clk            = "dss_fck",
1757         .addr           = omap44xx_dss_venc_dma_addrs,
1758         .user           = OCP_USER_SDMA,
1759 };
1760
1761 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1762         {
1763                 .pa_start       = 0x48043000,
1764                 .pa_end         = 0x480430ff,
1765                 .flags          = ADDR_TYPE_RT
1766         },
1767         { }
1768 };
1769
1770 /* l4_per -> dss_venc */
1771 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1772         .master         = &omap44xx_l4_per_hwmod,
1773         .slave          = &omap44xx_dss_venc_hwmod,
1774         .clk            = "l4_div_ck",
1775         .addr           = omap44xx_dss_venc_addrs,
1776         .user           = OCP_USER_MPU,
1777 };
1778
1779 /* dss_venc slave ports */
1780 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1781         &omap44xx_l3_main_2__dss_venc,
1782         &omap44xx_l4_per__dss_venc,
1783 };
1784
1785 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1786         .name           = "dss_venc",
1787         .class          = &omap44xx_venc_hwmod_class,
1788         .clkdm_name     = "l3_dss_clkdm",
1789         .main_clk       = "dss_tv_clk",
1790         .prcm = {
1791                 .omap4 = {
1792                         .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1793                         .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1794                 },
1795         },
1796         .slaves         = omap44xx_dss_venc_slaves,
1797         .slaves_cnt     = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1798 };
1799
1800 /*
1801  * 'gpio' class
1802  * general purpose io module
1803  */
1804
1805 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1806         .rev_offs       = 0x0000,
1807         .sysc_offs      = 0x0010,
1808         .syss_offs      = 0x0114,
1809         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1810                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811                            SYSS_HAS_RESET_STATUS),
1812         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1813                            SIDLE_SMART_WKUP),
1814         .sysc_fields    = &omap_hwmod_sysc_type1,
1815 };
1816
1817 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1818         .name   = "gpio",
1819         .sysc   = &omap44xx_gpio_sysc,
1820         .rev    = 2,
1821 };
1822
1823 /* gpio dev_attr */
1824 static struct omap_gpio_dev_attr gpio_dev_attr = {
1825         .bank_width     = 32,
1826         .dbck_flag      = true,
1827 };
1828
1829 /* gpio1 */
1830 static struct omap_hwmod omap44xx_gpio1_hwmod;
1831 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1832         { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1833         { .irq = -1 }
1834 };
1835
1836 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1837         {
1838                 .pa_start       = 0x4a310000,
1839                 .pa_end         = 0x4a3101ff,
1840                 .flags          = ADDR_TYPE_RT
1841         },
1842         { }
1843 };
1844
1845 /* l4_wkup -> gpio1 */
1846 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1847         .master         = &omap44xx_l4_wkup_hwmod,
1848         .slave          = &omap44xx_gpio1_hwmod,
1849         .clk            = "l4_wkup_clk_mux_ck",
1850         .addr           = omap44xx_gpio1_addrs,
1851         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1852 };
1853
1854 /* gpio1 slave ports */
1855 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1856         &omap44xx_l4_wkup__gpio1,
1857 };
1858
1859 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1860         { .role = "dbclk", .clk = "gpio1_dbclk" },
1861 };
1862
1863 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1864         .name           = "gpio1",
1865         .class          = &omap44xx_gpio_hwmod_class,
1866         .clkdm_name     = "l4_wkup_clkdm",
1867         .mpu_irqs       = omap44xx_gpio1_irqs,
1868         .main_clk       = "gpio1_ick",
1869         .prcm = {
1870                 .omap4 = {
1871                         .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1872                         .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1873                         .modulemode   = MODULEMODE_HWCTRL,
1874                 },
1875         },
1876         .opt_clks       = gpio1_opt_clks,
1877         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
1878         .dev_attr       = &gpio_dev_attr,
1879         .slaves         = omap44xx_gpio1_slaves,
1880         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio1_slaves),
1881 };
1882
1883 /* gpio2 */
1884 static struct omap_hwmod omap44xx_gpio2_hwmod;
1885 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1886         { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1887         { .irq = -1 }
1888 };
1889
1890 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1891         {
1892                 .pa_start       = 0x48055000,
1893                 .pa_end         = 0x480551ff,
1894                 .flags          = ADDR_TYPE_RT
1895         },
1896         { }
1897 };
1898
1899 /* l4_per -> gpio2 */
1900 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1901         .master         = &omap44xx_l4_per_hwmod,
1902         .slave          = &omap44xx_gpio2_hwmod,
1903         .clk            = "l4_div_ck",
1904         .addr           = omap44xx_gpio2_addrs,
1905         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1906 };
1907
1908 /* gpio2 slave ports */
1909 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1910         &omap44xx_l4_per__gpio2,
1911 };
1912
1913 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1914         { .role = "dbclk", .clk = "gpio2_dbclk" },
1915 };
1916
1917 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1918         .name           = "gpio2",
1919         .class          = &omap44xx_gpio_hwmod_class,
1920         .clkdm_name     = "l4_per_clkdm",
1921         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1922         .mpu_irqs       = omap44xx_gpio2_irqs,
1923         .main_clk       = "gpio2_ick",
1924         .prcm = {
1925                 .omap4 = {
1926                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1927                         .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1928                         .modulemode   = MODULEMODE_HWCTRL,
1929                 },
1930         },
1931         .opt_clks       = gpio2_opt_clks,
1932         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
1933         .dev_attr       = &gpio_dev_attr,
1934         .slaves         = omap44xx_gpio2_slaves,
1935         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio2_slaves),
1936 };
1937
1938 /* gpio3 */
1939 static struct omap_hwmod omap44xx_gpio3_hwmod;
1940 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1941         { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1942         { .irq = -1 }
1943 };
1944
1945 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1946         {
1947                 .pa_start       = 0x48057000,
1948                 .pa_end         = 0x480571ff,
1949                 .flags          = ADDR_TYPE_RT
1950         },
1951         { }
1952 };
1953
1954 /* l4_per -> gpio3 */
1955 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1956         .master         = &omap44xx_l4_per_hwmod,
1957         .slave          = &omap44xx_gpio3_hwmod,
1958         .clk            = "l4_div_ck",
1959         .addr           = omap44xx_gpio3_addrs,
1960         .user           = OCP_USER_MPU | OCP_USER_SDMA,
1961 };
1962
1963 /* gpio3 slave ports */
1964 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1965         &omap44xx_l4_per__gpio3,
1966 };
1967
1968 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1969         { .role = "dbclk", .clk = "gpio3_dbclk" },
1970 };
1971
1972 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1973         .name           = "gpio3",
1974         .class          = &omap44xx_gpio_hwmod_class,
1975         .clkdm_name     = "l4_per_clkdm",
1976         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1977         .mpu_irqs       = omap44xx_gpio3_irqs,
1978         .main_clk       = "gpio3_ick",
1979         .prcm = {
1980                 .omap4 = {
1981                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1982                         .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1983                         .modulemode   = MODULEMODE_HWCTRL,
1984                 },
1985         },
1986         .opt_clks       = gpio3_opt_clks,
1987         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
1988         .dev_attr       = &gpio_dev_attr,
1989         .slaves         = omap44xx_gpio3_slaves,
1990         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio3_slaves),
1991 };
1992
1993 /* gpio4 */
1994 static struct omap_hwmod omap44xx_gpio4_hwmod;
1995 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1996         { .irq = 32 + OMAP44XX_IRQ_GIC_START },
1997         { .irq = -1 }
1998 };
1999
2000 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2001         {
2002                 .pa_start       = 0x48059000,
2003                 .pa_end         = 0x480591ff,
2004                 .flags          = ADDR_TYPE_RT
2005         },
2006         { }
2007 };
2008
2009 /* l4_per -> gpio4 */
2010 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2011         .master         = &omap44xx_l4_per_hwmod,
2012         .slave          = &omap44xx_gpio4_hwmod,
2013         .clk            = "l4_div_ck",
2014         .addr           = omap44xx_gpio4_addrs,
2015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2016 };
2017
2018 /* gpio4 slave ports */
2019 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2020         &omap44xx_l4_per__gpio4,
2021 };
2022
2023 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2024         { .role = "dbclk", .clk = "gpio4_dbclk" },
2025 };
2026
2027 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2028         .name           = "gpio4",
2029         .class          = &omap44xx_gpio_hwmod_class,
2030         .clkdm_name     = "l4_per_clkdm",
2031         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2032         .mpu_irqs       = omap44xx_gpio4_irqs,
2033         .main_clk       = "gpio4_ick",
2034         .prcm = {
2035                 .omap4 = {
2036                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2037                         .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2038                         .modulemode   = MODULEMODE_HWCTRL,
2039                 },
2040         },
2041         .opt_clks       = gpio4_opt_clks,
2042         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
2043         .dev_attr       = &gpio_dev_attr,
2044         .slaves         = omap44xx_gpio4_slaves,
2045         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio4_slaves),
2046 };
2047
2048 /* gpio5 */
2049 static struct omap_hwmod omap44xx_gpio5_hwmod;
2050 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2051         { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2052         { .irq = -1 }
2053 };
2054
2055 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2056         {
2057                 .pa_start       = 0x4805b000,
2058                 .pa_end         = 0x4805b1ff,
2059                 .flags          = ADDR_TYPE_RT
2060         },
2061         { }
2062 };
2063
2064 /* l4_per -> gpio5 */
2065 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2066         .master         = &omap44xx_l4_per_hwmod,
2067         .slave          = &omap44xx_gpio5_hwmod,
2068         .clk            = "l4_div_ck",
2069         .addr           = omap44xx_gpio5_addrs,
2070         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2071 };
2072
2073 /* gpio5 slave ports */
2074 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2075         &omap44xx_l4_per__gpio5,
2076 };
2077
2078 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2079         { .role = "dbclk", .clk = "gpio5_dbclk" },
2080 };
2081
2082 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2083         .name           = "gpio5",
2084         .class          = &omap44xx_gpio_hwmod_class,
2085         .clkdm_name     = "l4_per_clkdm",
2086         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2087         .mpu_irqs       = omap44xx_gpio5_irqs,
2088         .main_clk       = "gpio5_ick",
2089         .prcm = {
2090                 .omap4 = {
2091                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2092                         .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2093                         .modulemode   = MODULEMODE_HWCTRL,
2094                 },
2095         },
2096         .opt_clks       = gpio5_opt_clks,
2097         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
2098         .dev_attr       = &gpio_dev_attr,
2099         .slaves         = omap44xx_gpio5_slaves,
2100         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio5_slaves),
2101 };
2102
2103 /* gpio6 */
2104 static struct omap_hwmod omap44xx_gpio6_hwmod;
2105 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2106         { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2107         { .irq = -1 }
2108 };
2109
2110 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2111         {
2112                 .pa_start       = 0x4805d000,
2113                 .pa_end         = 0x4805d1ff,
2114                 .flags          = ADDR_TYPE_RT
2115         },
2116         { }
2117 };
2118
2119 /* l4_per -> gpio6 */
2120 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2121         .master         = &omap44xx_l4_per_hwmod,
2122         .slave          = &omap44xx_gpio6_hwmod,
2123         .clk            = "l4_div_ck",
2124         .addr           = omap44xx_gpio6_addrs,
2125         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2126 };
2127
2128 /* gpio6 slave ports */
2129 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2130         &omap44xx_l4_per__gpio6,
2131 };
2132
2133 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2134         { .role = "dbclk", .clk = "gpio6_dbclk" },
2135 };
2136
2137 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2138         .name           = "gpio6",
2139         .class          = &omap44xx_gpio_hwmod_class,
2140         .clkdm_name     = "l4_per_clkdm",
2141         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2142         .mpu_irqs       = omap44xx_gpio6_irqs,
2143         .main_clk       = "gpio6_ick",
2144         .prcm = {
2145                 .omap4 = {
2146                         .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2147                         .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2148                         .modulemode   = MODULEMODE_HWCTRL,
2149                 },
2150         },
2151         .opt_clks       = gpio6_opt_clks,
2152         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
2153         .dev_attr       = &gpio_dev_attr,
2154         .slaves         = omap44xx_gpio6_slaves,
2155         .slaves_cnt     = ARRAY_SIZE(omap44xx_gpio6_slaves),
2156 };
2157
2158 /*
2159  * 'hsi' class
2160  * mipi high-speed synchronous serial interface (multichannel and full-duplex
2161  * serial if)
2162  */
2163
2164 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2165         .rev_offs       = 0x0000,
2166         .sysc_offs      = 0x0010,
2167         .syss_offs      = 0x0014,
2168         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2169                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2170                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2171         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2172                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2173                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2174         .sysc_fields    = &omap_hwmod_sysc_type1,
2175 };
2176
2177 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2178         .name   = "hsi",
2179         .sysc   = &omap44xx_hsi_sysc,
2180 };
2181
2182 /* hsi */
2183 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2184         { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2185         { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2186         { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2187         { .irq = -1 }
2188 };
2189
2190 /* hsi master ports */
2191 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2192         &omap44xx_hsi__l3_main_2,
2193 };
2194
2195 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2196         {
2197                 .pa_start       = 0x4a058000,
2198                 .pa_end         = 0x4a05bfff,
2199                 .flags          = ADDR_TYPE_RT
2200         },
2201         { }
2202 };
2203
2204 /* l4_cfg -> hsi */
2205 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2206         .master         = &omap44xx_l4_cfg_hwmod,
2207         .slave          = &omap44xx_hsi_hwmod,
2208         .clk            = "l4_div_ck",
2209         .addr           = omap44xx_hsi_addrs,
2210         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2211 };
2212
2213 /* hsi slave ports */
2214 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2215         &omap44xx_l4_cfg__hsi,
2216 };
2217
2218 static struct omap_hwmod omap44xx_hsi_hwmod = {
2219         .name           = "hsi",
2220         .class          = &omap44xx_hsi_hwmod_class,
2221         .clkdm_name     = "l3_init_clkdm",
2222         .mpu_irqs       = omap44xx_hsi_irqs,
2223         .main_clk       = "hsi_fck",
2224         .prcm = {
2225                 .omap4 = {
2226                         .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2227                         .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2228                         .modulemode   = MODULEMODE_HWCTRL,
2229                 },
2230         },
2231         .slaves         = omap44xx_hsi_slaves,
2232         .slaves_cnt     = ARRAY_SIZE(omap44xx_hsi_slaves),
2233         .masters        = omap44xx_hsi_masters,
2234         .masters_cnt    = ARRAY_SIZE(omap44xx_hsi_masters),
2235 };
2236
2237 /*
2238  * 'i2c' class
2239  * multimaster high-speed i2c controller
2240  */
2241
2242 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2243         .sysc_offs      = 0x0010,
2244         .syss_offs      = 0x0090,
2245         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2246                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2247                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2248         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2249                            SIDLE_SMART_WKUP),
2250         .sysc_fields    = &omap_hwmod_sysc_type1,
2251 };
2252
2253 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2254         .name   = "i2c",
2255         .sysc   = &omap44xx_i2c_sysc,
2256         .rev    = OMAP_I2C_IP_VERSION_2,
2257         .reset  = &omap_i2c_reset,
2258 };
2259
2260 static struct omap_i2c_dev_attr i2c_dev_attr = {
2261         .flags  = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2262 };
2263
2264 /* i2c1 */
2265 static struct omap_hwmod omap44xx_i2c1_hwmod;
2266 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2267         { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2268         { .irq = -1 }
2269 };
2270
2271 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2272         { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2273         { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2274         { .dma_req = -1 }
2275 };
2276
2277 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2278         {
2279                 .pa_start       = 0x48070000,
2280                 .pa_end         = 0x480700ff,
2281                 .flags          = ADDR_TYPE_RT
2282         },
2283         { }
2284 };
2285
2286 /* l4_per -> i2c1 */
2287 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2288         .master         = &omap44xx_l4_per_hwmod,
2289         .slave          = &omap44xx_i2c1_hwmod,
2290         .clk            = "l4_div_ck",
2291         .addr           = omap44xx_i2c1_addrs,
2292         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2293 };
2294
2295 /* i2c1 slave ports */
2296 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2297         &omap44xx_l4_per__i2c1,
2298 };
2299
2300 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2301         .name           = "i2c1",
2302         .class          = &omap44xx_i2c_hwmod_class,
2303         .clkdm_name     = "l4_per_clkdm",
2304         .flags          = HWMOD_16BIT_REG,
2305         .mpu_irqs       = omap44xx_i2c1_irqs,
2306         .sdma_reqs      = omap44xx_i2c1_sdma_reqs,
2307         .main_clk       = "i2c1_fck",
2308         .prcm = {
2309                 .omap4 = {
2310                         .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2311                         .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2312                         .modulemode   = MODULEMODE_SWCTRL,
2313                 },
2314         },
2315         .slaves         = omap44xx_i2c1_slaves,
2316         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c1_slaves),
2317         .dev_attr       = &i2c_dev_attr,
2318 };
2319
2320 /* i2c2 */
2321 static struct omap_hwmod omap44xx_i2c2_hwmod;
2322 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2323         { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2324         { .irq = -1 }
2325 };
2326
2327 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2328         { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2329         { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2330         { .dma_req = -1 }
2331 };
2332
2333 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2334         {
2335                 .pa_start       = 0x48072000,
2336                 .pa_end         = 0x480720ff,
2337                 .flags          = ADDR_TYPE_RT
2338         },
2339         { }
2340 };
2341
2342 /* l4_per -> i2c2 */
2343 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2344         .master         = &omap44xx_l4_per_hwmod,
2345         .slave          = &omap44xx_i2c2_hwmod,
2346         .clk            = "l4_div_ck",
2347         .addr           = omap44xx_i2c2_addrs,
2348         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2349 };
2350
2351 /* i2c2 slave ports */
2352 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2353         &omap44xx_l4_per__i2c2,
2354 };
2355
2356 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2357         .name           = "i2c2",
2358         .class          = &omap44xx_i2c_hwmod_class,
2359         .clkdm_name     = "l4_per_clkdm",
2360         .flags          = HWMOD_16BIT_REG,
2361         .mpu_irqs       = omap44xx_i2c2_irqs,
2362         .sdma_reqs      = omap44xx_i2c2_sdma_reqs,
2363         .main_clk       = "i2c2_fck",
2364         .prcm = {
2365                 .omap4 = {
2366                         .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2367                         .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2368                         .modulemode   = MODULEMODE_SWCTRL,
2369                 },
2370         },
2371         .slaves         = omap44xx_i2c2_slaves,
2372         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c2_slaves),
2373         .dev_attr       = &i2c_dev_attr,
2374 };
2375
2376 /* i2c3 */
2377 static struct omap_hwmod omap44xx_i2c3_hwmod;
2378 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2379         { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2380         { .irq = -1 }
2381 };
2382
2383 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2384         { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2385         { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2386         { .dma_req = -1 }
2387 };
2388
2389 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2390         {
2391                 .pa_start       = 0x48060000,
2392                 .pa_end         = 0x480600ff,
2393                 .flags          = ADDR_TYPE_RT
2394         },
2395         { }
2396 };
2397
2398 /* l4_per -> i2c3 */
2399 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2400         .master         = &omap44xx_l4_per_hwmod,
2401         .slave          = &omap44xx_i2c3_hwmod,
2402         .clk            = "l4_div_ck",
2403         .addr           = omap44xx_i2c3_addrs,
2404         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2405 };
2406
2407 /* i2c3 slave ports */
2408 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2409         &omap44xx_l4_per__i2c3,
2410 };
2411
2412 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2413         .name           = "i2c3",
2414         .class          = &omap44xx_i2c_hwmod_class,
2415         .clkdm_name     = "l4_per_clkdm",
2416         .flags          = HWMOD_16BIT_REG,
2417         .mpu_irqs       = omap44xx_i2c3_irqs,
2418         .sdma_reqs      = omap44xx_i2c3_sdma_reqs,
2419         .main_clk       = "i2c3_fck",
2420         .prcm = {
2421                 .omap4 = {
2422                         .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2423                         .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2424                         .modulemode   = MODULEMODE_SWCTRL,
2425                 },
2426         },
2427         .slaves         = omap44xx_i2c3_slaves,
2428         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c3_slaves),
2429         .dev_attr       = &i2c_dev_attr,
2430 };
2431
2432 /* i2c4 */
2433 static struct omap_hwmod omap44xx_i2c4_hwmod;
2434 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2435         { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2436         { .irq = -1 }
2437 };
2438
2439 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2440         { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2441         { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2442         { .dma_req = -1 }
2443 };
2444
2445 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2446         {
2447                 .pa_start       = 0x48350000,
2448                 .pa_end         = 0x483500ff,
2449                 .flags          = ADDR_TYPE_RT
2450         },
2451         { }
2452 };
2453
2454 /* l4_per -> i2c4 */
2455 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2456         .master         = &omap44xx_l4_per_hwmod,
2457         .slave          = &omap44xx_i2c4_hwmod,
2458         .clk            = "l4_div_ck",
2459         .addr           = omap44xx_i2c4_addrs,
2460         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2461 };
2462
2463 /* i2c4 slave ports */
2464 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2465         &omap44xx_l4_per__i2c4,
2466 };
2467
2468 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2469         .name           = "i2c4",
2470         .class          = &omap44xx_i2c_hwmod_class,
2471         .clkdm_name     = "l4_per_clkdm",
2472         .flags          = HWMOD_16BIT_REG,
2473         .mpu_irqs       = omap44xx_i2c4_irqs,
2474         .sdma_reqs      = omap44xx_i2c4_sdma_reqs,
2475         .main_clk       = "i2c4_fck",
2476         .prcm = {
2477                 .omap4 = {
2478                         .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2479                         .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2480                         .modulemode   = MODULEMODE_SWCTRL,
2481                 },
2482         },
2483         .slaves         = omap44xx_i2c4_slaves,
2484         .slaves_cnt     = ARRAY_SIZE(omap44xx_i2c4_slaves),
2485         .dev_attr       = &i2c_dev_attr,
2486 };
2487
2488 /*
2489  * 'ipu' class
2490  * imaging processor unit
2491  */
2492
2493 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2494         .name   = "ipu",
2495 };
2496
2497 /* ipu */
2498 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2499         { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2500         { .irq = -1 }
2501 };
2502
2503 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2504         { .name = "cpu0", .rst_shift = 0 },
2505 };
2506
2507 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2508         { .name = "cpu1", .rst_shift = 1 },
2509 };
2510
2511 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2512         { .name = "mmu_cache", .rst_shift = 2 },
2513 };
2514
2515 /* ipu master ports */
2516 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2517         &omap44xx_ipu__l3_main_2,
2518 };
2519
2520 /* l3_main_2 -> ipu */
2521 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2522         .master         = &omap44xx_l3_main_2_hwmod,
2523         .slave          = &omap44xx_ipu_hwmod,
2524         .clk            = "l3_div_ck",
2525         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2526 };
2527
2528 /* ipu slave ports */
2529 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2530         &omap44xx_l3_main_2__ipu,
2531 };
2532
2533 /* Pseudo hwmod for reset control purpose only */
2534 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2535         .name           = "ipu_c0",
2536         .class          = &omap44xx_ipu_hwmod_class,
2537         .clkdm_name     = "ducati_clkdm",
2538         .flags          = HWMOD_INIT_NO_RESET,
2539         .rst_lines      = omap44xx_ipu_c0_resets,
2540         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2541         .prcm = {
2542                 .omap4 = {
2543                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2544                 },
2545         },
2546 };
2547
2548 /* Pseudo hwmod for reset control purpose only */
2549 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2550         .name           = "ipu_c1",
2551         .class          = &omap44xx_ipu_hwmod_class,
2552         .clkdm_name     = "ducati_clkdm",
2553         .flags          = HWMOD_INIT_NO_RESET,
2554         .rst_lines      = omap44xx_ipu_c1_resets,
2555         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2556         .prcm = {
2557                 .omap4 = {
2558                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2559                 },
2560         },
2561 };
2562
2563 static struct omap_hwmod omap44xx_ipu_hwmod = {
2564         .name           = "ipu",
2565         .class          = &omap44xx_ipu_hwmod_class,
2566         .clkdm_name     = "ducati_clkdm",
2567         .mpu_irqs       = omap44xx_ipu_irqs,
2568         .rst_lines      = omap44xx_ipu_resets,
2569         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_ipu_resets),
2570         .main_clk       = "ipu_fck",
2571         .prcm = {
2572                 .omap4 = {
2573                         .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2574                         .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2575                         .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2576                         .modulemode   = MODULEMODE_HWCTRL,
2577                 },
2578         },
2579         .slaves         = omap44xx_ipu_slaves,
2580         .slaves_cnt     = ARRAY_SIZE(omap44xx_ipu_slaves),
2581         .masters        = omap44xx_ipu_masters,
2582         .masters_cnt    = ARRAY_SIZE(omap44xx_ipu_masters),
2583 };
2584
2585 /*
2586  * 'iss' class
2587  * external images sensor pixel data processor
2588  */
2589
2590 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2591         .rev_offs       = 0x0000,
2592         .sysc_offs      = 0x0010,
2593         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2594                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2595         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2596                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2597                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2598         .sysc_fields    = &omap_hwmod_sysc_type2,
2599 };
2600
2601 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2602         .name   = "iss",
2603         .sysc   = &omap44xx_iss_sysc,
2604 };
2605
2606 /* iss */
2607 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2608         { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2609         { .irq = -1 }
2610 };
2611
2612 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2613         { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2614         { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2615         { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2616         { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2617         { .dma_req = -1 }
2618 };
2619
2620 /* iss master ports */
2621 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2622         &omap44xx_iss__l3_main_2,
2623 };
2624
2625 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2626         {
2627                 .pa_start       = 0x52000000,
2628                 .pa_end         = 0x520000ff,
2629                 .flags          = ADDR_TYPE_RT
2630         },
2631         { }
2632 };
2633
2634 /* l3_main_2 -> iss */
2635 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2636         .master         = &omap44xx_l3_main_2_hwmod,
2637         .slave          = &omap44xx_iss_hwmod,
2638         .clk            = "l3_div_ck",
2639         .addr           = omap44xx_iss_addrs,
2640         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2641 };
2642
2643 /* iss slave ports */
2644 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2645         &omap44xx_l3_main_2__iss,
2646 };
2647
2648 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2649         { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2650 };
2651
2652 static struct omap_hwmod omap44xx_iss_hwmod = {
2653         .name           = "iss",
2654         .class          = &omap44xx_iss_hwmod_class,
2655         .clkdm_name     = "iss_clkdm",
2656         .mpu_irqs       = omap44xx_iss_irqs,
2657         .sdma_reqs      = omap44xx_iss_sdma_reqs,
2658         .main_clk       = "iss_fck",
2659         .prcm = {
2660                 .omap4 = {
2661                         .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2662                         .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2663                         .modulemode   = MODULEMODE_SWCTRL,
2664                 },
2665         },
2666         .opt_clks       = iss_opt_clks,
2667         .opt_clks_cnt   = ARRAY_SIZE(iss_opt_clks),
2668         .slaves         = omap44xx_iss_slaves,
2669         .slaves_cnt     = ARRAY_SIZE(omap44xx_iss_slaves),
2670         .masters        = omap44xx_iss_masters,
2671         .masters_cnt    = ARRAY_SIZE(omap44xx_iss_masters),
2672 };
2673
2674 /*
2675  * 'iva' class
2676  * multi-standard video encoder/decoder hardware accelerator
2677  */
2678
2679 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2680         .name   = "iva",
2681 };
2682
2683 /* iva */
2684 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2685         { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2686         { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2687         { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2688         { .irq = -1 }
2689 };
2690
2691 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2692         { .name = "logic", .rst_shift = 2 },
2693 };
2694
2695 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2696         { .name = "seq0", .rst_shift = 0 },
2697 };
2698
2699 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2700         { .name = "seq1", .rst_shift = 1 },
2701 };
2702
2703 /* iva master ports */
2704 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2705         &omap44xx_iva__l3_main_2,
2706         &omap44xx_iva__l3_instr,
2707 };
2708
2709 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2710         {
2711                 .pa_start       = 0x5a000000,
2712                 .pa_end         = 0x5a07ffff,
2713                 .flags          = ADDR_TYPE_RT
2714         },
2715         { }
2716 };
2717
2718 /* l3_main_2 -> iva */
2719 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2720         .master         = &omap44xx_l3_main_2_hwmod,
2721         .slave          = &omap44xx_iva_hwmod,
2722         .clk            = "l3_div_ck",
2723         .addr           = omap44xx_iva_addrs,
2724         .user           = OCP_USER_MPU,
2725 };
2726
2727 /* iva slave ports */
2728 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2729         &omap44xx_dsp__iva,
2730         &omap44xx_l3_main_2__iva,
2731 };
2732
2733 /* Pseudo hwmod for reset control purpose only */
2734 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2735         .name           = "iva_seq0",
2736         .class          = &omap44xx_iva_hwmod_class,
2737         .clkdm_name     = "ivahd_clkdm",
2738         .flags          = HWMOD_INIT_NO_RESET,
2739         .rst_lines      = omap44xx_iva_seq0_resets,
2740         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2741         .prcm = {
2742                 .omap4 = {
2743                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2744                 },
2745         },
2746 };
2747
2748 /* Pseudo hwmod for reset control purpose only */
2749 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2750         .name           = "iva_seq1",
2751         .class          = &omap44xx_iva_hwmod_class,
2752         .clkdm_name     = "ivahd_clkdm",
2753         .flags          = HWMOD_INIT_NO_RESET,
2754         .rst_lines      = omap44xx_iva_seq1_resets,
2755         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2756         .prcm = {
2757                 .omap4 = {
2758                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2759                 },
2760         },
2761 };
2762
2763 static struct omap_hwmod omap44xx_iva_hwmod = {
2764         .name           = "iva",
2765         .class          = &omap44xx_iva_hwmod_class,
2766         .clkdm_name     = "ivahd_clkdm",
2767         .mpu_irqs       = omap44xx_iva_irqs,
2768         .rst_lines      = omap44xx_iva_resets,
2769         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_iva_resets),
2770         .main_clk       = "iva_fck",
2771         .prcm = {
2772                 .omap4 = {
2773                         .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2774                         .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2775                         .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2776                         .modulemode   = MODULEMODE_HWCTRL,
2777                 },
2778         },
2779         .slaves         = omap44xx_iva_slaves,
2780         .slaves_cnt     = ARRAY_SIZE(omap44xx_iva_slaves),
2781         .masters        = omap44xx_iva_masters,
2782         .masters_cnt    = ARRAY_SIZE(omap44xx_iva_masters),
2783 };
2784
2785 /*
2786  * 'kbd' class
2787  * keyboard controller
2788  */
2789
2790 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2791         .rev_offs       = 0x0000,
2792         .sysc_offs      = 0x0010,
2793         .syss_offs      = 0x0014,
2794         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2795                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2796                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2797                            SYSS_HAS_RESET_STATUS),
2798         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2799         .sysc_fields    = &omap_hwmod_sysc_type1,
2800 };
2801
2802 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2803         .name   = "kbd",
2804         .sysc   = &omap44xx_kbd_sysc,
2805 };
2806
2807 /* kbd */
2808 static struct omap_hwmod omap44xx_kbd_hwmod;
2809 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2810         { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2811         { .irq = -1 }
2812 };
2813
2814 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2815         {
2816                 .pa_start       = 0x4a31c000,
2817                 .pa_end         = 0x4a31c07f,
2818                 .flags          = ADDR_TYPE_RT
2819         },
2820         { }
2821 };
2822
2823 /* l4_wkup -> kbd */
2824 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2825         .master         = &omap44xx_l4_wkup_hwmod,
2826         .slave          = &omap44xx_kbd_hwmod,
2827         .clk            = "l4_wkup_clk_mux_ck",
2828         .addr           = omap44xx_kbd_addrs,
2829         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2830 };
2831
2832 /* kbd slave ports */
2833 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2834         &omap44xx_l4_wkup__kbd,
2835 };
2836
2837 static struct omap_hwmod omap44xx_kbd_hwmod = {
2838         .name           = "kbd",
2839         .class          = &omap44xx_kbd_hwmod_class,
2840         .clkdm_name     = "l4_wkup_clkdm",
2841         .mpu_irqs       = omap44xx_kbd_irqs,
2842         .main_clk       = "kbd_fck",
2843         .prcm = {
2844                 .omap4 = {
2845                         .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2846                         .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2847                         .modulemode   = MODULEMODE_SWCTRL,
2848                 },
2849         },
2850         .slaves         = omap44xx_kbd_slaves,
2851         .slaves_cnt     = ARRAY_SIZE(omap44xx_kbd_slaves),
2852 };
2853
2854 /*
2855  * 'mailbox' class
2856  * mailbox module allowing communication between the on-chip processors using a
2857  * queued mailbox-interrupt mechanism.
2858  */
2859
2860 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2861         .rev_offs       = 0x0000,
2862         .sysc_offs      = 0x0010,
2863         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2864                            SYSC_HAS_SOFTRESET),
2865         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2866         .sysc_fields    = &omap_hwmod_sysc_type2,
2867 };
2868
2869 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2870         .name   = "mailbox",
2871         .sysc   = &omap44xx_mailbox_sysc,
2872 };
2873
2874 /* mailbox */
2875 static struct omap_hwmod omap44xx_mailbox_hwmod;
2876 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2877         { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2878         { .irq = -1 }
2879 };
2880
2881 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2882         {
2883                 .pa_start       = 0x4a0f4000,
2884                 .pa_end         = 0x4a0f41ff,
2885                 .flags          = ADDR_TYPE_RT
2886         },
2887         { }
2888 };
2889
2890 /* l4_cfg -> mailbox */
2891 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2892         .master         = &omap44xx_l4_cfg_hwmod,
2893         .slave          = &omap44xx_mailbox_hwmod,
2894         .clk            = "l4_div_ck",
2895         .addr           = omap44xx_mailbox_addrs,
2896         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2897 };
2898
2899 /* mailbox slave ports */
2900 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2901         &omap44xx_l4_cfg__mailbox,
2902 };
2903
2904 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2905         .name           = "mailbox",
2906         .class          = &omap44xx_mailbox_hwmod_class,
2907         .clkdm_name     = "l4_cfg_clkdm",
2908         .mpu_irqs       = omap44xx_mailbox_irqs,
2909         .prcm = {
2910                 .omap4 = {
2911                         .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2912                         .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2913                 },
2914         },
2915         .slaves         = omap44xx_mailbox_slaves,
2916         .slaves_cnt     = ARRAY_SIZE(omap44xx_mailbox_slaves),
2917 };
2918
2919 /*
2920  * 'mcbsp' class
2921  * multi channel buffered serial port controller
2922  */
2923
2924 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2925         .sysc_offs      = 0x008c,
2926         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2927                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2929         .sysc_fields    = &omap_hwmod_sysc_type1,
2930 };
2931
2932 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2933         .name   = "mcbsp",
2934         .sysc   = &omap44xx_mcbsp_sysc,
2935         .rev    = MCBSP_CONFIG_TYPE4,
2936 };
2937
2938 /* mcbsp1 */
2939 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2940 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2941         { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2942         { .irq = -1 }
2943 };
2944
2945 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2946         { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2947         { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2948         { .dma_req = -1 }
2949 };
2950
2951 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2952         {
2953                 .name           = "mpu",
2954                 .pa_start       = 0x40122000,
2955                 .pa_end         = 0x401220ff,
2956                 .flags          = ADDR_TYPE_RT
2957         },
2958         { }
2959 };
2960
2961 /* l4_abe -> mcbsp1 */
2962 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2963         .master         = &omap44xx_l4_abe_hwmod,
2964         .slave          = &omap44xx_mcbsp1_hwmod,
2965         .clk            = "ocp_abe_iclk",
2966         .addr           = omap44xx_mcbsp1_addrs,
2967         .user           = OCP_USER_MPU,
2968 };
2969
2970 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2971         {
2972                 .name           = "dma",
2973                 .pa_start       = 0x49022000,
2974                 .pa_end         = 0x490220ff,
2975                 .flags          = ADDR_TYPE_RT
2976         },
2977         { }
2978 };
2979
2980 /* l4_abe -> mcbsp1 (dma) */
2981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2982         .master         = &omap44xx_l4_abe_hwmod,
2983         .slave          = &omap44xx_mcbsp1_hwmod,
2984         .clk            = "ocp_abe_iclk",
2985         .addr           = omap44xx_mcbsp1_dma_addrs,
2986         .user           = OCP_USER_SDMA,
2987 };
2988
2989 /* mcbsp1 slave ports */
2990 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2991         &omap44xx_l4_abe__mcbsp1,
2992         &omap44xx_l4_abe__mcbsp1_dma,
2993 };
2994
2995 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2996         .name           = "mcbsp1",
2997         .class          = &omap44xx_mcbsp_hwmod_class,
2998         .clkdm_name     = "abe_clkdm",
2999         .mpu_irqs       = omap44xx_mcbsp1_irqs,
3000         .sdma_reqs      = omap44xx_mcbsp1_sdma_reqs,
3001         .main_clk       = "mcbsp1_fck",
3002         .prcm = {
3003                 .omap4 = {
3004                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3005                         .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3006                         .modulemode   = MODULEMODE_SWCTRL,
3007                 },
3008         },
3009         .slaves         = omap44xx_mcbsp1_slaves,
3010         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3011 };
3012
3013 /* mcbsp2 */
3014 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3015 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3016         { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3017         { .irq = -1 }
3018 };
3019
3020 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3021         { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3022         { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3023         { .dma_req = -1 }
3024 };
3025
3026 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3027         {
3028                 .name           = "mpu",
3029                 .pa_start       = 0x40124000,
3030                 .pa_end         = 0x401240ff,
3031                 .flags          = ADDR_TYPE_RT
3032         },
3033         { }
3034 };
3035
3036 /* l4_abe -> mcbsp2 */
3037 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3038         .master         = &omap44xx_l4_abe_hwmod,
3039         .slave          = &omap44xx_mcbsp2_hwmod,
3040         .clk            = "ocp_abe_iclk",
3041         .addr           = omap44xx_mcbsp2_addrs,
3042         .user           = OCP_USER_MPU,
3043 };
3044
3045 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3046         {
3047                 .name           = "dma",
3048                 .pa_start       = 0x49024000,
3049                 .pa_end         = 0x490240ff,
3050                 .flags          = ADDR_TYPE_RT
3051         },
3052         { }
3053 };
3054
3055 /* l4_abe -> mcbsp2 (dma) */
3056 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3057         .master         = &omap44xx_l4_abe_hwmod,
3058         .slave          = &omap44xx_mcbsp2_hwmod,
3059         .clk            = "ocp_abe_iclk",
3060         .addr           = omap44xx_mcbsp2_dma_addrs,
3061         .user           = OCP_USER_SDMA,
3062 };
3063
3064 /* mcbsp2 slave ports */
3065 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3066         &omap44xx_l4_abe__mcbsp2,
3067         &omap44xx_l4_abe__mcbsp2_dma,
3068 };
3069
3070 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3071         .name           = "mcbsp2",
3072         .class          = &omap44xx_mcbsp_hwmod_class,
3073         .clkdm_name     = "abe_clkdm",
3074         .mpu_irqs       = omap44xx_mcbsp2_irqs,
3075         .sdma_reqs      = omap44xx_mcbsp2_sdma_reqs,
3076         .main_clk       = "mcbsp2_fck",
3077         .prcm = {
3078                 .omap4 = {
3079                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3080                         .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3081                         .modulemode   = MODULEMODE_SWCTRL,
3082                 },
3083         },
3084         .slaves         = omap44xx_mcbsp2_slaves,
3085         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3086 };
3087
3088 /* mcbsp3 */
3089 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3090 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3091         { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3092         { .irq = -1 }
3093 };
3094
3095 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3096         { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3097         { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3098         { .dma_req = -1 }
3099 };
3100
3101 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3102         {
3103                 .name           = "mpu",
3104                 .pa_start       = 0x40126000,
3105                 .pa_end         = 0x401260ff,
3106                 .flags          = ADDR_TYPE_RT
3107         },
3108         { }
3109 };
3110
3111 /* l4_abe -> mcbsp3 */
3112 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3113         .master         = &omap44xx_l4_abe_hwmod,
3114         .slave          = &omap44xx_mcbsp3_hwmod,
3115         .clk            = "ocp_abe_iclk",
3116         .addr           = omap44xx_mcbsp3_addrs,
3117         .user           = OCP_USER_MPU,
3118 };
3119
3120 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3121         {
3122                 .name           = "dma",
3123                 .pa_start       = 0x49026000,
3124                 .pa_end         = 0x490260ff,
3125                 .flags          = ADDR_TYPE_RT
3126         },
3127         { }
3128 };
3129
3130 /* l4_abe -> mcbsp3 (dma) */
3131 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3132         .master         = &omap44xx_l4_abe_hwmod,
3133         .slave          = &omap44xx_mcbsp3_hwmod,
3134         .clk            = "ocp_abe_iclk",
3135         .addr           = omap44xx_mcbsp3_dma_addrs,
3136         .user           = OCP_USER_SDMA,
3137 };
3138
3139 /* mcbsp3 slave ports */
3140 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3141         &omap44xx_l4_abe__mcbsp3,
3142         &omap44xx_l4_abe__mcbsp3_dma,
3143 };
3144
3145 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3146         .name           = "mcbsp3",
3147         .class          = &omap44xx_mcbsp_hwmod_class,
3148         .clkdm_name     = "abe_clkdm",
3149         .mpu_irqs       = omap44xx_mcbsp3_irqs,
3150         .sdma_reqs      = omap44xx_mcbsp3_sdma_reqs,
3151         .main_clk       = "mcbsp3_fck",
3152         .prcm = {
3153                 .omap4 = {
3154                         .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3155                         .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3156                         .modulemode   = MODULEMODE_SWCTRL,
3157                 },
3158         },
3159         .slaves         = omap44xx_mcbsp3_slaves,
3160         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3161 };
3162
3163 /* mcbsp4 */
3164 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3165 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3166         { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3167         { .irq = -1 }
3168 };
3169
3170 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3171         { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3172         { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3173         { .dma_req = -1 }
3174 };
3175
3176 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3177         {
3178                 .pa_start       = 0x48096000,
3179                 .pa_end         = 0x480960ff,
3180                 .flags          = ADDR_TYPE_RT
3181         },
3182         { }
3183 };
3184
3185 /* l4_per -> mcbsp4 */
3186 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3187         .master         = &omap44xx_l4_per_hwmod,
3188         .slave          = &omap44xx_mcbsp4_hwmod,
3189         .clk            = "l4_div_ck",
3190         .addr           = omap44xx_mcbsp4_addrs,
3191         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3192 };
3193
3194 /* mcbsp4 slave ports */
3195 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3196         &omap44xx_l4_per__mcbsp4,
3197 };
3198
3199 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3200         .name           = "mcbsp4",
3201         .class          = &omap44xx_mcbsp_hwmod_class,
3202         .clkdm_name     = "l4_per_clkdm",
3203         .mpu_irqs       = omap44xx_mcbsp4_irqs,
3204         .sdma_reqs      = omap44xx_mcbsp4_sdma_reqs,
3205         .main_clk       = "mcbsp4_fck",
3206         .prcm = {
3207                 .omap4 = {
3208                         .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3209                         .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3210                         .modulemode   = MODULEMODE_SWCTRL,
3211                 },
3212         },
3213         .slaves         = omap44xx_mcbsp4_slaves,
3214         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3215 };
3216
3217 /*
3218  * 'mcpdm' class
3219  * multi channel pdm controller (proprietary interface with phoenix power
3220  * ic)
3221  */
3222
3223 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3224         .rev_offs       = 0x0000,
3225         .sysc_offs      = 0x0010,
3226         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3227                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3228         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3229                            SIDLE_SMART_WKUP),
3230         .sysc_fields    = &omap_hwmod_sysc_type2,
3231 };
3232
3233 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3234         .name   = "mcpdm",
3235         .sysc   = &omap44xx_mcpdm_sysc,
3236 };
3237
3238 /* mcpdm */
3239 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3240 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3241         { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3242         { .irq = -1 }
3243 };
3244
3245 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3246         { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3247         { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3248         { .dma_req = -1 }
3249 };
3250
3251 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3252         {
3253                 .pa_start       = 0x40132000,
3254                 .pa_end         = 0x4013207f,
3255                 .flags          = ADDR_TYPE_RT
3256         },
3257         { }
3258 };
3259
3260 /* l4_abe -> mcpdm */
3261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3262         .master         = &omap44xx_l4_abe_hwmod,
3263         .slave          = &omap44xx_mcpdm_hwmod,
3264         .clk            = "ocp_abe_iclk",
3265         .addr           = omap44xx_mcpdm_addrs,
3266         .user           = OCP_USER_MPU,
3267 };
3268
3269 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3270         {
3271                 .pa_start       = 0x49032000,
3272                 .pa_end         = 0x4903207f,
3273                 .flags          = ADDR_TYPE_RT
3274         },
3275         { }
3276 };
3277
3278 /* l4_abe -> mcpdm (dma) */
3279 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3280         .master         = &omap44xx_l4_abe_hwmod,
3281         .slave          = &omap44xx_mcpdm_hwmod,
3282         .clk            = "ocp_abe_iclk",
3283         .addr           = omap44xx_mcpdm_dma_addrs,
3284         .user           = OCP_USER_SDMA,
3285 };
3286
3287 /* mcpdm slave ports */
3288 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3289         &omap44xx_l4_abe__mcpdm,
3290         &omap44xx_l4_abe__mcpdm_dma,
3291 };
3292
3293 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3294         .name           = "mcpdm",
3295         .class          = &omap44xx_mcpdm_hwmod_class,
3296         .clkdm_name     = "abe_clkdm",
3297         .mpu_irqs       = omap44xx_mcpdm_irqs,
3298         .sdma_reqs      = omap44xx_mcpdm_sdma_reqs,
3299         .main_clk       = "mcpdm_fck",
3300         .prcm = {
3301                 .omap4 = {
3302                         .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3303                         .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3304                         .modulemode   = MODULEMODE_SWCTRL,
3305                 },
3306         },
3307         .slaves         = omap44xx_mcpdm_slaves,
3308         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3309 };
3310
3311 /*
3312  * 'mcspi' class
3313  * multichannel serial port interface (mcspi) / master/slave synchronous serial
3314  * bus
3315  */
3316
3317 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3318         .rev_offs       = 0x0000,
3319         .sysc_offs      = 0x0010,
3320         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3321                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3323                            SIDLE_SMART_WKUP),
3324         .sysc_fields    = &omap_hwmod_sysc_type2,
3325 };
3326
3327 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3328         .name   = "mcspi",
3329         .sysc   = &omap44xx_mcspi_sysc,
3330         .rev    = OMAP4_MCSPI_REV,
3331 };
3332
3333 /* mcspi1 */
3334 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3335 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3336         { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3337         { .irq = -1 }
3338 };
3339
3340 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3341         { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3342         { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3343         { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3344         { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3345         { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3346         { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3347         { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3348         { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3349         { .dma_req = -1 }
3350 };
3351
3352 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3353         {
3354                 .pa_start       = 0x48098000,
3355                 .pa_end         = 0x480981ff,
3356                 .flags          = ADDR_TYPE_RT
3357         },
3358         { }
3359 };
3360
3361 /* l4_per -> mcspi1 */
3362 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3363         .master         = &omap44xx_l4_per_hwmod,
3364         .slave          = &omap44xx_mcspi1_hwmod,
3365         .clk            = "l4_div_ck",
3366         .addr           = omap44xx_mcspi1_addrs,
3367         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3369
3370 /* mcspi1 slave ports */
3371 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3372         &omap44xx_l4_per__mcspi1,
3373 };
3374
3375 /* mcspi1 dev_attr */
3376 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3377         .num_chipselect = 4,
3378 };
3379
3380 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3381         .name           = "mcspi1",
3382         .class          = &omap44xx_mcspi_hwmod_class,
3383         .clkdm_name     = "l4_per_clkdm",
3384         .mpu_irqs       = omap44xx_mcspi1_irqs,
3385         .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
3386         .main_clk       = "mcspi1_fck",
3387         .prcm = {
3388                 .omap4 = {
3389                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3390                         .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3391                         .modulemode   = MODULEMODE_SWCTRL,
3392                 },
3393         },
3394         .dev_attr       = &mcspi1_dev_attr,
3395         .slaves         = omap44xx_mcspi1_slaves,
3396         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3397 };
3398
3399 /* mcspi2 */
3400 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3401 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3402         { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3403         { .irq = -1 }
3404 };
3405
3406 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3407         { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3408         { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3409         { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3410         { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3411         { .dma_req = -1 }
3412 };
3413
3414 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3415         {
3416                 .pa_start       = 0x4809a000,
3417                 .pa_end         = 0x4809a1ff,
3418                 .flags          = ADDR_TYPE_RT
3419         },
3420         { }
3421 };
3422
3423 /* l4_per -> mcspi2 */
3424 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3425         .master         = &omap44xx_l4_per_hwmod,
3426         .slave          = &omap44xx_mcspi2_hwmod,
3427         .clk            = "l4_div_ck",
3428         .addr           = omap44xx_mcspi2_addrs,
3429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3430 };
3431
3432 /* mcspi2 slave ports */
3433 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3434         &omap44xx_l4_per__mcspi2,
3435 };
3436
3437 /* mcspi2 dev_attr */
3438 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3439         .num_chipselect = 2,
3440 };
3441
3442 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3443         .name           = "mcspi2",
3444         .class          = &omap44xx_mcspi_hwmod_class,
3445         .clkdm_name     = "l4_per_clkdm",
3446         .mpu_irqs       = omap44xx_mcspi2_irqs,
3447         .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
3448         .main_clk       = "mcspi2_fck",
3449         .prcm = {
3450                 .omap4 = {
3451                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3452                         .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3453                         .modulemode   = MODULEMODE_SWCTRL,
3454                 },
3455         },
3456         .dev_attr       = &mcspi2_dev_attr,
3457         .slaves         = omap44xx_mcspi2_slaves,
3458         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3459 };
3460
3461 /* mcspi3 */
3462 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3463 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3464         { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3465         { .irq = -1 }
3466 };
3467
3468 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3469         { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3470         { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3471         { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3472         { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3473         { .dma_req = -1 }
3474 };
3475
3476 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3477         {
3478                 .pa_start       = 0x480b8000,
3479                 .pa_end         = 0x480b81ff,
3480                 .flags          = ADDR_TYPE_RT
3481         },
3482         { }
3483 };
3484
3485 /* l4_per -> mcspi3 */
3486 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3487         .master         = &omap44xx_l4_per_hwmod,
3488         .slave          = &omap44xx_mcspi3_hwmod,
3489         .clk            = "l4_div_ck",
3490         .addr           = omap44xx_mcspi3_addrs,
3491         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3492 };
3493
3494 /* mcspi3 slave ports */
3495 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3496         &omap44xx_l4_per__mcspi3,
3497 };
3498
3499 /* mcspi3 dev_attr */
3500 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3501         .num_chipselect = 2,
3502 };
3503
3504 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3505         .name           = "mcspi3",
3506         .class          = &omap44xx_mcspi_hwmod_class,
3507         .clkdm_name     = "l4_per_clkdm",
3508         .mpu_irqs       = omap44xx_mcspi3_irqs,
3509         .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
3510         .main_clk       = "mcspi3_fck",
3511         .prcm = {
3512                 .omap4 = {
3513                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3514                         .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3515                         .modulemode   = MODULEMODE_SWCTRL,
3516                 },
3517         },
3518         .dev_attr       = &mcspi3_dev_attr,
3519         .slaves         = omap44xx_mcspi3_slaves,
3520         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3521 };
3522
3523 /* mcspi4 */
3524 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3525 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3526         { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3527         { .irq = -1 }
3528 };
3529
3530 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3531         { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3532         { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3533         { .dma_req = -1 }
3534 };
3535
3536 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3537         {
3538                 .pa_start       = 0x480ba000,
3539                 .pa_end         = 0x480ba1ff,
3540                 .flags          = ADDR_TYPE_RT
3541         },
3542         { }
3543 };
3544
3545 /* l4_per -> mcspi4 */
3546 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3547         .master         = &omap44xx_l4_per_hwmod,
3548         .slave          = &omap44xx_mcspi4_hwmod,
3549         .clk            = "l4_div_ck",
3550         .addr           = omap44xx_mcspi4_addrs,
3551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3552 };
3553
3554 /* mcspi4 slave ports */
3555 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3556         &omap44xx_l4_per__mcspi4,
3557 };
3558
3559 /* mcspi4 dev_attr */
3560 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3561         .num_chipselect = 1,
3562 };
3563
3564 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3565         .name           = "mcspi4",
3566         .class          = &omap44xx_mcspi_hwmod_class,
3567         .clkdm_name     = "l4_per_clkdm",
3568         .mpu_irqs       = omap44xx_mcspi4_irqs,
3569         .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
3570         .main_clk       = "mcspi4_fck",
3571         .prcm = {
3572                 .omap4 = {
3573                         .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3574                         .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3575                         .modulemode   = MODULEMODE_SWCTRL,
3576                 },
3577         },
3578         .dev_attr       = &mcspi4_dev_attr,
3579         .slaves         = omap44xx_mcspi4_slaves,
3580         .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3581 };
3582
3583 /*
3584  * 'mmc' class
3585  * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3586  */
3587
3588 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3589         .rev_offs       = 0x0000,
3590         .sysc_offs      = 0x0010,
3591         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3592                            SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3593                            SYSC_HAS_SOFTRESET),
3594         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3595                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3596                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3597         .sysc_fields    = &omap_hwmod_sysc_type2,
3598 };
3599
3600 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3601         .name   = "mmc",
3602         .sysc   = &omap44xx_mmc_sysc,
3603 };
3604
3605 /* mmc1 */
3606 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3607         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3608         { .irq = -1 }
3609 };
3610
3611 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3612         { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3613         { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3614         { .dma_req = -1 }
3615 };
3616
3617 /* mmc1 master ports */
3618 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3619         &omap44xx_mmc1__l3_main_1,
3620 };
3621
3622 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3623         {
3624                 .pa_start       = 0x4809c000,
3625                 .pa_end         = 0x4809c3ff,
3626                 .flags          = ADDR_TYPE_RT
3627         },
3628         { }
3629 };
3630
3631 /* l4_per -> mmc1 */
3632 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3633         .master         = &omap44xx_l4_per_hwmod,
3634         .slave          = &omap44xx_mmc1_hwmod,
3635         .clk            = "l4_div_ck",
3636         .addr           = omap44xx_mmc1_addrs,
3637         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3638 };
3639
3640 /* mmc1 slave ports */
3641 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3642         &omap44xx_l4_per__mmc1,
3643 };
3644
3645 /* mmc1 dev_attr */
3646 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3647         .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3648 };
3649
3650 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3651         .name           = "mmc1",
3652         .class          = &omap44xx_mmc_hwmod_class,
3653         .clkdm_name     = "l3_init_clkdm",
3654         .mpu_irqs       = omap44xx_mmc1_irqs,
3655         .sdma_reqs      = omap44xx_mmc1_sdma_reqs,
3656         .main_clk       = "mmc1_fck",
3657         .prcm = {
3658                 .omap4 = {
3659                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3660                         .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3661                         .modulemode   = MODULEMODE_SWCTRL,
3662                 },
3663         },
3664         .dev_attr       = &mmc1_dev_attr,
3665         .slaves         = omap44xx_mmc1_slaves,
3666         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
3667         .masters        = omap44xx_mmc1_masters,
3668         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc1_masters),
3669 };
3670
3671 /* mmc2 */
3672 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3673         { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3674         { .irq = -1 }
3675 };
3676
3677 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3678         { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3679         { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3680         { .dma_req = -1 }
3681 };
3682
3683 /* mmc2 master ports */
3684 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3685         &omap44xx_mmc2__l3_main_1,
3686 };
3687
3688 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3689         {
3690                 .pa_start       = 0x480b4000,
3691                 .pa_end         = 0x480b43ff,
3692                 .flags          = ADDR_TYPE_RT
3693         },
3694         { }
3695 };
3696
3697 /* l4_per -> mmc2 */
3698 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3699         .master         = &omap44xx_l4_per_hwmod,
3700         .slave          = &omap44xx_mmc2_hwmod,
3701         .clk            = "l4_div_ck",
3702         .addr           = omap44xx_mmc2_addrs,
3703         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3704 };
3705
3706 /* mmc2 slave ports */
3707 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3708         &omap44xx_l4_per__mmc2,
3709 };
3710
3711 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3712         .name           = "mmc2",
3713         .class          = &omap44xx_mmc_hwmod_class,
3714         .clkdm_name     = "l3_init_clkdm",
3715         .mpu_irqs       = omap44xx_mmc2_irqs,
3716         .sdma_reqs      = omap44xx_mmc2_sdma_reqs,
3717         .main_clk       = "mmc2_fck",
3718         .prcm = {
3719                 .omap4 = {
3720                         .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3721                         .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3722                         .modulemode   = MODULEMODE_SWCTRL,
3723                 },
3724         },
3725         .slaves         = omap44xx_mmc2_slaves,
3726         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc2_slaves),
3727         .masters        = omap44xx_mmc2_masters,
3728         .masters_cnt    = ARRAY_SIZE(omap44xx_mmc2_masters),
3729 };
3730
3731 /* mmc3 */
3732 static struct omap_hwmod omap44xx_mmc3_hwmod;
3733 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3734         { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3735         { .irq = -1 }
3736 };
3737
3738 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3739         { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3740         { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3741         { .dma_req = -1 }
3742 };
3743
3744 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3745         {
3746                 .pa_start       = 0x480ad000,
3747                 .pa_end         = 0x480ad3ff,
3748                 .flags          = ADDR_TYPE_RT
3749         },
3750         { }
3751 };
3752
3753 /* l4_per -> mmc3 */
3754 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3755         .master         = &omap44xx_l4_per_hwmod,
3756         .slave          = &omap44xx_mmc3_hwmod,
3757         .clk            = "l4_div_ck",
3758         .addr           = omap44xx_mmc3_addrs,
3759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3760 };
3761
3762 /* mmc3 slave ports */
3763 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3764         &omap44xx_l4_per__mmc3,
3765 };
3766
3767 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3768         .name           = "mmc3",
3769         .class          = &omap44xx_mmc_hwmod_class,
3770         .clkdm_name     = "l4_per_clkdm",
3771         .mpu_irqs       = omap44xx_mmc3_irqs,
3772         .sdma_reqs      = omap44xx_mmc3_sdma_reqs,
3773         .main_clk       = "mmc3_fck",
3774         .prcm = {
3775                 .omap4 = {
3776                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3777                         .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3778                         .modulemode   = MODULEMODE_SWCTRL,
3779                 },
3780         },
3781         .slaves         = omap44xx_mmc3_slaves,
3782         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc3_slaves),
3783 };
3784
3785 /* mmc4 */
3786 static struct omap_hwmod omap44xx_mmc4_hwmod;
3787 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3788         { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3789         { .irq = -1 }
3790 };
3791
3792 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3793         { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3794         { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3795         { .dma_req = -1 }
3796 };
3797
3798 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3799         {
3800                 .pa_start       = 0x480d1000,
3801                 .pa_end         = 0x480d13ff,
3802                 .flags          = ADDR_TYPE_RT
3803         },
3804         { }
3805 };
3806
3807 /* l4_per -> mmc4 */
3808 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3809         .master         = &omap44xx_l4_per_hwmod,
3810         .slave          = &omap44xx_mmc4_hwmod,
3811         .clk            = "l4_div_ck",
3812         .addr           = omap44xx_mmc4_addrs,
3813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3814 };
3815
3816 /* mmc4 slave ports */
3817 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3818         &omap44xx_l4_per__mmc4,
3819 };
3820
3821 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3822         .name           = "mmc4",
3823         .class          = &omap44xx_mmc_hwmod_class,
3824         .clkdm_name     = "l4_per_clkdm",
3825         .mpu_irqs       = omap44xx_mmc4_irqs,
3826
3827         .sdma_reqs      = omap44xx_mmc4_sdma_reqs,
3828         .main_clk       = "mmc4_fck",
3829         .prcm = {
3830                 .omap4 = {
3831                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3832                         .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3833                         .modulemode   = MODULEMODE_SWCTRL,
3834                 },
3835         },
3836         .slaves         = omap44xx_mmc4_slaves,
3837         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc4_slaves),
3838 };
3839
3840 /* mmc5 */
3841 static struct omap_hwmod omap44xx_mmc5_hwmod;
3842 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3843         { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3844         { .irq = -1 }
3845 };
3846
3847 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3848         { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3849         { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3850         { .dma_req = -1 }
3851 };
3852
3853 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3854         {
3855                 .pa_start       = 0x480d5000,
3856                 .pa_end         = 0x480d53ff,
3857                 .flags          = ADDR_TYPE_RT
3858         },
3859         { }
3860 };
3861
3862 /* l4_per -> mmc5 */
3863 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3864         .master         = &omap44xx_l4_per_hwmod,
3865         .slave          = &omap44xx_mmc5_hwmod,
3866         .clk            = "l4_div_ck",
3867         .addr           = omap44xx_mmc5_addrs,
3868         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3869 };
3870
3871 /* mmc5 slave ports */
3872 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3873         &omap44xx_l4_per__mmc5,
3874 };
3875
3876 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3877         .name           = "mmc5",
3878         .class          = &omap44xx_mmc_hwmod_class,
3879         .clkdm_name     = "l4_per_clkdm",
3880         .mpu_irqs       = omap44xx_mmc5_irqs,
3881         .sdma_reqs      = omap44xx_mmc5_sdma_reqs,
3882         .main_clk       = "mmc5_fck",
3883         .prcm = {
3884                 .omap4 = {
3885                         .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3886                         .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3887                         .modulemode   = MODULEMODE_SWCTRL,
3888                 },
3889         },
3890         .slaves         = omap44xx_mmc5_slaves,
3891         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc5_slaves),
3892 };
3893
3894 /*
3895  * 'mpu' class
3896  * mpu sub-system
3897  */
3898
3899 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3900         .name   = "mpu",
3901 };
3902
3903 /* mpu */
3904 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3905         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3906         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3907         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3908         { .irq = -1 }
3909 };
3910
3911 /* mpu master ports */
3912 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3913         &omap44xx_mpu__l3_main_1,
3914         &omap44xx_mpu__l4_abe,
3915         &omap44xx_mpu__dmm,
3916 };
3917
3918 static struct omap_hwmod omap44xx_mpu_hwmod = {
3919         .name           = "mpu",
3920         .class          = &omap44xx_mpu_hwmod_class,
3921         .clkdm_name     = "mpuss_clkdm",
3922         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3923         .mpu_irqs       = omap44xx_mpu_irqs,
3924         .main_clk       = "dpll_mpu_m2_ck",
3925         .prcm = {
3926                 .omap4 = {
3927                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3928                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3929                 },
3930         },
3931         .masters        = omap44xx_mpu_masters,
3932         .masters_cnt    = ARRAY_SIZE(omap44xx_mpu_masters),
3933 };
3934
3935 /*
3936  * 'smartreflex' class
3937  * smartreflex module (monitor silicon performance and outputs a measure of
3938  * performance error)
3939  */
3940
3941 /* The IP is not compliant to type1 / type2 scheme */
3942 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3943         .sidle_shift    = 24,
3944         .enwkup_shift   = 26,
3945 };
3946
3947 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3948         .sysc_offs      = 0x0038,
3949         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3950         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3951                            SIDLE_SMART_WKUP),
3952         .sysc_fields    = &omap_hwmod_sysc_type_smartreflex,
3953 };
3954
3955 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3956         .name   = "smartreflex",
3957         .sysc   = &omap44xx_smartreflex_sysc,
3958         .rev    = 2,
3959 };
3960
3961 /* smartreflex_core */
3962 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
3963         .sensor_voltdm_name   = "core",
3964 };
3965
3966 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3967 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3968         { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3969         { .irq = -1 }
3970 };
3971
3972 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3973         {
3974                 .pa_start       = 0x4a0dd000,
3975                 .pa_end         = 0x4a0dd03f,
3976                 .flags          = ADDR_TYPE_RT
3977         },
3978         { }
3979 };
3980
3981 /* l4_cfg -> smartreflex_core */
3982 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3983         .master         = &omap44xx_l4_cfg_hwmod,
3984         .slave          = &omap44xx_smartreflex_core_hwmod,
3985         .clk            = "l4_div_ck",
3986         .addr           = omap44xx_smartreflex_core_addrs,
3987         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3988 };
3989
3990 /* smartreflex_core slave ports */
3991 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3992         &omap44xx_l4_cfg__smartreflex_core,
3993 };
3994
3995 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3996         .name           = "smartreflex_core",
3997         .class          = &omap44xx_smartreflex_hwmod_class,
3998         .clkdm_name     = "l4_ao_clkdm",
3999         .mpu_irqs       = omap44xx_smartreflex_core_irqs,
4000
4001         .main_clk       = "smartreflex_core_fck",
4002         .prcm = {
4003                 .omap4 = {
4004                         .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4005                         .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4006                         .modulemode   = MODULEMODE_SWCTRL,
4007                 },
4008         },
4009         .slaves         = omap44xx_smartreflex_core_slaves,
4010         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4011         .dev_attr       = &smartreflex_core_dev_attr,
4012 };
4013
4014 /* smartreflex_iva */
4015 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
4016         .sensor_voltdm_name     = "iva",
4017 };
4018
4019 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4020 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4021         { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4022         { .irq = -1 }
4023 };
4024
4025 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4026         {
4027                 .pa_start       = 0x4a0db000,
4028                 .pa_end         = 0x4a0db03f,
4029                 .flags          = ADDR_TYPE_RT
4030         },
4031         { }
4032 };
4033
4034 /* l4_cfg -> smartreflex_iva */
4035 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4036         .master         = &omap44xx_l4_cfg_hwmod,
4037         .slave          = &omap44xx_smartreflex_iva_hwmod,
4038         .clk            = "l4_div_ck",
4039         .addr           = omap44xx_smartreflex_iva_addrs,
4040         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4041 };
4042
4043 /* smartreflex_iva slave ports */
4044 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4045         &omap44xx_l4_cfg__smartreflex_iva,
4046 };
4047
4048 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4049         .name           = "smartreflex_iva",
4050         .class          = &omap44xx_smartreflex_hwmod_class,
4051         .clkdm_name     = "l4_ao_clkdm",
4052         .mpu_irqs       = omap44xx_smartreflex_iva_irqs,
4053         .main_clk       = "smartreflex_iva_fck",
4054         .prcm = {
4055                 .omap4 = {
4056                         .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4057                         .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4058                         .modulemode   = MODULEMODE_SWCTRL,
4059                 },
4060         },
4061         .slaves         = omap44xx_smartreflex_iva_slaves,
4062         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4063         .dev_attr       = &smartreflex_iva_dev_attr,
4064 };
4065
4066 /* smartreflex_mpu */
4067 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4068         .sensor_voltdm_name     = "mpu",
4069 };
4070
4071 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4072 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4073         { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4074         { .irq = -1 }
4075 };
4076
4077 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4078         {
4079                 .pa_start       = 0x4a0d9000,
4080                 .pa_end         = 0x4a0d903f,
4081                 .flags          = ADDR_TYPE_RT
4082         },
4083         { }
4084 };
4085
4086 /* l4_cfg -> smartreflex_mpu */
4087 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4088         .master         = &omap44xx_l4_cfg_hwmod,
4089         .slave          = &omap44xx_smartreflex_mpu_hwmod,
4090         .clk            = "l4_div_ck",
4091         .addr           = omap44xx_smartreflex_mpu_addrs,
4092         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4093 };
4094
4095 /* smartreflex_mpu slave ports */
4096 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4097         &omap44xx_l4_cfg__smartreflex_mpu,
4098 };
4099
4100 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4101         .name           = "smartreflex_mpu",
4102         .class          = &omap44xx_smartreflex_hwmod_class,
4103         .clkdm_name     = "l4_ao_clkdm",
4104         .mpu_irqs       = omap44xx_smartreflex_mpu_irqs,
4105         .main_clk       = "smartreflex_mpu_fck",
4106         .prcm = {
4107                 .omap4 = {
4108                         .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4109                         .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4110                         .modulemode   = MODULEMODE_SWCTRL,
4111                 },
4112         },
4113         .slaves         = omap44xx_smartreflex_mpu_slaves,
4114         .slaves_cnt     = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4115         .dev_attr       = &smartreflex_mpu_dev_attr,
4116 };
4117
4118 /*
4119  * 'spinlock' class
4120  * spinlock provides hardware assistance for synchronizing the processes
4121  * running on multiple processors
4122  */
4123
4124 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4125         .rev_offs       = 0x0000,
4126         .sysc_offs      = 0x0010,
4127         .syss_offs      = 0x0014,
4128         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4129                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4130                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4131         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4132                            SIDLE_SMART_WKUP),
4133         .sysc_fields    = &omap_hwmod_sysc_type1,
4134 };
4135
4136 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4137         .name   = "spinlock",
4138         .sysc   = &omap44xx_spinlock_sysc,
4139 };
4140
4141 /* spinlock */
4142 static struct omap_hwmod omap44xx_spinlock_hwmod;
4143 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4144         {
4145                 .pa_start       = 0x4a0f6000,
4146                 .pa_end         = 0x4a0f6fff,
4147                 .flags          = ADDR_TYPE_RT
4148         },
4149         { }
4150 };
4151
4152 /* l4_cfg -> spinlock */
4153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4154         .master         = &omap44xx_l4_cfg_hwmod,
4155         .slave          = &omap44xx_spinlock_hwmod,
4156         .clk            = "l4_div_ck",
4157         .addr           = omap44xx_spinlock_addrs,
4158         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4159 };
4160
4161 /* spinlock slave ports */
4162 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4163         &omap44xx_l4_cfg__spinlock,
4164 };
4165
4166 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4167         .name           = "spinlock",
4168         .class          = &omap44xx_spinlock_hwmod_class,
4169         .clkdm_name     = "l4_cfg_clkdm",
4170         .prcm = {
4171                 .omap4 = {
4172                         .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4173                         .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4174                 },
4175         },
4176         .slaves         = omap44xx_spinlock_slaves,
4177         .slaves_cnt     = ARRAY_SIZE(omap44xx_spinlock_slaves),
4178 };
4179
4180 /*
4181  * 'timer' class
4182  * general purpose timer module with accurate 1ms tick
4183  * This class contains several variants: ['timer_1ms', 'timer']
4184  */
4185
4186 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4187         .rev_offs       = 0x0000,
4188         .sysc_offs      = 0x0010,
4189         .syss_offs      = 0x0014,
4190         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4191                            SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4192                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4193                            SYSS_HAS_RESET_STATUS),
4194         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4195         .sysc_fields    = &omap_hwmod_sysc_type1,
4196 };
4197
4198 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4199         .name   = "timer",
4200         .sysc   = &omap44xx_timer_1ms_sysc,
4201 };
4202
4203 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4204         .rev_offs       = 0x0000,
4205         .sysc_offs      = 0x0010,
4206         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4207                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4208         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4209                            SIDLE_SMART_WKUP),
4210         .sysc_fields    = &omap_hwmod_sysc_type2,
4211 };
4212
4213 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4214         .name   = "timer",
4215         .sysc   = &omap44xx_timer_sysc,
4216 };
4217
4218 /* always-on timers dev attribute */
4219 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4220         .timer_capability       = OMAP_TIMER_ALWON,
4221 };
4222
4223 /* pwm timers dev attribute */
4224 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4225         .timer_capability       = OMAP_TIMER_HAS_PWM,
4226 };
4227
4228 /* timer1 */
4229 static struct omap_hwmod omap44xx_timer1_hwmod;
4230 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4231         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4232         { .irq = -1 }
4233 };
4234
4235 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4236         {
4237                 .pa_start       = 0x4a318000,
4238                 .pa_end         = 0x4a31807f,
4239                 .flags          = ADDR_TYPE_RT
4240         },
4241         { }
4242 };
4243
4244 /* l4_wkup -> timer1 */
4245 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4246         .master         = &omap44xx_l4_wkup_hwmod,
4247         .slave          = &omap44xx_timer1_hwmod,
4248         .clk            = "l4_wkup_clk_mux_ck",
4249         .addr           = omap44xx_timer1_addrs,
4250         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4251 };
4252
4253 /* timer1 slave ports */
4254 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4255         &omap44xx_l4_wkup__timer1,
4256 };
4257
4258 static struct omap_hwmod omap44xx_timer1_hwmod = {
4259         .name           = "timer1",
4260         .class          = &omap44xx_timer_1ms_hwmod_class,
4261         .clkdm_name     = "l4_wkup_clkdm",
4262         .mpu_irqs       = omap44xx_timer1_irqs,
4263         .main_clk       = "timer1_fck",
4264         .prcm = {
4265                 .omap4 = {
4266                         .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4267                         .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4268                         .modulemode   = MODULEMODE_SWCTRL,
4269                 },
4270         },
4271         .dev_attr       = &capability_alwon_dev_attr,
4272         .slaves         = omap44xx_timer1_slaves,
4273         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer1_slaves),
4274 };
4275
4276 /* timer2 */
4277 static struct omap_hwmod omap44xx_timer2_hwmod;
4278 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4279         { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4280         { .irq = -1 }
4281 };
4282
4283 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4284         {
4285                 .pa_start       = 0x48032000,
4286                 .pa_end         = 0x4803207f,
4287                 .flags          = ADDR_TYPE_RT
4288         },
4289         { }
4290 };
4291
4292 /* l4_per -> timer2 */
4293 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4294         .master         = &omap44xx_l4_per_hwmod,
4295         .slave          = &omap44xx_timer2_hwmod,
4296         .clk            = "l4_div_ck",
4297         .addr           = omap44xx_timer2_addrs,
4298         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4299 };
4300
4301 /* timer2 slave ports */
4302 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4303         &omap44xx_l4_per__timer2,
4304 };
4305
4306 static struct omap_hwmod omap44xx_timer2_hwmod = {
4307         .name           = "timer2",
4308         .class          = &omap44xx_timer_1ms_hwmod_class,
4309         .clkdm_name     = "l4_per_clkdm",
4310         .mpu_irqs       = omap44xx_timer2_irqs,
4311         .main_clk       = "timer2_fck",
4312         .prcm = {
4313                 .omap4 = {
4314                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4315                         .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4316                         .modulemode   = MODULEMODE_SWCTRL,
4317                 },
4318         },
4319         .dev_attr       = &capability_alwon_dev_attr,
4320         .slaves         = omap44xx_timer2_slaves,
4321         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer2_slaves),
4322 };
4323
4324 /* timer3 */
4325 static struct omap_hwmod omap44xx_timer3_hwmod;
4326 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4327         { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4328         { .irq = -1 }
4329 };
4330
4331 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4332         {
4333                 .pa_start       = 0x48034000,
4334                 .pa_end         = 0x4803407f,
4335                 .flags          = ADDR_TYPE_RT
4336         },
4337         { }
4338 };
4339
4340 /* l4_per -> timer3 */
4341 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4342         .master         = &omap44xx_l4_per_hwmod,
4343         .slave          = &omap44xx_timer3_hwmod,
4344         .clk            = "l4_div_ck",
4345         .addr           = omap44xx_timer3_addrs,
4346         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4347 };
4348
4349 /* timer3 slave ports */
4350 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4351         &omap44xx_l4_per__timer3,
4352 };
4353
4354 static struct omap_hwmod omap44xx_timer3_hwmod = {
4355         .name           = "timer3",
4356         .class          = &omap44xx_timer_hwmod_class,
4357         .clkdm_name     = "l4_per_clkdm",
4358         .mpu_irqs       = omap44xx_timer3_irqs,
4359         .main_clk       = "timer3_fck",
4360         .prcm = {
4361                 .omap4 = {
4362                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4363                         .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4364                         .modulemode   = MODULEMODE_SWCTRL,
4365                 },
4366         },
4367         .dev_attr       = &capability_alwon_dev_attr,
4368         .slaves         = omap44xx_timer3_slaves,
4369         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer3_slaves),
4370 };
4371
4372 /* timer4 */
4373 static struct omap_hwmod omap44xx_timer4_hwmod;
4374 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4375         { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4376         { .irq = -1 }
4377 };
4378
4379 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4380         {
4381                 .pa_start       = 0x48036000,
4382                 .pa_end         = 0x4803607f,
4383                 .flags          = ADDR_TYPE_RT
4384         },
4385         { }
4386 };
4387
4388 /* l4_per -> timer4 */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4390         .master         = &omap44xx_l4_per_hwmod,
4391         .slave          = &omap44xx_timer4_hwmod,
4392         .clk            = "l4_div_ck",
4393         .addr           = omap44xx_timer4_addrs,
4394         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4395 };
4396
4397 /* timer4 slave ports */
4398 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4399         &omap44xx_l4_per__timer4,
4400 };
4401
4402 static struct omap_hwmod omap44xx_timer4_hwmod = {
4403         .name           = "timer4",
4404         .class          = &omap44xx_timer_hwmod_class,
4405         .clkdm_name     = "l4_per_clkdm",
4406         .mpu_irqs       = omap44xx_timer4_irqs,
4407         .main_clk       = "timer4_fck",
4408         .prcm = {
4409                 .omap4 = {
4410                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4411                         .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4412                         .modulemode   = MODULEMODE_SWCTRL,
4413                 },
4414         },
4415         .dev_attr       = &capability_alwon_dev_attr,
4416         .slaves         = omap44xx_timer4_slaves,
4417         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer4_slaves),
4418 };
4419
4420 /* timer5 */
4421 static struct omap_hwmod omap44xx_timer5_hwmod;
4422 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4423         { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4424         { .irq = -1 }
4425 };
4426
4427 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4428         {
4429                 .pa_start       = 0x40138000,
4430                 .pa_end         = 0x4013807f,
4431                 .flags          = ADDR_TYPE_RT
4432         },
4433         { }
4434 };
4435
4436 /* l4_abe -> timer5 */
4437 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4438         .master         = &omap44xx_l4_abe_hwmod,
4439         .slave          = &omap44xx_timer5_hwmod,
4440         .clk            = "ocp_abe_iclk",
4441         .addr           = omap44xx_timer5_addrs,
4442         .user           = OCP_USER_MPU,
4443 };
4444
4445 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4446         {
4447                 .pa_start       = 0x49038000,
4448                 .pa_end         = 0x4903807f,
4449                 .flags          = ADDR_TYPE_RT
4450         },
4451         { }
4452 };
4453
4454 /* l4_abe -> timer5 (dma) */
4455 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4456         .master         = &omap44xx_l4_abe_hwmod,
4457         .slave          = &omap44xx_timer5_hwmod,
4458         .clk            = "ocp_abe_iclk",
4459         .addr           = omap44xx_timer5_dma_addrs,
4460         .user           = OCP_USER_SDMA,
4461 };
4462
4463 /* timer5 slave ports */
4464 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4465         &omap44xx_l4_abe__timer5,
4466         &omap44xx_l4_abe__timer5_dma,
4467 };
4468
4469 static struct omap_hwmod omap44xx_timer5_hwmod = {
4470         .name           = "timer5",
4471         .class          = &omap44xx_timer_hwmod_class,
4472         .clkdm_name     = "abe_clkdm",
4473         .mpu_irqs       = omap44xx_timer5_irqs,
4474         .main_clk       = "timer5_fck",
4475         .prcm = {
4476                 .omap4 = {
4477                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4478                         .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4479                         .modulemode   = MODULEMODE_SWCTRL,
4480                 },
4481         },
4482         .dev_attr       = &capability_alwon_dev_attr,
4483         .slaves         = omap44xx_timer5_slaves,
4484         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer5_slaves),
4485 };
4486
4487 /* timer6 */
4488 static struct omap_hwmod omap44xx_timer6_hwmod;
4489 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4490         { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4491         { .irq = -1 }
4492 };
4493
4494 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4495         {
4496                 .pa_start       = 0x4013a000,
4497                 .pa_end         = 0x4013a07f,
4498                 .flags          = ADDR_TYPE_RT
4499         },
4500         { }
4501 };
4502
4503 /* l4_abe -> timer6 */
4504 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4505         .master         = &omap44xx_l4_abe_hwmod,
4506         .slave          = &omap44xx_timer6_hwmod,
4507         .clk            = "ocp_abe_iclk",
4508         .addr           = omap44xx_timer6_addrs,
4509         .user           = OCP_USER_MPU,
4510 };
4511
4512 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4513         {
4514                 .pa_start       = 0x4903a000,
4515                 .pa_end         = 0x4903a07f,
4516                 .flags          = ADDR_TYPE_RT
4517         },
4518         { }
4519 };
4520
4521 /* l4_abe -> timer6 (dma) */
4522 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4523         .master         = &omap44xx_l4_abe_hwmod,
4524         .slave          = &omap44xx_timer6_hwmod,
4525         .clk            = "ocp_abe_iclk",
4526         .addr           = omap44xx_timer6_dma_addrs,
4527         .user           = OCP_USER_SDMA,
4528 };
4529
4530 /* timer6 slave ports */
4531 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4532         &omap44xx_l4_abe__timer6,
4533         &omap44xx_l4_abe__timer6_dma,
4534 };
4535
4536 static struct omap_hwmod omap44xx_timer6_hwmod = {
4537         .name           = "timer6",
4538         .class          = &omap44xx_timer_hwmod_class,
4539         .clkdm_name     = "abe_clkdm",
4540         .mpu_irqs       = omap44xx_timer6_irqs,
4541
4542         .main_clk       = "timer6_fck",
4543         .prcm = {
4544                 .omap4 = {
4545                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4546                         .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4547                         .modulemode   = MODULEMODE_SWCTRL,
4548                 },
4549         },
4550         .dev_attr       = &capability_alwon_dev_attr,
4551         .slaves         = omap44xx_timer6_slaves,
4552         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer6_slaves),
4553 };
4554
4555 /* timer7 */
4556 static struct omap_hwmod omap44xx_timer7_hwmod;
4557 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4558         { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4559         { .irq = -1 }
4560 };
4561
4562 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4563         {
4564                 .pa_start       = 0x4013c000,
4565                 .pa_end         = 0x4013c07f,
4566                 .flags          = ADDR_TYPE_RT
4567         },
4568         { }
4569 };
4570
4571 /* l4_abe -> timer7 */
4572 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4573         .master         = &omap44xx_l4_abe_hwmod,
4574         .slave          = &omap44xx_timer7_hwmod,
4575         .clk            = "ocp_abe_iclk",
4576         .addr           = omap44xx_timer7_addrs,
4577         .user           = OCP_USER_MPU,
4578 };
4579
4580 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4581         {
4582                 .pa_start       = 0x4903c000,
4583                 .pa_end         = 0x4903c07f,
4584                 .flags          = ADDR_TYPE_RT
4585         },
4586         { }
4587 };
4588
4589 /* l4_abe -> timer7 (dma) */
4590 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4591         .master         = &omap44xx_l4_abe_hwmod,
4592         .slave          = &omap44xx_timer7_hwmod,
4593         .clk            = "ocp_abe_iclk",
4594         .addr           = omap44xx_timer7_dma_addrs,
4595         .user           = OCP_USER_SDMA,
4596 };
4597
4598 /* timer7 slave ports */
4599 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4600         &omap44xx_l4_abe__timer7,
4601         &omap44xx_l4_abe__timer7_dma,
4602 };
4603
4604 static struct omap_hwmod omap44xx_timer7_hwmod = {
4605         .name           = "timer7",
4606         .class          = &omap44xx_timer_hwmod_class,
4607         .clkdm_name     = "abe_clkdm",
4608         .mpu_irqs       = omap44xx_timer7_irqs,
4609         .main_clk       = "timer7_fck",
4610         .prcm = {
4611                 .omap4 = {
4612                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4613                         .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4614                         .modulemode   = MODULEMODE_SWCTRL,
4615                 },
4616         },
4617         .dev_attr       = &capability_alwon_dev_attr,
4618         .slaves         = omap44xx_timer7_slaves,
4619         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer7_slaves),
4620 };
4621
4622 /* timer8 */
4623 static struct omap_hwmod omap44xx_timer8_hwmod;
4624 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4625         { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4626         { .irq = -1 }
4627 };
4628
4629 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4630         {
4631                 .pa_start       = 0x4013e000,
4632                 .pa_end         = 0x4013e07f,
4633                 .flags          = ADDR_TYPE_RT
4634         },
4635         { }
4636 };
4637
4638 /* l4_abe -> timer8 */
4639 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4640         .master         = &omap44xx_l4_abe_hwmod,
4641         .slave          = &omap44xx_timer8_hwmod,
4642         .clk            = "ocp_abe_iclk",
4643         .addr           = omap44xx_timer8_addrs,
4644         .user           = OCP_USER_MPU,
4645 };
4646
4647 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4648         {
4649                 .pa_start       = 0x4903e000,
4650                 .pa_end         = 0x4903e07f,
4651                 .flags          = ADDR_TYPE_RT
4652         },
4653         { }
4654 };
4655
4656 /* l4_abe -> timer8 (dma) */
4657 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4658         .master         = &omap44xx_l4_abe_hwmod,
4659         .slave          = &omap44xx_timer8_hwmod,
4660         .clk            = "ocp_abe_iclk",
4661         .addr           = omap44xx_timer8_dma_addrs,
4662         .user           = OCP_USER_SDMA,
4663 };
4664
4665 /* timer8 slave ports */
4666 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4667         &omap44xx_l4_abe__timer8,
4668         &omap44xx_l4_abe__timer8_dma,
4669 };
4670
4671 static struct omap_hwmod omap44xx_timer8_hwmod = {
4672         .name           = "timer8",
4673         .class          = &omap44xx_timer_hwmod_class,
4674         .clkdm_name     = "abe_clkdm",
4675         .mpu_irqs       = omap44xx_timer8_irqs,
4676         .main_clk       = "timer8_fck",
4677         .prcm = {
4678                 .omap4 = {
4679                         .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4680                         .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4681                         .modulemode   = MODULEMODE_SWCTRL,
4682                 },
4683         },
4684         .dev_attr       = &capability_pwm_dev_attr,
4685         .slaves         = omap44xx_timer8_slaves,
4686         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer8_slaves),
4687 };
4688
4689 /* timer9 */
4690 static struct omap_hwmod omap44xx_timer9_hwmod;
4691 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4692         { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4693         { .irq = -1 }
4694 };
4695
4696 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4697         {
4698                 .pa_start       = 0x4803e000,
4699                 .pa_end         = 0x4803e07f,
4700                 .flags          = ADDR_TYPE_RT
4701         },
4702         { }
4703 };
4704
4705 /* l4_per -> timer9 */
4706 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4707         .master         = &omap44xx_l4_per_hwmod,
4708         .slave          = &omap44xx_timer9_hwmod,
4709         .clk            = "l4_div_ck",
4710         .addr           = omap44xx_timer9_addrs,
4711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4712 };
4713
4714 /* timer9 slave ports */
4715 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4716         &omap44xx_l4_per__timer9,
4717 };
4718
4719 static struct omap_hwmod omap44xx_timer9_hwmod = {
4720         .name           = "timer9",
4721         .class          = &omap44xx_timer_hwmod_class,
4722         .clkdm_name     = "l4_per_clkdm",
4723         .mpu_irqs       = omap44xx_timer9_irqs,
4724         .main_clk       = "timer9_fck",
4725         .prcm = {
4726                 .omap4 = {
4727                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4728                         .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4729                         .modulemode   = MODULEMODE_SWCTRL,
4730                 },
4731         },
4732         .dev_attr       = &capability_pwm_dev_attr,
4733         .slaves         = omap44xx_timer9_slaves,
4734         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer9_slaves),
4735 };
4736
4737 /* timer10 */
4738 static struct omap_hwmod omap44xx_timer10_hwmod;
4739 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4740         { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4741         { .irq = -1 }
4742 };
4743
4744 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4745         {
4746                 .pa_start       = 0x48086000,
4747                 .pa_end         = 0x4808607f,
4748                 .flags          = ADDR_TYPE_RT
4749         },
4750         { }
4751 };
4752
4753 /* l4_per -> timer10 */
4754 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4755         .master         = &omap44xx_l4_per_hwmod,
4756         .slave          = &omap44xx_timer10_hwmod,
4757         .clk            = "l4_div_ck",
4758         .addr           = omap44xx_timer10_addrs,
4759         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4760 };
4761
4762 /* timer10 slave ports */
4763 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4764         &omap44xx_l4_per__timer10,
4765 };
4766
4767 static struct omap_hwmod omap44xx_timer10_hwmod = {
4768         .name           = "timer10",
4769         .class          = &omap44xx_timer_1ms_hwmod_class,
4770         .clkdm_name     = "l4_per_clkdm",
4771         .mpu_irqs       = omap44xx_timer10_irqs,
4772         .main_clk       = "timer10_fck",
4773         .prcm = {
4774                 .omap4 = {
4775                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4776                         .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4777                         .modulemode   = MODULEMODE_SWCTRL,
4778                 },
4779         },
4780         .dev_attr       = &capability_pwm_dev_attr,
4781         .slaves         = omap44xx_timer10_slaves,
4782         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer10_slaves),
4783 };
4784
4785 /* timer11 */
4786 static struct omap_hwmod omap44xx_timer11_hwmod;
4787 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4788         { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4789         { .irq = -1 }
4790 };
4791
4792 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4793         {
4794                 .pa_start       = 0x48088000,
4795                 .pa_end         = 0x4808807f,
4796                 .flags          = ADDR_TYPE_RT
4797         },
4798         { }
4799 };
4800
4801 /* l4_per -> timer11 */
4802 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4803         .master         = &omap44xx_l4_per_hwmod,
4804         .slave          = &omap44xx_timer11_hwmod,
4805         .clk            = "l4_div_ck",
4806         .addr           = omap44xx_timer11_addrs,
4807         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4808 };
4809
4810 /* timer11 slave ports */
4811 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4812         &omap44xx_l4_per__timer11,
4813 };
4814
4815 static struct omap_hwmod omap44xx_timer11_hwmod = {
4816         .name           = "timer11",
4817         .class          = &omap44xx_timer_hwmod_class,
4818         .clkdm_name     = "l4_per_clkdm",
4819         .mpu_irqs       = omap44xx_timer11_irqs,
4820         .main_clk       = "timer11_fck",
4821         .prcm = {
4822                 .omap4 = {
4823                         .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4824                         .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4825                         .modulemode   = MODULEMODE_SWCTRL,
4826                 },
4827         },
4828         .dev_attr       = &capability_pwm_dev_attr,
4829         .slaves         = omap44xx_timer11_slaves,
4830         .slaves_cnt     = ARRAY_SIZE(omap44xx_timer11_slaves),
4831 };
4832
4833 /*
4834  * 'uart' class
4835  * universal asynchronous receiver/transmitter (uart)
4836  */
4837
4838 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4839         .rev_offs       = 0x0050,
4840         .sysc_offs      = 0x0054,
4841         .syss_offs      = 0x0058,
4842         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4843                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4844                            SYSS_HAS_RESET_STATUS),
4845         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4846                            SIDLE_SMART_WKUP),
4847         .sysc_fields    = &omap_hwmod_sysc_type1,
4848 };
4849
4850 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4851         .name   = "uart",
4852         .sysc   = &omap44xx_uart_sysc,
4853 };
4854
4855 /* uart1 */
4856 static struct omap_hwmod omap44xx_uart1_hwmod;
4857 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4858         { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4859         { .irq = -1 }
4860 };
4861
4862 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4863         { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4864         { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4865         { .dma_req = -1 }
4866 };
4867
4868 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4869         {
4870                 .pa_start       = 0x4806a000,
4871                 .pa_end         = 0x4806a0ff,
4872                 .flags          = ADDR_TYPE_RT
4873         },
4874         { }
4875 };
4876
4877 /* l4_per -> uart1 */
4878 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4879         .master         = &omap44xx_l4_per_hwmod,
4880         .slave          = &omap44xx_uart1_hwmod,
4881         .clk            = "l4_div_ck",
4882         .addr           = omap44xx_uart1_addrs,
4883         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4884 };
4885
4886 /* uart1 slave ports */
4887 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4888         &omap44xx_l4_per__uart1,
4889 };
4890
4891 static struct omap_hwmod omap44xx_uart1_hwmod = {
4892         .name           = "uart1",
4893         .class          = &omap44xx_uart_hwmod_class,
4894         .clkdm_name     = "l4_per_clkdm",
4895         .mpu_irqs       = omap44xx_uart1_irqs,
4896         .sdma_reqs      = omap44xx_uart1_sdma_reqs,
4897         .main_clk       = "uart1_fck",
4898         .prcm = {
4899                 .omap4 = {
4900                         .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4901                         .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4902                         .modulemode   = MODULEMODE_SWCTRL,
4903                 },
4904         },
4905         .slaves         = omap44xx_uart1_slaves,
4906         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart1_slaves),
4907 };
4908
4909 /* uart2 */
4910 static struct omap_hwmod omap44xx_uart2_hwmod;
4911 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4912         { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4913         { .irq = -1 }
4914 };
4915
4916 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4917         { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4918         { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4919         { .dma_req = -1 }
4920 };
4921
4922 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4923         {
4924                 .pa_start       = 0x4806c000,
4925                 .pa_end         = 0x4806c0ff,
4926                 .flags          = ADDR_TYPE_RT
4927         },
4928         { }
4929 };
4930
4931 /* l4_per -> uart2 */
4932 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4933         .master         = &omap44xx_l4_per_hwmod,
4934         .slave          = &omap44xx_uart2_hwmod,
4935         .clk            = "l4_div_ck",
4936         .addr           = omap44xx_uart2_addrs,
4937         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4938 };
4939
4940 /* uart2 slave ports */
4941 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4942         &omap44xx_l4_per__uart2,
4943 };
4944
4945 static struct omap_hwmod omap44xx_uart2_hwmod = {
4946         .name           = "uart2",
4947         .class          = &omap44xx_uart_hwmod_class,
4948         .clkdm_name     = "l4_per_clkdm",
4949         .mpu_irqs       = omap44xx_uart2_irqs,
4950         .sdma_reqs      = omap44xx_uart2_sdma_reqs,
4951         .main_clk       = "uart2_fck",
4952         .prcm = {
4953                 .omap4 = {
4954                         .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4955                         .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4956                         .modulemode   = MODULEMODE_SWCTRL,
4957                 },
4958         },
4959         .slaves         = omap44xx_uart2_slaves,
4960         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart2_slaves),
4961 };
4962
4963 /* uart3 */
4964 static struct omap_hwmod omap44xx_uart3_hwmod;
4965 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4966         { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4967         { .irq = -1 }
4968 };
4969
4970 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4971         { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4972         { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4973         { .dma_req = -1 }
4974 };
4975
4976 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4977         {
4978                 .pa_start       = 0x48020000,
4979                 .pa_end         = 0x480200ff,
4980                 .flags          = ADDR_TYPE_RT
4981         },
4982         { }
4983 };
4984
4985 /* l4_per -> uart3 */
4986 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4987         .master         = &omap44xx_l4_per_hwmod,
4988         .slave          = &omap44xx_uart3_hwmod,
4989         .clk            = "l4_div_ck",
4990         .addr           = omap44xx_uart3_addrs,
4991         .user           = OCP_USER_MPU | OCP_USER_SDMA,
4992 };
4993
4994 /* uart3 slave ports */
4995 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4996         &omap44xx_l4_per__uart3,
4997 };
4998
4999 static struct omap_hwmod omap44xx_uart3_hwmod = {
5000         .name           = "uart3",
5001         .class          = &omap44xx_uart_hwmod_class,
5002         .clkdm_name     = "l4_per_clkdm",
5003         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5004         .mpu_irqs       = omap44xx_uart3_irqs,
5005         .sdma_reqs      = omap44xx_uart3_sdma_reqs,
5006         .main_clk       = "uart3_fck",
5007         .prcm = {
5008                 .omap4 = {
5009                         .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5010                         .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5011                         .modulemode   = MODULEMODE_SWCTRL,
5012                 },
5013         },
5014         .slaves         = omap44xx_uart3_slaves,
5015         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart3_slaves),
5016 };
5017
5018 /* uart4 */
5019 static struct omap_hwmod omap44xx_uart4_hwmod;
5020 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5021         { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5022         { .irq = -1 }
5023 };
5024
5025 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5026         { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5027         { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5028         { .dma_req = -1 }
5029 };
5030
5031 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5032         {
5033                 .pa_start       = 0x4806e000,
5034                 .pa_end         = 0x4806e0ff,
5035                 .flags          = ADDR_TYPE_RT
5036         },
5037         { }
5038 };
5039
5040 /* l4_per -> uart4 */
5041 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5042         .master         = &omap44xx_l4_per_hwmod,
5043         .slave          = &omap44xx_uart4_hwmod,
5044         .clk            = "l4_div_ck",
5045         .addr           = omap44xx_uart4_addrs,
5046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5047 };
5048
5049 /* uart4 slave ports */
5050 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5051         &omap44xx_l4_per__uart4,
5052 };
5053
5054 static struct omap_hwmod omap44xx_uart4_hwmod = {
5055         .name           = "uart4",
5056         .class          = &omap44xx_uart_hwmod_class,
5057         .clkdm_name     = "l4_per_clkdm",
5058         .mpu_irqs       = omap44xx_uart4_irqs,
5059         .sdma_reqs      = omap44xx_uart4_sdma_reqs,
5060         .main_clk       = "uart4_fck",
5061         .prcm = {
5062                 .omap4 = {
5063                         .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5064                         .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5065                         .modulemode   = MODULEMODE_SWCTRL,
5066                 },
5067         },
5068         .slaves         = omap44xx_uart4_slaves,
5069         .slaves_cnt     = ARRAY_SIZE(omap44xx_uart4_slaves),
5070 };
5071
5072 /*
5073  * 'usb_otg_hs' class
5074  * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5075  */
5076
5077 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5078         .rev_offs       = 0x0400,
5079         .sysc_offs      = 0x0404,
5080         .syss_offs      = 0x0408,
5081         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5082                            SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5083                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5084         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5085                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5086                            MSTANDBY_SMART),
5087         .sysc_fields    = &omap_hwmod_sysc_type1,
5088 };
5089
5090 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5091         .name   = "usb_otg_hs",
5092         .sysc   = &omap44xx_usb_otg_hs_sysc,
5093 };
5094
5095 /* usb_otg_hs */
5096 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5097         { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5098         { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5099         { .irq = -1 }
5100 };
5101
5102 /* usb_otg_hs master ports */
5103 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5104         &omap44xx_usb_otg_hs__l3_main_2,
5105 };
5106
5107 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5108         {
5109                 .pa_start       = 0x4a0ab000,
5110                 .pa_end         = 0x4a0ab003,
5111                 .flags          = ADDR_TYPE_RT
5112         },
5113         { }
5114 };
5115
5116 /* l4_cfg -> usb_otg_hs */
5117 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5118         .master         = &omap44xx_l4_cfg_hwmod,
5119         .slave          = &omap44xx_usb_otg_hs_hwmod,
5120         .clk            = "l4_div_ck",
5121         .addr           = omap44xx_usb_otg_hs_addrs,
5122         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5123 };
5124
5125 /* usb_otg_hs slave ports */
5126 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5127         &omap44xx_l4_cfg__usb_otg_hs,
5128 };
5129
5130 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5131         { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5132 };
5133
5134 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5135         .name           = "usb_otg_hs",
5136         .class          = &omap44xx_usb_otg_hs_hwmod_class,
5137         .clkdm_name     = "l3_init_clkdm",
5138         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5139         .mpu_irqs       = omap44xx_usb_otg_hs_irqs,
5140         .main_clk       = "usb_otg_hs_ick",
5141         .prcm = {
5142                 .omap4 = {
5143                         .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5144                         .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5145                         .modulemode   = MODULEMODE_HWCTRL,
5146                 },
5147         },
5148         .opt_clks       = usb_otg_hs_opt_clks,
5149         .opt_clks_cnt   = ARRAY_SIZE(usb_otg_hs_opt_clks),
5150         .slaves         = omap44xx_usb_otg_hs_slaves,
5151         .slaves_cnt     = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5152         .masters        = omap44xx_usb_otg_hs_masters,
5153         .masters_cnt    = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5154 };
5155
5156 /*
5157  * 'wd_timer' class
5158  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5159  * overflow condition
5160  */
5161
5162 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5163         .rev_offs       = 0x0000,
5164         .sysc_offs      = 0x0010,
5165         .syss_offs      = 0x0014,
5166         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5167                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5168         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5169                            SIDLE_SMART_WKUP),
5170         .sysc_fields    = &omap_hwmod_sysc_type1,
5171 };
5172
5173 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5174         .name           = "wd_timer",
5175         .sysc           = &omap44xx_wd_timer_sysc,
5176         .pre_shutdown   = &omap2_wd_timer_disable,
5177 };
5178
5179 /* wd_timer2 */
5180 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5181 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5182         { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5183         { .irq = -1 }
5184 };
5185
5186 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5187         {
5188                 .pa_start       = 0x4a314000,
5189                 .pa_end         = 0x4a31407f,
5190                 .flags          = ADDR_TYPE_RT
5191         },
5192         { }
5193 };
5194
5195 /* l4_wkup -> wd_timer2 */
5196 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5197         .master         = &omap44xx_l4_wkup_hwmod,
5198         .slave          = &omap44xx_wd_timer2_hwmod,
5199         .clk            = "l4_wkup_clk_mux_ck",
5200         .addr           = omap44xx_wd_timer2_addrs,
5201         .user           = OCP_USER_MPU | OCP_USER_SDMA,
5202 };
5203
5204 /* wd_timer2 slave ports */
5205 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5206         &omap44xx_l4_wkup__wd_timer2,
5207 };
5208
5209 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5210         .name           = "wd_timer2",
5211         .class          = &omap44xx_wd_timer_hwmod_class,
5212         .clkdm_name     = "l4_wkup_clkdm",
5213         .mpu_irqs       = omap44xx_wd_timer2_irqs,
5214         .main_clk       = "wd_timer2_fck",
5215         .prcm = {
5216                 .omap4 = {
5217                         .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5218                         .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5219                         .modulemode   = MODULEMODE_SWCTRL,
5220                 },
5221         },
5222         .slaves         = omap44xx_wd_timer2_slaves,
5223         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5224 };
5225
5226 /* wd_timer3 */
5227 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5228 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5229         { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5230         { .irq = -1 }
5231 };
5232
5233 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5234         {
5235                 .pa_start       = 0x40130000,
5236                 .pa_end         = 0x4013007f,
5237                 .flags          = ADDR_TYPE_RT
5238         },
5239         { }
5240 };
5241
5242 /* l4_abe -> wd_timer3 */
5243 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5244         .master         = &omap44xx_l4_abe_hwmod,
5245         .slave          = &omap44xx_wd_timer3_hwmod,
5246         .clk            = "ocp_abe_iclk",
5247         .addr           = omap44xx_wd_timer3_addrs,
5248         .user           = OCP_USER_MPU,
5249 };
5250
5251 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5252         {
5253                 .pa_start       = 0x49030000,
5254                 .pa_end         = 0x4903007f,
5255                 .flags          = ADDR_TYPE_RT
5256         },
5257         { }
5258 };
5259
5260 /* l4_abe -> wd_timer3 (dma) */
5261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5262         .master         = &omap44xx_l4_abe_hwmod,
5263         .slave          = &omap44xx_wd_timer3_hwmod,
5264         .clk            = "ocp_abe_iclk",
5265         .addr           = omap44xx_wd_timer3_dma_addrs,
5266         .user           = OCP_USER_SDMA,
5267 };
5268
5269 /* wd_timer3 slave ports */
5270 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5271         &omap44xx_l4_abe__wd_timer3,
5272         &omap44xx_l4_abe__wd_timer3_dma,
5273 };
5274
5275 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5276         .name           = "wd_timer3",
5277         .class          = &omap44xx_wd_timer_hwmod_class,
5278         .clkdm_name     = "abe_clkdm",
5279         .mpu_irqs       = omap44xx_wd_timer3_irqs,
5280         .main_clk       = "wd_timer3_fck",
5281         .prcm = {
5282                 .omap4 = {
5283                         .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5284                         .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5285                         .modulemode   = MODULEMODE_SWCTRL,
5286                 },
5287         },
5288         .slaves         = omap44xx_wd_timer3_slaves,
5289         .slaves_cnt     = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5290 };
5291
5292 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5293
5294         /* dmm class */
5295         &omap44xx_dmm_hwmod,
5296
5297         /* emif_fw class */
5298         &omap44xx_emif_fw_hwmod,
5299
5300         /* l3 class */
5301         &omap44xx_l3_instr_hwmod,
5302         &omap44xx_l3_main_1_hwmod,
5303         &omap44xx_l3_main_2_hwmod,
5304         &omap44xx_l3_main_3_hwmod,
5305
5306         /* l4 class */
5307         &omap44xx_l4_abe_hwmod,
5308         &omap44xx_l4_cfg_hwmod,
5309         &omap44xx_l4_per_hwmod,
5310         &omap44xx_l4_wkup_hwmod,
5311
5312         /* mpu_bus class */
5313         &omap44xx_mpu_private_hwmod,
5314
5315         /* aess class */
5316 /*      &omap44xx_aess_hwmod, */
5317
5318         /* bandgap class */
5319         &omap44xx_bandgap_hwmod,
5320
5321         /* counter class */
5322 /*      &omap44xx_counter_32k_hwmod, */
5323
5324         /* dma class */
5325         &omap44xx_dma_system_hwmod,
5326
5327         /* dmic class */
5328         &omap44xx_dmic_hwmod,
5329
5330         /* dsp class */
5331         &omap44xx_dsp_hwmod,
5332         &omap44xx_dsp_c0_hwmod,
5333
5334         /* dss class */
5335         &omap44xx_dss_hwmod,
5336         &omap44xx_dss_dispc_hwmod,
5337         &omap44xx_dss_dsi1_hwmod,
5338         &omap44xx_dss_dsi2_hwmod,
5339         &omap44xx_dss_hdmi_hwmod,
5340         &omap44xx_dss_rfbi_hwmod,
5341         &omap44xx_dss_venc_hwmod,
5342
5343         /* gpio class */
5344         &omap44xx_gpio1_hwmod,
5345         &omap44xx_gpio2_hwmod,
5346         &omap44xx_gpio3_hwmod,
5347         &omap44xx_gpio4_hwmod,
5348         &omap44xx_gpio5_hwmod,
5349         &omap44xx_gpio6_hwmod,
5350
5351         /* hsi class */
5352 /*      &omap44xx_hsi_hwmod, */
5353
5354         /* i2c class */
5355         &omap44xx_i2c1_hwmod,
5356         &omap44xx_i2c2_hwmod,
5357         &omap44xx_i2c3_hwmod,
5358         &omap44xx_i2c4_hwmod,
5359
5360         /* ipu class */
5361         &omap44xx_ipu_hwmod,
5362         &omap44xx_ipu_c0_hwmod,
5363         &omap44xx_ipu_c1_hwmod,
5364
5365         /* iss class */
5366 /*      &omap44xx_iss_hwmod, */
5367
5368         /* iva class */
5369         &omap44xx_iva_hwmod,
5370         &omap44xx_iva_seq0_hwmod,
5371         &omap44xx_iva_seq1_hwmod,
5372
5373         /* kbd class */
5374         &omap44xx_kbd_hwmod,
5375
5376         /* mailbox class */
5377         &omap44xx_mailbox_hwmod,
5378
5379         /* mcbsp class */
5380         &omap44xx_mcbsp1_hwmod,
5381         &omap44xx_mcbsp2_hwmod,
5382         &omap44xx_mcbsp3_hwmod,
5383         &omap44xx_mcbsp4_hwmod,
5384
5385         /* mcpdm class */
5386         &omap44xx_mcpdm_hwmod,
5387
5388         /* mcspi class */
5389         &omap44xx_mcspi1_hwmod,
5390         &omap44xx_mcspi2_hwmod,
5391         &omap44xx_mcspi3_hwmod,
5392         &omap44xx_mcspi4_hwmod,
5393
5394         /* mmc class */
5395         &omap44xx_mmc1_hwmod,
5396         &omap44xx_mmc2_hwmod,
5397         &omap44xx_mmc3_hwmod,
5398         &omap44xx_mmc4_hwmod,
5399         &omap44xx_mmc5_hwmod,
5400
5401         /* mpu class */
5402         &omap44xx_mpu_hwmod,
5403
5404         /* smartreflex class */
5405         &omap44xx_smartreflex_core_hwmod,
5406         &omap44xx_smartreflex_iva_hwmod,
5407         &omap44xx_smartreflex_mpu_hwmod,
5408
5409         /* spinlock class */
5410         &omap44xx_spinlock_hwmod,
5411
5412         /* timer class */
5413         &omap44xx_timer1_hwmod,
5414         &omap44xx_timer2_hwmod,
5415         &omap44xx_timer3_hwmod,
5416         &omap44xx_timer4_hwmod,
5417         &omap44xx_timer5_hwmod,
5418         &omap44xx_timer6_hwmod,
5419         &omap44xx_timer7_hwmod,
5420         &omap44xx_timer8_hwmod,
5421         &omap44xx_timer9_hwmod,
5422         &omap44xx_timer10_hwmod,
5423         &omap44xx_timer11_hwmod,
5424
5425         /* uart class */
5426         &omap44xx_uart1_hwmod,
5427         &omap44xx_uart2_hwmod,
5428         &omap44xx_uart3_hwmod,
5429         &omap44xx_uart4_hwmod,
5430
5431         /* usb_otg_hs class */
5432         &omap44xx_usb_otg_hs_hwmod,
5433
5434         /* wd_timer class */
5435         &omap44xx_wd_timer2_hwmod,
5436         &omap44xx_wd_timer3_hwmod,
5437
5438         NULL,
5439 };
5440
5441 int __init omap44xx_hwmod_init(void)
5442 {
5443         return omap_hwmod_register(omap44xx_hwmods);
5444 }
5445