2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2011 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
23 #include <plat/omap_hwmod.h>
26 #include <plat/gpio.h>
28 #include <plat/mcspi.h>
29 #include <plat/mcbsp.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
35 #include "omap_hwmod_common_data.h"
37 #include "smartreflex.h"
41 #include "prm-regbits-44xx.h"
44 /* Base offset for all OMAP4 interrupts external to MPUSS */
45 #define OMAP44XX_IRQ_GIC_START 32
47 /* Base offset for all OMAP4 dma requests */
48 #define OMAP44XX_DMA_REQ_START 1
50 /* Backward references (IPs with Bus Master capability) */
51 static struct omap_hwmod omap44xx_aess_hwmod;
52 static struct omap_hwmod omap44xx_dma_system_hwmod;
53 static struct omap_hwmod omap44xx_dmm_hwmod;
54 static struct omap_hwmod omap44xx_dsp_hwmod;
55 static struct omap_hwmod omap44xx_dss_hwmod;
56 static struct omap_hwmod omap44xx_emif_fw_hwmod;
57 static struct omap_hwmod omap44xx_hsi_hwmod;
58 static struct omap_hwmod omap44xx_ipu_hwmod;
59 static struct omap_hwmod omap44xx_iss_hwmod;
60 static struct omap_hwmod omap44xx_iva_hwmod;
61 static struct omap_hwmod omap44xx_l3_instr_hwmod;
62 static struct omap_hwmod omap44xx_l3_main_1_hwmod;
63 static struct omap_hwmod omap44xx_l3_main_2_hwmod;
64 static struct omap_hwmod omap44xx_l3_main_3_hwmod;
65 static struct omap_hwmod omap44xx_l4_abe_hwmod;
66 static struct omap_hwmod omap44xx_l4_cfg_hwmod;
67 static struct omap_hwmod omap44xx_l4_per_hwmod;
68 static struct omap_hwmod omap44xx_l4_wkup_hwmod;
69 static struct omap_hwmod omap44xx_mmc1_hwmod;
70 static struct omap_hwmod omap44xx_mmc2_hwmod;
71 static struct omap_hwmod omap44xx_mpu_hwmod;
72 static struct omap_hwmod omap44xx_mpu_private_hwmod;
73 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod;
76 * Interconnects omap_hwmod structures
77 * hwmods that compose the global OMAP interconnect
84 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
89 static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
90 { .irq = 113 + OMAP44XX_IRQ_GIC_START },
94 /* l3_main_1 -> dmm */
95 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
96 .master = &omap44xx_l3_main_1_hwmod,
97 .slave = &omap44xx_dmm_hwmod,
99 .user = OCP_USER_SDMA,
102 static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
104 .pa_start = 0x4e000000,
105 .pa_end = 0x4e0007ff,
106 .flags = ADDR_TYPE_RT
112 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
113 .master = &omap44xx_mpu_hwmod,
114 .slave = &omap44xx_dmm_hwmod,
116 .addr = omap44xx_dmm_addrs,
117 .user = OCP_USER_MPU,
120 /* dmm slave ports */
121 static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
122 &omap44xx_l3_main_1__dmm,
126 static struct omap_hwmod omap44xx_dmm_hwmod = {
128 .class = &omap44xx_dmm_hwmod_class,
129 .clkdm_name = "l3_emif_clkdm",
132 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
133 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
136 .slaves = omap44xx_dmm_slaves,
137 .slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
138 .mpu_irqs = omap44xx_dmm_irqs,
143 * instance(s): emif_fw
145 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
151 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
152 .master = &omap44xx_dmm_hwmod,
153 .slave = &omap44xx_emif_fw_hwmod,
155 .user = OCP_USER_MPU | OCP_USER_SDMA,
158 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
160 .pa_start = 0x4a20c000,
161 .pa_end = 0x4a20c0ff,
162 .flags = ADDR_TYPE_RT
167 /* l4_cfg -> emif_fw */
168 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
169 .master = &omap44xx_l4_cfg_hwmod,
170 .slave = &omap44xx_emif_fw_hwmod,
172 .addr = omap44xx_emif_fw_addrs,
173 .user = OCP_USER_MPU,
176 /* emif_fw slave ports */
177 static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
178 &omap44xx_dmm__emif_fw,
179 &omap44xx_l4_cfg__emif_fw,
182 static struct omap_hwmod omap44xx_emif_fw_hwmod = {
184 .class = &omap44xx_emif_fw_hwmod_class,
185 .clkdm_name = "l3_emif_clkdm",
188 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
189 .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
192 .slaves = omap44xx_emif_fw_slaves,
193 .slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
198 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
200 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
205 /* iva -> l3_instr */
206 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
207 .master = &omap44xx_iva_hwmod,
208 .slave = &omap44xx_l3_instr_hwmod,
210 .user = OCP_USER_MPU | OCP_USER_SDMA,
213 /* l3_main_3 -> l3_instr */
214 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
215 .master = &omap44xx_l3_main_3_hwmod,
216 .slave = &omap44xx_l3_instr_hwmod,
218 .user = OCP_USER_MPU | OCP_USER_SDMA,
221 /* l3_instr slave ports */
222 static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
223 &omap44xx_iva__l3_instr,
224 &omap44xx_l3_main_3__l3_instr,
227 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
229 .class = &omap44xx_l3_hwmod_class,
230 .clkdm_name = "l3_instr_clkdm",
233 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
234 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
235 .modulemode = MODULEMODE_HWCTRL,
238 .slaves = omap44xx_l3_instr_slaves,
239 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
243 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
244 { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
245 { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
249 /* dsp -> l3_main_1 */
250 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
251 .master = &omap44xx_dsp_hwmod,
252 .slave = &omap44xx_l3_main_1_hwmod,
254 .user = OCP_USER_MPU | OCP_USER_SDMA,
257 /* dss -> l3_main_1 */
258 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
259 .master = &omap44xx_dss_hwmod,
260 .slave = &omap44xx_l3_main_1_hwmod,
262 .user = OCP_USER_MPU | OCP_USER_SDMA,
265 /* l3_main_2 -> l3_main_1 */
266 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
267 .master = &omap44xx_l3_main_2_hwmod,
268 .slave = &omap44xx_l3_main_1_hwmod,
270 .user = OCP_USER_MPU | OCP_USER_SDMA,
273 /* l4_cfg -> l3_main_1 */
274 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
275 .master = &omap44xx_l4_cfg_hwmod,
276 .slave = &omap44xx_l3_main_1_hwmod,
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
281 /* mmc1 -> l3_main_1 */
282 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
283 .master = &omap44xx_mmc1_hwmod,
284 .slave = &omap44xx_l3_main_1_hwmod,
286 .user = OCP_USER_MPU | OCP_USER_SDMA,
289 /* mmc2 -> l3_main_1 */
290 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
291 .master = &omap44xx_mmc2_hwmod,
292 .slave = &omap44xx_l3_main_1_hwmod,
294 .user = OCP_USER_MPU | OCP_USER_SDMA,
297 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
299 .pa_start = 0x44000000,
300 .pa_end = 0x44000fff,
301 .flags = ADDR_TYPE_RT
306 /* mpu -> l3_main_1 */
307 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
308 .master = &omap44xx_mpu_hwmod,
309 .slave = &omap44xx_l3_main_1_hwmod,
311 .addr = omap44xx_l3_main_1_addrs,
312 .user = OCP_USER_MPU,
315 /* l3_main_1 slave ports */
316 static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
317 &omap44xx_dsp__l3_main_1,
318 &omap44xx_dss__l3_main_1,
319 &omap44xx_l3_main_2__l3_main_1,
320 &omap44xx_l4_cfg__l3_main_1,
321 &omap44xx_mmc1__l3_main_1,
322 &omap44xx_mmc2__l3_main_1,
323 &omap44xx_mpu__l3_main_1,
326 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
328 .class = &omap44xx_l3_hwmod_class,
329 .clkdm_name = "l3_1_clkdm",
330 .mpu_irqs = omap44xx_l3_main_1_irqs,
333 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
334 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
337 .slaves = omap44xx_l3_main_1_slaves,
338 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
342 /* dma_system -> l3_main_2 */
343 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
344 .master = &omap44xx_dma_system_hwmod,
345 .slave = &omap44xx_l3_main_2_hwmod,
347 .user = OCP_USER_MPU | OCP_USER_SDMA,
350 /* hsi -> l3_main_2 */
351 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
352 .master = &omap44xx_hsi_hwmod,
353 .slave = &omap44xx_l3_main_2_hwmod,
355 .user = OCP_USER_MPU | OCP_USER_SDMA,
358 /* ipu -> l3_main_2 */
359 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
360 .master = &omap44xx_ipu_hwmod,
361 .slave = &omap44xx_l3_main_2_hwmod,
363 .user = OCP_USER_MPU | OCP_USER_SDMA,
366 /* iss -> l3_main_2 */
367 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
368 .master = &omap44xx_iss_hwmod,
369 .slave = &omap44xx_l3_main_2_hwmod,
371 .user = OCP_USER_MPU | OCP_USER_SDMA,
374 /* iva -> l3_main_2 */
375 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
376 .master = &omap44xx_iva_hwmod,
377 .slave = &omap44xx_l3_main_2_hwmod,
379 .user = OCP_USER_MPU | OCP_USER_SDMA,
382 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
384 .pa_start = 0x44800000,
385 .pa_end = 0x44801fff,
386 .flags = ADDR_TYPE_RT
391 /* l3_main_1 -> l3_main_2 */
392 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
393 .master = &omap44xx_l3_main_1_hwmod,
394 .slave = &omap44xx_l3_main_2_hwmod,
396 .addr = omap44xx_l3_main_2_addrs,
397 .user = OCP_USER_MPU,
400 /* l4_cfg -> l3_main_2 */
401 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
402 .master = &omap44xx_l4_cfg_hwmod,
403 .slave = &omap44xx_l3_main_2_hwmod,
405 .user = OCP_USER_MPU | OCP_USER_SDMA,
408 /* usb_otg_hs -> l3_main_2 */
409 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
410 .master = &omap44xx_usb_otg_hs_hwmod,
411 .slave = &omap44xx_l3_main_2_hwmod,
413 .user = OCP_USER_MPU | OCP_USER_SDMA,
416 /* l3_main_2 slave ports */
417 static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
418 &omap44xx_dma_system__l3_main_2,
419 &omap44xx_hsi__l3_main_2,
420 &omap44xx_ipu__l3_main_2,
421 &omap44xx_iss__l3_main_2,
422 &omap44xx_iva__l3_main_2,
423 &omap44xx_l3_main_1__l3_main_2,
424 &omap44xx_l4_cfg__l3_main_2,
425 &omap44xx_usb_otg_hs__l3_main_2,
428 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
430 .class = &omap44xx_l3_hwmod_class,
431 .clkdm_name = "l3_2_clkdm",
434 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
435 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
438 .slaves = omap44xx_l3_main_2_slaves,
439 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
443 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
445 .pa_start = 0x45000000,
446 .pa_end = 0x45000fff,
447 .flags = ADDR_TYPE_RT
452 /* l3_main_1 -> l3_main_3 */
453 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
454 .master = &omap44xx_l3_main_1_hwmod,
455 .slave = &omap44xx_l3_main_3_hwmod,
457 .addr = omap44xx_l3_main_3_addrs,
458 .user = OCP_USER_MPU,
461 /* l3_main_2 -> l3_main_3 */
462 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
463 .master = &omap44xx_l3_main_2_hwmod,
464 .slave = &omap44xx_l3_main_3_hwmod,
466 .user = OCP_USER_MPU | OCP_USER_SDMA,
469 /* l4_cfg -> l3_main_3 */
470 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
471 .master = &omap44xx_l4_cfg_hwmod,
472 .slave = &omap44xx_l3_main_3_hwmod,
474 .user = OCP_USER_MPU | OCP_USER_SDMA,
477 /* l3_main_3 slave ports */
478 static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
479 &omap44xx_l3_main_1__l3_main_3,
480 &omap44xx_l3_main_2__l3_main_3,
481 &omap44xx_l4_cfg__l3_main_3,
484 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
486 .class = &omap44xx_l3_hwmod_class,
487 .clkdm_name = "l3_instr_clkdm",
490 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
491 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
492 .modulemode = MODULEMODE_HWCTRL,
495 .slaves = omap44xx_l3_main_3_slaves,
496 .slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
501 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
503 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
509 static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
510 .master = &omap44xx_aess_hwmod,
511 .slave = &omap44xx_l4_abe_hwmod,
512 .clk = "ocp_abe_iclk",
513 .user = OCP_USER_MPU | OCP_USER_SDMA,
517 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
518 .master = &omap44xx_dsp_hwmod,
519 .slave = &omap44xx_l4_abe_hwmod,
520 .clk = "ocp_abe_iclk",
521 .user = OCP_USER_MPU | OCP_USER_SDMA,
524 /* l3_main_1 -> l4_abe */
525 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
526 .master = &omap44xx_l3_main_1_hwmod,
527 .slave = &omap44xx_l4_abe_hwmod,
529 .user = OCP_USER_MPU | OCP_USER_SDMA,
533 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
534 .master = &omap44xx_mpu_hwmod,
535 .slave = &omap44xx_l4_abe_hwmod,
536 .clk = "ocp_abe_iclk",
537 .user = OCP_USER_MPU | OCP_USER_SDMA,
540 /* l4_abe slave ports */
541 static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
542 &omap44xx_aess__l4_abe,
543 &omap44xx_dsp__l4_abe,
544 &omap44xx_l3_main_1__l4_abe,
545 &omap44xx_mpu__l4_abe,
548 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
550 .class = &omap44xx_l4_hwmod_class,
551 .clkdm_name = "abe_clkdm",
554 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
557 .slaves = omap44xx_l4_abe_slaves,
558 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
562 /* l3_main_1 -> l4_cfg */
563 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
564 .master = &omap44xx_l3_main_1_hwmod,
565 .slave = &omap44xx_l4_cfg_hwmod,
567 .user = OCP_USER_MPU | OCP_USER_SDMA,
570 /* l4_cfg slave ports */
571 static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
572 &omap44xx_l3_main_1__l4_cfg,
575 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
577 .class = &omap44xx_l4_hwmod_class,
578 .clkdm_name = "l4_cfg_clkdm",
581 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
582 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
585 .slaves = omap44xx_l4_cfg_slaves,
586 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
590 /* l3_main_2 -> l4_per */
591 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
592 .master = &omap44xx_l3_main_2_hwmod,
593 .slave = &omap44xx_l4_per_hwmod,
595 .user = OCP_USER_MPU | OCP_USER_SDMA,
598 /* l4_per slave ports */
599 static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
600 &omap44xx_l3_main_2__l4_per,
603 static struct omap_hwmod omap44xx_l4_per_hwmod = {
605 .class = &omap44xx_l4_hwmod_class,
606 .clkdm_name = "l4_per_clkdm",
609 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
610 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
613 .slaves = omap44xx_l4_per_slaves,
614 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
618 /* l4_cfg -> l4_wkup */
619 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
620 .master = &omap44xx_l4_cfg_hwmod,
621 .slave = &omap44xx_l4_wkup_hwmod,
623 .user = OCP_USER_MPU | OCP_USER_SDMA,
626 /* l4_wkup slave ports */
627 static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
628 &omap44xx_l4_cfg__l4_wkup,
631 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
633 .class = &omap44xx_l4_hwmod_class,
634 .clkdm_name = "l4_wkup_clkdm",
637 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
638 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
641 .slaves = omap44xx_l4_wkup_slaves,
642 .slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
647 * instance(s): mpu_private
649 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
654 /* mpu -> mpu_private */
655 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
656 .master = &omap44xx_mpu_hwmod,
657 .slave = &omap44xx_mpu_private_hwmod,
659 .user = OCP_USER_MPU | OCP_USER_SDMA,
662 /* mpu_private slave ports */
663 static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
664 &omap44xx_mpu__mpu_private,
667 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
668 .name = "mpu_private",
669 .class = &omap44xx_mpu_bus_hwmod_class,
670 .clkdm_name = "mpuss_clkdm",
671 .slaves = omap44xx_mpu_private_slaves,
672 .slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
676 * Modules omap_hwmod structures
678 * The following IPs are excluded for the moment because:
679 * - They do not need an explicit SW control using omap_hwmod API.
680 * - They still need to be validated with the driver
681 * properly adapted to omap_hwmod / omap_device
688 * ctrl_module_pad_core
689 * ctrl_module_pad_wkup
722 * audio engine sub system
725 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
728 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
729 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
730 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
731 MSTANDBY_SMART_WKUP),
732 .sysc_fields = &omap_hwmod_sysc_type2,
735 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
737 .sysc = &omap44xx_aess_sysc,
741 static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
742 { .irq = 99 + OMAP44XX_IRQ_GIC_START },
746 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
747 { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START },
748 { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START },
749 { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START },
750 { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START },
751 { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START },
752 { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
753 { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
754 { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
758 /* aess master ports */
759 static struct omap_hwmod_ocp_if *omap44xx_aess_masters[] = {
760 &omap44xx_aess__l4_abe,
763 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
765 .pa_start = 0x401f1000,
766 .pa_end = 0x401f13ff,
767 .flags = ADDR_TYPE_RT
773 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
774 .master = &omap44xx_l4_abe_hwmod,
775 .slave = &omap44xx_aess_hwmod,
776 .clk = "ocp_abe_iclk",
777 .addr = omap44xx_aess_addrs,
778 .user = OCP_USER_MPU,
781 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
783 .pa_start = 0x490f1000,
784 .pa_end = 0x490f13ff,
785 .flags = ADDR_TYPE_RT
790 /* l4_abe -> aess (dma) */
791 static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
792 .master = &omap44xx_l4_abe_hwmod,
793 .slave = &omap44xx_aess_hwmod,
794 .clk = "ocp_abe_iclk",
795 .addr = omap44xx_aess_dma_addrs,
796 .user = OCP_USER_SDMA,
799 /* aess slave ports */
800 static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
801 &omap44xx_l4_abe__aess,
802 &omap44xx_l4_abe__aess_dma,
805 static struct omap_hwmod omap44xx_aess_hwmod = {
807 .class = &omap44xx_aess_hwmod_class,
808 .clkdm_name = "abe_clkdm",
809 .mpu_irqs = omap44xx_aess_irqs,
810 .sdma_reqs = omap44xx_aess_sdma_reqs,
811 .main_clk = "aess_fck",
814 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
815 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
816 .modulemode = MODULEMODE_SWCTRL,
819 .slaves = omap44xx_aess_slaves,
820 .slaves_cnt = ARRAY_SIZE(omap44xx_aess_slaves),
821 .masters = omap44xx_aess_masters,
822 .masters_cnt = ARRAY_SIZE(omap44xx_aess_masters),
827 * bangap reference for ldo regulators
830 static struct omap_hwmod_class omap44xx_bandgap_hwmod_class = {
835 static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
836 { .role = "fclk", .clk = "bandgap_fclk" },
839 static struct omap_hwmod omap44xx_bandgap_hwmod = {
841 .class = &omap44xx_bandgap_hwmod_class,
842 .clkdm_name = "l4_wkup_clkdm",
845 .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
848 .opt_clks = bandgap_opt_clks,
849 .opt_clks_cnt = ARRAY_SIZE(bandgap_opt_clks),
854 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
857 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
860 .sysc_flags = SYSC_HAS_SIDLEMODE,
861 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
863 .sysc_fields = &omap_hwmod_sysc_type1,
866 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
868 .sysc = &omap44xx_counter_sysc,
872 static struct omap_hwmod omap44xx_counter_32k_hwmod;
873 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
875 .pa_start = 0x4a304000,
876 .pa_end = 0x4a30401f,
877 .flags = ADDR_TYPE_RT
882 /* l4_wkup -> counter_32k */
883 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
884 .master = &omap44xx_l4_wkup_hwmod,
885 .slave = &omap44xx_counter_32k_hwmod,
886 .clk = "l4_wkup_clk_mux_ck",
887 .addr = omap44xx_counter_32k_addrs,
888 .user = OCP_USER_MPU | OCP_USER_SDMA,
891 /* counter_32k slave ports */
892 static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
893 &omap44xx_l4_wkup__counter_32k,
896 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
897 .name = "counter_32k",
898 .class = &omap44xx_counter_hwmod_class,
899 .clkdm_name = "l4_wkup_clkdm",
900 .flags = HWMOD_SWSUP_SIDLE,
901 .main_clk = "sys_32k_ck",
904 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
905 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
908 .slaves = omap44xx_counter_32k_slaves,
909 .slaves_cnt = ARRAY_SIZE(omap44xx_counter_32k_slaves),
914 * dma controller for data exchange between memory to memory (i.e. internal or
915 * external memory) and gp peripherals to memory or memory to gp peripherals
918 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
922 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
923 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
924 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
925 SYSS_HAS_RESET_STATUS),
926 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
927 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
928 .sysc_fields = &omap_hwmod_sysc_type1,
931 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
933 .sysc = &omap44xx_dma_sysc,
937 static struct omap_dma_dev_attr dma_dev_attr = {
938 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
939 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
944 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
945 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
946 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
947 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
948 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
952 /* dma_system master ports */
953 static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
954 &omap44xx_dma_system__l3_main_2,
957 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
959 .pa_start = 0x4a056000,
960 .pa_end = 0x4a056fff,
961 .flags = ADDR_TYPE_RT
966 /* l4_cfg -> dma_system */
967 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
968 .master = &omap44xx_l4_cfg_hwmod,
969 .slave = &omap44xx_dma_system_hwmod,
971 .addr = omap44xx_dma_system_addrs,
972 .user = OCP_USER_MPU | OCP_USER_SDMA,
975 /* dma_system slave ports */
976 static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
977 &omap44xx_l4_cfg__dma_system,
980 static struct omap_hwmod omap44xx_dma_system_hwmod = {
981 .name = "dma_system",
982 .class = &omap44xx_dma_hwmod_class,
983 .clkdm_name = "l3_dma_clkdm",
984 .mpu_irqs = omap44xx_dma_system_irqs,
985 .main_clk = "l3_div_ck",
988 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
989 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
992 .dev_attr = &dma_dev_attr,
993 .slaves = omap44xx_dma_system_slaves,
994 .slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
995 .masters = omap44xx_dma_system_masters,
996 .masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
1001 * digital microphone controller
1004 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
1006 .sysc_offs = 0x0010,
1007 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1008 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1009 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1011 .sysc_fields = &omap_hwmod_sysc_type2,
1014 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
1016 .sysc = &omap44xx_dmic_sysc,
1020 static struct omap_hwmod omap44xx_dmic_hwmod;
1021 static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
1022 { .irq = 114 + OMAP44XX_IRQ_GIC_START },
1026 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
1027 { .dma_req = 66 + OMAP44XX_DMA_REQ_START },
1031 static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
1033 .pa_start = 0x4012e000,
1034 .pa_end = 0x4012e07f,
1035 .flags = ADDR_TYPE_RT
1040 /* l4_abe -> dmic */
1041 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
1042 .master = &omap44xx_l4_abe_hwmod,
1043 .slave = &omap44xx_dmic_hwmod,
1044 .clk = "ocp_abe_iclk",
1045 .addr = omap44xx_dmic_addrs,
1046 .user = OCP_USER_MPU,
1049 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
1051 .pa_start = 0x4902e000,
1052 .pa_end = 0x4902e07f,
1053 .flags = ADDR_TYPE_RT
1058 /* l4_abe -> dmic (dma) */
1059 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
1060 .master = &omap44xx_l4_abe_hwmod,
1061 .slave = &omap44xx_dmic_hwmod,
1062 .clk = "ocp_abe_iclk",
1063 .addr = omap44xx_dmic_dma_addrs,
1064 .user = OCP_USER_SDMA,
1067 /* dmic slave ports */
1068 static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
1069 &omap44xx_l4_abe__dmic,
1070 &omap44xx_l4_abe__dmic_dma,
1073 static struct omap_hwmod omap44xx_dmic_hwmod = {
1075 .class = &omap44xx_dmic_hwmod_class,
1076 .clkdm_name = "abe_clkdm",
1077 .mpu_irqs = omap44xx_dmic_irqs,
1078 .sdma_reqs = omap44xx_dmic_sdma_reqs,
1079 .main_clk = "dmic_fck",
1082 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
1083 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
1084 .modulemode = MODULEMODE_SWCTRL,
1087 .slaves = omap44xx_dmic_slaves,
1088 .slaves_cnt = ARRAY_SIZE(omap44xx_dmic_slaves),
1096 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
1101 static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
1102 { .irq = 28 + OMAP44XX_IRQ_GIC_START },
1106 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
1107 { .name = "mmu_cache", .rst_shift = 1 },
1110 static struct omap_hwmod_rst_info omap44xx_dsp_c0_resets[] = {
1111 { .name = "dsp", .rst_shift = 0 },
1115 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
1116 .master = &omap44xx_dsp_hwmod,
1117 .slave = &omap44xx_iva_hwmod,
1118 .clk = "dpll_iva_m5x2_ck",
1121 /* dsp master ports */
1122 static struct omap_hwmod_ocp_if *omap44xx_dsp_masters[] = {
1123 &omap44xx_dsp__l3_main_1,
1124 &omap44xx_dsp__l4_abe,
1129 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
1130 .master = &omap44xx_l4_cfg_hwmod,
1131 .slave = &omap44xx_dsp_hwmod,
1133 .user = OCP_USER_MPU | OCP_USER_SDMA,
1136 /* dsp slave ports */
1137 static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
1138 &omap44xx_l4_cfg__dsp,
1141 /* Pseudo hwmod for reset control purpose only */
1142 static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
1144 .class = &omap44xx_dsp_hwmod_class,
1145 .clkdm_name = "tesla_clkdm",
1146 .flags = HWMOD_INIT_NO_RESET,
1147 .rst_lines = omap44xx_dsp_c0_resets,
1148 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
1151 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1156 static struct omap_hwmod omap44xx_dsp_hwmod = {
1158 .class = &omap44xx_dsp_hwmod_class,
1159 .clkdm_name = "tesla_clkdm",
1160 .mpu_irqs = omap44xx_dsp_irqs,
1161 .rst_lines = omap44xx_dsp_resets,
1162 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
1163 .main_clk = "dsp_fck",
1166 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
1167 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
1168 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
1169 .modulemode = MODULEMODE_HWCTRL,
1172 .slaves = omap44xx_dsp_slaves,
1173 .slaves_cnt = ARRAY_SIZE(omap44xx_dsp_slaves),
1174 .masters = omap44xx_dsp_masters,
1175 .masters_cnt = ARRAY_SIZE(omap44xx_dsp_masters),
1180 * display sub-system
1183 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
1185 .syss_offs = 0x0014,
1186 .sysc_flags = SYSS_HAS_RESET_STATUS,
1189 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
1191 .sysc = &omap44xx_dss_sysc,
1192 .reset = omap_dss_reset,
1196 /* dss master ports */
1197 static struct omap_hwmod_ocp_if *omap44xx_dss_masters[] = {
1198 &omap44xx_dss__l3_main_1,
1201 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
1203 .pa_start = 0x58000000,
1204 .pa_end = 0x5800007f,
1205 .flags = ADDR_TYPE_RT
1210 /* l3_main_2 -> dss */
1211 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
1212 .master = &omap44xx_l3_main_2_hwmod,
1213 .slave = &omap44xx_dss_hwmod,
1215 .addr = omap44xx_dss_dma_addrs,
1216 .user = OCP_USER_SDMA,
1219 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
1221 .pa_start = 0x48040000,
1222 .pa_end = 0x4804007f,
1223 .flags = ADDR_TYPE_RT
1229 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
1230 .master = &omap44xx_l4_per_hwmod,
1231 .slave = &omap44xx_dss_hwmod,
1233 .addr = omap44xx_dss_addrs,
1234 .user = OCP_USER_MPU,
1237 /* dss slave ports */
1238 static struct omap_hwmod_ocp_if *omap44xx_dss_slaves[] = {
1239 &omap44xx_l3_main_2__dss,
1240 &omap44xx_l4_per__dss,
1243 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
1244 { .role = "sys_clk", .clk = "dss_sys_clk" },
1245 { .role = "tv_clk", .clk = "dss_tv_clk" },
1246 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
1249 static struct omap_hwmod omap44xx_dss_hwmod = {
1251 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1252 .class = &omap44xx_dss_hwmod_class,
1253 .clkdm_name = "l3_dss_clkdm",
1254 .main_clk = "dss_dss_clk",
1257 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1258 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1261 .opt_clks = dss_opt_clks,
1262 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
1263 .slaves = omap44xx_dss_slaves,
1264 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_slaves),
1265 .masters = omap44xx_dss_masters,
1266 .masters_cnt = ARRAY_SIZE(omap44xx_dss_masters),
1271 * display controller
1274 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
1276 .sysc_offs = 0x0010,
1277 .syss_offs = 0x0014,
1278 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1279 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
1280 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1281 SYSS_HAS_RESET_STATUS),
1282 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1283 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1284 .sysc_fields = &omap_hwmod_sysc_type1,
1287 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
1289 .sysc = &omap44xx_dispc_sysc,
1293 static struct omap_hwmod omap44xx_dss_dispc_hwmod;
1294 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
1295 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
1299 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
1300 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
1304 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
1306 .pa_start = 0x58001000,
1307 .pa_end = 0x58001fff,
1308 .flags = ADDR_TYPE_RT
1313 /* l3_main_2 -> dss_dispc */
1314 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
1315 .master = &omap44xx_l3_main_2_hwmod,
1316 .slave = &omap44xx_dss_dispc_hwmod,
1318 .addr = omap44xx_dss_dispc_dma_addrs,
1319 .user = OCP_USER_SDMA,
1322 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
1324 .pa_start = 0x48041000,
1325 .pa_end = 0x48041fff,
1326 .flags = ADDR_TYPE_RT
1331 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
1333 .has_framedonetv_irq = 1
1336 /* l4_per -> dss_dispc */
1337 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
1338 .master = &omap44xx_l4_per_hwmod,
1339 .slave = &omap44xx_dss_dispc_hwmod,
1341 .addr = omap44xx_dss_dispc_addrs,
1342 .user = OCP_USER_MPU,
1345 /* dss_dispc slave ports */
1346 static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
1347 &omap44xx_l3_main_2__dss_dispc,
1348 &omap44xx_l4_per__dss_dispc,
1351 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
1352 .name = "dss_dispc",
1353 .class = &omap44xx_dispc_hwmod_class,
1354 .clkdm_name = "l3_dss_clkdm",
1355 .mpu_irqs = omap44xx_dss_dispc_irqs,
1356 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
1357 .main_clk = "dss_dss_clk",
1360 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1361 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1364 .slaves = omap44xx_dss_dispc_slaves,
1365 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
1366 .dev_attr = &omap44xx_dss_dispc_dev_attr
1371 * display serial interface controller
1374 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
1376 .sysc_offs = 0x0010,
1377 .syss_offs = 0x0014,
1378 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1379 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1380 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1381 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1382 .sysc_fields = &omap_hwmod_sysc_type1,
1385 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
1387 .sysc = &omap44xx_dsi_sysc,
1391 static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
1392 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
1393 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
1397 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
1398 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
1402 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
1404 .pa_start = 0x58004000,
1405 .pa_end = 0x580041ff,
1406 .flags = ADDR_TYPE_RT
1411 /* l3_main_2 -> dss_dsi1 */
1412 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
1413 .master = &omap44xx_l3_main_2_hwmod,
1414 .slave = &omap44xx_dss_dsi1_hwmod,
1416 .addr = omap44xx_dss_dsi1_dma_addrs,
1417 .user = OCP_USER_SDMA,
1420 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
1422 .pa_start = 0x48044000,
1423 .pa_end = 0x480441ff,
1424 .flags = ADDR_TYPE_RT
1429 /* l4_per -> dss_dsi1 */
1430 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
1431 .master = &omap44xx_l4_per_hwmod,
1432 .slave = &omap44xx_dss_dsi1_hwmod,
1434 .addr = omap44xx_dss_dsi1_addrs,
1435 .user = OCP_USER_MPU,
1438 /* dss_dsi1 slave ports */
1439 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
1440 &omap44xx_l3_main_2__dss_dsi1,
1441 &omap44xx_l4_per__dss_dsi1,
1444 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
1445 { .role = "sys_clk", .clk = "dss_sys_clk" },
1448 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
1450 .class = &omap44xx_dsi_hwmod_class,
1451 .clkdm_name = "l3_dss_clkdm",
1452 .mpu_irqs = omap44xx_dss_dsi1_irqs,
1453 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
1454 .main_clk = "dss_dss_clk",
1457 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1458 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1461 .opt_clks = dss_dsi1_opt_clks,
1462 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
1463 .slaves = omap44xx_dss_dsi1_slaves,
1464 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
1468 static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
1469 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
1470 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
1474 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
1475 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
1479 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
1481 .pa_start = 0x58005000,
1482 .pa_end = 0x580051ff,
1483 .flags = ADDR_TYPE_RT
1488 /* l3_main_2 -> dss_dsi2 */
1489 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
1490 .master = &omap44xx_l3_main_2_hwmod,
1491 .slave = &omap44xx_dss_dsi2_hwmod,
1493 .addr = omap44xx_dss_dsi2_dma_addrs,
1494 .user = OCP_USER_SDMA,
1497 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
1499 .pa_start = 0x48045000,
1500 .pa_end = 0x480451ff,
1501 .flags = ADDR_TYPE_RT
1506 /* l4_per -> dss_dsi2 */
1507 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
1508 .master = &omap44xx_l4_per_hwmod,
1509 .slave = &omap44xx_dss_dsi2_hwmod,
1511 .addr = omap44xx_dss_dsi2_addrs,
1512 .user = OCP_USER_MPU,
1515 /* dss_dsi2 slave ports */
1516 static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
1517 &omap44xx_l3_main_2__dss_dsi2,
1518 &omap44xx_l4_per__dss_dsi2,
1521 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
1522 { .role = "sys_clk", .clk = "dss_sys_clk" },
1525 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
1527 .class = &omap44xx_dsi_hwmod_class,
1528 .clkdm_name = "l3_dss_clkdm",
1529 .mpu_irqs = omap44xx_dss_dsi2_irqs,
1530 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
1531 .main_clk = "dss_dss_clk",
1534 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1535 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1538 .opt_clks = dss_dsi2_opt_clks,
1539 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
1540 .slaves = omap44xx_dss_dsi2_slaves,
1541 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
1549 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
1551 .sysc_offs = 0x0010,
1552 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1553 SYSC_HAS_SOFTRESET),
1554 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1556 .sysc_fields = &omap_hwmod_sysc_type2,
1559 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
1561 .sysc = &omap44xx_hdmi_sysc,
1565 static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
1566 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
1567 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
1571 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
1572 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
1576 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
1578 .pa_start = 0x58006000,
1579 .pa_end = 0x58006fff,
1580 .flags = ADDR_TYPE_RT
1585 /* l3_main_2 -> dss_hdmi */
1586 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
1587 .master = &omap44xx_l3_main_2_hwmod,
1588 .slave = &omap44xx_dss_hdmi_hwmod,
1590 .addr = omap44xx_dss_hdmi_dma_addrs,
1591 .user = OCP_USER_SDMA,
1594 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
1596 .pa_start = 0x48046000,
1597 .pa_end = 0x48046fff,
1598 .flags = ADDR_TYPE_RT
1603 /* l4_per -> dss_hdmi */
1604 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
1605 .master = &omap44xx_l4_per_hwmod,
1606 .slave = &omap44xx_dss_hdmi_hwmod,
1608 .addr = omap44xx_dss_hdmi_addrs,
1609 .user = OCP_USER_MPU,
1612 /* dss_hdmi slave ports */
1613 static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
1614 &omap44xx_l3_main_2__dss_hdmi,
1615 &omap44xx_l4_per__dss_hdmi,
1618 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
1619 { .role = "sys_clk", .clk = "dss_sys_clk" },
1622 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
1624 .class = &omap44xx_hdmi_hwmod_class,
1625 .clkdm_name = "l3_dss_clkdm",
1626 .mpu_irqs = omap44xx_dss_hdmi_irqs,
1627 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
1628 .main_clk = "dss_48mhz_clk",
1631 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1632 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1635 .opt_clks = dss_hdmi_opt_clks,
1636 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
1637 .slaves = omap44xx_dss_hdmi_slaves,
1638 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
1643 * remote frame buffer interface
1646 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
1648 .sysc_offs = 0x0010,
1649 .syss_offs = 0x0014,
1650 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1651 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1652 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1653 .sysc_fields = &omap_hwmod_sysc_type1,
1656 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
1658 .sysc = &omap44xx_rfbi_sysc,
1662 static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
1663 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
1664 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
1668 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
1670 .pa_start = 0x58002000,
1671 .pa_end = 0x580020ff,
1672 .flags = ADDR_TYPE_RT
1677 /* l3_main_2 -> dss_rfbi */
1678 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
1679 .master = &omap44xx_l3_main_2_hwmod,
1680 .slave = &omap44xx_dss_rfbi_hwmod,
1682 .addr = omap44xx_dss_rfbi_dma_addrs,
1683 .user = OCP_USER_SDMA,
1686 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
1688 .pa_start = 0x48042000,
1689 .pa_end = 0x480420ff,
1690 .flags = ADDR_TYPE_RT
1695 /* l4_per -> dss_rfbi */
1696 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
1697 .master = &omap44xx_l4_per_hwmod,
1698 .slave = &omap44xx_dss_rfbi_hwmod,
1700 .addr = omap44xx_dss_rfbi_addrs,
1701 .user = OCP_USER_MPU,
1704 /* dss_rfbi slave ports */
1705 static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
1706 &omap44xx_l3_main_2__dss_rfbi,
1707 &omap44xx_l4_per__dss_rfbi,
1710 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
1711 { .role = "ick", .clk = "dss_fck" },
1714 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
1716 .class = &omap44xx_rfbi_hwmod_class,
1717 .clkdm_name = "l3_dss_clkdm",
1718 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
1719 .main_clk = "dss_dss_clk",
1722 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1723 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1726 .opt_clks = dss_rfbi_opt_clks,
1727 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
1728 .slaves = omap44xx_dss_rfbi_slaves,
1729 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
1737 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
1742 static struct omap_hwmod omap44xx_dss_venc_hwmod;
1743 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
1745 .pa_start = 0x58003000,
1746 .pa_end = 0x580030ff,
1747 .flags = ADDR_TYPE_RT
1752 /* l3_main_2 -> dss_venc */
1753 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
1754 .master = &omap44xx_l3_main_2_hwmod,
1755 .slave = &omap44xx_dss_venc_hwmod,
1757 .addr = omap44xx_dss_venc_dma_addrs,
1758 .user = OCP_USER_SDMA,
1761 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
1763 .pa_start = 0x48043000,
1764 .pa_end = 0x480430ff,
1765 .flags = ADDR_TYPE_RT
1770 /* l4_per -> dss_venc */
1771 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
1772 .master = &omap44xx_l4_per_hwmod,
1773 .slave = &omap44xx_dss_venc_hwmod,
1775 .addr = omap44xx_dss_venc_addrs,
1776 .user = OCP_USER_MPU,
1779 /* dss_venc slave ports */
1780 static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
1781 &omap44xx_l3_main_2__dss_venc,
1782 &omap44xx_l4_per__dss_venc,
1785 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
1787 .class = &omap44xx_venc_hwmod_class,
1788 .clkdm_name = "l3_dss_clkdm",
1789 .main_clk = "dss_tv_clk",
1792 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
1793 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
1796 .slaves = omap44xx_dss_venc_slaves,
1797 .slaves_cnt = ARRAY_SIZE(omap44xx_dss_venc_slaves),
1802 * general purpose io module
1805 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1807 .sysc_offs = 0x0010,
1808 .syss_offs = 0x0114,
1809 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1810 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1811 SYSS_HAS_RESET_STATUS),
1812 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1814 .sysc_fields = &omap_hwmod_sysc_type1,
1817 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1819 .sysc = &omap44xx_gpio_sysc,
1824 static struct omap_gpio_dev_attr gpio_dev_attr = {
1830 static struct omap_hwmod omap44xx_gpio1_hwmod;
1831 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
1832 { .irq = 29 + OMAP44XX_IRQ_GIC_START },
1836 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
1838 .pa_start = 0x4a310000,
1839 .pa_end = 0x4a3101ff,
1840 .flags = ADDR_TYPE_RT
1845 /* l4_wkup -> gpio1 */
1846 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
1847 .master = &omap44xx_l4_wkup_hwmod,
1848 .slave = &omap44xx_gpio1_hwmod,
1849 .clk = "l4_wkup_clk_mux_ck",
1850 .addr = omap44xx_gpio1_addrs,
1851 .user = OCP_USER_MPU | OCP_USER_SDMA,
1854 /* gpio1 slave ports */
1855 static struct omap_hwmod_ocp_if *omap44xx_gpio1_slaves[] = {
1856 &omap44xx_l4_wkup__gpio1,
1859 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1860 { .role = "dbclk", .clk = "gpio1_dbclk" },
1863 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1865 .class = &omap44xx_gpio_hwmod_class,
1866 .clkdm_name = "l4_wkup_clkdm",
1867 .mpu_irqs = omap44xx_gpio1_irqs,
1868 .main_clk = "gpio1_ick",
1871 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1872 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1873 .modulemode = MODULEMODE_HWCTRL,
1876 .opt_clks = gpio1_opt_clks,
1877 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1878 .dev_attr = &gpio_dev_attr,
1879 .slaves = omap44xx_gpio1_slaves,
1880 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio1_slaves),
1884 static struct omap_hwmod omap44xx_gpio2_hwmod;
1885 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
1886 { .irq = 30 + OMAP44XX_IRQ_GIC_START },
1890 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
1892 .pa_start = 0x48055000,
1893 .pa_end = 0x480551ff,
1894 .flags = ADDR_TYPE_RT
1899 /* l4_per -> gpio2 */
1900 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
1901 .master = &omap44xx_l4_per_hwmod,
1902 .slave = &omap44xx_gpio2_hwmod,
1904 .addr = omap44xx_gpio2_addrs,
1905 .user = OCP_USER_MPU | OCP_USER_SDMA,
1908 /* gpio2 slave ports */
1909 static struct omap_hwmod_ocp_if *omap44xx_gpio2_slaves[] = {
1910 &omap44xx_l4_per__gpio2,
1913 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1914 { .role = "dbclk", .clk = "gpio2_dbclk" },
1917 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1919 .class = &omap44xx_gpio_hwmod_class,
1920 .clkdm_name = "l4_per_clkdm",
1921 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1922 .mpu_irqs = omap44xx_gpio2_irqs,
1923 .main_clk = "gpio2_ick",
1926 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1927 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1928 .modulemode = MODULEMODE_HWCTRL,
1931 .opt_clks = gpio2_opt_clks,
1932 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1933 .dev_attr = &gpio_dev_attr,
1934 .slaves = omap44xx_gpio2_slaves,
1935 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio2_slaves),
1939 static struct omap_hwmod omap44xx_gpio3_hwmod;
1940 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
1941 { .irq = 31 + OMAP44XX_IRQ_GIC_START },
1945 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
1947 .pa_start = 0x48057000,
1948 .pa_end = 0x480571ff,
1949 .flags = ADDR_TYPE_RT
1954 /* l4_per -> gpio3 */
1955 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
1956 .master = &omap44xx_l4_per_hwmod,
1957 .slave = &omap44xx_gpio3_hwmod,
1959 .addr = omap44xx_gpio3_addrs,
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
1963 /* gpio3 slave ports */
1964 static struct omap_hwmod_ocp_if *omap44xx_gpio3_slaves[] = {
1965 &omap44xx_l4_per__gpio3,
1968 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1969 { .role = "dbclk", .clk = "gpio3_dbclk" },
1972 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1974 .class = &omap44xx_gpio_hwmod_class,
1975 .clkdm_name = "l4_per_clkdm",
1976 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1977 .mpu_irqs = omap44xx_gpio3_irqs,
1978 .main_clk = "gpio3_ick",
1981 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1982 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1983 .modulemode = MODULEMODE_HWCTRL,
1986 .opt_clks = gpio3_opt_clks,
1987 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1988 .dev_attr = &gpio_dev_attr,
1989 .slaves = omap44xx_gpio3_slaves,
1990 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio3_slaves),
1994 static struct omap_hwmod omap44xx_gpio4_hwmod;
1995 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
1996 { .irq = 32 + OMAP44XX_IRQ_GIC_START },
2000 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
2002 .pa_start = 0x48059000,
2003 .pa_end = 0x480591ff,
2004 .flags = ADDR_TYPE_RT
2009 /* l4_per -> gpio4 */
2010 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
2011 .master = &omap44xx_l4_per_hwmod,
2012 .slave = &omap44xx_gpio4_hwmod,
2014 .addr = omap44xx_gpio4_addrs,
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2018 /* gpio4 slave ports */
2019 static struct omap_hwmod_ocp_if *omap44xx_gpio4_slaves[] = {
2020 &omap44xx_l4_per__gpio4,
2023 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
2024 { .role = "dbclk", .clk = "gpio4_dbclk" },
2027 static struct omap_hwmod omap44xx_gpio4_hwmod = {
2029 .class = &omap44xx_gpio_hwmod_class,
2030 .clkdm_name = "l4_per_clkdm",
2031 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2032 .mpu_irqs = omap44xx_gpio4_irqs,
2033 .main_clk = "gpio4_ick",
2036 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
2037 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
2038 .modulemode = MODULEMODE_HWCTRL,
2041 .opt_clks = gpio4_opt_clks,
2042 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
2043 .dev_attr = &gpio_dev_attr,
2044 .slaves = omap44xx_gpio4_slaves,
2045 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio4_slaves),
2049 static struct omap_hwmod omap44xx_gpio5_hwmod;
2050 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
2051 { .irq = 33 + OMAP44XX_IRQ_GIC_START },
2055 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
2057 .pa_start = 0x4805b000,
2058 .pa_end = 0x4805b1ff,
2059 .flags = ADDR_TYPE_RT
2064 /* l4_per -> gpio5 */
2065 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
2066 .master = &omap44xx_l4_per_hwmod,
2067 .slave = &omap44xx_gpio5_hwmod,
2069 .addr = omap44xx_gpio5_addrs,
2070 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073 /* gpio5 slave ports */
2074 static struct omap_hwmod_ocp_if *omap44xx_gpio5_slaves[] = {
2075 &omap44xx_l4_per__gpio5,
2078 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
2079 { .role = "dbclk", .clk = "gpio5_dbclk" },
2082 static struct omap_hwmod omap44xx_gpio5_hwmod = {
2084 .class = &omap44xx_gpio_hwmod_class,
2085 .clkdm_name = "l4_per_clkdm",
2086 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2087 .mpu_irqs = omap44xx_gpio5_irqs,
2088 .main_clk = "gpio5_ick",
2091 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
2092 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
2093 .modulemode = MODULEMODE_HWCTRL,
2096 .opt_clks = gpio5_opt_clks,
2097 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
2098 .dev_attr = &gpio_dev_attr,
2099 .slaves = omap44xx_gpio5_slaves,
2100 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio5_slaves),
2104 static struct omap_hwmod omap44xx_gpio6_hwmod;
2105 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
2106 { .irq = 34 + OMAP44XX_IRQ_GIC_START },
2110 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
2112 .pa_start = 0x4805d000,
2113 .pa_end = 0x4805d1ff,
2114 .flags = ADDR_TYPE_RT
2119 /* l4_per -> gpio6 */
2120 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
2121 .master = &omap44xx_l4_per_hwmod,
2122 .slave = &omap44xx_gpio6_hwmod,
2124 .addr = omap44xx_gpio6_addrs,
2125 .user = OCP_USER_MPU | OCP_USER_SDMA,
2128 /* gpio6 slave ports */
2129 static struct omap_hwmod_ocp_if *omap44xx_gpio6_slaves[] = {
2130 &omap44xx_l4_per__gpio6,
2133 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
2134 { .role = "dbclk", .clk = "gpio6_dbclk" },
2137 static struct omap_hwmod omap44xx_gpio6_hwmod = {
2139 .class = &omap44xx_gpio_hwmod_class,
2140 .clkdm_name = "l4_per_clkdm",
2141 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2142 .mpu_irqs = omap44xx_gpio6_irqs,
2143 .main_clk = "gpio6_ick",
2146 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
2147 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
2148 .modulemode = MODULEMODE_HWCTRL,
2151 .opt_clks = gpio6_opt_clks,
2152 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
2153 .dev_attr = &gpio_dev_attr,
2154 .slaves = omap44xx_gpio6_slaves,
2155 .slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
2160 * mipi high-speed synchronous serial interface (multichannel and full-duplex
2164 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
2166 .sysc_offs = 0x0010,
2167 .syss_offs = 0x0014,
2168 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
2169 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2170 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2171 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2172 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2173 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2174 .sysc_fields = &omap_hwmod_sysc_type1,
2177 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
2179 .sysc = &omap44xx_hsi_sysc,
2183 static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
2184 { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
2185 { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
2186 { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
2190 /* hsi master ports */
2191 static struct omap_hwmod_ocp_if *omap44xx_hsi_masters[] = {
2192 &omap44xx_hsi__l3_main_2,
2195 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
2197 .pa_start = 0x4a058000,
2198 .pa_end = 0x4a05bfff,
2199 .flags = ADDR_TYPE_RT
2205 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
2206 .master = &omap44xx_l4_cfg_hwmod,
2207 .slave = &omap44xx_hsi_hwmod,
2209 .addr = omap44xx_hsi_addrs,
2210 .user = OCP_USER_MPU | OCP_USER_SDMA,
2213 /* hsi slave ports */
2214 static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
2215 &omap44xx_l4_cfg__hsi,
2218 static struct omap_hwmod omap44xx_hsi_hwmod = {
2220 .class = &omap44xx_hsi_hwmod_class,
2221 .clkdm_name = "l3_init_clkdm",
2222 .mpu_irqs = omap44xx_hsi_irqs,
2223 .main_clk = "hsi_fck",
2226 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
2227 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
2228 .modulemode = MODULEMODE_HWCTRL,
2231 .slaves = omap44xx_hsi_slaves,
2232 .slaves_cnt = ARRAY_SIZE(omap44xx_hsi_slaves),
2233 .masters = omap44xx_hsi_masters,
2234 .masters_cnt = ARRAY_SIZE(omap44xx_hsi_masters),
2239 * multimaster high-speed i2c controller
2242 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
2243 .sysc_offs = 0x0010,
2244 .syss_offs = 0x0090,
2245 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2246 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2247 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2248 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2250 .sysc_fields = &omap_hwmod_sysc_type1,
2253 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
2255 .sysc = &omap44xx_i2c_sysc,
2256 .rev = OMAP_I2C_IP_VERSION_2,
2257 .reset = &omap_i2c_reset,
2260 static struct omap_i2c_dev_attr i2c_dev_attr = {
2261 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
2265 static struct omap_hwmod omap44xx_i2c1_hwmod;
2266 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
2267 { .irq = 56 + OMAP44XX_IRQ_GIC_START },
2271 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
2272 { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
2273 { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
2277 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
2279 .pa_start = 0x48070000,
2280 .pa_end = 0x480700ff,
2281 .flags = ADDR_TYPE_RT
2286 /* l4_per -> i2c1 */
2287 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
2288 .master = &omap44xx_l4_per_hwmod,
2289 .slave = &omap44xx_i2c1_hwmod,
2291 .addr = omap44xx_i2c1_addrs,
2292 .user = OCP_USER_MPU | OCP_USER_SDMA,
2295 /* i2c1 slave ports */
2296 static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
2297 &omap44xx_l4_per__i2c1,
2300 static struct omap_hwmod omap44xx_i2c1_hwmod = {
2302 .class = &omap44xx_i2c_hwmod_class,
2303 .clkdm_name = "l4_per_clkdm",
2304 .flags = HWMOD_16BIT_REG,
2305 .mpu_irqs = omap44xx_i2c1_irqs,
2306 .sdma_reqs = omap44xx_i2c1_sdma_reqs,
2307 .main_clk = "i2c1_fck",
2310 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
2311 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
2312 .modulemode = MODULEMODE_SWCTRL,
2315 .slaves = omap44xx_i2c1_slaves,
2316 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
2317 .dev_attr = &i2c_dev_attr,
2321 static struct omap_hwmod omap44xx_i2c2_hwmod;
2322 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
2323 { .irq = 57 + OMAP44XX_IRQ_GIC_START },
2327 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
2328 { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
2329 { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
2333 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
2335 .pa_start = 0x48072000,
2336 .pa_end = 0x480720ff,
2337 .flags = ADDR_TYPE_RT
2342 /* l4_per -> i2c2 */
2343 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
2344 .master = &omap44xx_l4_per_hwmod,
2345 .slave = &omap44xx_i2c2_hwmod,
2347 .addr = omap44xx_i2c2_addrs,
2348 .user = OCP_USER_MPU | OCP_USER_SDMA,
2351 /* i2c2 slave ports */
2352 static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
2353 &omap44xx_l4_per__i2c2,
2356 static struct omap_hwmod omap44xx_i2c2_hwmod = {
2358 .class = &omap44xx_i2c_hwmod_class,
2359 .clkdm_name = "l4_per_clkdm",
2360 .flags = HWMOD_16BIT_REG,
2361 .mpu_irqs = omap44xx_i2c2_irqs,
2362 .sdma_reqs = omap44xx_i2c2_sdma_reqs,
2363 .main_clk = "i2c2_fck",
2366 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
2367 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
2368 .modulemode = MODULEMODE_SWCTRL,
2371 .slaves = omap44xx_i2c2_slaves,
2372 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
2373 .dev_attr = &i2c_dev_attr,
2377 static struct omap_hwmod omap44xx_i2c3_hwmod;
2378 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
2379 { .irq = 61 + OMAP44XX_IRQ_GIC_START },
2383 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
2384 { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
2385 { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
2389 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
2391 .pa_start = 0x48060000,
2392 .pa_end = 0x480600ff,
2393 .flags = ADDR_TYPE_RT
2398 /* l4_per -> i2c3 */
2399 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
2400 .master = &omap44xx_l4_per_hwmod,
2401 .slave = &omap44xx_i2c3_hwmod,
2403 .addr = omap44xx_i2c3_addrs,
2404 .user = OCP_USER_MPU | OCP_USER_SDMA,
2407 /* i2c3 slave ports */
2408 static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
2409 &omap44xx_l4_per__i2c3,
2412 static struct omap_hwmod omap44xx_i2c3_hwmod = {
2414 .class = &omap44xx_i2c_hwmod_class,
2415 .clkdm_name = "l4_per_clkdm",
2416 .flags = HWMOD_16BIT_REG,
2417 .mpu_irqs = omap44xx_i2c3_irqs,
2418 .sdma_reqs = omap44xx_i2c3_sdma_reqs,
2419 .main_clk = "i2c3_fck",
2422 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
2423 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
2424 .modulemode = MODULEMODE_SWCTRL,
2427 .slaves = omap44xx_i2c3_slaves,
2428 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
2429 .dev_attr = &i2c_dev_attr,
2433 static struct omap_hwmod omap44xx_i2c4_hwmod;
2434 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
2435 { .irq = 62 + OMAP44XX_IRQ_GIC_START },
2439 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
2440 { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
2441 { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
2445 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
2447 .pa_start = 0x48350000,
2448 .pa_end = 0x483500ff,
2449 .flags = ADDR_TYPE_RT
2454 /* l4_per -> i2c4 */
2455 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
2456 .master = &omap44xx_l4_per_hwmod,
2457 .slave = &omap44xx_i2c4_hwmod,
2459 .addr = omap44xx_i2c4_addrs,
2460 .user = OCP_USER_MPU | OCP_USER_SDMA,
2463 /* i2c4 slave ports */
2464 static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
2465 &omap44xx_l4_per__i2c4,
2468 static struct omap_hwmod omap44xx_i2c4_hwmod = {
2470 .class = &omap44xx_i2c_hwmod_class,
2471 .clkdm_name = "l4_per_clkdm",
2472 .flags = HWMOD_16BIT_REG,
2473 .mpu_irqs = omap44xx_i2c4_irqs,
2474 .sdma_reqs = omap44xx_i2c4_sdma_reqs,
2475 .main_clk = "i2c4_fck",
2478 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
2479 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
2480 .modulemode = MODULEMODE_SWCTRL,
2483 .slaves = omap44xx_i2c4_slaves,
2484 .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
2485 .dev_attr = &i2c_dev_attr,
2490 * imaging processor unit
2493 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
2498 static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
2499 { .irq = 100 + OMAP44XX_IRQ_GIC_START },
2503 static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
2504 { .name = "cpu0", .rst_shift = 0 },
2507 static struct omap_hwmod_rst_info omap44xx_ipu_c1_resets[] = {
2508 { .name = "cpu1", .rst_shift = 1 },
2511 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
2512 { .name = "mmu_cache", .rst_shift = 2 },
2515 /* ipu master ports */
2516 static struct omap_hwmod_ocp_if *omap44xx_ipu_masters[] = {
2517 &omap44xx_ipu__l3_main_2,
2520 /* l3_main_2 -> ipu */
2521 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
2522 .master = &omap44xx_l3_main_2_hwmod,
2523 .slave = &omap44xx_ipu_hwmod,
2525 .user = OCP_USER_MPU | OCP_USER_SDMA,
2528 /* ipu slave ports */
2529 static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
2530 &omap44xx_l3_main_2__ipu,
2533 /* Pseudo hwmod for reset control purpose only */
2534 static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
2536 .class = &omap44xx_ipu_hwmod_class,
2537 .clkdm_name = "ducati_clkdm",
2538 .flags = HWMOD_INIT_NO_RESET,
2539 .rst_lines = omap44xx_ipu_c0_resets,
2540 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
2543 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2548 /* Pseudo hwmod for reset control purpose only */
2549 static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
2551 .class = &omap44xx_ipu_hwmod_class,
2552 .clkdm_name = "ducati_clkdm",
2553 .flags = HWMOD_INIT_NO_RESET,
2554 .rst_lines = omap44xx_ipu_c1_resets,
2555 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
2558 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2563 static struct omap_hwmod omap44xx_ipu_hwmod = {
2565 .class = &omap44xx_ipu_hwmod_class,
2566 .clkdm_name = "ducati_clkdm",
2567 .mpu_irqs = omap44xx_ipu_irqs,
2568 .rst_lines = omap44xx_ipu_resets,
2569 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
2570 .main_clk = "ipu_fck",
2573 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2574 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2575 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2576 .modulemode = MODULEMODE_HWCTRL,
2579 .slaves = omap44xx_ipu_slaves,
2580 .slaves_cnt = ARRAY_SIZE(omap44xx_ipu_slaves),
2581 .masters = omap44xx_ipu_masters,
2582 .masters_cnt = ARRAY_SIZE(omap44xx_ipu_masters),
2587 * external images sensor pixel data processor
2590 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
2592 .sysc_offs = 0x0010,
2593 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
2594 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2595 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2596 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2597 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2598 .sysc_fields = &omap_hwmod_sysc_type2,
2601 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
2603 .sysc = &omap44xx_iss_sysc,
2607 static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
2608 { .irq = 24 + OMAP44XX_IRQ_GIC_START },
2612 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
2613 { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START },
2614 { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
2615 { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
2616 { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
2620 /* iss master ports */
2621 static struct omap_hwmod_ocp_if *omap44xx_iss_masters[] = {
2622 &omap44xx_iss__l3_main_2,
2625 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
2627 .pa_start = 0x52000000,
2628 .pa_end = 0x520000ff,
2629 .flags = ADDR_TYPE_RT
2634 /* l3_main_2 -> iss */
2635 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
2636 .master = &omap44xx_l3_main_2_hwmod,
2637 .slave = &omap44xx_iss_hwmod,
2639 .addr = omap44xx_iss_addrs,
2640 .user = OCP_USER_MPU | OCP_USER_SDMA,
2643 /* iss slave ports */
2644 static struct omap_hwmod_ocp_if *omap44xx_iss_slaves[] = {
2645 &omap44xx_l3_main_2__iss,
2648 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
2649 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
2652 static struct omap_hwmod omap44xx_iss_hwmod = {
2654 .class = &omap44xx_iss_hwmod_class,
2655 .clkdm_name = "iss_clkdm",
2656 .mpu_irqs = omap44xx_iss_irqs,
2657 .sdma_reqs = omap44xx_iss_sdma_reqs,
2658 .main_clk = "iss_fck",
2661 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
2662 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
2663 .modulemode = MODULEMODE_SWCTRL,
2666 .opt_clks = iss_opt_clks,
2667 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
2668 .slaves = omap44xx_iss_slaves,
2669 .slaves_cnt = ARRAY_SIZE(omap44xx_iss_slaves),
2670 .masters = omap44xx_iss_masters,
2671 .masters_cnt = ARRAY_SIZE(omap44xx_iss_masters),
2676 * multi-standard video encoder/decoder hardware accelerator
2679 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
2684 static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
2685 { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
2686 { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
2687 { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
2691 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
2692 { .name = "logic", .rst_shift = 2 },
2695 static struct omap_hwmod_rst_info omap44xx_iva_seq0_resets[] = {
2696 { .name = "seq0", .rst_shift = 0 },
2699 static struct omap_hwmod_rst_info omap44xx_iva_seq1_resets[] = {
2700 { .name = "seq1", .rst_shift = 1 },
2703 /* iva master ports */
2704 static struct omap_hwmod_ocp_if *omap44xx_iva_masters[] = {
2705 &omap44xx_iva__l3_main_2,
2706 &omap44xx_iva__l3_instr,
2709 static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
2711 .pa_start = 0x5a000000,
2712 .pa_end = 0x5a07ffff,
2713 .flags = ADDR_TYPE_RT
2718 /* l3_main_2 -> iva */
2719 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
2720 .master = &omap44xx_l3_main_2_hwmod,
2721 .slave = &omap44xx_iva_hwmod,
2723 .addr = omap44xx_iva_addrs,
2724 .user = OCP_USER_MPU,
2727 /* iva slave ports */
2728 static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
2730 &omap44xx_l3_main_2__iva,
2733 /* Pseudo hwmod for reset control purpose only */
2734 static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
2736 .class = &omap44xx_iva_hwmod_class,
2737 .clkdm_name = "ivahd_clkdm",
2738 .flags = HWMOD_INIT_NO_RESET,
2739 .rst_lines = omap44xx_iva_seq0_resets,
2740 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
2743 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2748 /* Pseudo hwmod for reset control purpose only */
2749 static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
2751 .class = &omap44xx_iva_hwmod_class,
2752 .clkdm_name = "ivahd_clkdm",
2753 .flags = HWMOD_INIT_NO_RESET,
2754 .rst_lines = omap44xx_iva_seq1_resets,
2755 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
2758 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2763 static struct omap_hwmod omap44xx_iva_hwmod = {
2765 .class = &omap44xx_iva_hwmod_class,
2766 .clkdm_name = "ivahd_clkdm",
2767 .mpu_irqs = omap44xx_iva_irqs,
2768 .rst_lines = omap44xx_iva_resets,
2769 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
2770 .main_clk = "iva_fck",
2773 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
2774 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
2775 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
2776 .modulemode = MODULEMODE_HWCTRL,
2779 .slaves = omap44xx_iva_slaves,
2780 .slaves_cnt = ARRAY_SIZE(omap44xx_iva_slaves),
2781 .masters = omap44xx_iva_masters,
2782 .masters_cnt = ARRAY_SIZE(omap44xx_iva_masters),
2787 * keyboard controller
2790 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
2792 .sysc_offs = 0x0010,
2793 .syss_offs = 0x0014,
2794 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2795 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2796 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2797 SYSS_HAS_RESET_STATUS),
2798 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2799 .sysc_fields = &omap_hwmod_sysc_type1,
2802 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
2804 .sysc = &omap44xx_kbd_sysc,
2808 static struct omap_hwmod omap44xx_kbd_hwmod;
2809 static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
2810 { .irq = 120 + OMAP44XX_IRQ_GIC_START },
2814 static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
2816 .pa_start = 0x4a31c000,
2817 .pa_end = 0x4a31c07f,
2818 .flags = ADDR_TYPE_RT
2823 /* l4_wkup -> kbd */
2824 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
2825 .master = &omap44xx_l4_wkup_hwmod,
2826 .slave = &omap44xx_kbd_hwmod,
2827 .clk = "l4_wkup_clk_mux_ck",
2828 .addr = omap44xx_kbd_addrs,
2829 .user = OCP_USER_MPU | OCP_USER_SDMA,
2832 /* kbd slave ports */
2833 static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
2834 &omap44xx_l4_wkup__kbd,
2837 static struct omap_hwmod omap44xx_kbd_hwmod = {
2839 .class = &omap44xx_kbd_hwmod_class,
2840 .clkdm_name = "l4_wkup_clkdm",
2841 .mpu_irqs = omap44xx_kbd_irqs,
2842 .main_clk = "kbd_fck",
2845 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
2846 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
2847 .modulemode = MODULEMODE_SWCTRL,
2850 .slaves = omap44xx_kbd_slaves,
2851 .slaves_cnt = ARRAY_SIZE(omap44xx_kbd_slaves),
2856 * mailbox module allowing communication between the on-chip processors using a
2857 * queued mailbox-interrupt mechanism.
2860 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
2862 .sysc_offs = 0x0010,
2863 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2864 SYSC_HAS_SOFTRESET),
2865 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2866 .sysc_fields = &omap_hwmod_sysc_type2,
2869 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
2871 .sysc = &omap44xx_mailbox_sysc,
2875 static struct omap_hwmod omap44xx_mailbox_hwmod;
2876 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
2877 { .irq = 26 + OMAP44XX_IRQ_GIC_START },
2881 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
2883 .pa_start = 0x4a0f4000,
2884 .pa_end = 0x4a0f41ff,
2885 .flags = ADDR_TYPE_RT
2890 /* l4_cfg -> mailbox */
2891 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
2892 .master = &omap44xx_l4_cfg_hwmod,
2893 .slave = &omap44xx_mailbox_hwmod,
2895 .addr = omap44xx_mailbox_addrs,
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2899 /* mailbox slave ports */
2900 static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
2901 &omap44xx_l4_cfg__mailbox,
2904 static struct omap_hwmod omap44xx_mailbox_hwmod = {
2906 .class = &omap44xx_mailbox_hwmod_class,
2907 .clkdm_name = "l4_cfg_clkdm",
2908 .mpu_irqs = omap44xx_mailbox_irqs,
2911 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
2912 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
2915 .slaves = omap44xx_mailbox_slaves,
2916 .slaves_cnt = ARRAY_SIZE(omap44xx_mailbox_slaves),
2921 * multi channel buffered serial port controller
2924 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2925 .sysc_offs = 0x008c,
2926 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2927 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2928 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2929 .sysc_fields = &omap_hwmod_sysc_type1,
2932 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2934 .sysc = &omap44xx_mcbsp_sysc,
2935 .rev = MCBSP_CONFIG_TYPE4,
2939 static struct omap_hwmod omap44xx_mcbsp1_hwmod;
2940 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
2941 { .irq = 17 + OMAP44XX_IRQ_GIC_START },
2945 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2946 { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
2947 { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
2951 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2954 .pa_start = 0x40122000,
2955 .pa_end = 0x401220ff,
2956 .flags = ADDR_TYPE_RT
2961 /* l4_abe -> mcbsp1 */
2962 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2963 .master = &omap44xx_l4_abe_hwmod,
2964 .slave = &omap44xx_mcbsp1_hwmod,
2965 .clk = "ocp_abe_iclk",
2966 .addr = omap44xx_mcbsp1_addrs,
2967 .user = OCP_USER_MPU,
2970 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2973 .pa_start = 0x49022000,
2974 .pa_end = 0x490220ff,
2975 .flags = ADDR_TYPE_RT
2980 /* l4_abe -> mcbsp1 (dma) */
2981 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
2982 .master = &omap44xx_l4_abe_hwmod,
2983 .slave = &omap44xx_mcbsp1_hwmod,
2984 .clk = "ocp_abe_iclk",
2985 .addr = omap44xx_mcbsp1_dma_addrs,
2986 .user = OCP_USER_SDMA,
2989 /* mcbsp1 slave ports */
2990 static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
2991 &omap44xx_l4_abe__mcbsp1,
2992 &omap44xx_l4_abe__mcbsp1_dma,
2995 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
2997 .class = &omap44xx_mcbsp_hwmod_class,
2998 .clkdm_name = "abe_clkdm",
2999 .mpu_irqs = omap44xx_mcbsp1_irqs,
3000 .sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
3001 .main_clk = "mcbsp1_fck",
3004 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
3005 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
3006 .modulemode = MODULEMODE_SWCTRL,
3009 .slaves = omap44xx_mcbsp1_slaves,
3010 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp1_slaves),
3014 static struct omap_hwmod omap44xx_mcbsp2_hwmod;
3015 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
3016 { .irq = 22 + OMAP44XX_IRQ_GIC_START },
3020 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
3021 { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
3022 { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
3026 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
3029 .pa_start = 0x40124000,
3030 .pa_end = 0x401240ff,
3031 .flags = ADDR_TYPE_RT
3036 /* l4_abe -> mcbsp2 */
3037 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3038 .master = &omap44xx_l4_abe_hwmod,
3039 .slave = &omap44xx_mcbsp2_hwmod,
3040 .clk = "ocp_abe_iclk",
3041 .addr = omap44xx_mcbsp2_addrs,
3042 .user = OCP_USER_MPU,
3045 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
3048 .pa_start = 0x49024000,
3049 .pa_end = 0x490240ff,
3050 .flags = ADDR_TYPE_RT
3055 /* l4_abe -> mcbsp2 (dma) */
3056 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
3057 .master = &omap44xx_l4_abe_hwmod,
3058 .slave = &omap44xx_mcbsp2_hwmod,
3059 .clk = "ocp_abe_iclk",
3060 .addr = omap44xx_mcbsp2_dma_addrs,
3061 .user = OCP_USER_SDMA,
3064 /* mcbsp2 slave ports */
3065 static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
3066 &omap44xx_l4_abe__mcbsp2,
3067 &omap44xx_l4_abe__mcbsp2_dma,
3070 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
3072 .class = &omap44xx_mcbsp_hwmod_class,
3073 .clkdm_name = "abe_clkdm",
3074 .mpu_irqs = omap44xx_mcbsp2_irqs,
3075 .sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
3076 .main_clk = "mcbsp2_fck",
3079 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
3080 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
3081 .modulemode = MODULEMODE_SWCTRL,
3084 .slaves = omap44xx_mcbsp2_slaves,
3085 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp2_slaves),
3089 static struct omap_hwmod omap44xx_mcbsp3_hwmod;
3090 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
3091 { .irq = 23 + OMAP44XX_IRQ_GIC_START },
3095 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
3096 { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
3097 { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
3101 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
3104 .pa_start = 0x40126000,
3105 .pa_end = 0x401260ff,
3106 .flags = ADDR_TYPE_RT
3111 /* l4_abe -> mcbsp3 */
3112 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3113 .master = &omap44xx_l4_abe_hwmod,
3114 .slave = &omap44xx_mcbsp3_hwmod,
3115 .clk = "ocp_abe_iclk",
3116 .addr = omap44xx_mcbsp3_addrs,
3117 .user = OCP_USER_MPU,
3120 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
3123 .pa_start = 0x49026000,
3124 .pa_end = 0x490260ff,
3125 .flags = ADDR_TYPE_RT
3130 /* l4_abe -> mcbsp3 (dma) */
3131 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
3132 .master = &omap44xx_l4_abe_hwmod,
3133 .slave = &omap44xx_mcbsp3_hwmod,
3134 .clk = "ocp_abe_iclk",
3135 .addr = omap44xx_mcbsp3_dma_addrs,
3136 .user = OCP_USER_SDMA,
3139 /* mcbsp3 slave ports */
3140 static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
3141 &omap44xx_l4_abe__mcbsp3,
3142 &omap44xx_l4_abe__mcbsp3_dma,
3145 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
3147 .class = &omap44xx_mcbsp_hwmod_class,
3148 .clkdm_name = "abe_clkdm",
3149 .mpu_irqs = omap44xx_mcbsp3_irqs,
3150 .sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
3151 .main_clk = "mcbsp3_fck",
3154 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
3155 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
3156 .modulemode = MODULEMODE_SWCTRL,
3159 .slaves = omap44xx_mcbsp3_slaves,
3160 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp3_slaves),
3164 static struct omap_hwmod omap44xx_mcbsp4_hwmod;
3165 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
3166 { .irq = 16 + OMAP44XX_IRQ_GIC_START },
3170 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
3171 { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
3172 { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
3176 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
3178 .pa_start = 0x48096000,
3179 .pa_end = 0x480960ff,
3180 .flags = ADDR_TYPE_RT
3185 /* l4_per -> mcbsp4 */
3186 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3187 .master = &omap44xx_l4_per_hwmod,
3188 .slave = &omap44xx_mcbsp4_hwmod,
3190 .addr = omap44xx_mcbsp4_addrs,
3191 .user = OCP_USER_MPU | OCP_USER_SDMA,
3194 /* mcbsp4 slave ports */
3195 static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
3196 &omap44xx_l4_per__mcbsp4,
3199 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
3201 .class = &omap44xx_mcbsp_hwmod_class,
3202 .clkdm_name = "l4_per_clkdm",
3203 .mpu_irqs = omap44xx_mcbsp4_irqs,
3204 .sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
3205 .main_clk = "mcbsp4_fck",
3208 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
3209 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
3210 .modulemode = MODULEMODE_SWCTRL,
3213 .slaves = omap44xx_mcbsp4_slaves,
3214 .slaves_cnt = ARRAY_SIZE(omap44xx_mcbsp4_slaves),
3219 * multi channel pdm controller (proprietary interface with phoenix power
3223 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
3225 .sysc_offs = 0x0010,
3226 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3227 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3228 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3230 .sysc_fields = &omap_hwmod_sysc_type2,
3233 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
3235 .sysc = &omap44xx_mcpdm_sysc,
3239 static struct omap_hwmod omap44xx_mcpdm_hwmod;
3240 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
3241 { .irq = 112 + OMAP44XX_IRQ_GIC_START },
3245 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
3246 { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
3247 { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
3251 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
3253 .pa_start = 0x40132000,
3254 .pa_end = 0x4013207f,
3255 .flags = ADDR_TYPE_RT
3260 /* l4_abe -> mcpdm */
3261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3262 .master = &omap44xx_l4_abe_hwmod,
3263 .slave = &omap44xx_mcpdm_hwmod,
3264 .clk = "ocp_abe_iclk",
3265 .addr = omap44xx_mcpdm_addrs,
3266 .user = OCP_USER_MPU,
3269 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
3271 .pa_start = 0x49032000,
3272 .pa_end = 0x4903207f,
3273 .flags = ADDR_TYPE_RT
3278 /* l4_abe -> mcpdm (dma) */
3279 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
3280 .master = &omap44xx_l4_abe_hwmod,
3281 .slave = &omap44xx_mcpdm_hwmod,
3282 .clk = "ocp_abe_iclk",
3283 .addr = omap44xx_mcpdm_dma_addrs,
3284 .user = OCP_USER_SDMA,
3287 /* mcpdm slave ports */
3288 static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
3289 &omap44xx_l4_abe__mcpdm,
3290 &omap44xx_l4_abe__mcpdm_dma,
3293 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
3295 .class = &omap44xx_mcpdm_hwmod_class,
3296 .clkdm_name = "abe_clkdm",
3297 .mpu_irqs = omap44xx_mcpdm_irqs,
3298 .sdma_reqs = omap44xx_mcpdm_sdma_reqs,
3299 .main_clk = "mcpdm_fck",
3302 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
3303 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
3304 .modulemode = MODULEMODE_SWCTRL,
3307 .slaves = omap44xx_mcpdm_slaves,
3308 .slaves_cnt = ARRAY_SIZE(omap44xx_mcpdm_slaves),
3313 * multichannel serial port interface (mcspi) / master/slave synchronous serial
3317 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
3319 .sysc_offs = 0x0010,
3320 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
3321 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
3322 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3324 .sysc_fields = &omap_hwmod_sysc_type2,
3327 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
3329 .sysc = &omap44xx_mcspi_sysc,
3330 .rev = OMAP4_MCSPI_REV,
3334 static struct omap_hwmod omap44xx_mcspi1_hwmod;
3335 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
3336 { .irq = 65 + OMAP44XX_IRQ_GIC_START },
3340 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
3341 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
3342 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
3343 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
3344 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
3345 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
3346 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
3347 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
3348 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
3352 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
3354 .pa_start = 0x48098000,
3355 .pa_end = 0x480981ff,
3356 .flags = ADDR_TYPE_RT
3361 /* l4_per -> mcspi1 */
3362 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3363 .master = &omap44xx_l4_per_hwmod,
3364 .slave = &omap44xx_mcspi1_hwmod,
3366 .addr = omap44xx_mcspi1_addrs,
3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3370 /* mcspi1 slave ports */
3371 static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
3372 &omap44xx_l4_per__mcspi1,
3375 /* mcspi1 dev_attr */
3376 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
3377 .num_chipselect = 4,
3380 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
3382 .class = &omap44xx_mcspi_hwmod_class,
3383 .clkdm_name = "l4_per_clkdm",
3384 .mpu_irqs = omap44xx_mcspi1_irqs,
3385 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
3386 .main_clk = "mcspi1_fck",
3389 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
3390 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
3391 .modulemode = MODULEMODE_SWCTRL,
3394 .dev_attr = &mcspi1_dev_attr,
3395 .slaves = omap44xx_mcspi1_slaves,
3396 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi1_slaves),
3400 static struct omap_hwmod omap44xx_mcspi2_hwmod;
3401 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
3402 { .irq = 66 + OMAP44XX_IRQ_GIC_START },
3406 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
3407 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
3408 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
3409 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
3410 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
3414 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
3416 .pa_start = 0x4809a000,
3417 .pa_end = 0x4809a1ff,
3418 .flags = ADDR_TYPE_RT
3423 /* l4_per -> mcspi2 */
3424 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3425 .master = &omap44xx_l4_per_hwmod,
3426 .slave = &omap44xx_mcspi2_hwmod,
3428 .addr = omap44xx_mcspi2_addrs,
3429 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 /* mcspi2 slave ports */
3433 static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
3434 &omap44xx_l4_per__mcspi2,
3437 /* mcspi2 dev_attr */
3438 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
3439 .num_chipselect = 2,
3442 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
3444 .class = &omap44xx_mcspi_hwmod_class,
3445 .clkdm_name = "l4_per_clkdm",
3446 .mpu_irqs = omap44xx_mcspi2_irqs,
3447 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
3448 .main_clk = "mcspi2_fck",
3451 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
3452 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
3453 .modulemode = MODULEMODE_SWCTRL,
3456 .dev_attr = &mcspi2_dev_attr,
3457 .slaves = omap44xx_mcspi2_slaves,
3458 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi2_slaves),
3462 static struct omap_hwmod omap44xx_mcspi3_hwmod;
3463 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
3464 { .irq = 91 + OMAP44XX_IRQ_GIC_START },
3468 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
3469 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
3470 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
3471 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
3472 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
3476 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
3478 .pa_start = 0x480b8000,
3479 .pa_end = 0x480b81ff,
3480 .flags = ADDR_TYPE_RT
3485 /* l4_per -> mcspi3 */
3486 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3487 .master = &omap44xx_l4_per_hwmod,
3488 .slave = &omap44xx_mcspi3_hwmod,
3490 .addr = omap44xx_mcspi3_addrs,
3491 .user = OCP_USER_MPU | OCP_USER_SDMA,
3494 /* mcspi3 slave ports */
3495 static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
3496 &omap44xx_l4_per__mcspi3,
3499 /* mcspi3 dev_attr */
3500 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
3501 .num_chipselect = 2,
3504 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
3506 .class = &omap44xx_mcspi_hwmod_class,
3507 .clkdm_name = "l4_per_clkdm",
3508 .mpu_irqs = omap44xx_mcspi3_irqs,
3509 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
3510 .main_clk = "mcspi3_fck",
3513 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
3514 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
3515 .modulemode = MODULEMODE_SWCTRL,
3518 .dev_attr = &mcspi3_dev_attr,
3519 .slaves = omap44xx_mcspi3_slaves,
3520 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi3_slaves),
3524 static struct omap_hwmod omap44xx_mcspi4_hwmod;
3525 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
3526 { .irq = 48 + OMAP44XX_IRQ_GIC_START },
3530 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
3531 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
3532 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
3536 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
3538 .pa_start = 0x480ba000,
3539 .pa_end = 0x480ba1ff,
3540 .flags = ADDR_TYPE_RT
3545 /* l4_per -> mcspi4 */
3546 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3547 .master = &omap44xx_l4_per_hwmod,
3548 .slave = &omap44xx_mcspi4_hwmod,
3550 .addr = omap44xx_mcspi4_addrs,
3551 .user = OCP_USER_MPU | OCP_USER_SDMA,
3554 /* mcspi4 slave ports */
3555 static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
3556 &omap44xx_l4_per__mcspi4,
3559 /* mcspi4 dev_attr */
3560 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
3561 .num_chipselect = 1,
3564 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
3566 .class = &omap44xx_mcspi_hwmod_class,
3567 .clkdm_name = "l4_per_clkdm",
3568 .mpu_irqs = omap44xx_mcspi4_irqs,
3569 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
3570 .main_clk = "mcspi4_fck",
3573 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
3574 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
3575 .modulemode = MODULEMODE_SWCTRL,
3578 .dev_attr = &mcspi4_dev_attr,
3579 .slaves = omap44xx_mcspi4_slaves,
3580 .slaves_cnt = ARRAY_SIZE(omap44xx_mcspi4_slaves),
3585 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
3588 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
3590 .sysc_offs = 0x0010,
3591 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
3592 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
3593 SYSC_HAS_SOFTRESET),
3594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3595 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3596 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
3597 .sysc_fields = &omap_hwmod_sysc_type2,
3600 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3602 .sysc = &omap44xx_mmc_sysc,
3606 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3607 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3611 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
3612 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
3613 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
3617 /* mmc1 master ports */
3618 static struct omap_hwmod_ocp_if *omap44xx_mmc1_masters[] = {
3619 &omap44xx_mmc1__l3_main_1,
3622 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
3624 .pa_start = 0x4809c000,
3625 .pa_end = 0x4809c3ff,
3626 .flags = ADDR_TYPE_RT
3631 /* l4_per -> mmc1 */
3632 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3633 .master = &omap44xx_l4_per_hwmod,
3634 .slave = &omap44xx_mmc1_hwmod,
3636 .addr = omap44xx_mmc1_addrs,
3637 .user = OCP_USER_MPU | OCP_USER_SDMA,
3640 /* mmc1 slave ports */
3641 static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3642 &omap44xx_l4_per__mmc1,
3646 static struct omap_mmc_dev_attr mmc1_dev_attr = {
3647 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3650 static struct omap_hwmod omap44xx_mmc1_hwmod = {
3652 .class = &omap44xx_mmc_hwmod_class,
3653 .clkdm_name = "l3_init_clkdm",
3654 .mpu_irqs = omap44xx_mmc1_irqs,
3655 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
3656 .main_clk = "mmc1_fck",
3659 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
3660 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
3661 .modulemode = MODULEMODE_SWCTRL,
3664 .dev_attr = &mmc1_dev_attr,
3665 .slaves = omap44xx_mmc1_slaves,
3666 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3667 .masters = omap44xx_mmc1_masters,
3668 .masters_cnt = ARRAY_SIZE(omap44xx_mmc1_masters),
3672 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
3673 { .irq = 86 + OMAP44XX_IRQ_GIC_START },
3677 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
3678 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
3679 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
3683 /* mmc2 master ports */
3684 static struct omap_hwmod_ocp_if *omap44xx_mmc2_masters[] = {
3685 &omap44xx_mmc2__l3_main_1,
3688 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
3690 .pa_start = 0x480b4000,
3691 .pa_end = 0x480b43ff,
3692 .flags = ADDR_TYPE_RT
3697 /* l4_per -> mmc2 */
3698 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3699 .master = &omap44xx_l4_per_hwmod,
3700 .slave = &omap44xx_mmc2_hwmod,
3702 .addr = omap44xx_mmc2_addrs,
3703 .user = OCP_USER_MPU | OCP_USER_SDMA,
3706 /* mmc2 slave ports */
3707 static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
3708 &omap44xx_l4_per__mmc2,
3711 static struct omap_hwmod omap44xx_mmc2_hwmod = {
3713 .class = &omap44xx_mmc_hwmod_class,
3714 .clkdm_name = "l3_init_clkdm",
3715 .mpu_irqs = omap44xx_mmc2_irqs,
3716 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
3717 .main_clk = "mmc2_fck",
3720 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
3721 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
3722 .modulemode = MODULEMODE_SWCTRL,
3725 .slaves = omap44xx_mmc2_slaves,
3726 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc2_slaves),
3727 .masters = omap44xx_mmc2_masters,
3728 .masters_cnt = ARRAY_SIZE(omap44xx_mmc2_masters),
3732 static struct omap_hwmod omap44xx_mmc3_hwmod;
3733 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
3734 { .irq = 94 + OMAP44XX_IRQ_GIC_START },
3738 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
3739 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
3740 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
3744 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
3746 .pa_start = 0x480ad000,
3747 .pa_end = 0x480ad3ff,
3748 .flags = ADDR_TYPE_RT
3753 /* l4_per -> mmc3 */
3754 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3755 .master = &omap44xx_l4_per_hwmod,
3756 .slave = &omap44xx_mmc3_hwmod,
3758 .addr = omap44xx_mmc3_addrs,
3759 .user = OCP_USER_MPU | OCP_USER_SDMA,
3762 /* mmc3 slave ports */
3763 static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
3764 &omap44xx_l4_per__mmc3,
3767 static struct omap_hwmod omap44xx_mmc3_hwmod = {
3769 .class = &omap44xx_mmc_hwmod_class,
3770 .clkdm_name = "l4_per_clkdm",
3771 .mpu_irqs = omap44xx_mmc3_irqs,
3772 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
3773 .main_clk = "mmc3_fck",
3776 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
3777 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
3778 .modulemode = MODULEMODE_SWCTRL,
3781 .slaves = omap44xx_mmc3_slaves,
3782 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc3_slaves),
3786 static struct omap_hwmod omap44xx_mmc4_hwmod;
3787 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
3788 { .irq = 96 + OMAP44XX_IRQ_GIC_START },
3792 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
3793 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
3794 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
3798 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
3800 .pa_start = 0x480d1000,
3801 .pa_end = 0x480d13ff,
3802 .flags = ADDR_TYPE_RT
3807 /* l4_per -> mmc4 */
3808 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3809 .master = &omap44xx_l4_per_hwmod,
3810 .slave = &omap44xx_mmc4_hwmod,
3812 .addr = omap44xx_mmc4_addrs,
3813 .user = OCP_USER_MPU | OCP_USER_SDMA,
3816 /* mmc4 slave ports */
3817 static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
3818 &omap44xx_l4_per__mmc4,
3821 static struct omap_hwmod omap44xx_mmc4_hwmod = {
3823 .class = &omap44xx_mmc_hwmod_class,
3824 .clkdm_name = "l4_per_clkdm",
3825 .mpu_irqs = omap44xx_mmc4_irqs,
3827 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
3828 .main_clk = "mmc4_fck",
3831 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
3832 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
3833 .modulemode = MODULEMODE_SWCTRL,
3836 .slaves = omap44xx_mmc4_slaves,
3837 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc4_slaves),
3841 static struct omap_hwmod omap44xx_mmc5_hwmod;
3842 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
3843 { .irq = 59 + OMAP44XX_IRQ_GIC_START },
3847 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
3848 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
3849 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
3853 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
3855 .pa_start = 0x480d5000,
3856 .pa_end = 0x480d53ff,
3857 .flags = ADDR_TYPE_RT
3862 /* l4_per -> mmc5 */
3863 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3864 .master = &omap44xx_l4_per_hwmod,
3865 .slave = &omap44xx_mmc5_hwmod,
3867 .addr = omap44xx_mmc5_addrs,
3868 .user = OCP_USER_MPU | OCP_USER_SDMA,
3871 /* mmc5 slave ports */
3872 static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
3873 &omap44xx_l4_per__mmc5,
3876 static struct omap_hwmod omap44xx_mmc5_hwmod = {
3878 .class = &omap44xx_mmc_hwmod_class,
3879 .clkdm_name = "l4_per_clkdm",
3880 .mpu_irqs = omap44xx_mmc5_irqs,
3881 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
3882 .main_clk = "mmc5_fck",
3885 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
3886 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
3887 .modulemode = MODULEMODE_SWCTRL,
3890 .slaves = omap44xx_mmc5_slaves,
3891 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc5_slaves),
3899 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
3904 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
3905 { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
3906 { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
3907 { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
3911 /* mpu master ports */
3912 static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
3913 &omap44xx_mpu__l3_main_1,
3914 &omap44xx_mpu__l4_abe,
3918 static struct omap_hwmod omap44xx_mpu_hwmod = {
3920 .class = &omap44xx_mpu_hwmod_class,
3921 .clkdm_name = "mpuss_clkdm",
3922 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
3923 .mpu_irqs = omap44xx_mpu_irqs,
3924 .main_clk = "dpll_mpu_m2_ck",
3927 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
3928 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
3931 .masters = omap44xx_mpu_masters,
3932 .masters_cnt = ARRAY_SIZE(omap44xx_mpu_masters),
3936 * 'smartreflex' class
3937 * smartreflex module (monitor silicon performance and outputs a measure of
3938 * performance error)
3941 /* The IP is not compliant to type1 / type2 scheme */
3942 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
3947 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
3948 .sysc_offs = 0x0038,
3949 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
3950 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3952 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
3955 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
3956 .name = "smartreflex",
3957 .sysc = &omap44xx_smartreflex_sysc,
3961 /* smartreflex_core */
3962 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
3963 .sensor_voltdm_name = "core",
3966 static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
3967 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
3968 { .irq = 19 + OMAP44XX_IRQ_GIC_START },
3972 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
3974 .pa_start = 0x4a0dd000,
3975 .pa_end = 0x4a0dd03f,
3976 .flags = ADDR_TYPE_RT
3981 /* l4_cfg -> smartreflex_core */
3982 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3983 .master = &omap44xx_l4_cfg_hwmod,
3984 .slave = &omap44xx_smartreflex_core_hwmod,
3986 .addr = omap44xx_smartreflex_core_addrs,
3987 .user = OCP_USER_MPU | OCP_USER_SDMA,
3990 /* smartreflex_core slave ports */
3991 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
3992 &omap44xx_l4_cfg__smartreflex_core,
3995 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
3996 .name = "smartreflex_core",
3997 .class = &omap44xx_smartreflex_hwmod_class,
3998 .clkdm_name = "l4_ao_clkdm",
3999 .mpu_irqs = omap44xx_smartreflex_core_irqs,
4001 .main_clk = "smartreflex_core_fck",
4004 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
4005 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
4006 .modulemode = MODULEMODE_SWCTRL,
4009 .slaves = omap44xx_smartreflex_core_slaves,
4010 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
4011 .dev_attr = &smartreflex_core_dev_attr,
4014 /* smartreflex_iva */
4015 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
4016 .sensor_voltdm_name = "iva",
4019 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
4020 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
4021 { .irq = 102 + OMAP44XX_IRQ_GIC_START },
4025 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4027 .pa_start = 0x4a0db000,
4028 .pa_end = 0x4a0db03f,
4029 .flags = ADDR_TYPE_RT
4034 /* l4_cfg -> smartreflex_iva */
4035 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4036 .master = &omap44xx_l4_cfg_hwmod,
4037 .slave = &omap44xx_smartreflex_iva_hwmod,
4039 .addr = omap44xx_smartreflex_iva_addrs,
4040 .user = OCP_USER_MPU | OCP_USER_SDMA,
4043 /* smartreflex_iva slave ports */
4044 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
4045 &omap44xx_l4_cfg__smartreflex_iva,
4048 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
4049 .name = "smartreflex_iva",
4050 .class = &omap44xx_smartreflex_hwmod_class,
4051 .clkdm_name = "l4_ao_clkdm",
4052 .mpu_irqs = omap44xx_smartreflex_iva_irqs,
4053 .main_clk = "smartreflex_iva_fck",
4056 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
4057 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
4058 .modulemode = MODULEMODE_SWCTRL,
4061 .slaves = omap44xx_smartreflex_iva_slaves,
4062 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
4063 .dev_attr = &smartreflex_iva_dev_attr,
4066 /* smartreflex_mpu */
4067 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
4068 .sensor_voltdm_name = "mpu",
4071 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
4072 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
4073 { .irq = 18 + OMAP44XX_IRQ_GIC_START },
4077 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4079 .pa_start = 0x4a0d9000,
4080 .pa_end = 0x4a0d903f,
4081 .flags = ADDR_TYPE_RT
4086 /* l4_cfg -> smartreflex_mpu */
4087 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4088 .master = &omap44xx_l4_cfg_hwmod,
4089 .slave = &omap44xx_smartreflex_mpu_hwmod,
4091 .addr = omap44xx_smartreflex_mpu_addrs,
4092 .user = OCP_USER_MPU | OCP_USER_SDMA,
4095 /* smartreflex_mpu slave ports */
4096 static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
4097 &omap44xx_l4_cfg__smartreflex_mpu,
4100 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
4101 .name = "smartreflex_mpu",
4102 .class = &omap44xx_smartreflex_hwmod_class,
4103 .clkdm_name = "l4_ao_clkdm",
4104 .mpu_irqs = omap44xx_smartreflex_mpu_irqs,
4105 .main_clk = "smartreflex_mpu_fck",
4108 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
4109 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
4110 .modulemode = MODULEMODE_SWCTRL,
4113 .slaves = omap44xx_smartreflex_mpu_slaves,
4114 .slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
4115 .dev_attr = &smartreflex_mpu_dev_attr,
4120 * spinlock provides hardware assistance for synchronizing the processes
4121 * running on multiple processors
4124 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
4126 .sysc_offs = 0x0010,
4127 .syss_offs = 0x0014,
4128 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4129 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
4130 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
4131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4133 .sysc_fields = &omap_hwmod_sysc_type1,
4136 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
4138 .sysc = &omap44xx_spinlock_sysc,
4142 static struct omap_hwmod omap44xx_spinlock_hwmod;
4143 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4145 .pa_start = 0x4a0f6000,
4146 .pa_end = 0x4a0f6fff,
4147 .flags = ADDR_TYPE_RT
4152 /* l4_cfg -> spinlock */
4153 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4154 .master = &omap44xx_l4_cfg_hwmod,
4155 .slave = &omap44xx_spinlock_hwmod,
4157 .addr = omap44xx_spinlock_addrs,
4158 .user = OCP_USER_MPU | OCP_USER_SDMA,
4161 /* spinlock slave ports */
4162 static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
4163 &omap44xx_l4_cfg__spinlock,
4166 static struct omap_hwmod omap44xx_spinlock_hwmod = {
4168 .class = &omap44xx_spinlock_hwmod_class,
4169 .clkdm_name = "l4_cfg_clkdm",
4172 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
4173 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
4176 .slaves = omap44xx_spinlock_slaves,
4177 .slaves_cnt = ARRAY_SIZE(omap44xx_spinlock_slaves),
4182 * general purpose timer module with accurate 1ms tick
4183 * This class contains several variants: ['timer_1ms', 'timer']
4186 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
4188 .sysc_offs = 0x0010,
4189 .syss_offs = 0x0014,
4190 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
4191 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
4192 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4193 SYSS_HAS_RESET_STATUS),
4194 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
4195 .sysc_fields = &omap_hwmod_sysc_type1,
4198 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
4200 .sysc = &omap44xx_timer_1ms_sysc,
4203 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
4205 .sysc_offs = 0x0010,
4206 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
4207 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
4208 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4210 .sysc_fields = &omap_hwmod_sysc_type2,
4213 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
4215 .sysc = &omap44xx_timer_sysc,
4218 /* always-on timers dev attribute */
4219 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
4220 .timer_capability = OMAP_TIMER_ALWON,
4223 /* pwm timers dev attribute */
4224 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
4225 .timer_capability = OMAP_TIMER_HAS_PWM,
4229 static struct omap_hwmod omap44xx_timer1_hwmod;
4230 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
4231 { .irq = 37 + OMAP44XX_IRQ_GIC_START },
4235 static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
4237 .pa_start = 0x4a318000,
4238 .pa_end = 0x4a31807f,
4239 .flags = ADDR_TYPE_RT
4244 /* l4_wkup -> timer1 */
4245 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4246 .master = &omap44xx_l4_wkup_hwmod,
4247 .slave = &omap44xx_timer1_hwmod,
4248 .clk = "l4_wkup_clk_mux_ck",
4249 .addr = omap44xx_timer1_addrs,
4250 .user = OCP_USER_MPU | OCP_USER_SDMA,
4253 /* timer1 slave ports */
4254 static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
4255 &omap44xx_l4_wkup__timer1,
4258 static struct omap_hwmod omap44xx_timer1_hwmod = {
4260 .class = &omap44xx_timer_1ms_hwmod_class,
4261 .clkdm_name = "l4_wkup_clkdm",
4262 .mpu_irqs = omap44xx_timer1_irqs,
4263 .main_clk = "timer1_fck",
4266 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
4267 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
4268 .modulemode = MODULEMODE_SWCTRL,
4271 .dev_attr = &capability_alwon_dev_attr,
4272 .slaves = omap44xx_timer1_slaves,
4273 .slaves_cnt = ARRAY_SIZE(omap44xx_timer1_slaves),
4277 static struct omap_hwmod omap44xx_timer2_hwmod;
4278 static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
4279 { .irq = 38 + OMAP44XX_IRQ_GIC_START },
4283 static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
4285 .pa_start = 0x48032000,
4286 .pa_end = 0x4803207f,
4287 .flags = ADDR_TYPE_RT
4292 /* l4_per -> timer2 */
4293 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4294 .master = &omap44xx_l4_per_hwmod,
4295 .slave = &omap44xx_timer2_hwmod,
4297 .addr = omap44xx_timer2_addrs,
4298 .user = OCP_USER_MPU | OCP_USER_SDMA,
4301 /* timer2 slave ports */
4302 static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
4303 &omap44xx_l4_per__timer2,
4306 static struct omap_hwmod omap44xx_timer2_hwmod = {
4308 .class = &omap44xx_timer_1ms_hwmod_class,
4309 .clkdm_name = "l4_per_clkdm",
4310 .mpu_irqs = omap44xx_timer2_irqs,
4311 .main_clk = "timer2_fck",
4314 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
4315 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
4316 .modulemode = MODULEMODE_SWCTRL,
4319 .dev_attr = &capability_alwon_dev_attr,
4320 .slaves = omap44xx_timer2_slaves,
4321 .slaves_cnt = ARRAY_SIZE(omap44xx_timer2_slaves),
4325 static struct omap_hwmod omap44xx_timer3_hwmod;
4326 static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
4327 { .irq = 39 + OMAP44XX_IRQ_GIC_START },
4331 static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
4333 .pa_start = 0x48034000,
4334 .pa_end = 0x4803407f,
4335 .flags = ADDR_TYPE_RT
4340 /* l4_per -> timer3 */
4341 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4342 .master = &omap44xx_l4_per_hwmod,
4343 .slave = &omap44xx_timer3_hwmod,
4345 .addr = omap44xx_timer3_addrs,
4346 .user = OCP_USER_MPU | OCP_USER_SDMA,
4349 /* timer3 slave ports */
4350 static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
4351 &omap44xx_l4_per__timer3,
4354 static struct omap_hwmod omap44xx_timer3_hwmod = {
4356 .class = &omap44xx_timer_hwmod_class,
4357 .clkdm_name = "l4_per_clkdm",
4358 .mpu_irqs = omap44xx_timer3_irqs,
4359 .main_clk = "timer3_fck",
4362 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
4363 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
4364 .modulemode = MODULEMODE_SWCTRL,
4367 .dev_attr = &capability_alwon_dev_attr,
4368 .slaves = omap44xx_timer3_slaves,
4369 .slaves_cnt = ARRAY_SIZE(omap44xx_timer3_slaves),
4373 static struct omap_hwmod omap44xx_timer4_hwmod;
4374 static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
4375 { .irq = 40 + OMAP44XX_IRQ_GIC_START },
4379 static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
4381 .pa_start = 0x48036000,
4382 .pa_end = 0x4803607f,
4383 .flags = ADDR_TYPE_RT
4388 /* l4_per -> timer4 */
4389 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4390 .master = &omap44xx_l4_per_hwmod,
4391 .slave = &omap44xx_timer4_hwmod,
4393 .addr = omap44xx_timer4_addrs,
4394 .user = OCP_USER_MPU | OCP_USER_SDMA,
4397 /* timer4 slave ports */
4398 static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
4399 &omap44xx_l4_per__timer4,
4402 static struct omap_hwmod omap44xx_timer4_hwmod = {
4404 .class = &omap44xx_timer_hwmod_class,
4405 .clkdm_name = "l4_per_clkdm",
4406 .mpu_irqs = omap44xx_timer4_irqs,
4407 .main_clk = "timer4_fck",
4410 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
4411 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
4412 .modulemode = MODULEMODE_SWCTRL,
4415 .dev_attr = &capability_alwon_dev_attr,
4416 .slaves = omap44xx_timer4_slaves,
4417 .slaves_cnt = ARRAY_SIZE(omap44xx_timer4_slaves),
4421 static struct omap_hwmod omap44xx_timer5_hwmod;
4422 static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
4423 { .irq = 41 + OMAP44XX_IRQ_GIC_START },
4427 static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
4429 .pa_start = 0x40138000,
4430 .pa_end = 0x4013807f,
4431 .flags = ADDR_TYPE_RT
4436 /* l4_abe -> timer5 */
4437 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4438 .master = &omap44xx_l4_abe_hwmod,
4439 .slave = &omap44xx_timer5_hwmod,
4440 .clk = "ocp_abe_iclk",
4441 .addr = omap44xx_timer5_addrs,
4442 .user = OCP_USER_MPU,
4445 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
4447 .pa_start = 0x49038000,
4448 .pa_end = 0x4903807f,
4449 .flags = ADDR_TYPE_RT
4454 /* l4_abe -> timer5 (dma) */
4455 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4456 .master = &omap44xx_l4_abe_hwmod,
4457 .slave = &omap44xx_timer5_hwmod,
4458 .clk = "ocp_abe_iclk",
4459 .addr = omap44xx_timer5_dma_addrs,
4460 .user = OCP_USER_SDMA,
4463 /* timer5 slave ports */
4464 static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
4465 &omap44xx_l4_abe__timer5,
4466 &omap44xx_l4_abe__timer5_dma,
4469 static struct omap_hwmod omap44xx_timer5_hwmod = {
4471 .class = &omap44xx_timer_hwmod_class,
4472 .clkdm_name = "abe_clkdm",
4473 .mpu_irqs = omap44xx_timer5_irqs,
4474 .main_clk = "timer5_fck",
4477 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
4478 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
4479 .modulemode = MODULEMODE_SWCTRL,
4482 .dev_attr = &capability_alwon_dev_attr,
4483 .slaves = omap44xx_timer5_slaves,
4484 .slaves_cnt = ARRAY_SIZE(omap44xx_timer5_slaves),
4488 static struct omap_hwmod omap44xx_timer6_hwmod;
4489 static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
4490 { .irq = 42 + OMAP44XX_IRQ_GIC_START },
4494 static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
4496 .pa_start = 0x4013a000,
4497 .pa_end = 0x4013a07f,
4498 .flags = ADDR_TYPE_RT
4503 /* l4_abe -> timer6 */
4504 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4505 .master = &omap44xx_l4_abe_hwmod,
4506 .slave = &omap44xx_timer6_hwmod,
4507 .clk = "ocp_abe_iclk",
4508 .addr = omap44xx_timer6_addrs,
4509 .user = OCP_USER_MPU,
4512 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
4514 .pa_start = 0x4903a000,
4515 .pa_end = 0x4903a07f,
4516 .flags = ADDR_TYPE_RT
4521 /* l4_abe -> timer6 (dma) */
4522 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4523 .master = &omap44xx_l4_abe_hwmod,
4524 .slave = &omap44xx_timer6_hwmod,
4525 .clk = "ocp_abe_iclk",
4526 .addr = omap44xx_timer6_dma_addrs,
4527 .user = OCP_USER_SDMA,
4530 /* timer6 slave ports */
4531 static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
4532 &omap44xx_l4_abe__timer6,
4533 &omap44xx_l4_abe__timer6_dma,
4536 static struct omap_hwmod omap44xx_timer6_hwmod = {
4538 .class = &omap44xx_timer_hwmod_class,
4539 .clkdm_name = "abe_clkdm",
4540 .mpu_irqs = omap44xx_timer6_irqs,
4542 .main_clk = "timer6_fck",
4545 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
4546 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
4547 .modulemode = MODULEMODE_SWCTRL,
4550 .dev_attr = &capability_alwon_dev_attr,
4551 .slaves = omap44xx_timer6_slaves,
4552 .slaves_cnt = ARRAY_SIZE(omap44xx_timer6_slaves),
4556 static struct omap_hwmod omap44xx_timer7_hwmod;
4557 static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
4558 { .irq = 43 + OMAP44XX_IRQ_GIC_START },
4562 static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
4564 .pa_start = 0x4013c000,
4565 .pa_end = 0x4013c07f,
4566 .flags = ADDR_TYPE_RT
4571 /* l4_abe -> timer7 */
4572 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4573 .master = &omap44xx_l4_abe_hwmod,
4574 .slave = &omap44xx_timer7_hwmod,
4575 .clk = "ocp_abe_iclk",
4576 .addr = omap44xx_timer7_addrs,
4577 .user = OCP_USER_MPU,
4580 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
4582 .pa_start = 0x4903c000,
4583 .pa_end = 0x4903c07f,
4584 .flags = ADDR_TYPE_RT
4589 /* l4_abe -> timer7 (dma) */
4590 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4591 .master = &omap44xx_l4_abe_hwmod,
4592 .slave = &omap44xx_timer7_hwmod,
4593 .clk = "ocp_abe_iclk",
4594 .addr = omap44xx_timer7_dma_addrs,
4595 .user = OCP_USER_SDMA,
4598 /* timer7 slave ports */
4599 static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
4600 &omap44xx_l4_abe__timer7,
4601 &omap44xx_l4_abe__timer7_dma,
4604 static struct omap_hwmod omap44xx_timer7_hwmod = {
4606 .class = &omap44xx_timer_hwmod_class,
4607 .clkdm_name = "abe_clkdm",
4608 .mpu_irqs = omap44xx_timer7_irqs,
4609 .main_clk = "timer7_fck",
4612 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
4613 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
4614 .modulemode = MODULEMODE_SWCTRL,
4617 .dev_attr = &capability_alwon_dev_attr,
4618 .slaves = omap44xx_timer7_slaves,
4619 .slaves_cnt = ARRAY_SIZE(omap44xx_timer7_slaves),
4623 static struct omap_hwmod omap44xx_timer8_hwmod;
4624 static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
4625 { .irq = 44 + OMAP44XX_IRQ_GIC_START },
4629 static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
4631 .pa_start = 0x4013e000,
4632 .pa_end = 0x4013e07f,
4633 .flags = ADDR_TYPE_RT
4638 /* l4_abe -> timer8 */
4639 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4640 .master = &omap44xx_l4_abe_hwmod,
4641 .slave = &omap44xx_timer8_hwmod,
4642 .clk = "ocp_abe_iclk",
4643 .addr = omap44xx_timer8_addrs,
4644 .user = OCP_USER_MPU,
4647 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
4649 .pa_start = 0x4903e000,
4650 .pa_end = 0x4903e07f,
4651 .flags = ADDR_TYPE_RT
4656 /* l4_abe -> timer8 (dma) */
4657 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4658 .master = &omap44xx_l4_abe_hwmod,
4659 .slave = &omap44xx_timer8_hwmod,
4660 .clk = "ocp_abe_iclk",
4661 .addr = omap44xx_timer8_dma_addrs,
4662 .user = OCP_USER_SDMA,
4665 /* timer8 slave ports */
4666 static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
4667 &omap44xx_l4_abe__timer8,
4668 &omap44xx_l4_abe__timer8_dma,
4671 static struct omap_hwmod omap44xx_timer8_hwmod = {
4673 .class = &omap44xx_timer_hwmod_class,
4674 .clkdm_name = "abe_clkdm",
4675 .mpu_irqs = omap44xx_timer8_irqs,
4676 .main_clk = "timer8_fck",
4679 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
4680 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
4681 .modulemode = MODULEMODE_SWCTRL,
4684 .dev_attr = &capability_pwm_dev_attr,
4685 .slaves = omap44xx_timer8_slaves,
4686 .slaves_cnt = ARRAY_SIZE(omap44xx_timer8_slaves),
4690 static struct omap_hwmod omap44xx_timer9_hwmod;
4691 static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
4692 { .irq = 45 + OMAP44XX_IRQ_GIC_START },
4696 static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
4698 .pa_start = 0x4803e000,
4699 .pa_end = 0x4803e07f,
4700 .flags = ADDR_TYPE_RT
4705 /* l4_per -> timer9 */
4706 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4707 .master = &omap44xx_l4_per_hwmod,
4708 .slave = &omap44xx_timer9_hwmod,
4710 .addr = omap44xx_timer9_addrs,
4711 .user = OCP_USER_MPU | OCP_USER_SDMA,
4714 /* timer9 slave ports */
4715 static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
4716 &omap44xx_l4_per__timer9,
4719 static struct omap_hwmod omap44xx_timer9_hwmod = {
4721 .class = &omap44xx_timer_hwmod_class,
4722 .clkdm_name = "l4_per_clkdm",
4723 .mpu_irqs = omap44xx_timer9_irqs,
4724 .main_clk = "timer9_fck",
4727 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
4728 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
4729 .modulemode = MODULEMODE_SWCTRL,
4732 .dev_attr = &capability_pwm_dev_attr,
4733 .slaves = omap44xx_timer9_slaves,
4734 .slaves_cnt = ARRAY_SIZE(omap44xx_timer9_slaves),
4738 static struct omap_hwmod omap44xx_timer10_hwmod;
4739 static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
4740 { .irq = 46 + OMAP44XX_IRQ_GIC_START },
4744 static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
4746 .pa_start = 0x48086000,
4747 .pa_end = 0x4808607f,
4748 .flags = ADDR_TYPE_RT
4753 /* l4_per -> timer10 */
4754 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4755 .master = &omap44xx_l4_per_hwmod,
4756 .slave = &omap44xx_timer10_hwmod,
4758 .addr = omap44xx_timer10_addrs,
4759 .user = OCP_USER_MPU | OCP_USER_SDMA,
4762 /* timer10 slave ports */
4763 static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
4764 &omap44xx_l4_per__timer10,
4767 static struct omap_hwmod omap44xx_timer10_hwmod = {
4769 .class = &omap44xx_timer_1ms_hwmod_class,
4770 .clkdm_name = "l4_per_clkdm",
4771 .mpu_irqs = omap44xx_timer10_irqs,
4772 .main_clk = "timer10_fck",
4775 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
4776 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
4777 .modulemode = MODULEMODE_SWCTRL,
4780 .dev_attr = &capability_pwm_dev_attr,
4781 .slaves = omap44xx_timer10_slaves,
4782 .slaves_cnt = ARRAY_SIZE(omap44xx_timer10_slaves),
4786 static struct omap_hwmod omap44xx_timer11_hwmod;
4787 static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
4788 { .irq = 47 + OMAP44XX_IRQ_GIC_START },
4792 static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
4794 .pa_start = 0x48088000,
4795 .pa_end = 0x4808807f,
4796 .flags = ADDR_TYPE_RT
4801 /* l4_per -> timer11 */
4802 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4803 .master = &omap44xx_l4_per_hwmod,
4804 .slave = &omap44xx_timer11_hwmod,
4806 .addr = omap44xx_timer11_addrs,
4807 .user = OCP_USER_MPU | OCP_USER_SDMA,
4810 /* timer11 slave ports */
4811 static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
4812 &omap44xx_l4_per__timer11,
4815 static struct omap_hwmod omap44xx_timer11_hwmod = {
4817 .class = &omap44xx_timer_hwmod_class,
4818 .clkdm_name = "l4_per_clkdm",
4819 .mpu_irqs = omap44xx_timer11_irqs,
4820 .main_clk = "timer11_fck",
4823 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
4824 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
4825 .modulemode = MODULEMODE_SWCTRL,
4828 .dev_attr = &capability_pwm_dev_attr,
4829 .slaves = omap44xx_timer11_slaves,
4830 .slaves_cnt = ARRAY_SIZE(omap44xx_timer11_slaves),
4835 * universal asynchronous receiver/transmitter (uart)
4838 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
4840 .sysc_offs = 0x0054,
4841 .syss_offs = 0x0058,
4842 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
4843 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
4844 SYSS_HAS_RESET_STATUS),
4845 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
4847 .sysc_fields = &omap_hwmod_sysc_type1,
4850 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
4852 .sysc = &omap44xx_uart_sysc,
4856 static struct omap_hwmod omap44xx_uart1_hwmod;
4857 static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
4858 { .irq = 72 + OMAP44XX_IRQ_GIC_START },
4862 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
4863 { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
4864 { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
4868 static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
4870 .pa_start = 0x4806a000,
4871 .pa_end = 0x4806a0ff,
4872 .flags = ADDR_TYPE_RT
4877 /* l4_per -> uart1 */
4878 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4879 .master = &omap44xx_l4_per_hwmod,
4880 .slave = &omap44xx_uart1_hwmod,
4882 .addr = omap44xx_uart1_addrs,
4883 .user = OCP_USER_MPU | OCP_USER_SDMA,
4886 /* uart1 slave ports */
4887 static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
4888 &omap44xx_l4_per__uart1,
4891 static struct omap_hwmod omap44xx_uart1_hwmod = {
4893 .class = &omap44xx_uart_hwmod_class,
4894 .clkdm_name = "l4_per_clkdm",
4895 .mpu_irqs = omap44xx_uart1_irqs,
4896 .sdma_reqs = omap44xx_uart1_sdma_reqs,
4897 .main_clk = "uart1_fck",
4900 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
4901 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
4902 .modulemode = MODULEMODE_SWCTRL,
4905 .slaves = omap44xx_uart1_slaves,
4906 .slaves_cnt = ARRAY_SIZE(omap44xx_uart1_slaves),
4910 static struct omap_hwmod omap44xx_uart2_hwmod;
4911 static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
4912 { .irq = 73 + OMAP44XX_IRQ_GIC_START },
4916 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
4917 { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
4918 { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
4922 static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
4924 .pa_start = 0x4806c000,
4925 .pa_end = 0x4806c0ff,
4926 .flags = ADDR_TYPE_RT
4931 /* l4_per -> uart2 */
4932 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4933 .master = &omap44xx_l4_per_hwmod,
4934 .slave = &omap44xx_uart2_hwmod,
4936 .addr = omap44xx_uart2_addrs,
4937 .user = OCP_USER_MPU | OCP_USER_SDMA,
4940 /* uart2 slave ports */
4941 static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
4942 &omap44xx_l4_per__uart2,
4945 static struct omap_hwmod omap44xx_uart2_hwmod = {
4947 .class = &omap44xx_uart_hwmod_class,
4948 .clkdm_name = "l4_per_clkdm",
4949 .mpu_irqs = omap44xx_uart2_irqs,
4950 .sdma_reqs = omap44xx_uart2_sdma_reqs,
4951 .main_clk = "uart2_fck",
4954 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
4955 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
4956 .modulemode = MODULEMODE_SWCTRL,
4959 .slaves = omap44xx_uart2_slaves,
4960 .slaves_cnt = ARRAY_SIZE(omap44xx_uart2_slaves),
4964 static struct omap_hwmod omap44xx_uart3_hwmod;
4965 static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
4966 { .irq = 74 + OMAP44XX_IRQ_GIC_START },
4970 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
4971 { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
4972 { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
4976 static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
4978 .pa_start = 0x48020000,
4979 .pa_end = 0x480200ff,
4980 .flags = ADDR_TYPE_RT
4985 /* l4_per -> uart3 */
4986 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4987 .master = &omap44xx_l4_per_hwmod,
4988 .slave = &omap44xx_uart3_hwmod,
4990 .addr = omap44xx_uart3_addrs,
4991 .user = OCP_USER_MPU | OCP_USER_SDMA,
4994 /* uart3 slave ports */
4995 static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
4996 &omap44xx_l4_per__uart3,
4999 static struct omap_hwmod omap44xx_uart3_hwmod = {
5001 .class = &omap44xx_uart_hwmod_class,
5002 .clkdm_name = "l4_per_clkdm",
5003 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
5004 .mpu_irqs = omap44xx_uart3_irqs,
5005 .sdma_reqs = omap44xx_uart3_sdma_reqs,
5006 .main_clk = "uart3_fck",
5009 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
5010 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
5011 .modulemode = MODULEMODE_SWCTRL,
5014 .slaves = omap44xx_uart3_slaves,
5015 .slaves_cnt = ARRAY_SIZE(omap44xx_uart3_slaves),
5019 static struct omap_hwmod omap44xx_uart4_hwmod;
5020 static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
5021 { .irq = 70 + OMAP44XX_IRQ_GIC_START },
5025 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
5026 { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
5027 { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
5031 static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
5033 .pa_start = 0x4806e000,
5034 .pa_end = 0x4806e0ff,
5035 .flags = ADDR_TYPE_RT
5040 /* l4_per -> uart4 */
5041 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
5042 .master = &omap44xx_l4_per_hwmod,
5043 .slave = &omap44xx_uart4_hwmod,
5045 .addr = omap44xx_uart4_addrs,
5046 .user = OCP_USER_MPU | OCP_USER_SDMA,
5049 /* uart4 slave ports */
5050 static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
5051 &omap44xx_l4_per__uart4,
5054 static struct omap_hwmod omap44xx_uart4_hwmod = {
5056 .class = &omap44xx_uart_hwmod_class,
5057 .clkdm_name = "l4_per_clkdm",
5058 .mpu_irqs = omap44xx_uart4_irqs,
5059 .sdma_reqs = omap44xx_uart4_sdma_reqs,
5060 .main_clk = "uart4_fck",
5063 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
5064 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
5065 .modulemode = MODULEMODE_SWCTRL,
5068 .slaves = omap44xx_uart4_slaves,
5069 .slaves_cnt = ARRAY_SIZE(omap44xx_uart4_slaves),
5073 * 'usb_otg_hs' class
5074 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
5077 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
5079 .sysc_offs = 0x0404,
5080 .syss_offs = 0x0408,
5081 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
5082 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
5083 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5084 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5085 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
5087 .sysc_fields = &omap_hwmod_sysc_type1,
5090 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
5091 .name = "usb_otg_hs",
5092 .sysc = &omap44xx_usb_otg_hs_sysc,
5096 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
5097 { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
5098 { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
5102 /* usb_otg_hs master ports */
5103 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_masters[] = {
5104 &omap44xx_usb_otg_hs__l3_main_2,
5107 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
5109 .pa_start = 0x4a0ab000,
5110 .pa_end = 0x4a0ab003,
5111 .flags = ADDR_TYPE_RT
5116 /* l4_cfg -> usb_otg_hs */
5117 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
5118 .master = &omap44xx_l4_cfg_hwmod,
5119 .slave = &omap44xx_usb_otg_hs_hwmod,
5121 .addr = omap44xx_usb_otg_hs_addrs,
5122 .user = OCP_USER_MPU | OCP_USER_SDMA,
5125 /* usb_otg_hs slave ports */
5126 static struct omap_hwmod_ocp_if *omap44xx_usb_otg_hs_slaves[] = {
5127 &omap44xx_l4_cfg__usb_otg_hs,
5130 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
5131 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
5134 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
5135 .name = "usb_otg_hs",
5136 .class = &omap44xx_usb_otg_hs_hwmod_class,
5137 .clkdm_name = "l3_init_clkdm",
5138 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
5139 .mpu_irqs = omap44xx_usb_otg_hs_irqs,
5140 .main_clk = "usb_otg_hs_ick",
5143 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
5144 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
5145 .modulemode = MODULEMODE_HWCTRL,
5148 .opt_clks = usb_otg_hs_opt_clks,
5149 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
5150 .slaves = omap44xx_usb_otg_hs_slaves,
5151 .slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
5152 .masters = omap44xx_usb_otg_hs_masters,
5153 .masters_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_masters),
5158 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
5159 * overflow condition
5162 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
5164 .sysc_offs = 0x0010,
5165 .syss_offs = 0x0014,
5166 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
5167 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
5168 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
5170 .sysc_fields = &omap_hwmod_sysc_type1,
5173 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
5175 .sysc = &omap44xx_wd_timer_sysc,
5176 .pre_shutdown = &omap2_wd_timer_disable,
5180 static struct omap_hwmod omap44xx_wd_timer2_hwmod;
5181 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
5182 { .irq = 80 + OMAP44XX_IRQ_GIC_START },
5186 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
5188 .pa_start = 0x4a314000,
5189 .pa_end = 0x4a31407f,
5190 .flags = ADDR_TYPE_RT
5195 /* l4_wkup -> wd_timer2 */
5196 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
5197 .master = &omap44xx_l4_wkup_hwmod,
5198 .slave = &omap44xx_wd_timer2_hwmod,
5199 .clk = "l4_wkup_clk_mux_ck",
5200 .addr = omap44xx_wd_timer2_addrs,
5201 .user = OCP_USER_MPU | OCP_USER_SDMA,
5204 /* wd_timer2 slave ports */
5205 static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
5206 &omap44xx_l4_wkup__wd_timer2,
5209 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
5210 .name = "wd_timer2",
5211 .class = &omap44xx_wd_timer_hwmod_class,
5212 .clkdm_name = "l4_wkup_clkdm",
5213 .mpu_irqs = omap44xx_wd_timer2_irqs,
5214 .main_clk = "wd_timer2_fck",
5217 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
5218 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
5219 .modulemode = MODULEMODE_SWCTRL,
5222 .slaves = omap44xx_wd_timer2_slaves,
5223 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer2_slaves),
5227 static struct omap_hwmod omap44xx_wd_timer3_hwmod;
5228 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
5229 { .irq = 36 + OMAP44XX_IRQ_GIC_START },
5233 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
5235 .pa_start = 0x40130000,
5236 .pa_end = 0x4013007f,
5237 .flags = ADDR_TYPE_RT
5242 /* l4_abe -> wd_timer3 */
5243 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
5244 .master = &omap44xx_l4_abe_hwmod,
5245 .slave = &omap44xx_wd_timer3_hwmod,
5246 .clk = "ocp_abe_iclk",
5247 .addr = omap44xx_wd_timer3_addrs,
5248 .user = OCP_USER_MPU,
5251 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
5253 .pa_start = 0x49030000,
5254 .pa_end = 0x4903007f,
5255 .flags = ADDR_TYPE_RT
5260 /* l4_abe -> wd_timer3 (dma) */
5261 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
5262 .master = &omap44xx_l4_abe_hwmod,
5263 .slave = &omap44xx_wd_timer3_hwmod,
5264 .clk = "ocp_abe_iclk",
5265 .addr = omap44xx_wd_timer3_dma_addrs,
5266 .user = OCP_USER_SDMA,
5269 /* wd_timer3 slave ports */
5270 static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
5271 &omap44xx_l4_abe__wd_timer3,
5272 &omap44xx_l4_abe__wd_timer3_dma,
5275 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
5276 .name = "wd_timer3",
5277 .class = &omap44xx_wd_timer_hwmod_class,
5278 .clkdm_name = "abe_clkdm",
5279 .mpu_irqs = omap44xx_wd_timer3_irqs,
5280 .main_clk = "wd_timer3_fck",
5283 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
5284 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
5285 .modulemode = MODULEMODE_SWCTRL,
5288 .slaves = omap44xx_wd_timer3_slaves,
5289 .slaves_cnt = ARRAY_SIZE(omap44xx_wd_timer3_slaves),
5292 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5295 &omap44xx_dmm_hwmod,
5298 &omap44xx_emif_fw_hwmod,
5301 &omap44xx_l3_instr_hwmod,
5302 &omap44xx_l3_main_1_hwmod,
5303 &omap44xx_l3_main_2_hwmod,
5304 &omap44xx_l3_main_3_hwmod,
5307 &omap44xx_l4_abe_hwmod,
5308 &omap44xx_l4_cfg_hwmod,
5309 &omap44xx_l4_per_hwmod,
5310 &omap44xx_l4_wkup_hwmod,
5313 &omap44xx_mpu_private_hwmod,
5316 /* &omap44xx_aess_hwmod, */
5319 &omap44xx_bandgap_hwmod,
5322 /* &omap44xx_counter_32k_hwmod, */
5325 &omap44xx_dma_system_hwmod,
5328 &omap44xx_dmic_hwmod,
5331 &omap44xx_dsp_hwmod,
5332 &omap44xx_dsp_c0_hwmod,
5335 &omap44xx_dss_hwmod,
5336 &omap44xx_dss_dispc_hwmod,
5337 &omap44xx_dss_dsi1_hwmod,
5338 &omap44xx_dss_dsi2_hwmod,
5339 &omap44xx_dss_hdmi_hwmod,
5340 &omap44xx_dss_rfbi_hwmod,
5341 &omap44xx_dss_venc_hwmod,
5344 &omap44xx_gpio1_hwmod,
5345 &omap44xx_gpio2_hwmod,
5346 &omap44xx_gpio3_hwmod,
5347 &omap44xx_gpio4_hwmod,
5348 &omap44xx_gpio5_hwmod,
5349 &omap44xx_gpio6_hwmod,
5352 /* &omap44xx_hsi_hwmod, */
5355 &omap44xx_i2c1_hwmod,
5356 &omap44xx_i2c2_hwmod,
5357 &omap44xx_i2c3_hwmod,
5358 &omap44xx_i2c4_hwmod,
5361 &omap44xx_ipu_hwmod,
5362 &omap44xx_ipu_c0_hwmod,
5363 &omap44xx_ipu_c1_hwmod,
5366 /* &omap44xx_iss_hwmod, */
5369 &omap44xx_iva_hwmod,
5370 &omap44xx_iva_seq0_hwmod,
5371 &omap44xx_iva_seq1_hwmod,
5374 &omap44xx_kbd_hwmod,
5377 &omap44xx_mailbox_hwmod,
5380 &omap44xx_mcbsp1_hwmod,
5381 &omap44xx_mcbsp2_hwmod,
5382 &omap44xx_mcbsp3_hwmod,
5383 &omap44xx_mcbsp4_hwmod,
5386 &omap44xx_mcpdm_hwmod,
5389 &omap44xx_mcspi1_hwmod,
5390 &omap44xx_mcspi2_hwmod,
5391 &omap44xx_mcspi3_hwmod,
5392 &omap44xx_mcspi4_hwmod,
5395 &omap44xx_mmc1_hwmod,
5396 &omap44xx_mmc2_hwmod,
5397 &omap44xx_mmc3_hwmod,
5398 &omap44xx_mmc4_hwmod,
5399 &omap44xx_mmc5_hwmod,
5402 &omap44xx_mpu_hwmod,
5404 /* smartreflex class */
5405 &omap44xx_smartreflex_core_hwmod,
5406 &omap44xx_smartreflex_iva_hwmod,
5407 &omap44xx_smartreflex_mpu_hwmod,
5409 /* spinlock class */
5410 &omap44xx_spinlock_hwmod,
5413 &omap44xx_timer1_hwmod,
5414 &omap44xx_timer2_hwmod,
5415 &omap44xx_timer3_hwmod,
5416 &omap44xx_timer4_hwmod,
5417 &omap44xx_timer5_hwmod,
5418 &omap44xx_timer6_hwmod,
5419 &omap44xx_timer7_hwmod,
5420 &omap44xx_timer8_hwmod,
5421 &omap44xx_timer9_hwmod,
5422 &omap44xx_timer10_hwmod,
5423 &omap44xx_timer11_hwmod,
5426 &omap44xx_uart1_hwmod,
5427 &omap44xx_uart2_hwmod,
5428 &omap44xx_uart3_hwmod,
5429 &omap44xx_uart4_hwmod,
5431 /* usb_otg_hs class */
5432 &omap44xx_usb_otg_hs_hwmod,
5434 /* wd_timer class */
5435 &omap44xx_wd_timer2_hwmod,
5436 &omap44xx_wd_timer3_hwmod,
5441 int __init omap44xx_hwmod_init(void)
5443 return omap_hwmod_register(omap44xx_hwmods);